1 /* bnx2x_fw_defs.h: Broadcom Everest network driver.
3 * Copyright (c) 2007-2008 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
11 #define CSTORM_ASSERT_LIST_INDEX_OFFSET \
12 (IS_E1H_OFFSET ? 0x7000 : 0x1000)
13 #define CSTORM_ASSERT_LIST_OFFSET(idx) \
14 (IS_E1H_OFFSET ? (0x7020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
15 #define CSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \
16 (IS_E1H_OFFSET ? (0x8522 + ((function>>1) * 0x40) + \
17 ((function&1) * 0x100) + (index * 0x4)) : (0x1922 + (function * \
18 0x40) + (index * 0x4)))
19 #define CSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \
20 (IS_E1H_OFFSET ? (0x8500 + ((function>>1) * 0x40) + \
21 ((function&1) * 0x100)) : (0x1900 + (function * 0x40)))
22 #define CSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \
23 (IS_E1H_OFFSET ? (0x8508 + ((function>>1) * 0x40) + \
24 ((function&1) * 0x100)) : (0x1908 + (function * 0x40)))
25 #define CSTORM_FUNCTION_MODE_OFFSET \
26 (IS_E1H_OFFSET ? 0x11e8 : 0xffffffff)
27 #define CSTORM_HC_BTR_OFFSET(port) \
28 (IS_E1H_OFFSET ? (0x8704 + (port * 0xf0)) : (0x1984 + (port * 0xc0)))
29 #define CSTORM_SB_HC_DISABLE_OFFSET(port, cpu_id, index) \
30 (IS_E1H_OFFSET ? (0x801a + (port * 0x280) + (cpu_id * 0x28) + \
31 (index * 0x4)) : (0x141a + (port * 0x280) + (cpu_id * 0x28) + \
33 #define CSTORM_SB_HC_TIMEOUT_OFFSET(port, cpu_id, index) \
34 (IS_E1H_OFFSET ? (0x8018 + (port * 0x280) + (cpu_id * 0x28) + \
35 (index * 0x4)) : (0x1418 + (port * 0x280) + (cpu_id * 0x28) + \
37 #define CSTORM_SB_HOST_SB_ADDR_OFFSET(port, cpu_id) \
38 (IS_E1H_OFFSET ? (0x8000 + (port * 0x280) + (cpu_id * 0x28)) : \
39 (0x1400 + (port * 0x280) + (cpu_id * 0x28)))
40 #define CSTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, cpu_id) \
41 (IS_E1H_OFFSET ? (0x8008 + (port * 0x280) + (cpu_id * 0x28)) : \
42 (0x1408 + (port * 0x280) + (cpu_id * 0x28)))
43 #define CSTORM_STATS_FLAGS_OFFSET(function) \
44 (IS_E1H_OFFSET ? (0x1108 + (function * 0x8)) : (0x5108 + \
46 #define TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(function) \
47 (IS_E1H_OFFSET ? (0x31c0 + (function * 0x20)) : 0xffffffff)
48 #define TSTORM_ASSERT_LIST_INDEX_OFFSET \
49 (IS_E1H_OFFSET ? 0xa000 : 0x1000)
50 #define TSTORM_ASSERT_LIST_OFFSET(idx) \
51 (IS_E1H_OFFSET ? (0xa020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
52 #define TSTORM_CLIENT_CONFIG_OFFSET(port, client_id) \
53 (IS_E1H_OFFSET ? (0x3350 + (port * 0x190) + (client_id * 0x10)) \
54 : (0x9c0 + (port * 0x130) + (client_id * 0x10)))
55 #define TSTORM_COMMON_SAFC_WORKAROUND_ENABLE_OFFSET \
56 (IS_E1H_OFFSET ? 0x1ad8 : 0xffffffff)
57 #define TSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \
58 (IS_E1H_OFFSET ? (0xb01a + ((function>>1) * 0x28) + \
59 ((function&1) * 0xa0) + (index * 0x4)) : (0x141a + (function * \
60 0x28) + (index * 0x4)))
61 #define TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \
62 (IS_E1H_OFFSET ? (0xb000 + ((function>>1) * 0x28) + \
63 ((function&1) * 0xa0)) : (0x1400 + (function * 0x28)))
64 #define TSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \
65 (IS_E1H_OFFSET ? (0xb008 + ((function>>1) * 0x28) + \
66 ((function&1) * 0xa0)) : (0x1408 + (function * 0x28)))
67 #define TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(function) \
68 (IS_E1H_OFFSET ? (0x2b80 + (function * 0x8)) : (0x4b68 + \
70 #define TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(function) \
71 (IS_E1H_OFFSET ? (0x3000 + (function * 0x38)) : (0x1500 + \
73 #define TSTORM_FUNCTION_MODE_OFFSET \
74 (IS_E1H_OFFSET ? 0x1ad0 : 0xffffffff)
75 #define TSTORM_HC_BTR_OFFSET(port) \
76 (IS_E1H_OFFSET ? (0xb144 + (port * 0x30)) : (0x1454 + (port * 0x18)))
77 #define TSTORM_INDIRECTION_TABLE_OFFSET(function) \
78 (IS_E1H_OFFSET ? (0x12c8 + (function * 0x80)) : (0x22c8 + \
80 #define TSTORM_INDIRECTION_TABLE_SIZE 0x80
81 #define TSTORM_MAC_FILTER_CONFIG_OFFSET(function) \
82 (IS_E1H_OFFSET ? (0x3008 + (function * 0x38)) : (0x1508 + \
84 #define TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stats_counter_id) \
85 (IS_E1H_OFFSET ? (0x2010 + (port * 0x5b0) + (stats_counter_id * \
86 0x50)) : (0x4080 + (port * 0x5b0) + (stats_counter_id * 0x50)))
87 #define TSTORM_STATS_FLAGS_OFFSET(function) \
88 (IS_E1H_OFFSET ? (0x2c00 + (function * 0x8)) : (0x4b88 + \
90 #define TSTORM_TPA_EXIST_OFFSET (IS_E1H_OFFSET ? 0x3680 : 0x1c20)
91 #define USTORM_AGG_DATA_OFFSET (IS_E1H_OFFSET ? 0xa040 : 0x2c10)
92 #define USTORM_AGG_DATA_SIZE (IS_E1H_OFFSET ? 0x2440 : 0x1200)
93 #define USTORM_ASSERT_LIST_INDEX_OFFSET \
94 (IS_E1H_OFFSET ? 0x8960 : 0x1000)
95 #define USTORM_ASSERT_LIST_OFFSET(idx) \
96 (IS_E1H_OFFSET ? (0x8980 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
97 #define USTORM_CQE_PAGE_BASE_OFFSET(port, clientId) \
98 (IS_E1H_OFFSET ? (0x8018 + (port * 0x4b0) + (clientId * 0x30)) : \
99 (0x5330 + (port * 0x260) + (clientId * 0x20)))
100 #define USTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \
101 (IS_E1H_OFFSET ? (0x9522 + ((function>>1) * 0x40) + \
102 ((function&1) * 0x100) + (index * 0x4)) : (0x1922 + (function * \
103 0x40) + (index * 0x4)))
104 #define USTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \
105 (IS_E1H_OFFSET ? (0x9500 + ((function>>1) * 0x40) + \
106 ((function&1) * 0x100)) : (0x1900 + (function * 0x40)))
107 #define USTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \
108 (IS_E1H_OFFSET ? (0x9508 + ((function>>1) * 0x40) + \
109 ((function&1) * 0x100)) : (0x1908 + (function * 0x40)))
110 #define USTORM_FUNCTION_MODE_OFFSET \
111 (IS_E1H_OFFSET ? 0x2448 : 0xffffffff)
112 #define USTORM_HC_BTR_OFFSET(port) \
113 (IS_E1H_OFFSET ? (0x9704 + (port * 0xf0)) : (0x1984 + (port * 0xc0)))
114 #define USTORM_MAX_AGG_SIZE_OFFSET(port, clientId) \
115 (IS_E1H_OFFSET ? (0x8010 + (port * 0x4b0) + (clientId * 0x30)) : \
116 (0x5328 + (port * 0x260) + (clientId * 0x20)))
117 #define USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(function) \
118 (IS_E1H_OFFSET ? (0x2408 + (function * 0x8)) : (0x5308 + \
120 #define USTORM_RX_PRODS_OFFSET(port, client_id) \
121 (IS_E1H_OFFSET ? (0x8000 + (port * 0x4b0) + (client_id * 0x30)) \
122 : (0x5318 + (port * 0x260) + (client_id * 0x20)))
123 #define USTORM_SB_HC_DISABLE_OFFSET(port, cpu_id, index) \
124 (IS_E1H_OFFSET ? (0x901a + (port * 0x280) + (cpu_id * 0x28) + \
125 (index * 0x4)) : (0x141a + (port * 0x280) + (cpu_id * 0x28) + \
127 #define USTORM_SB_HC_TIMEOUT_OFFSET(port, cpu_id, index) \
128 (IS_E1H_OFFSET ? (0x9018 + (port * 0x280) + (cpu_id * 0x28) + \
129 (index * 0x4)) : (0x1418 + (port * 0x280) + (cpu_id * 0x28) + \
131 #define USTORM_SB_HOST_SB_ADDR_OFFSET(port, cpu_id) \
132 (IS_E1H_OFFSET ? (0x9000 + (port * 0x280) + (cpu_id * 0x28)) : \
133 (0x1400 + (port * 0x280) + (cpu_id * 0x28)))
134 #define USTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, cpu_id) \
135 (IS_E1H_OFFSET ? (0x9008 + (port * 0x280) + (cpu_id * 0x28)) : \
136 (0x1408 + (port * 0x280) + (cpu_id * 0x28)))
137 #define XSTORM_ASSERT_LIST_INDEX_OFFSET \
138 (IS_E1H_OFFSET ? 0x9000 : 0x1000)
139 #define XSTORM_ASSERT_LIST_OFFSET(idx) \
140 (IS_E1H_OFFSET ? (0x9020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
141 #define XSTORM_CMNG_PER_PORT_VARS_OFFSET(port) \
142 (IS_E1H_OFFSET ? (0x24a8 + (port * 0x50)) : (0x3ba0 + (port * 0x50)))
143 #define XSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \
144 (IS_E1H_OFFSET ? (0xa01a + ((function>>1) * 0x28) + \
145 ((function&1) * 0xa0) + (index * 0x4)) : (0x141a + (function * \
146 0x28) + (index * 0x4)))
147 #define XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \
148 (IS_E1H_OFFSET ? (0xa000 + ((function>>1) * 0x28) + \
149 ((function&1) * 0xa0)) : (0x1400 + (function * 0x28)))
150 #define XSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \
151 (IS_E1H_OFFSET ? (0xa008 + ((function>>1) * 0x28) + \
152 ((function&1) * 0xa0)) : (0x1408 + (function * 0x28)))
153 #define XSTORM_E1HOV_OFFSET(function) \
154 (IS_E1H_OFFSET ? (0x2c10 + (function * 0x2)) : 0xffffffff)
155 #define XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(function) \
156 (IS_E1H_OFFSET ? (0x2418 + (function * 0x8)) : (0x3b70 + \
158 #define XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(function) \
159 (IS_E1H_OFFSET ? (0x2588 + (function * 0x90)) : (0x3c80 + \
161 #define XSTORM_FUNCTION_MODE_OFFSET \
162 (IS_E1H_OFFSET ? 0x2c20 : 0xffffffff)
163 #define XSTORM_HC_BTR_OFFSET(port) \
164 (IS_E1H_OFFSET ? (0xa144 + (port * 0x30)) : (0x1454 + (port * 0x18)))
165 #define XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stats_counter_id) \
166 (IS_E1H_OFFSET ? (0xc000 + (port * 0x3f0) + (stats_counter_id * \
167 0x38)) : (0x3378 + (port * 0x3f0) + (stats_counter_id * 0x38)))
168 #define XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(function) \
169 (IS_E1H_OFFSET ? (0x2548 + (function * 0x90)) : (0x3c40 + \
171 #define XSTORM_SPQ_PAGE_BASE_OFFSET(function) \
172 (IS_E1H_OFFSET ? (0x2000 + (function * 0x10)) : (0x3328 + \
174 #define XSTORM_SPQ_PROD_OFFSET(function) \
175 (IS_E1H_OFFSET ? (0x2008 + (function * 0x10)) : (0x3330 + \
177 #define XSTORM_STATS_FLAGS_OFFSET(function) \
178 (IS_E1H_OFFSET ? (0x23d8 + (function * 0x8)) : (0x3b60 + \
180 #define COMMON_ASM_INVALID_ASSERT_OPCODE 0x0
183 * This file defines HSI constatnts for the ETH flow
185 #ifdef _EVEREST_MICROCODE
186 #include "microcode_constants.h"
187 #include "eth_rx_bd.h"
188 #include "eth_tx_bd.h"
189 #include "eth_rx_cqe.h"
190 #include "eth_rx_sge.h"
191 #include "eth_rx_cqe_next_page.h"
195 #define DEFAULT_HASH_TYPE 0
196 #define IPV4_HASH_TYPE 1
197 #define TCP_IPV4_HASH_TYPE 2
198 #define IPV6_HASH_TYPE 3
199 #define TCP_IPV6_HASH_TYPE 4
201 /* Ethernet Ring parmaters */
202 #define X_ETH_LOCAL_RING_SIZE 13
203 #define FIRST_BD_IN_PKT 0
204 #define PARSE_BD_INDEX 1
205 #define NUM_OF_ETH_BDS_IN_PAGE \
206 ((PAGE_SIZE) / (STRUCT_SIZE(eth_tx_bd)/8))
210 #define U_ETH_LOCAL_BD_RING_SIZE (16)
211 #define U_ETH_LOCAL_SGE_RING_SIZE (12)
212 #define U_ETH_SGL_SIZE (8)
215 #define U_ETH_BDS_PER_PAGE_MASK \
216 ((PAGE_SIZE/(STRUCT_SIZE(eth_rx_bd)/8))-1)
217 #define U_ETH_CQE_PER_PAGE_MASK \
218 ((PAGE_SIZE/(STRUCT_SIZE(eth_rx_cqe)/8))-1)
219 #define U_ETH_SGES_PER_PAGE_MASK \
220 ((PAGE_SIZE/(STRUCT_SIZE(eth_rx_sge)/8))-1)
222 #define U_ETH_SGES_PER_PAGE_INVERSE_MASK \
223 (0xFFFF - ((PAGE_SIZE/((STRUCT_SIZE(eth_rx_sge))/8))-1))
226 #define TU_ETH_CQES_PER_PAGE \
227 (PAGE_SIZE/(STRUCT_SIZE(eth_rx_cqe_next_page)/8))
228 #define U_ETH_BDS_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_bd)/8))
229 #define U_ETH_SGES_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_sge)/8))
231 #define U_ETH_UNDEFINED_Q 0xFF
233 /* values of command IDs in the ramrod message */
234 #define RAMROD_CMD_ID_ETH_PORT_SETUP (80)
235 #define RAMROD_CMD_ID_ETH_CLIENT_SETUP (85)
236 #define RAMROD_CMD_ID_ETH_STAT_QUERY (90)
237 #define RAMROD_CMD_ID_ETH_UPDATE (100)
238 #define RAMROD_CMD_ID_ETH_HALT (105)
239 #define RAMROD_CMD_ID_ETH_SET_MAC (110)
240 #define RAMROD_CMD_ID_ETH_CFC_DEL (115)
241 #define RAMROD_CMD_ID_ETH_PORT_DEL (120)
242 #define RAMROD_CMD_ID_ETH_FORWARD_SETUP (125)
245 /* command values for set mac command */
246 #define T_ETH_MAC_COMMAND_SET 0
247 #define T_ETH_MAC_COMMAND_INVALIDATE 1
249 #define T_ETH_INDIRECTION_TABLE_SIZE 128
251 /*The CRC32 seed, that is used for the hash(reduction) multicast address */
252 #define T_ETH_CRC32_HASH_SEED 0x00000000
254 /* Maximal L2 clients supported */
255 #define ETH_MAX_RX_CLIENTS_E1 19
256 #define ETH_MAX_RX_CLIENTS_E1H 25
258 /* Maximal aggregation queues supported */
259 #define ETH_MAX_AGGREGATION_QUEUES_E1 (32)
260 #define ETH_MAX_AGGREGATION_QUEUES_E1H (64)
263 #define ETH_RSS_MODE_DISABLED 0
264 #define ETH_RSS_MODE_REGULAR 1
268 * This file defines HSI constatnts common to all microcode flows
271 /* Connection types */
272 #define ETH_CONNECTION_TYPE 0
273 #define TOE_CONNECTION_TYPE 1
274 #define RDMA_CONNECTION_TYPE 2
275 #define ISCSI_CONNECTION_TYPE 3
276 #define FCOE_CONNECTION_TYPE 4
277 #define RESERVED_CONNECTION_TYPE_0 5
278 #define RESERVED_CONNECTION_TYPE_1 6
279 #define RESERVED_CONNECTION_TYPE_2 7
282 #define PROTOCOL_STATE_BIT_OFFSET 6
284 #define ETH_STATE (ETH_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
285 #define TOE_STATE (TOE_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
286 #define RDMA_STATE (RDMA_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
288 /* microcode fixed page page size 4K (chains and ring segments) */
289 #define MC_PAGE_SIZE (4096)
292 /* Host coalescing constants */
295 #define HC_USTORM_DEF_SB_NUM_INDICES 8
296 #define HC_CSTORM_DEF_SB_NUM_INDICES 8
297 #define HC_XSTORM_DEF_SB_NUM_INDICES 4
298 #define HC_TSTORM_DEF_SB_NUM_INDICES 4
299 #define HC_USTORM_SB_NUM_INDICES 4
300 #define HC_CSTORM_SB_NUM_INDICES 4
302 /* index values - which counterto update */
304 #define HC_INDEX_U_TOE_RX_CQ_CONS 0
305 #define HC_INDEX_U_ETH_RX_CQ_CONS 1
306 #define HC_INDEX_U_ETH_RX_BD_CONS 2
307 #define HC_INDEX_U_FCOE_EQ_CONS 3
309 #define HC_INDEX_C_TOE_TX_CQ_CONS 0
310 #define HC_INDEX_C_ETH_TX_CQ_CONS 1
311 #define HC_INDEX_C_ISCSI_EQ_CONS 2
313 #define HC_INDEX_DEF_X_SPQ_CONS 0
315 #define HC_INDEX_DEF_C_RDMA_EQ_CONS 0
316 #define HC_INDEX_DEF_C_RDMA_NAL_PROD 1
317 #define HC_INDEX_DEF_C_ETH_FW_TX_CQ_CONS 2
318 #define HC_INDEX_DEF_C_ETH_SLOW_PATH 3
319 #define HC_INDEX_DEF_C_ETH_RDMA_CQ_CONS 4
320 #define HC_INDEX_DEF_C_ETH_ISCSI_CQ_CONS 5
322 #define HC_INDEX_DEF_U_ETH_RDMA_RX_CQ_CONS 0
323 #define HC_INDEX_DEF_U_ETH_ISCSI_RX_CQ_CONS 1
324 #define HC_INDEX_DEF_U_ETH_RDMA_RX_BD_CONS 2
325 #define HC_INDEX_DEF_U_ETH_ISCSI_RX_BD_CONS 3
328 /* used by the driver to get the SB offset */
333 #define ATTENTION_ID 4
335 /* max number of slow path commands per port */
336 #define MAX_RAMRODS_PER_PORT (8)
338 /* values for RX ETH CQE type field */
339 #define RX_ETH_CQE_TYPE_ETH_FASTPATH (0)
340 #define RX_ETH_CQE_TYPE_ETH_RAMROD (1)
343 /**** DEFINES FOR TIMERS/CLOCKS RESOLUTIONS ****/
344 #define EMULATION_FREQUENCY_FACTOR (1600)
345 #define FPGA_FREQUENCY_FACTOR (100)
347 #define TIMERS_TICK_SIZE_CHIP (1e-3)
348 #define TIMERS_TICK_SIZE_EMUL \
349 ((TIMERS_TICK_SIZE_CHIP)/((EMULATION_FREQUENCY_FACTOR)))
350 #define TIMERS_TICK_SIZE_FPGA \
351 ((TIMERS_TICK_SIZE_CHIP)/((FPGA_FREQUENCY_FACTOR)))
353 #define TSEMI_CLK1_RESUL_CHIP (1e-3)
354 #define TSEMI_CLK1_RESUL_EMUL \
355 ((TSEMI_CLK1_RESUL_CHIP)/(EMULATION_FREQUENCY_FACTOR))
356 #define TSEMI_CLK1_RESUL_FPGA \
357 ((TSEMI_CLK1_RESUL_CHIP)/(FPGA_FREQUENCY_FACTOR))
359 #define USEMI_CLK1_RESUL_CHIP \
360 (TIMERS_TICK_SIZE_CHIP)
361 #define USEMI_CLK1_RESUL_EMUL \
362 (TIMERS_TICK_SIZE_EMUL)
363 #define USEMI_CLK1_RESUL_FPGA \
364 (TIMERS_TICK_SIZE_FPGA)
366 #define XSEMI_CLK1_RESUL_CHIP (1e-3)
367 #define XSEMI_CLK1_RESUL_EMUL \
368 ((XSEMI_CLK1_RESUL_CHIP)/(EMULATION_FREQUENCY_FACTOR))
369 #define XSEMI_CLK1_RESUL_FPGA \
370 ((XSEMI_CLK1_RESUL_CHIP)/(FPGA_FREQUENCY_FACTOR))
372 #define XSEMI_CLK2_RESUL_CHIP (1e-6)
373 #define XSEMI_CLK2_RESUL_EMUL \
374 ((XSEMI_CLK2_RESUL_CHIP)/(EMULATION_FREQUENCY_FACTOR))
375 #define XSEMI_CLK2_RESUL_FPGA \
376 ((XSEMI_CLK2_RESUL_CHIP)/(FPGA_FREQUENCY_FACTOR))
378 #define SDM_TIMER_TICK_RESUL_CHIP (4*(1e-6))
379 #define SDM_TIMER_TICK_RESUL_EMUL \
380 ((SDM_TIMER_TICK_RESUL_CHIP)/(EMULATION_FREQUENCY_FACTOR))
381 #define SDM_TIMER_TICK_RESUL_FPGA \
382 ((SDM_TIMER_TICK_RESUL_CHIP)/(FPGA_FREQUENCY_FACTOR))
385 /**** END DEFINES FOR TIMERS/CLOCKS RESOLUTIONS ****/
386 #define XSTORM_IP_ID_ROLL_HALF 0x8000
387 #define XSTORM_IP_ID_ROLL_ALL 0
389 #define FW_LOG_LIST_SIZE (50)
391 #define NUM_OF_PROTOCOLS 4
392 #define NUM_OF_SAFC_BITS 16
393 #define MAX_COS_NUMBER 4
394 #define MAX_T_STAT_COUNTER_ID 18
395 #define MAX_X_STAT_COUNTER_ID 18
396 #define MAX_U_STAT_COUNTER_ID 18
399 #define UNKNOWN_ADDRESS 0
400 #define UNICAST_ADDRESS 1
401 #define MULTICAST_ADDRESS 2
402 #define BROADCAST_ADDRESS 3
404 #define SINGLE_FUNCTION 0
405 #define MULTI_FUNCTION 1