2 * Frame buffer driver for Trident TGUI, Blade and Image series
4 * Copyright 2001, 2002 - Jani Monoses <jani@iv.ro>
7 * CREDITS:(in order of appearance)
8 * skeletonfb.c by Geert Uytterhoeven and other fb code in drivers/video
9 * Special thanks ;) to Mattia Crivellini <tia@mclink.it>
10 * much inspired by the XFree86 4.x Trident driver sources
11 * by Alan Hourihane the FreeVGA project
12 * Francesco Salvestrini <salvestrini@users.sf.net> XP support,
15 * timing value tweaking so it looks good on every monitor in every mode
18 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/pci.h>
23 #include <linux/delay.h>
24 #include <video/vga.h>
25 #include <video/trident.h>
27 struct tridentfb_par {
28 void __iomem *io_virt; /* iospace virtual memory address */
32 void (*init_accel) (struct tridentfb_par *, int, int);
33 void (*wait_engine) (struct tridentfb_par *);
35 (struct tridentfb_par *par, u32, u32, u32, u32, u32, u32);
37 (struct tridentfb_par *par, u32, u32, u32, u32, u32, u32);
39 (struct tridentfb_par *par, const char*,
40 u32, u32, u32, u32, u32, u32);
41 unsigned char eng_oper; /* engine operation... */
44 static struct fb_fix_screeninfo tridentfb_fix = {
46 .type = FB_TYPE_PACKED_PIXELS,
48 .visual = FB_VISUAL_PSEUDOCOLOR,
49 .accel = FB_ACCEL_NONE,
52 /* defaults which are normally overriden by user values */
55 static char *mode_option __devinitdata = "640x480-8@60";
56 static int bpp __devinitdata = 8;
58 static int noaccel __devinitdata;
63 static int fp __devinitdata;
64 static int crt __devinitdata;
66 static int memsize __devinitdata;
67 static int memdiff __devinitdata;
70 module_param(mode_option, charp, 0);
71 MODULE_PARM_DESC(mode_option, "Initial video mode e.g. '648x480-8@60'");
72 module_param_named(mode, mode_option, charp, 0);
73 MODULE_PARM_DESC(mode, "Initial video mode e.g. '648x480-8@60' (deprecated)");
74 module_param(bpp, int, 0);
75 module_param(center, int, 0);
76 module_param(stretch, int, 0);
77 module_param(noaccel, int, 0);
78 module_param(memsize, int, 0);
79 module_param(memdiff, int, 0);
80 module_param(nativex, int, 0);
81 module_param(fp, int, 0);
82 MODULE_PARM_DESC(fp, "Define if flatpanel is connected");
83 module_param(crt, int, 0);
84 MODULE_PARM_DESC(crt, "Define if CRT is connected");
86 static inline int is_oldclock(int id)
88 return (id == TGUI9440) ||
93 static inline int is_oldprotect(int id)
95 return is_oldclock(id) ||
96 (id == PROVIDIA9685) ||
101 static inline int is_blade(int id)
103 return (id == BLADE3D) ||
104 (id == CYBERBLADEE4) ||
105 (id == CYBERBLADEi7) ||
106 (id == CYBERBLADEi7D) ||
107 (id == CYBERBLADEi1) ||
108 (id == CYBERBLADEi1D) ||
109 (id == CYBERBLADEAi1) ||
110 (id == CYBERBLADEAi1D);
113 static inline int is_xp(int id)
115 return (id == CYBERBLADEXPAi1) ||
116 (id == CYBERBLADEXPm8) ||
117 (id == CYBERBLADEXPm16);
120 static inline int is3Dchip(int id)
122 return is_blade(id) || is_xp(id) ||
123 (id == CYBER9397) || (id == CYBER9397DVD) ||
124 (id == CYBER9520) || (id == CYBER9525DVD) ||
125 (id == IMAGE975) || (id == IMAGE985);
128 static inline int iscyber(int id)
144 case CYBERBLADEXPAi1:
148 case CYBERBLADEi7: /* VIA MPV4 integrated version */
150 /* case CYBERBLDAEXPm8: Strange */
151 /* case CYBERBLDAEXPm16: Strange */
156 static inline void t_outb(struct tridentfb_par *p, u8 val, u16 reg)
158 fb_writeb(val, p->io_virt + reg);
161 static inline u8 t_inb(struct tridentfb_par *p, u16 reg)
163 return fb_readb(p->io_virt + reg);
166 static inline void writemmr(struct tridentfb_par *par, u16 r, u32 v)
168 fb_writel(v, par->io_virt + r);
171 static inline u32 readmmr(struct tridentfb_par *par, u16 r)
173 return fb_readl(par->io_virt + r);
177 * Blade specific acceleration.
180 #define point(x, y) ((y) << 16 | (x))
182 static void blade_init_accel(struct tridentfb_par *par, int pitch, int bpp)
184 int v1 = (pitch >> 3) << 20;
185 int tmp = bpp == 24 ? 2 : (bpp >> 4);
186 int v2 = v1 | (tmp << 29);
188 writemmr(par, 0x21C0, v2);
189 writemmr(par, 0x21C4, v2);
190 writemmr(par, 0x21B8, v2);
191 writemmr(par, 0x21BC, v2);
192 writemmr(par, 0x21D0, v1);
193 writemmr(par, 0x21D4, v1);
194 writemmr(par, 0x21C8, v1);
195 writemmr(par, 0x21CC, v1);
196 writemmr(par, 0x216C, 0);
199 static void blade_wait_engine(struct tridentfb_par *par)
201 while (readmmr(par, STATUS) & 0xFA800000)
205 static void blade_fill_rect(struct tridentfb_par *par,
206 u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
208 writemmr(par, COLOR, c);
209 writemmr(par, ROP, rop ? ROP_X : ROP_S);
210 writemmr(par, CMD, 0x20000000 | 1 << 19 | 1 << 4 | 2 << 2);
212 writemmr(par, DST1, point(x, y));
213 writemmr(par, DST2, point(x + w - 1, y + h - 1));
216 static void blade_image_blit(struct tridentfb_par *par, const char *data,
217 u32 x, u32 y, u32 w, u32 h, u32 c, u32 b)
219 unsigned size = ((w + 31) >> 5) * h;
221 writemmr(par, COLOR, c);
222 writemmr(par, BGCOLOR, b);
223 writemmr(par, CMD, 0xa0000000 | 3 << 19);
225 writemmr(par, DST1, point(x, y));
226 writemmr(par, DST2, point(x + w - 1, y + h - 1));
228 memcpy(par->io_virt + 0x10000, data, 4 * size);
231 static void blade_copy_rect(struct tridentfb_par *par,
232 u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
235 u32 s1 = point(x1, y1);
236 u32 s2 = point(x1 + w - 1, y1 + h - 1);
237 u32 d1 = point(x2, y2);
238 u32 d2 = point(x2 + w - 1, y2 + h - 1);
240 if ((y1 > y2) || ((y1 == y2) && (x1 > x2)))
243 writemmr(par, ROP, ROP_S);
244 writemmr(par, CMD, 0xE0000000 | 1 << 19 | 1 << 4 | 1 << 2 | direction);
246 writemmr(par, SRC1, direction ? s2 : s1);
247 writemmr(par, SRC2, direction ? s1 : s2);
248 writemmr(par, DST1, direction ? d2 : d1);
249 writemmr(par, DST2, direction ? d1 : d2);
253 * BladeXP specific acceleration functions
256 static void xp_init_accel(struct tridentfb_par *par, int pitch, int bpp)
258 unsigned char x = bpp == 24 ? 3 : (bpp >> 4);
259 int v1 = pitch << (bpp == 24 ? 20 : (18 + x));
261 switch (pitch << (bpp >> 3)) {
277 t_outb(par, x, 0x2125);
279 par->eng_oper = x | 0x40;
281 writemmr(par, 0x2154, v1);
282 writemmr(par, 0x2150, v1);
283 t_outb(par, 3, 0x2126);
286 static void xp_wait_engine(struct tridentfb_par *par)
291 while (t_inb(par, STATUS) & 0x80) {
293 if (count == 10000000) {
299 t_outb(par, 0x00, STATUS);
307 static void xp_fill_rect(struct tridentfb_par *par,
308 u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
310 writemmr(par, 0x2127, ROP_P);
311 writemmr(par, 0x2158, c);
312 writemmr(par, DRAWFL, 0x4000);
313 writemmr(par, OLDDIM, point(h, w));
314 writemmr(par, OLDDST, point(y, x));
315 t_outb(par, 0x01, OLDCMD);
316 t_outb(par, par->eng_oper, 0x2125);
319 static void xp_copy_rect(struct tridentfb_par *par,
320 u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
322 u32 x1_tmp, x2_tmp, y1_tmp, y2_tmp;
323 int direction = 0x0004;
325 if ((x1 < x2) && (y1 == y2)) {
343 writemmr(par, DRAWFL, direction);
344 t_outb(par, ROP_S, 0x2127);
345 writemmr(par, OLDSRC, point(y1_tmp, x1_tmp));
346 writemmr(par, OLDDST, point(y2_tmp, x2_tmp));
347 writemmr(par, OLDDIM, point(h, w));
348 t_outb(par, 0x01, OLDCMD);
352 * Image specific acceleration functions
354 static void image_init_accel(struct tridentfb_par *par, int pitch, int bpp)
356 int tmp = bpp == 24 ? 2: (bpp >> 4);
358 writemmr(par, 0x2120, 0xF0000000);
359 writemmr(par, 0x2120, 0x40000000 | tmp);
360 writemmr(par, 0x2120, 0x80000000);
361 writemmr(par, 0x2144, 0x00000000);
362 writemmr(par, 0x2148, 0x00000000);
363 writemmr(par, 0x2150, 0x00000000);
364 writemmr(par, 0x2154, 0x00000000);
365 writemmr(par, 0x2120, 0x60000000 | (pitch << 16) | pitch);
366 writemmr(par, 0x216C, 0x00000000);
367 writemmr(par, 0x2170, 0x00000000);
368 writemmr(par, 0x217C, 0x00000000);
369 writemmr(par, 0x2120, 0x10000000);
370 writemmr(par, 0x2130, (2047 << 16) | 2047);
373 static void image_wait_engine(struct tridentfb_par *par)
375 while (readmmr(par, 0x2164) & 0xF0000000)
379 static void image_fill_rect(struct tridentfb_par *par,
380 u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
382 writemmr(par, 0x2120, 0x80000000);
383 writemmr(par, 0x2120, 0x90000000 | ROP_S);
385 writemmr(par, 0x2144, c);
387 writemmr(par, DST1, point(x, y));
388 writemmr(par, DST2, point(x + w - 1, y + h - 1));
390 writemmr(par, 0x2124, 0x80000000 | 3 << 22 | 1 << 10 | 1 << 9);
393 static void image_copy_rect(struct tridentfb_par *par,
394 u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
397 u32 s1 = point(x1, y1);
398 u32 s2 = point(x1 + w - 1, y1 + h - 1);
399 u32 d1 = point(x2, y2);
400 u32 d2 = point(x2 + w - 1, y2 + h - 1);
402 if ((y1 > y2) || ((y1 == y2) && (x1 > x2)))
405 writemmr(par, 0x2120, 0x80000000);
406 writemmr(par, 0x2120, 0x90000000 | ROP_S);
408 writemmr(par, SRC1, direction ? s2 : s1);
409 writemmr(par, SRC2, direction ? s1 : s2);
410 writemmr(par, DST1, direction ? d2 : d1);
411 writemmr(par, DST2, direction ? d1 : d2);
412 writemmr(par, 0x2124,
413 0x80000000 | 1 << 22 | 1 << 10 | 1 << 7 | direction);
417 * TGUI 9440/96XX acceleration
420 static void tgui_init_accel(struct tridentfb_par *par, int pitch, int bpp)
422 unsigned char x = bpp == 24 ? 3 : (bpp >> 4);
424 /* disable clipping */
425 writemmr(par, 0x2148, 0);
426 writemmr(par, 0x214C, point(4095, 2047));
428 switch ((pitch * bpp) / 8) {
444 fb_writew(x, par->io_virt + 0x2122);
447 static void tgui_fill_rect(struct tridentfb_par *par,
448 u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
450 t_outb(par, ROP_P, 0x2127);
451 writemmr(par, OLDCLR, c);
452 writemmr(par, DRAWFL, 0x4020);
453 writemmr(par, OLDDIM, point(w - 1, h - 1));
454 writemmr(par, OLDDST, point(x, y));
455 t_outb(par, 1, OLDCMD);
458 static void tgui_copy_rect(struct tridentfb_par *par,
459 u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
462 u16 x1_tmp, x2_tmp, y1_tmp, y2_tmp;
464 if ((x1 < x2) && (y1 == y2)) {
482 writemmr(par, DRAWFL, 0x4 | flags);
483 t_outb(par, ROP_S, 0x2127);
484 writemmr(par, OLDSRC, point(x1_tmp, y1_tmp));
485 writemmr(par, OLDDST, point(x2_tmp, y2_tmp));
486 writemmr(par, OLDDIM, point(w - 1, h - 1));
487 t_outb(par, 1, OLDCMD);
491 * Accel functions called by the upper layers
493 #ifdef CONFIG_FB_TRIDENT_ACCEL
494 static void tridentfb_fillrect(struct fb_info *info,
495 const struct fb_fillrect *fr)
497 struct tridentfb_par *par = info->par;
500 if (info->flags & FBINFO_HWACCEL_DISABLED) {
501 cfb_fillrect(info, fr);
504 if (info->var.bits_per_pixel == 8) {
509 col = ((u32 *)(info->pseudo_palette))[fr->color];
511 par->wait_engine(par);
512 par->fill_rect(par, fr->dx, fr->dy, fr->width,
513 fr->height, col, fr->rop);
516 static void tridentfb_imageblit(struct fb_info *info,
517 const struct fb_image *img)
519 struct tridentfb_par *par = info->par;
522 if ((info->flags & FBINFO_HWACCEL_DISABLED) || img->depth != 1) {
523 cfb_imageblit(info, img);
526 if (info->var.bits_per_pixel == 8) {
530 bgcol = img->bg_color;
532 bgcol |= bgcol << 16;
534 col = ((u32 *)(info->pseudo_palette))[img->fg_color];
535 bgcol = ((u32 *)(info->pseudo_palette))[img->bg_color];
538 par->wait_engine(par);
540 par->image_blit(par, img->data, img->dx, img->dy,
541 img->width, img->height, col, bgcol);
543 cfb_imageblit(info, img);
546 static void tridentfb_copyarea(struct fb_info *info,
547 const struct fb_copyarea *ca)
549 struct tridentfb_par *par = info->par;
551 if (info->flags & FBINFO_HWACCEL_DISABLED) {
552 cfb_copyarea(info, ca);
555 par->wait_engine(par);
556 par->copy_rect(par, ca->sx, ca->sy, ca->dx, ca->dy,
557 ca->width, ca->height);
560 static int tridentfb_sync(struct fb_info *info)
562 struct tridentfb_par *par = info->par;
564 if (!(info->flags & FBINFO_HWACCEL_DISABLED))
565 par->wait_engine(par);
569 #define tridentfb_fillrect cfb_fillrect
570 #define tridentfb_copyarea cfb_copyarea
571 #define tridentfb_imageblit cfb_imageblit
572 #endif /* CONFIG_FB_TRIDENT_ACCEL */
575 * Hardware access functions
578 static inline unsigned char read3X4(struct tridentfb_par *par, int reg)
580 return vga_mm_rcrt(par->io_virt, reg);
583 static inline void write3X4(struct tridentfb_par *par, int reg,
586 vga_mm_wcrt(par->io_virt, reg, val);
589 static inline unsigned char read3CE(struct tridentfb_par *par,
592 return vga_mm_rgfx(par->io_virt, reg);
595 static inline void writeAttr(struct tridentfb_par *par, int reg,
598 fb_readb(par->io_virt + VGA_IS1_RC); /* flip-flop to index */
599 vga_mm_wattr(par->io_virt, reg, val);
602 static inline void write3CE(struct tridentfb_par *par, int reg,
605 vga_mm_wgfx(par->io_virt, reg, val);
608 static void enable_mmio(struct tridentfb_par *par)
613 /* Unprotect registers */
614 vga_io_wseq(NewMode1, 0x80);
615 if (!is_oldprotect(par->chip_id))
616 vga_io_wseq(Protection, 0x92);
620 outb(inb(0x3D5) | 0x01, 0x3D5);
623 static void disable_mmio(struct tridentfb_par *par)
626 vga_mm_rseq(par->io_virt, 0x0B);
628 /* Unprotect registers */
629 vga_mm_wseq(par->io_virt, NewMode1, 0x80);
630 if (!is_oldprotect(par->chip_id))
631 vga_mm_wseq(par->io_virt, Protection, 0x92);
634 t_outb(par, PCIReg, 0x3D4);
635 t_outb(par, t_inb(par, 0x3D5) & ~0x01, 0x3D5);
638 static inline void crtc_unlock(struct tridentfb_par *par)
640 write3X4(par, VGA_CRTC_V_SYNC_END,
641 read3X4(par, VGA_CRTC_V_SYNC_END) & 0x7F);
644 /* Return flat panel's maximum x resolution */
645 static int __devinit get_nativex(struct tridentfb_par *par)
652 tmp = (read3CE(par, VertStretch) >> 4) & 3;
673 output("%dx%d flat panel found\n", x, y);
678 static inline void set_lwidth(struct tridentfb_par *par, int width)
680 write3X4(par, VGA_CRTC_OFFSET, width & 0xFF);
681 write3X4(par, AddColReg,
682 (read3X4(par, AddColReg) & 0xCF) | ((width & 0x300) >> 4));
685 /* For resolutions smaller than FP resolution stretch */
686 static void screen_stretch(struct tridentfb_par *par)
688 if (par->chip_id != CYBERBLADEXPAi1)
689 write3CE(par, BiosReg, 0);
691 write3CE(par, BiosReg, 8);
692 write3CE(par, VertStretch, (read3CE(par, VertStretch) & 0x7C) | 1);
693 write3CE(par, HorStretch, (read3CE(par, HorStretch) & 0x7C) | 1);
696 /* For resolutions smaller than FP resolution center */
697 static inline void screen_center(struct tridentfb_par *par)
699 write3CE(par, VertStretch, (read3CE(par, VertStretch) & 0x7C) | 0x80);
700 write3CE(par, HorStretch, (read3CE(par, HorStretch) & 0x7C) | 0x80);
703 /* Address of first shown pixel in display memory */
704 static void set_screen_start(struct tridentfb_par *par, int base)
707 write3X4(par, VGA_CRTC_START_LO, base & 0xFF);
708 write3X4(par, VGA_CRTC_START_HI, (base & 0xFF00) >> 8);
709 tmp = read3X4(par, CRTCModuleTest) & 0xDF;
710 write3X4(par, CRTCModuleTest, tmp | ((base & 0x10000) >> 11));
711 tmp = read3X4(par, CRTHiOrd) & 0xF8;
712 write3X4(par, CRTHiOrd, tmp | ((base & 0xE0000) >> 17));
715 /* Set dotclock frequency */
716 static void set_vclk(struct tridentfb_par *par, unsigned long freq)
719 unsigned long fi, d, di;
720 unsigned char best_m = 0, best_n = 0, best_k = 0;
721 unsigned char hi, lo;
722 unsigned char shift = !is_oldclock(par->chip_id) ? 2 : 1;
725 for (k = shift; k >= 0; k--)
726 for (m = 1; m < 32; m++) {
727 n = ((m + 2) << shift) - 8;
728 for (n = (n < 0 ? 0 : n); n < 122; n++) {
729 fi = ((14318l * (n + 8)) / (m + 2)) >> k;
731 if (di < d || (di == d && k == best_k)) {
742 if (is_oldclock(par->chip_id)) {
743 lo = best_n | (best_m << 7);
744 hi = (best_m >> 1) | (best_k << 4);
747 hi = best_m | (best_k << 6);
750 if (is3Dchip(par->chip_id)) {
751 vga_mm_wseq(par->io_virt, ClockHigh, hi);
752 vga_mm_wseq(par->io_virt, ClockLow, lo);
754 t_outb(par, lo, 0x43C8);
755 t_outb(par, hi, 0x43C9);
757 debug("VCLK = %X %X\n", hi, lo);
760 /* Set number of lines for flat panels*/
761 static void set_number_of_lines(struct tridentfb_par *par, int lines)
763 int tmp = read3CE(par, CyberEnhance) & 0x8F;
766 else if (lines > 768)
768 else if (lines > 600)
770 else if (lines > 480)
772 write3CE(par, CyberEnhance, tmp);
776 * If we see that FP is active we assume we have one.
777 * Otherwise we have a CRT display. User can override.
779 static int __devinit is_flatpanel(struct tridentfb_par *par)
783 if (crt || !iscyber(par->chip_id))
785 return (read3CE(par, FPConfig) & 0x10) ? 1 : 0;
788 /* Try detecting the video memory size */
789 static unsigned int __devinit get_memsize(struct tridentfb_par *par)
791 unsigned char tmp, tmp2;
794 /* If memory size provided by user */
798 switch (par->chip_id) {
803 tmp = read3X4(par, SPR) & 0x0F;
819 k = 10 * Mb; /* XP */
825 k = 12 * Mb; /* XP */
828 k = 14 * Mb; /* XP */
831 k = 16 * Mb; /* XP */
835 tmp2 = vga_mm_rseq(par->io_virt, 0xC1);
865 output("framebuffer size = %d Kb\n", k / Kb);
869 /* See if we can handle the video mode described in var */
870 static int tridentfb_check_var(struct fb_var_screeninfo *var,
871 struct fb_info *info)
873 struct tridentfb_par *par = info->par;
874 int bpp = var->bits_per_pixel;
876 int ramdac = 230000; /* 230MHz for most 3D chips */
879 /* check color depth */
881 bpp = var->bits_per_pixel = 32;
882 if (bpp != 8 && bpp != 16 && bpp != 32)
884 if (par->chip_id == TGUI9440 && bpp == 32)
886 /* check whether resolution fits on panel and in memory */
887 if (par->flatpanel && nativex && var->xres > nativex)
889 /* various resolution checks */
890 var->xres = (var->xres + 7) & ~0x7;
891 if (var->xres > var->xres_virtual)
892 var->xres_virtual = var->xres;
893 if (var->yres > var->yres_virtual)
894 var->yres_virtual = var->yres;
895 if (var->xres_virtual > 4095 || var->yres > 2048)
897 /* prevent from position overflow for acceleration */
898 if (var->yres_virtual > 0xffff)
900 line_length = var->xres_virtual * bpp / 8;
902 if (!is3Dchip(par->chip_id) &&
903 !(info->flags & FBINFO_HWACCEL_DISABLED)) {
904 /* acceleration requires line length to be power of 2 */
905 if (line_length <= 512)
906 var->xres_virtual = 512 * 8 / bpp;
907 else if (line_length <= 1024)
908 var->xres_virtual = 1024 * 8 / bpp;
909 else if (line_length <= 2048)
910 var->xres_virtual = 2048 * 8 / bpp;
911 else if (line_length <= 4096)
912 var->xres_virtual = 4096 * 8 / bpp;
913 else if (line_length <= 8192)
914 var->xres_virtual = 8192 * 8 / bpp;
918 line_length = var->xres_virtual * bpp / 8;
921 /* datasheet specifies how to set panning only up to 4 MB */
922 if (line_length * (var->yres_virtual - var->yres) > (4 << 20))
923 var->yres_virtual = ((4 << 20) / line_length) + var->yres;
925 if (line_length * var->yres_virtual > info->fix.smem_len)
932 var->green = var->red;
933 var->blue = var->red;
936 var->red.offset = 11;
937 var->green.offset = 5;
938 var->blue.offset = 0;
940 var->green.length = 6;
941 var->blue.length = 5;
944 var->red.offset = 16;
945 var->green.offset = 8;
946 var->blue.offset = 0;
948 var->green.length = 8;
949 var->blue.length = 8;
955 if (is_xp(par->chip_id))
958 switch (par->chip_id) {
960 ramdac = (bpp >= 16) ? 45000 : 90000;
974 /* The clock is doubled for 32 bpp */
978 if (PICOS2KHZ(var->pixclock) > ramdac)
987 /* Pan the display */
988 static int tridentfb_pan_display(struct fb_var_screeninfo *var,
989 struct fb_info *info)
991 struct tridentfb_par *par = info->par;
995 offset = (var->xoffset + (var->yoffset * var->xres_virtual))
996 * var->bits_per_pixel / 32;
997 set_screen_start(par, offset);
1002 static inline void shadowmode_on(struct tridentfb_par *par)
1004 write3CE(par, CyberControl, read3CE(par, CyberControl) | 0x81);
1007 static inline void shadowmode_off(struct tridentfb_par *par)
1009 write3CE(par, CyberControl, read3CE(par, CyberControl) & 0x7E);
1012 /* Set the hardware to the requested video mode */
1013 static int tridentfb_set_par(struct fb_info *info)
1015 struct tridentfb_par *par = info->par;
1016 u32 htotal, hdispend, hsyncstart, hsyncend, hblankstart, hblankend;
1017 u32 vtotal, vdispend, vsyncstart, vsyncend, vblankstart, vblankend;
1018 struct fb_var_screeninfo *var = &info->var;
1019 int bpp = var->bits_per_pixel;
1024 hdispend = var->xres / 8 - 1;
1025 hsyncstart = (var->xres + var->right_margin) / 8;
1026 hsyncend = (var->xres + var->right_margin + var->hsync_len) / 8;
1027 htotal = (var->xres + var->left_margin + var->right_margin +
1028 var->hsync_len) / 8 - 5;
1029 hblankstart = hdispend + 1;
1030 hblankend = htotal + 3;
1032 vdispend = var->yres - 1;
1033 vsyncstart = var->yres + var->lower_margin;
1034 vsyncend = vsyncstart + var->vsync_len;
1035 vtotal = var->upper_margin + vsyncend - 2;
1036 vblankstart = vdispend + 1;
1039 if (info->var.vmode & FB_VMODE_INTERLACED) {
1050 write3CE(par, CyberControl, 8);
1052 if (var->sync & FB_SYNC_HOR_HIGH_ACT)
1054 if (var->sync & FB_SYNC_VERT_HIGH_ACT)
1057 if (par->flatpanel && var->xres < nativex) {
1059 * on flat panels with native size larger
1060 * than requested resolution decide whether
1061 * we stretch or center
1063 t_outb(par, tmp | 0xC0, VGA_MIS_W);
1070 screen_stretch(par);
1073 t_outb(par, tmp, VGA_MIS_W);
1074 write3CE(par, CyberControl, 8);
1077 /* vertical timing values */
1078 write3X4(par, VGA_CRTC_V_TOTAL, vtotal & 0xFF);
1079 write3X4(par, VGA_CRTC_V_DISP_END, vdispend & 0xFF);
1080 write3X4(par, VGA_CRTC_V_SYNC_START, vsyncstart & 0xFF);
1081 write3X4(par, VGA_CRTC_V_SYNC_END, (vsyncend & 0x0F));
1082 write3X4(par, VGA_CRTC_V_BLANK_START, vblankstart & 0xFF);
1083 write3X4(par, VGA_CRTC_V_BLANK_END, vblankend & 0xFF);
1085 /* horizontal timing values */
1086 write3X4(par, VGA_CRTC_H_TOTAL, htotal & 0xFF);
1087 write3X4(par, VGA_CRTC_H_DISP, hdispend & 0xFF);
1088 write3X4(par, VGA_CRTC_H_SYNC_START, hsyncstart & 0xFF);
1089 write3X4(par, VGA_CRTC_H_SYNC_END,
1090 (hsyncend & 0x1F) | ((hblankend & 0x20) << 2));
1091 write3X4(par, VGA_CRTC_H_BLANK_START, hblankstart & 0xFF);
1092 write3X4(par, VGA_CRTC_H_BLANK_END, hblankend & 0x1F);
1094 /* higher bits of vertical timing values */
1096 if (vtotal & 0x100) tmp |= 0x01;
1097 if (vdispend & 0x100) tmp |= 0x02;
1098 if (vsyncstart & 0x100) tmp |= 0x04;
1099 if (vblankstart & 0x100) tmp |= 0x08;
1101 if (vtotal & 0x200) tmp |= 0x20;
1102 if (vdispend & 0x200) tmp |= 0x40;
1103 if (vsyncstart & 0x200) tmp |= 0x80;
1104 write3X4(par, VGA_CRTC_OVERFLOW, tmp);
1106 tmp = read3X4(par, CRTHiOrd) & 0x07;
1107 tmp |= 0x08; /* line compare bit 10 */
1108 if (vtotal & 0x400) tmp |= 0x80;
1109 if (vblankstart & 0x400) tmp |= 0x40;
1110 if (vsyncstart & 0x400) tmp |= 0x20;
1111 if (vdispend & 0x400) tmp |= 0x10;
1112 write3X4(par, CRTHiOrd, tmp);
1114 tmp = (htotal >> 8) & 0x01;
1115 tmp |= (hdispend >> 7) & 0x02;
1116 tmp |= (hsyncstart >> 5) & 0x08;
1117 tmp |= (hblankstart >> 4) & 0x10;
1118 write3X4(par, HorizOverflow, tmp);
1121 if (vblankstart & 0x200) tmp |= 0x20;
1122 //FIXME if (info->var.vmode & FB_VMODE_DOUBLE) tmp |= 0x80; /* double scan for 200 line modes */
1123 write3X4(par, VGA_CRTC_MAX_SCAN, tmp);
1125 write3X4(par, VGA_CRTC_LINE_COMPARE, 0xFF);
1126 write3X4(par, VGA_CRTC_PRESET_ROW, 0);
1127 write3X4(par, VGA_CRTC_MODE, 0xC3);
1129 write3X4(par, LinearAddReg, 0x20); /* enable linear addressing */
1131 tmp = (info->var.vmode & FB_VMODE_INTERLACED) ? 0x84 : 0x80;
1132 /* enable access extended memory */
1133 write3X4(par, CRTCModuleTest, tmp);
1134 tmp = read3CE(par, MiscIntContReg) & ~0x4;
1135 if (info->var.vmode & FB_VMODE_INTERLACED)
1137 write3CE(par, MiscIntContReg, tmp);
1139 /* enable GE for text acceleration */
1140 write3X4(par, GraphEngReg, 0x80);
1157 write3X4(par, PixelBusReg, tmp);
1159 tmp = read3X4(par, DRAMControl);
1160 if (!is_oldprotect(par->chip_id))
1162 if (iscyber(par->chip_id))
1164 write3X4(par, DRAMControl, tmp); /* both IO, linear enable */
1166 write3X4(par, InterfaceSel, read3X4(par, InterfaceSel) | 0x40);
1167 if (!is_xp(par->chip_id))
1168 write3X4(par, Performance, read3X4(par, Performance) | 0x10);
1169 /* MMIO & PCI read and write burst enable */
1170 if (par->chip_id != TGUI9440 && par->chip_id != IMAGE975)
1171 write3X4(par, PCIReg, read3X4(par, PCIReg) | 0x06);
1173 vga_mm_wseq(par->io_virt, 0, 3);
1174 vga_mm_wseq(par->io_virt, 1, 1); /* set char clock 8 dots wide */
1175 /* enable 4 maps because needed in chain4 mode */
1176 vga_mm_wseq(par->io_virt, 2, 0x0F);
1177 vga_mm_wseq(par->io_virt, 3, 0);
1178 vga_mm_wseq(par->io_virt, 4, 0x0E); /* memory mode enable bitmaps ?? */
1180 /* convert from picoseconds to kHz */
1181 vclk = PICOS2KHZ(info->var.pixclock);
1183 /* divide clock by 2 if 32bpp chain4 mode display and CPU path */
1184 tmp = read3CE(par, MiscExtFunc) & 0xF0;
1185 if (bpp == 32 || (par->chip_id == TGUI9440 && bpp == 16)) {
1189 set_vclk(par, vclk);
1190 write3CE(par, MiscExtFunc, tmp | 0x12);
1191 write3CE(par, 0x5, 0x40); /* no CGA compat, allow 256 col */
1192 write3CE(par, 0x6, 0x05); /* graphics mode */
1193 write3CE(par, 0x7, 0x0F); /* planes? */
1195 /* graphics mode and support 256 color modes */
1196 writeAttr(par, 0x10, 0x41);
1197 writeAttr(par, 0x12, 0x0F); /* planes */
1198 writeAttr(par, 0x13, 0); /* horizontal pel panning */
1201 for (tmp = 0; tmp < 0x10; tmp++)
1202 writeAttr(par, tmp, tmp);
1203 fb_readb(par->io_virt + VGA_IS1_RC); /* flip-flop to index */
1204 t_outb(par, 0x20, VGA_ATT_W); /* enable attr */
1219 t_inb(par, VGA_PEL_IW);
1220 t_inb(par, VGA_PEL_MSK);
1221 t_inb(par, VGA_PEL_MSK);
1222 t_inb(par, VGA_PEL_MSK);
1223 t_inb(par, VGA_PEL_MSK);
1224 t_outb(par, tmp, VGA_PEL_MSK);
1225 t_inb(par, VGA_PEL_IW);
1228 set_number_of_lines(par, info->var.yres);
1229 info->fix.line_length = info->var.xres_virtual * bpp / 8;
1230 set_lwidth(par, info->fix.line_length / 8);
1232 if (!(info->flags & FBINFO_HWACCEL_DISABLED))
1233 par->init_accel(par, info->var.xres_virtual, bpp);
1235 info->fix.visual = (bpp == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
1236 info->cmap.len = (bpp == 8) ? 256 : 16;
1241 /* Set one color register */
1242 static int tridentfb_setcolreg(unsigned regno, unsigned red, unsigned green,
1243 unsigned blue, unsigned transp,
1244 struct fb_info *info)
1246 int bpp = info->var.bits_per_pixel;
1247 struct tridentfb_par *par = info->par;
1249 if (regno >= info->cmap.len)
1253 t_outb(par, 0xFF, VGA_PEL_MSK);
1254 t_outb(par, regno, VGA_PEL_IW);
1256 t_outb(par, red >> 10, VGA_PEL_D);
1257 t_outb(par, green >> 10, VGA_PEL_D);
1258 t_outb(par, blue >> 10, VGA_PEL_D);
1260 } else if (regno < 16) {
1261 if (bpp == 16) { /* RGB 565 */
1264 col = (red & 0xF800) | ((green & 0xFC00) >> 5) |
1265 ((blue & 0xF800) >> 11);
1267 ((u32 *)(info->pseudo_palette))[regno] = col;
1268 } else if (bpp == 32) /* ARGB 8888 */
1269 ((u32 *)info->pseudo_palette)[regno] =
1270 ((transp & 0xFF00) << 16) |
1271 ((red & 0xFF00) << 8) |
1272 ((green & 0xFF00)) |
1273 ((blue & 0xFF00) >> 8);
1279 /* Try blanking the screen. For flat panels it does nothing */
1280 static int tridentfb_blank(int blank_mode, struct fb_info *info)
1282 unsigned char PMCont, DPMSCont;
1283 struct tridentfb_par *par = info->par;
1288 t_outb(par, 0x04, 0x83C8); /* Read DPMS Control */
1289 PMCont = t_inb(par, 0x83C6) & 0xFC;
1290 DPMSCont = read3CE(par, PowerStatus) & 0xFC;
1291 switch (blank_mode) {
1292 case FB_BLANK_UNBLANK:
1293 /* Screen: On, HSync: On, VSync: On */
1294 case FB_BLANK_NORMAL:
1295 /* Screen: Off, HSync: On, VSync: On */
1299 case FB_BLANK_HSYNC_SUSPEND:
1300 /* Screen: Off, HSync: Off, VSync: On */
1304 case FB_BLANK_VSYNC_SUSPEND:
1305 /* Screen: Off, HSync: On, VSync: Off */
1309 case FB_BLANK_POWERDOWN:
1310 /* Screen: Off, HSync: Off, VSync: Off */
1316 write3CE(par, PowerStatus, DPMSCont);
1317 t_outb(par, 4, 0x83C8);
1318 t_outb(par, PMCont, 0x83C6);
1322 /* let fbcon do a softblank for us */
1323 return (blank_mode == FB_BLANK_NORMAL) ? 1 : 0;
1326 static struct fb_ops tridentfb_ops = {
1327 .owner = THIS_MODULE,
1328 .fb_setcolreg = tridentfb_setcolreg,
1329 .fb_pan_display = tridentfb_pan_display,
1330 .fb_blank = tridentfb_blank,
1331 .fb_check_var = tridentfb_check_var,
1332 .fb_set_par = tridentfb_set_par,
1333 .fb_fillrect = tridentfb_fillrect,
1334 .fb_copyarea = tridentfb_copyarea,
1335 .fb_imageblit = tridentfb_imageblit,
1336 #ifdef CONFIG_FB_TRIDENT_ACCEL
1337 .fb_sync = tridentfb_sync,
1341 static int __devinit trident_pci_probe(struct pci_dev *dev,
1342 const struct pci_device_id *id)
1345 unsigned char revision;
1346 struct fb_info *info;
1347 struct tridentfb_par *default_par;
1351 err = pci_enable_device(dev);
1355 info = framebuffer_alloc(sizeof(struct tridentfb_par), &dev->dev);
1358 default_par = info->par;
1360 chip_id = id->device;
1362 #ifndef CONFIG_FB_TRIDENT_ACCEL
1366 /* If PCI id is 0x9660 then further detect chip type */
1368 if (chip_id == TGUI9660) {
1369 revision = vga_io_rseq(RevisionID);
1373 chip_id = PROVIDIA9685;
1377 chip_id = CYBER9397;
1380 chip_id = CYBER9397DVD;
1389 chip_id = CYBER9385;
1392 chip_id = CYBER9382;
1395 chip_id = CYBER9388;
1402 chip3D = is3Dchip(chip_id);
1404 if (is_xp(chip_id)) {
1405 default_par->init_accel = xp_init_accel;
1406 default_par->wait_engine = xp_wait_engine;
1407 default_par->fill_rect = xp_fill_rect;
1408 default_par->copy_rect = xp_copy_rect;
1409 tridentfb_fix.accel = FB_ACCEL_TRIDENT_BLADEXP;
1410 } else if (is_blade(chip_id)) {
1411 default_par->init_accel = blade_init_accel;
1412 default_par->wait_engine = blade_wait_engine;
1413 default_par->fill_rect = blade_fill_rect;
1414 default_par->copy_rect = blade_copy_rect;
1415 default_par->image_blit = blade_image_blit;
1416 tridentfb_fix.accel = FB_ACCEL_TRIDENT_BLADE3D;
1417 } else if (chip3D) { /* 3DImage family left */
1418 default_par->init_accel = image_init_accel;
1419 default_par->wait_engine = image_wait_engine;
1420 default_par->fill_rect = image_fill_rect;
1421 default_par->copy_rect = image_copy_rect;
1422 tridentfb_fix.accel = FB_ACCEL_TRIDENT_3DIMAGE;
1423 } else { /* TGUI 9440/96XX family */
1424 default_par->init_accel = tgui_init_accel;
1425 default_par->wait_engine = xp_wait_engine;
1426 default_par->fill_rect = tgui_fill_rect;
1427 default_par->copy_rect = tgui_copy_rect;
1428 tridentfb_fix.accel = FB_ACCEL_TRIDENT_TGUI;
1431 default_par->chip_id = chip_id;
1433 /* setup MMIO region */
1434 tridentfb_fix.mmio_start = pci_resource_start(dev, 1);
1435 tridentfb_fix.mmio_len = pci_resource_len(dev, 1);
1437 if (!request_mem_region(tridentfb_fix.mmio_start,
1438 tridentfb_fix.mmio_len, "tridentfb")) {
1439 debug("request_region failed!\n");
1440 framebuffer_release(info);
1444 default_par->io_virt = ioremap_nocache(tridentfb_fix.mmio_start,
1445 tridentfb_fix.mmio_len);
1447 if (!default_par->io_virt) {
1448 debug("ioremap failed\n");
1453 enable_mmio(default_par);
1455 /* setup framebuffer memory */
1456 tridentfb_fix.smem_start = pci_resource_start(dev, 0);
1457 tridentfb_fix.smem_len = get_memsize(default_par);
1459 if (!request_mem_region(tridentfb_fix.smem_start,
1460 tridentfb_fix.smem_len, "tridentfb")) {
1461 debug("request_mem_region failed!\n");
1462 disable_mmio(info->par);
1467 info->screen_base = ioremap_nocache(tridentfb_fix.smem_start,
1468 tridentfb_fix.smem_len);
1470 if (!info->screen_base) {
1471 debug("ioremap failed\n");
1476 default_par->flatpanel = is_flatpanel(default_par);
1478 if (default_par->flatpanel)
1479 nativex = get_nativex(default_par);
1481 info->fix = tridentfb_fix;
1482 info->fbops = &tridentfb_ops;
1483 info->pseudo_palette = default_par->pseudo_pal;
1485 info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
1486 if (!noaccel && default_par->init_accel) {
1487 info->flags &= ~FBINFO_HWACCEL_DISABLED;
1488 info->flags |= FBINFO_HWACCEL_COPYAREA;
1489 info->flags |= FBINFO_HWACCEL_FILLRECT;
1491 info->flags |= FBINFO_HWACCEL_DISABLED;
1493 info->pixmap.addr = kmalloc(4096, GFP_KERNEL);
1494 if (!info->pixmap.addr) {
1499 info->pixmap.size = 4096;
1500 info->pixmap.buf_align = 4;
1501 info->pixmap.scan_align = 1;
1502 info->pixmap.access_align = 32;
1503 info->pixmap.flags = FB_PIXMAP_SYSTEM;
1505 if (default_par->image_blit) {
1506 info->flags |= FBINFO_HWACCEL_IMAGEBLIT;
1507 info->pixmap.scan_align = 4;
1511 printk(KERN_DEBUG "disabling acceleration\n");
1512 info->flags |= FBINFO_HWACCEL_DISABLED;
1513 info->pixmap.scan_align = 1;
1516 if (!fb_find_mode(&info->var, info,
1517 mode_option, NULL, 0, NULL, bpp)) {
1521 err = fb_alloc_cmap(&info->cmap, 256, 0);
1525 info->var.activate |= FB_ACTIVATE_NOW;
1526 info->device = &dev->dev;
1527 if (register_framebuffer(info) < 0) {
1528 printk(KERN_ERR "tridentfb: could not register framebuffer\n");
1529 fb_dealloc_cmap(&info->cmap);
1533 output("fb%d: %s frame buffer device %dx%d-%dbpp\n",
1534 info->node, info->fix.id, info->var.xres,
1535 info->var.yres, info->var.bits_per_pixel);
1537 pci_set_drvdata(dev, info);
1541 kfree(info->pixmap.addr);
1542 if (info->screen_base)
1543 iounmap(info->screen_base);
1544 release_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len);
1545 disable_mmio(info->par);
1547 if (default_par->io_virt)
1548 iounmap(default_par->io_virt);
1549 release_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len);
1550 framebuffer_release(info);
1554 static void __devexit trident_pci_remove(struct pci_dev *dev)
1556 struct fb_info *info = pci_get_drvdata(dev);
1557 struct tridentfb_par *par = info->par;
1559 unregister_framebuffer(info);
1560 iounmap(par->io_virt);
1561 iounmap(info->screen_base);
1562 release_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len);
1563 release_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len);
1564 pci_set_drvdata(dev, NULL);
1565 kfree(info->pixmap.addr);
1566 framebuffer_release(info);
1569 /* List of boards that we are trying to support */
1570 static struct pci_device_id trident_devices[] = {
1571 {PCI_VENDOR_ID_TRIDENT, BLADE3D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1572 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1573 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi7D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1574 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1575 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi1D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1576 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEAi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1577 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEAi1D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1578 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEE4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1579 {PCI_VENDOR_ID_TRIDENT, TGUI9440, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1580 {PCI_VENDOR_ID_TRIDENT, TGUI9660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1581 {PCI_VENDOR_ID_TRIDENT, IMAGE975, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1582 {PCI_VENDOR_ID_TRIDENT, IMAGE985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1583 {PCI_VENDOR_ID_TRIDENT, CYBER9320, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1584 {PCI_VENDOR_ID_TRIDENT, CYBER9388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1585 {PCI_VENDOR_ID_TRIDENT, CYBER9520, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1586 {PCI_VENDOR_ID_TRIDENT, CYBER9525DVD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1587 {PCI_VENDOR_ID_TRIDENT, CYBER9397, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1588 {PCI_VENDOR_ID_TRIDENT, CYBER9397DVD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1589 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPAi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1590 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPm8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1591 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPm16, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1595 MODULE_DEVICE_TABLE(pci, trident_devices);
1597 static struct pci_driver tridentfb_pci_driver = {
1598 .name = "tridentfb",
1599 .id_table = trident_devices,
1600 .probe = trident_pci_probe,
1601 .remove = __devexit_p(trident_pci_remove)
1605 * Parse user specified options (`video=trident:')
1607 * video=trident:800x600,bpp=16,noaccel
1610 static int __init tridentfb_setup(char *options)
1613 if (!options || !*options)
1615 while ((opt = strsep(&options, ",")) != NULL) {
1618 if (!strncmp(opt, "noaccel", 7))
1620 else if (!strncmp(opt, "fp", 2))
1622 else if (!strncmp(opt, "crt", 3))
1624 else if (!strncmp(opt, "bpp=", 4))
1625 bpp = simple_strtoul(opt + 4, NULL, 0);
1626 else if (!strncmp(opt, "center", 6))
1628 else if (!strncmp(opt, "stretch", 7))
1630 else if (!strncmp(opt, "memsize=", 8))
1631 memsize = simple_strtoul(opt + 8, NULL, 0);
1632 else if (!strncmp(opt, "memdiff=", 8))
1633 memdiff = simple_strtoul(opt + 8, NULL, 0);
1634 else if (!strncmp(opt, "nativex=", 8))
1635 nativex = simple_strtoul(opt + 8, NULL, 0);
1643 static int __init tridentfb_init(void)
1646 char *option = NULL;
1648 if (fb_get_options("tridentfb", &option))
1650 tridentfb_setup(option);
1652 return pci_register_driver(&tridentfb_pci_driver);
1655 static void __exit tridentfb_exit(void)
1657 pci_unregister_driver(&tridentfb_pci_driver);
1660 module_init(tridentfb_init);
1661 module_exit(tridentfb_exit);
1663 MODULE_AUTHOR("Jani Monoses <jani@iv.ro>");
1664 MODULE_DESCRIPTION("Framebuffer driver for Trident cards");
1665 MODULE_LICENSE("GPL");