1 /**************************************************************************
3 * Copyright © 2000-2008 Alacritech, Inc. All rights reserved.
5 * $Id: sxg.h,v 1.3 2008/07/24 17:25:08 chris Exp $
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY ALACRITECH, INC. ``AS IS'' AND ANY
19 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
21 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ALACRITECH, INC. OR
22 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
23 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
24 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
25 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
26 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
27 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
28 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * The views and conclusions contained in the software and documentation
32 * are those of the authors and should not be interpreted as representing
33 * official policies, either expressed or implied, of Alacritech, Inc.
35 **************************************************************************/
40 * This is the base set of header definitions for the SXG driver.
42 #ifndef __SXG_DRIVER_H__
43 #define __SXG_DRIVER_H__
45 #define SLIC_DUMP_ENABLED 0
47 #define SXG_DRV_NAME "sxg" /* TBD: This might be removed eventually */
48 #define SXG_DRV_VERSION "1.0.1"
50 extern char sxg_driver_name[];
52 #define SXG_NETDEV_WEIGHT 64
55 * struct sxg_stats - Probably move these to someplace where
56 * the slicstat (sxgstat?) program can get them.
60 u64 DumbXmtUcastPkts; /* directed packets */
61 u64 DumbXmtMcastPkts; /* Multicast packets */
62 u64 DumbXmtBcastPkts; /* OID_GEN_BROADCAST_FRAMES_RCV */
63 u64 DumbXmtUcastBytes; /* OID_GEN_DIRECTED_BYTES_XMIT */
64 u64 DumbXmtMcastBytes; /* OID_GEN_MULTICAST_BYTES_XMIT */
65 u64 DumbXmtBcastBytes; /* OID_GEN_BROADCAST_BYTES_XMIT */
66 u64 XmtQLen; /* OID_GEN_TRANSMIT_QUEUE_LENGTH */
67 u64 XmtZeroFull; /* Transmit ring zero full */
69 u64 DumbRcvUcastBytes; /* OID_GEN_DIRECTED_BYTES_RCV */
70 u64 DumbRcvMcastBytes; /* OID_GEN_MULTICAST_BYTES_RCV */
71 u64 DumbRcvBcastBytes; /* OID_GEN_BROADCAST_BYTES_RCV */
72 u64 DumbRcvUcastPkts; /* directed packets */
73 u64 DumbRcvMcastPkts; /* Multicast packets */
74 u64 DumbRcvBcastPkts; /* OID_GEN_BROADCAST_FRAMES_RCV */
75 u64 PdqFull; /* Processed Data Queue Full */
76 u64 EventRingFull; /* Event ring full */
78 u64 NoSglBuf; /* SGL buffer allocation failure */
79 u64 NoMem; /* Memory allocation failure */
80 u64 NumInts; /* Interrupts */
81 u64 FalseInts; /* Interrupt with ISR == 0 */
82 /* Sahara receive status */
83 u64 TransportCsum; /* SXG_RCV_STATUS_TRANSPORT_CSUM */
84 u64 TransportUflow; /* SXG_RCV_STATUS_TRANSPORT_UFLOW */
85 u64 TransportHdrLen; /* SXG_RCV_STATUS_TRANSPORT_HDRLEN */
86 u64 NetworkCsum; /* SXG_RCV_STATUS_NETWORK_CSUM: */
87 u64 NetworkUflow; /* SXG_RCV_STATUS_NETWORK_UFLOW: */
88 u64 NetworkHdrLen; /* SXG_RCV_STATUS_NETWORK_HDRLEN: */
89 u64 Parity; /* SXG_RCV_STATUS_PARITY */
90 u64 LinkParity; /* SXG_RCV_STATUS_LINK_PARITY: */
91 u64 LinkEarly; /* SXG_RCV_STATUS_LINK_EARLY: */
92 u64 LinkBufOflow; /* SXG_RCV_STATUS_LINK_BUFOFLOW: */
93 u64 LinkCode; /* SXG_RCV_STATUS_LINK_CODE: */
94 u64 LinkDribble; /* SXG_RCV_STATUS_LINK_DRIBBLE: */
95 u64 LinkCrc; /* SXG_RCV_STATUS_LINK_CRC: */
96 u64 LinkOflow; /* SXG_RCV_STATUS_LINK_OFLOW: */
97 u64 LinkUflow; /* SXG_RCV_STATUS_LINK_UFLOW: */
101 /* DUMB-NIC Send path definitions */
103 #define SXG_COMPLETE_DUMB_SEND(_pAdapt, _skb, _phys_addr, _size) { \
105 pci_unmap_single(_pAdapt->pcidev, _size, _phys_addr, PCI_DMA_TODEVICE); \
106 dev_kfree_skb_irq(_skb); \
109 #define SXG_DROP_DUMB_SEND(_pAdapt, _skb) { \
111 dev_kfree_skb(_skb); \
115 * Locate current receive header buffer location. Use this
116 * instead of RcvDataHdr->VirtualAddress since the data
117 * may have been offset by SXG_ADVANCE_MDL_OFFSET
119 #define SXG_RECEIVE_DATA_LOCATION(_RcvDataHdr) (_RcvDataHdr)->skb->data
121 /* Dumb-NIC receive processing */
122 /* Define an SXG_PACKET as an NDIS_PACKET */
123 #define PSXG_PACKET struct sk_buff *
124 /* Indications array size */
125 #define SXG_RCV_ARRAYSIZE 64
127 #define SXG_ALLOCATE_RCV_PACKET(_pAdapt, _RcvDataBufferHdr, BufferSize) {\
128 struct sk_buff * skb; \
129 skb = netdev_alloc_skb(_pAdapt->netdev, BufferSize); \
131 (_RcvDataBufferHdr)->skb = skb; \
133 _RcvDataBufferHdr->PhysicalAddress = pci_map_single(adapter->pcidev,\
134 _RcvDataBufferHdr->skb->data, BufferSize, PCI_DMA_FROMDEVICE); \
136 (_RcvDataBufferHdr)->skb = NULL; \
140 #define SXG_FREE_RCV_PACKET(_RcvDataBufferHdr) { \
141 if((_RcvDataBufferHdr)->skb) { \
142 dev_kfree_skb((_RcvDataBufferHdr)->skb); \
147 * Macro to add a NDIS_PACKET to an indication array
148 * If we fill up our array of packet pointers, then indicate this
149 * block up now and start on a new one.
151 #define SXG_ADD_RCV_PACKET(_pAdapt, _Packet, _PrevPacket, _IndicationList, \
153 (_IndicationList)[_NumPackets] = (_Packet); \
155 if((_NumPackets) == SXG_RCV_ARRAYSIZE) { \
156 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "IndicRcv", \
157 (_NumPackets), 0, 0, 0); \
158 netif_rx((_IndicationList),(_NumPackets)); \
163 #define SXG_INDICATE_PACKETS(_pAdapt, _IndicationList, _NumPackets) { \
165 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "IndicRcv", \
166 (_NumPackets), 0, 0, 0); \
167 netif_rx((_IndicationList),(_NumPackets)); \
172 #define SXG_REINIATIALIZE_PACKET(_Packet) \
173 {} /*_NdisReinitializePacket(_Packet)*/
174 /* this is not necessary with an skb */
176 /* Definitions to initialize Dumb-nic Receive NBLs */
177 #define SXG_RCV_PACKET_BUFFER_HDR(_Packet) (((struct sxg_rcv_nbl_reserved *)\
178 ((_Packet)->MiniportReservedEx))->RcvDataBufferHdr)
180 #define SXG_RCV_SET_CHECKSUM_INFO(_Packet, _Cpi) \
181 NDIS_PER_PACKET_INFO_FROM_PACKET((_Packet), \
182 TcpIpChecksumPacketInfo) = (PVOID)(_Cpi)
184 #define SXG_RCV_SET_TOEPLITZ(_Packet, _Toeplitz, _Type, _Function) { \
185 NDIS_PACKET_SET_HASH_VALUE((_Packet), (_Toeplitz)); \
186 NDIS_PACKET_SET_HASH_TYPE((_Packet), (_Type)); \
187 NDIS_PACKET_SET_HASH_FUNCTION((_Packet), (_Function)); \
190 #define SXG_RCV_SET_VLAN_INFO(_Packet, _VlanId, _Priority) { \
191 NDIS_PACKET_8021Q_INFO _Packet8021qInfo; \
192 _Packet8021qInfo.TagHeader.VlanId = (_VlanId); \
193 _Packet8021qInfo.TagHeader.UserPriority = (_Priority); \
194 NDIS_PER_PACKET_INFO_FROM_PACKET((_Packet), Ieee8021QNetBufferListInfo) = \
195 _Packet8021qInfo.Value; \
198 #define SXG_ADJUST_RCV_PACKET(_Packet, _RcvDataBufferHdr, _Event) { \
199 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "DumbRcv", \
200 (_RcvDataBufferHdr), (_Packet), \
201 (_Event)->Status, 0); \
202 /* ASSERT((_Event)->Length <= (_RcvDataBufferHdr)->Size); */ \
203 skb_put(Packet, (_Event)->Length); \
207 * Macros to free a receive data buffer and receive data descriptor block
208 * NOTE - Lock must be held with RCV macros
210 #define SXG_GET_RCV_DATA_BUFFER(_pAdapt, _Hdr) { \
211 struct list_entry *_ple; \
213 if((_pAdapt)->FreeRcvBufferCount) { \
214 ASSERT(!(IsListEmpty(&(_pAdapt)->FreeRcvBuffers))); \
215 _ple = RemoveHeadList(&(_pAdapt)->FreeRcvBuffers); \
216 (_Hdr) = container_of(_ple, struct sxg_rcv_data_buffer_hdr, \
218 (_pAdapt)->FreeRcvBufferCount--; \
219 ASSERT((_Hdr)->State == SXG_BUFFER_FREE); \
223 #define SXG_FREE_RCV_DATA_BUFFER(_pAdapt, _Hdr) { \
224 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "RtnDHdr", \
225 (_Hdr), (_pAdapt)->FreeRcvBufferCount, \
226 (_Hdr)->State, 0/*(_Hdr)->VirtualAddress*/); \
227 /* SXG_RESTORE_MDL_OFFSET(_Hdr); */ \
228 (_pAdapt)->FreeRcvBufferCount++; \
229 ASSERT(((_pAdapt)->AllRcvBlockCount * SXG_RCV_DESCRIPTORS_PER_BLOCK) \
230 >= (_pAdapt)->FreeRcvBufferCount); \
231 ASSERT((_Hdr)->State != SXG_BUFFER_FREE); \
232 (_Hdr)->State = SXG_BUFFER_FREE; \
233 InsertTailList(&(_pAdapt)->FreeRcvBuffers, &((_Hdr)->FreeList)); \
236 #define SXG_FREE_RCV_DESCRIPTOR_BLOCK(_pAdapt, _Hdr) { \
237 ASSERT((_Hdr)->State != SXG_BUFFER_FREE); \
238 (_Hdr)->State = SXG_BUFFER_FREE; \
239 (_pAdapt)->FreeRcvBlockCount++; \
240 ASSERT((_pAdapt)->AllRcvBlockCount >= (_pAdapt)->FreeRcvBlockCount); \
241 InsertTailList(&(_pAdapt)->FreeRcvBlocks, &(_Hdr)->FreeList); \
245 #define SXG_FREE_SGL_BUFFER(_pAdapt, _Sgl, _NB, _irq) { \
247 spin_lock_irqsave(&(_pAdapt)->SglQLock, sgl_flags); \
249 spin_lock(&(_pAdapt)->SglQLock); \
250 (_pAdapt)->FreeSglBufferCount++; \
251 ASSERT((_pAdapt)->AllSglBufferCount >= (_pAdapt)->FreeSglBufferCount); \
252 ASSERT(!((_Sgl)->State & SXG_BUFFER_FREE)); \
253 (_Sgl)->State = SXG_BUFFER_FREE; \
254 InsertTailList(&(_pAdapt)->FreeSglBuffers, &(_Sgl)->FreeList); \
256 spin_unlock_irqrestore(&(_pAdapt)->SglQLock, sgl_flags); \
258 spin_unlock(&(_pAdapt)->SglQLock); \
262 * Get an SGL buffer from the free queue. The first part of this macro
263 * attempts to keep ahead of buffer depletion by allocating more when
264 * we hit a minimum threshold. Note that we don't grab the lock
265 * until after that. We're dealing with round numbers here, so we don't need to,
266 * and not grabbing it avoids a possible double-trip.
268 #define SXG_GET_SGL_BUFFER(_pAdapt, _Sgl, _irq) { \
269 struct list_entry *_ple; \
270 if ((_pAdapt->FreeSglBufferCount < SXG_MIN_SGL_BUFFERS) && \
271 (_pAdapt->AllSglBufferCount < SXG_MAX_SGL_BUFFERS) && \
272 (atomic_read(&_pAdapt->pending_allocations) == 0)) { \
273 sxg_allocate_buffer_memory(_pAdapt, \
274 (sizeof(struct sxg_scatter_gather) + SXG_SGL_BUF_SIZE),\
275 SXG_BUFFER_TYPE_SGL); \
279 spin_lock_irqsave(&(_pAdapt)->SglQLock, sgl_flags); \
281 spin_lock(&(_pAdapt)->SglQLock); \
282 if((_pAdapt)->FreeSglBufferCount) { \
283 ASSERT(!(IsListEmpty(&(_pAdapt)->FreeSglBuffers))); \
284 _ple = RemoveHeadList(&(_pAdapt)->FreeSglBuffers); \
285 (_Sgl) = container_of(_ple, struct sxg_scatter_gather, \
287 (_pAdapt)->FreeSglBufferCount--; \
288 ASSERT((_Sgl)->State == SXG_BUFFER_FREE); \
289 (_Sgl)->State = SXG_BUFFER_BUSY; \
290 (_Sgl)->pSgl = NULL; \
293 spin_unlock_irqrestore(&(_pAdapt)->SglQLock, sgl_flags);\
295 spin_unlock(&(_pAdapt)->SglQLock); \
299 * struct sxg_multicast_address
300 * Linked list of multicast addresses.
302 struct sxg_multicast_address {
303 unsigned char Address[6];
304 struct sxg_multicast_address *Next;
308 * Structure to maintain chimney send and receive buffer queues.
309 * This structure maintains NET_BUFFER_LIST queues that are
310 * given to us via the Chimney MiniportTcpOffloadSend and
311 * MiniportTcpOffloadReceive routines. This structure DOES NOT
312 * manage our data buffer queue
314 struct sxg_buffer_queue {
315 u32 Type; /* Slow or fast - See below */
316 u32 Direction; /* Xmt or Rcv */
317 u32 Bytes; /* Byte count */
318 u32 * Head; /* Send queue head */
319 u32 * Tail; /* Send queue tail */
320 /* PNET_BUFFER_LIST NextNBL;*/ /* Short cut - next NBL */
321 /* PNET_BUFFER NextNB; */ /* Short cut - next NB */
324 #define SXG_SLOW_SEND_BUFFER 0
325 #define SXG_FAST_SEND_BUFFER 1
326 #define SXG_RECEIVE_BUFFER 2
328 #define SXG_INIT_BUFFER(_Buffer, _Type) { \
329 (_Buffer)->Type = (_Type); \
330 if((_Type) == SXG_RECEIVE_BUFFER) { \
331 (_Buffer)->Direction = 0; \
333 (_Buffer)->Direction = NDIS_SG_LIST_WRITE_TO_DEVICE; \
335 (_Buffer)->Bytes = 0; \
336 (_Buffer)->Head = NULL; \
337 (_Buffer)->Tail = NULL; \
341 #define SXG_RSS_CPU_COUNT(_pAdapt) \
342 ((_pAdapt)->RssEnabled ? NR_CPUS : 1)
344 /* DRIVER and ADAPTER structures */
347 * Adapter states - These states closely match the adapter states
348 * documented in the DDK (with a few exceptions).
351 SXG_STATE_INITIALIZING, /* Initializing */
352 SXG_STATE_BOOTDIAG, /* Boot-Diagnostic mode */
353 SXG_STATE_PAUSING, /* Pausing */
354 SXG_STATE_PAUSED, /* Paused */
355 SXG_STATE_RUNNING, /* Running */
356 SXG_STATE_RESETTING, /* Reset in progress */
357 SXG_STATE_SLEEP, /* Sleeping */
358 SXG_STATE_DIAG, /* Diagnostic mode */
359 SXG_STATE_HALTING, /* Halting */
360 SXG_STATE_HALTED, /* Down or not-initialized */
361 SXG_STATE_SHUTDOWN /* shutdown */
365 enum SXG_LINK_STATE {
370 /* Link initialization timeout in 100us units */
371 #define SXG_LINK_TIMEOUT 100000 /* 10 Seconds - REDUCE! */
374 /* Microcode file selection codes */
376 SXG_UCODE_SAHARA, /* Sahara ucode */
377 SXG_UCODE_SDIAGCPU, /* Sahara CPU diagnostic ucode */
378 SXG_UCODE_SDIAGSYS /* Sahara system diagnostic ucode */
382 #define SXG_DISABLE_ALL_INTERRUPTS(_padapt) sxg_disable_interrupt(_padapt)
383 #define SXG_ENABLE_ALL_INTERRUPTS(_padapt) sxg_enable_interrupt(_padapt)
385 /* This probably lives in a proto.h file. Move later */
386 #define SXG_MULTICAST_PACKET(_pether) ((_pether)->ether_dhost[0] & 0x01)
387 #define SXG_BROADCAST_PACKET(_pether) \
388 ((*(u32 *)(_pether)->ether_dhost == 0xFFFFFFFF) && \
389 (*(u16 *)&(_pether)->ether_dhost[4] == 0xFFFF))
392 #define SXG_ID DPFLTR_IHVNETWORK_ID
393 #define SXG_ERROR DPFLTR_ERROR_LEVEL
396 * struct sxg_driver structure -
398 * contains information about the sxg driver. There is only
399 * one of these, and it is defined as a global.
403 struct adapter_t *Adapters; /* Linked list of adapters */
404 ushort AdapterID; /* Maintain unique adapter ID */
407 #ifdef STATUS_SUCCESS
408 #undef STATUS_SUCCESS
411 /* TODO: We need to try and use NETDEV_TX_* before posting this out */
412 #define STATUS_SUCCESS 0
413 #define STATUS_PENDING 0
414 #define STATUS_FAILURE -1
415 #define STATUS_ERROR -2
416 #define STATUS_NOT_SUPPORTED -3
417 #define STATUS_BUFFER_TOO_SHORT -4
418 #define STATUS_RESOURCES -5
420 #define SLIC_MAX_CARDS 32
421 #define SLIC_MAX_PORTS 4 /* Max # of ports per card */
422 #if SLIC_DUMP_ENABLED
426 * This cannot be bigger than the max DMA size the card supports,
427 * given the current code structure in the host and ucode.
428 * Mojave supports 16K, Oasis supports 16K-1, so
429 * just set this at 15K, shouldnt make that much of a diff.
431 #define DUMP_BUF_SIZE 0x3C00
434 #define MIN(a, b) ((u32)(a) < (u32)(b) ? (a) : (b))
435 #define MAX(a, b) ((u32)(a) > (u32)(b) ? (a) : (b))
437 struct mcast_address {
438 unsigned char address[6];
439 struct mcast_address *next;
442 #define CARD_DOWN 0x00000000
443 #define CARD_UP 0x00000001
444 #define CARD_FAIL 0x00000002
445 #define CARD_DIAG 0x00000003
446 #define CARD_SLEEP 0x00000004
448 #define ADAPT_DOWN 0x00
449 #define ADAPT_UP 0x01
450 #define ADAPT_FAIL 0x02
451 #define ADAPT_RESET 0x03
452 #define ADAPT_SLEEP 0x04
454 #define ADAPT_FLAGS_BOOTTIME 0x0001
455 #define ADAPT_FLAGS_IS64BIT 0x0002
456 #define ADAPT_FLAGS_PENDINGLINKDOWN 0x0004
457 #define ADAPT_FLAGS_FIBERMEDIA 0x0008
458 #define ADAPT_FLAGS_LOCKS_ALLOCED 0x0010
459 #define ADAPT_FLAGS_INT_REGISTERED 0x0020
460 #define ADAPT_FLAGS_LOAD_TIMER_SET 0x0040
461 #define ADAPT_FLAGS_STATS_TIMER_SET 0x0080
462 #define ADAPT_FLAGS_RESET_TIMER_SET 0x0100
464 #define LINK_DOWN 0x00
465 #define LINK_CONFIG 0x01
468 #define LINK_10MB 0x00
469 #define LINK_100MB 0x01
470 #define LINK_AUTOSPEED 0x02
471 #define LINK_1000MB 0x03
472 #define LINK_10000MB 0x04
474 #define LINK_HALFD 0x00
475 #define LINK_FULLD 0x01
476 #define LINK_AUTOD 0x02
478 #define MAC_DIRECTED 0x00000001
479 #define MAC_BCAST 0x00000002
480 #define MAC_MCAST 0x00000004
481 #define MAC_PROMISC 0x00000008
482 #define MAC_LOOPBACK 0x00000010
483 #define MAC_ALLMCAST 0x00000020
485 #define SLIC_DUPLEX(x) ((x==LINK_FULLD) ? "FDX" : "HDX")
486 #define SLIC_SPEED(x) ((x==LINK_100MB) ? "100Mb" : \
487 ((x==LINK_1000MB) ? "1000Mb" : " 10Mb"))
488 #define SLIC_LINKSTATE(x) ((x==LINK_DOWN) ? "Down" : "Up ")
489 #define SLIC_ADAPTER_STATE(x) ((x==ADAPT_UP) ? "UP" : "Down")
490 #define SLIC_CARD_STATE(x) ((x==CARD_UP) ? "UP" : "Down")
493 struct ether_header {
494 unsigned char ether_dhost[6];
495 unsigned char ether_shost[6];
500 #define NUM_CFG_SPACES 2
501 #define NUM_CFG_REGS 64
504 * We split LSS sends across four microcode queues derived from
505 * destination TCP port (if TCP/IP).
507 #define SXG_LARGE_SEND_QUEUE_MASK 0x3
508 #define ISCSI_PORT 0xbc0c /* 3260 */
511 struct adapter_t *adapter[SLIC_MAX_PORTS];
512 struct physcard *next;
513 unsigned int adapters_allocd;
516 struct sxgbase_driver {
517 spinlock_t driver_lock;
518 unsigned long flags; /* irqsave for spinlock */
521 u32 num_sxg_ports_active;
523 struct physcard *phys_card;
530 struct napi_struct napi;
531 struct physcard *physcard;
532 unsigned int physport;
533 unsigned int slotnumber;
534 unsigned int functionnumber;
540 void __iomem * base_addr;
544 unsigned int activated;
546 unsigned int isp_initialized;
548 unsigned char linkstate;
550 unsigned char macaddr[6];
551 unsigned char currmacaddr[6];
553 ushort devflags_prev;
555 struct mcast_address *mcastaddrs;
556 struct timer_list pingtimer;
558 struct timer_list statstimer;
560 struct timer_list vpci_timer;
562 struct timer_list loadtimer;
569 u32 error_interrupts;
570 u32 error_rmiss_interrupts;
575 u32 linkevent_interrupts;
578 u32 false_interrupts;
587 u32 rcv_interrupt_yields;
589 struct net_device_stats stats;
590 u32 * MiniportHandle; /* Our miniport handle */
591 enum SXG_STATE State; /* Adapter state */
592 enum SXG_LINK_STATE LinkState; /* Link state */
593 u64 LinkSpeed; /* Link Speed */
594 u32 PowerState; /* NDIS power state */
595 struct adapter_t *Next; /* Linked list */
596 ushort AdapterID; /* 1..n */
597 struct net_device * netdev;
598 struct net_device * next_netdevice;
599 struct pci_dev *pcidev;
601 struct sxg_multicast_address *MulticastAddrs; /* Multicast list */
602 u64 MulticastMask; /* Multicast mask */
603 u32 *InterruptHandle; /* Register Interrupt handle */
604 u32 InterruptLevel; /* From Resource list */
605 u32 InterruptVector; /* From Resource list */
606 spinlock_t AdapterLock; /* Serialize access adapter routines */
607 spinlock_t Bit64RegLock; /* For writing 64-bit addresses */
608 struct sxg_hw_regs *HwRegs; /* Sahara HW Register Memory (BAR0/1) */
609 struct sxg_ucode_regs *UcodeRegs; /* Microcode Register Memory (BAR2/3) */
610 struct sxg_tcb_regs *TcbRegs; /* Same as Ucode regs - See sxghw.h */
611 ushort FrameSize; /* Maximum frame size */
612 u32 * DmaHandle; /* NDIS DMA handle */
613 u32 * PacketPoolHandle; /* Used with NDIS 5.2 only. Don't ifdef out */
614 u32 * BufferPoolHandle; /* Used with NDIS 5.2 only. Don't ifdef out */
615 u32 MacFilter; /* NDIS MAC Filter */
616 struct sxg_event_ring *EventRings; /* Host event rings. 1/CPU to 16 max */
617 dma_addr_t PEventRings; /* Physical address */
618 u32 NextEvent[SXG_MAX_RSS]; /* Current location in ring */
619 dma_addr_t PTcbBuffers; /* TCB Buffers - physical address */
620 dma_addr_t PTcbCompBuffers; /* TCB Composite Buffers - phys addr */
621 struct sxg_xmt_ring *XmtRings; /* Transmit rings */
622 dma_addr_t PXmtRings; /* Transmit rings - physical address */
623 struct sxg_ring_info XmtRingZeroInfo; /* Transmit ring 0 info */
625 spinlock_t XmtZeroLock; /* Transmit ring 0 lock */
626 u32 * XmtRingZeroIndex; /* Shared XMT ring 0 index */
627 dma_addr_t PXmtRingZeroIndex; /* Shared XMT ring 0 index - physical */
628 struct list_entry FreeProtocolHeaders;/* Free protocol headers */
629 u32 FreeProtoHdrCount; /* Count */
630 void * ProtocolHeaders; /* Block of protocol header */
631 dma_addr_t PProtocolHeaders; /* Block of protocol headers - phys */
633 struct sxg_rcv_ring *RcvRings; /* Receive rings */
634 dma_addr_t PRcvRings; /* Receive rings - physical address */
635 struct sxg_ucode_stats *ucode_stats; /* Ucode Stats */
636 /* Ucode Stats - physical address */
637 dma_addr_t pucode_stats;
639 struct sxg_ring_info RcvRingZeroInfo; /* Receive ring 0 info */
641 u32 * Isr; /* Interrupt status register */
642 dma_addr_t PIsr; /* ISR - physical address */
643 u32 IsrCopy[SXG_MAX_RSS]; /* Copy of ISR */
644 ushort InterruptsEnabled; /* Bitmask of enabled vectors */
645 unsigned char *IndirectionTable; /* RSS indirection table */
646 dma_addr_t PIndirectionTable; /* Physical address */
647 ushort RssTableSize; /* From NDIS_RECEIVE_SCALE_PARAMETERS */
648 ushort HashKeySize; /* From NDIS_RECEIVE_SCALE_PARAMETERS */
649 unsigned char HashSecretKey[40]; /* rss key */
651 /* Receive buffer queues */
652 spinlock_t RcvQLock; /* Receive Queue Lock */
653 struct list_entry FreeRcvBuffers; /* Free SXG_DATA_BUFFER queue */
654 struct list_entry FreeRcvBlocks; /* Free SXG_RCV_DESCRIPTOR_BLOCK Q */
655 struct list_entry AllRcvBlocks; /* All SXG_RCV_BLOCKs */
656 ushort FreeRcvBufferCount; /* Number of free rcv data buffers */
657 ushort FreeRcvBlockCount; /* # of free rcv descriptor blocks */
658 ushort AllRcvBlockCount; /* Number of total receive blocks */
659 ushort ReceiveBufferSize; /* SXG_RCV_DATA/JUMBO_BUFFER_SIZE only */
660 /* Converted this to a atomic variable
661 u32 AllocationsPending; */
662 atomic_t pending_allocations;
663 u32 AllocationsPending; /* Receive allocation pending */
664 u32 RcvBuffersOnCard; /* SXG_DATA_BUFFERS owned by card */
666 spinlock_t SglQLock; /* SGL Queue Lock */
667 struct list_entry FreeSglBuffers; /* Free struct sxg_scatter_gather */
668 struct list_entry AllSglBuffers; /* All struct sxg_scatter_gather */
669 ushort FreeSglBufferCount; /* Number of free SGL buffers */
670 ushort AllSglBufferCount; /* Number of total SGL buffers */
671 u32 CurrentTime; /* Tick count */
672 u32 FastpathConnections;/* # of fastpath connections */
673 /* Various single-bit flags: */
674 u32 BasicAllocations:1; /* Locks and listheads */
675 u32 IntRegistered:1; /* Interrupt registered */
676 u32 PingOutstanding:1; /* Ping outstanding to card */
677 u32 Dead:1; /* Card dead */
678 u32 DumpDriver:1; /* OID_SLIC_DRIVER_DUMP request */
679 u32 DumpCard:1; /* OID_SLIC_CARD_DUMP request */
680 u32 DumpCmdRunning:1; /* Dump command in progress */
681 u32 DebugRunning:1; /* AGDB debug in progress */
682 u32 JumboEnabled:1; /* Jumbo frames enabled */
683 u32 MsiEnabled:1; /* MSI interrupt enabled */
684 u32 RssEnabled:1; /* RSS Enabled */
685 u32 FailOnBadEeprom:1; /* Fail on Bad Eeprom */
686 u32 DiagStart:1; /* Init adapter for diagnostic start */
688 u32 PendingRcvCount; /* Outstanding rcv indications */
689 u32 PendingXmtCount; /* Outstanding send requests */
690 struct sxg_stats Stats; /* Statistics */
691 u32 ReassBufs; /* Number of reassembly buffers */
692 /* Card Crash Info */
693 ushort CrashLocation; /* Microcode crash location */
694 unsigned char CrashCpu; /* Sahara CPU ID */
696 /* PDIAG_CMD DiagCmds; */ /* List of free diagnostic commands */
697 /* PDIAG_BUFFER DiagBuffers; */ /* List of free diagnostic buffers */
698 /* PDIAG_REQ DiagReqQ; */ /* List of outstanding (asynchronous) diag requests */
699 /* u32 DiagCmdTimeout; */ /* Time out for diag cmds (seconds) XXXTODO - replace with SXG_PARAM var? */
700 /* unsigned char DiagDmaDesc[DMA_CPU_CTXS]; */ /* Free DMA descriptors bit field (32 CPU ctx * 8 DMA ctx) */
702 * Put preprocessor-conditional fields at the end so we don't
703 * have to recompile sxgdbg everytime we reconfigure the driver
705 #if defined(CONFIG_X86)
706 u32 AddrUpper; /* Upper 32 bits of 64-bit register */
708 unsigned short max_aggregation;
709 unsigned short min_aggregation;
710 /*#if SXG_FAILURE_DUMP */
711 /* NDIS_EVENT DumpThreadEvent; */ /* syncronize dump thread */
712 /* BOOLEAN DumpThreadRunning; */ /* termination flag */
713 /* PSXG_DUMP_CMD DumpBuffer; */ /* 68k - Cmd and Buffer */
714 /* dma_addr_t PDumpBuffer; */ /* Physical address */
715 /*#endif */ /* SXG_FAILURE_DUMP */
718 #if SLIC_DUMP_ENABLED
719 #define SLIC_DUMP_REQUESTED 1
720 #define SLIC_DUMP_IN_PROGRESS 2
721 #define SLIC_DUMP_DONE 3
724 * Microcode crash information structure. This
725 * structure is written out to the card's SRAM when the microcode panic's.
727 struct slic_crash_info {
732 #define CRASH_INFO_OFFSET 0x155C
736 #define UPDATE_STATS(largestat, newstat, oldstat) \
738 if ((newstat) < (oldstat)) \
739 (largestat) += ((newstat) + (0xFFFFFFFF - oldstat + 1)); \
741 (largestat) += ((newstat) - (oldstat)); \
744 #define UPDATE_STATS_GB(largestat, newstat, oldstat) \
746 (largestat) += ((newstat) - (oldstat)); \
749 #define ETHER_EQ_ADDR(_AddrA, _AddrB, _Result) \
752 if (*(u32 *)(_AddrA) != *(u32 *)(_AddrB)) \
754 if (*(u16 *)(&((_AddrA)[4])) != *(u16 *)(&((_AddrB)[4]))) \
758 #define ETHERMAXFRAME 1514
759 #define JUMBOMAXFRAME 9014
761 #if defined(CONFIG_X86_64) || defined(CONFIG_IA64)
762 #define SXG_GET_ADDR_LOW(_addr) (u32)((u64)(_addr) & 0x00000000FFFFFFFF)
763 #define SXG_GET_ADDR_HIGH(_addr) \
764 (u32)(((u64)(_addr) >> 32) & 0x00000000FFFFFFFF)
766 #define SXG_GET_ADDR_LOW(_addr) (u32)_addr
767 #define SXG_GET_ADDR_HIGH(_addr) (u32)0
771 #define DONT_FLUSH FALSE
773 #define SIOCSLICDUMPCARD (SIOCDEVPRIVATE+9)
774 #define SIOCSLICSETINTAGG (SIOCDEVPRIVATE+10)
775 #define SIOCSLICTRACEDUMP (SIOCDEVPRIVATE+11)
777 extern struct ethtool_ops sxg_nic_ethtool_ops;
778 #define SXG_COMPLETE_SLOW_SEND_LIMIT 128
779 #endif /* __SXG_DRIVER_H__ */