2 * This file contains miscellaneous low-level functions.
3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
5 * Largely rewritten by Cort Dougan (cort@cs.nmt.edu)
7 * Adapted for iSeries by Mike Corrigan (mikejc@us.ibm.com)
8 * PPC64 updates by Dave Engebretsen (engebret@us.ibm.com)
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version
13 * 2 of the License, or (at your option) any later version.
17 #include <linux/config.h>
18 #include <linux/sys.h>
19 #include <asm/unistd.h>
20 #include <asm/errno.h>
21 #include <asm/processor.h>
23 #include <asm/cache.h>
24 #include <asm/ppc_asm.h>
25 #include <asm/asm-offsets.h>
26 #include <asm/cputable.h>
27 #include <asm/thread_info.h>
43 #ifdef CONFIG_IRQSTACKS
44 _GLOBAL(call_do_softirq)
47 stdu r1,THREAD_SIZE-112(r3)
55 _GLOBAL(call___do_IRQ)
58 stdu r1,THREAD_SIZE-112(r5)
65 #endif /* CONFIG_IRQSTACKS */
69 .tc ppc64_caches[TC],ppc64_caches
73 * Write any modified data cache blocks out to memory
74 * and invalidate the corresponding instruction cache blocks.
76 * flush_icache_range(unsigned long start, unsigned long stop)
78 * flush all bytes from start through stop-1 inclusive
81 _KPROBE(__flush_icache_range)
84 * Flush the data cache to memory
86 * Different systems have different cache line sizes
87 * and in some cases i-cache and d-cache line sizes differ from
90 ld r10,PPC64_CACHES@toc(r2)
91 lwz r7,DCACHEL1LINESIZE(r10)/* Get cache line size */
93 andc r6,r3,r5 /* round low to line bdy */
94 subf r8,r6,r4 /* compute length */
95 add r8,r8,r5 /* ensure we get enough */
96 lwz r9,DCACHEL1LOGLINESIZE(r10) /* Get log-2 of cache line size */
97 srw. r8,r8,r9 /* compute line count */
98 beqlr /* nothing to do? */
105 /* Now invalidate the instruction cache */
107 lwz r7,ICACHEL1LINESIZE(r10) /* Get Icache line size */
109 andc r6,r3,r5 /* round low to line bdy */
110 subf r8,r6,r4 /* compute length */
112 lwz r9,ICACHEL1LOGLINESIZE(r10) /* Get log-2 of Icache line size */
113 srw. r8,r8,r9 /* compute line count */
114 beqlr /* nothing to do? */
123 * Like above, but only do the D-cache.
125 * flush_dcache_range(unsigned long start, unsigned long stop)
127 * flush all bytes from start to stop-1 inclusive
129 _GLOBAL(flush_dcache_range)
132 * Flush the data cache to memory
134 * Different systems have different cache line sizes
136 ld r10,PPC64_CACHES@toc(r2)
137 lwz r7,DCACHEL1LINESIZE(r10) /* Get dcache line size */
139 andc r6,r3,r5 /* round low to line bdy */
140 subf r8,r6,r4 /* compute length */
141 add r8,r8,r5 /* ensure we get enough */
142 lwz r9,DCACHEL1LOGLINESIZE(r10) /* Get log-2 of dcache line size */
143 srw. r8,r8,r9 /* compute line count */
144 beqlr /* nothing to do? */
153 * Like above, but works on non-mapped physical addresses.
154 * Use only for non-LPAR setups ! It also assumes real mode
155 * is cacheable. Used for flushing out the DART before using
156 * it as uncacheable memory
158 * flush_dcache_phys_range(unsigned long start, unsigned long stop)
160 * flush all bytes from start to stop-1 inclusive
162 _GLOBAL(flush_dcache_phys_range)
163 ld r10,PPC64_CACHES@toc(r2)
164 lwz r7,DCACHEL1LINESIZE(r10) /* Get dcache line size */
166 andc r6,r3,r5 /* round low to line bdy */
167 subf r8,r6,r4 /* compute length */
168 add r8,r8,r5 /* ensure we get enough */
169 lwz r9,DCACHEL1LOGLINESIZE(r10) /* Get log-2 of dcache line size */
170 srw. r8,r8,r9 /* compute line count */
171 beqlr /* nothing to do? */
172 mfmsr r5 /* Disable MMU Data Relocation */
185 mtmsr r5 /* Re-enable MMU Data Relocation */
190 _GLOBAL(flush_inval_dcache_range)
191 ld r10,PPC64_CACHES@toc(r2)
192 lwz r7,DCACHEL1LINESIZE(r10) /* Get dcache line size */
194 andc r6,r3,r5 /* round low to line bdy */
195 subf r8,r6,r4 /* compute length */
196 add r8,r8,r5 /* ensure we get enough */
197 lwz r9,DCACHEL1LOGLINESIZE(r10)/* Get log-2 of dcache line size */
198 srw. r8,r8,r9 /* compute line count */
199 beqlr /* nothing to do? */
212 * Flush a particular page from the data cache to RAM.
213 * Note: this is necessary because the instruction cache does *not*
214 * snoop from the data cache.
216 * void __flush_dcache_icache(void *page)
218 _GLOBAL(__flush_dcache_icache)
220 * Flush the data cache to memory
222 * Different systems have different cache line sizes
225 /* Flush the dcache */
226 ld r7,PPC64_CACHES@toc(r2)
227 clrrdi r3,r3,PAGE_SHIFT /* Page align */
228 lwz r4,DCACHEL1LINESPERPAGE(r7) /* Get # dcache lines per page */
229 lwz r5,DCACHEL1LINESIZE(r7) /* Get dcache line size */
237 /* Now invalidate the icache */
239 lwz r4,ICACHEL1LINESPERPAGE(r7) /* Get # icache lines per page */
240 lwz r5,ICACHEL1LINESIZE(r7) /* Get icache line size */
249 * identify_cpu and calls setup_cpu
250 * In: r3 = base of the cpu_specs array
251 * r4 = address of cur_cpu_spec
252 * r5 = relocation offset
254 _GLOBAL(identify_cpu)
257 lwz r8,CPU_SPEC_PVR_MASK(r3)
259 lwz r9,CPU_SPEC_PVR_VALUE(r3)
262 addi r3,r3,CPU_SPEC_ENTRY_SIZE
267 ld r4,CPU_SPEC_SETUP(r3)
274 /* Calling convention for cpu setup is r3=offset, r4=cur_cpu_spec */
280 * do_cpu_ftr_fixups - goes through the list of CPU feature fixups
281 * and writes nop's over sections of code that don't apply for this cpu.
282 * r3 = data offset (not changed)
284 _GLOBAL(do_cpu_ftr_fixups)
285 /* Get CPU 0 features */
286 LOAD_REG_IMMEDIATE(r6,cur_cpu_spec)
290 ld r4,CPU_SPEC_FEATURES(r4)
291 /* Get the fixup table */
292 LOAD_REG_IMMEDIATE(r6,__start___ftr_fixup)
294 LOAD_REG_IMMEDIATE(r7,__stop___ftr_fixup)
300 ld r8,-32(r6) /* mask */
302 ld r9,-24(r6) /* value */
305 ld r8,-16(r6) /* section begin */
306 ld r9,-8(r6) /* section end */
309 /* write nops over the section of code */
310 /* todo: if large section, add a branch at the start of it */
314 lis r0,0x60000000@h /* nop */
316 andi. r10,r4,CPU_FTR_SPLIT_ID_CACHE@l
318 dcbst 0,r8 /* suboptimal, but simpler */
323 sync /* additional sync needed on g4 */
327 #if defined(CONFIG_PPC_PMAC) || defined(CONFIG_PPC_MAPLE)
329 * Do an IO access in real mode
360 * Do an IO access in real mode
389 #endif /* defined(CONFIG_PPC_PMAC) || defined(CONFIG_PPC_MAPLE) */
391 #ifdef CONFIG_CPU_FREQ_PMAC64
393 * SCOM access functions for 970 (FX only for now)
395 * unsigned long scom970_read(unsigned int address);
396 * void scom970_write(unsigned int address, unsigned long value);
398 * The address passed in is the 24 bits register address. This code
399 * is 970 specific and will not check the status bits, so you should
400 * know what you are doing.
402 _GLOBAL(scom970_read)
409 /* rotate 24 bits SCOM address 8 bits left and mask out it's low 8 bits
410 * (including parity). On current CPUs they must be 0'd,
411 * and finally or in RW bit
416 /* do the actual scom read */
425 /* XXX: fixup result on some buggy 970's (ouch ! we lost a bit, bah
426 * that's the best we can do). Not implemented yet as we don't use
427 * the scom on any of the bogus CPUs yet, but may have to be done
431 /* restore interrupts */
436 _GLOBAL(scom970_write)
443 /* rotate 24 bits SCOM address 8 bits left and mask out it's low 8 bits
444 * (including parity). On current CPUs they must be 0'd.
450 mtspr SPRN_SCOMD,r4 /* write data */
452 mtspr SPRN_SCOMC,r3 /* write command */
457 /* restore interrupts */
460 #endif /* CONFIG_CPU_FREQ_PMAC64 */
464 * Create a kernel thread
465 * kernel_thread(fn, arg, flags)
467 _GLOBAL(kernel_thread)
470 stdu r1,-STACK_FRAME_OVERHEAD(r1)
473 ori r3,r5,CLONE_VM /* flags */
474 oris r3,r3,(CLONE_UNTRACED>>16)
475 li r4,0 /* new sp (unused) */
478 cmpdi 0,r3,0 /* parent or child? */
479 bne 1f /* return if parent */
481 stdu r0,-STACK_FRAME_OVERHEAD(r1)
484 mtlr r29 /* fn addr in lr */
485 mr r3,r30 /* load arg and call fn */
487 li r0,__NR_exit /* exit after child exits */
490 1: addi r1,r1,STACK_FRAME_OVERHEAD
496 * disable_kernel_fp()
499 _GLOBAL(disable_kernel_fp)
501 rldicl r0,r3,(63-MSR_FP_LG),1
502 rldicl r3,r0,(MSR_FP_LG+1),0
503 mtmsrd r3 /* disable use of fpu now */
507 #ifdef CONFIG_ALTIVEC
509 #if 0 /* this has no callers for now */
511 * disable_kernel_altivec()
514 _GLOBAL(disable_kernel_altivec)
516 rldicl r0,r3,(63-MSR_VEC_LG),1
517 rldicl r3,r0,(MSR_VEC_LG+1),0
518 mtmsrd r3 /* disable use of VMX now */
524 * giveup_altivec(tsk)
525 * Disable VMX for the task given as the argument,
526 * and save the vector registers in its thread_struct.
527 * Enables the VMX for use in the kernel on return.
529 _GLOBAL(giveup_altivec)
532 mtmsrd r5 /* enable use of VMX now */
535 beqlr- /* if no previous owner, done */
536 addi r3,r3,THREAD /* want THREAD of task */
544 ld r4,_MSR-STACK_FRAME_OVERHEAD(r5)
546 andc r4,r4,r3 /* disable FP for previous task */
547 std r4,_MSR-STACK_FRAME_OVERHEAD(r5)
551 ld r4,last_task_used_altivec@got(r2)
553 #endif /* CONFIG_SMP */
556 #endif /* CONFIG_ALTIVEC */
565 /* kexec_wait(phys_cpu)
567 * wait for the flag to change, indicating this kernel is going away but
568 * the slave code for the next one is at addresses 0 to 100.
570 * This is used by all slaves.
572 * Physical (hardware) cpu id should be in r3.
577 addi r5,r5,kexec_flag-1b
580 #ifdef CONFIG_KEXEC /* use no memory without kexec */
587 /* this can be in text because we won't change it until we are
588 * running in real anyways
596 /* kexec_smp_wait(void)
598 * call with interrupts off
599 * note: this is a terminal routine, it does not save lr
601 * get phys id from paca
602 * set paca id to -1 to say we got here
603 * switch to real mode
604 * join other cpus in kexec_wait(phys_id)
606 _GLOBAL(kexec_smp_wait)
607 lhz r3,PACAHWCPUID(r13)
609 sth r4,PACAHWCPUID(r13) /* let others know we left */
614 * switch to real mode (turn mmu off)
615 * we use the early kernel trick that the hardware ignores bits
616 * 0 and 1 (big endian) of the effective address in real mode
618 * don't overwrite r3 here, it is live for kexec_wait above.
620 real_mode: /* assume normal blr return */
623 mflr r11 /* return address to SRR0 */
635 * kexec_sequence(newstack, start, image, control, clear_all())
637 * does the grungy work with stack switching and real mode switches
638 * also does simple calls to other code
641 _GLOBAL(kexec_sequence)
645 /* switch stacks to newstack -- &kexec_stack.stack */
646 stdu r1,THREAD_SIZE-112(r3)
652 /* save regs for local vars on new stack.
653 * yes, we won't go back, but ...
665 /* save args into preserved regs */
666 mr r31,r3 /* newstack (both) */
667 mr r30,r4 /* start (real) */
668 mr r29,r5 /* image (virt) */
669 mr r28,r6 /* control, unused */
670 mr r27,r7 /* clear_all() fn desc */
671 mr r26,r8 /* spare */
672 lhz r25,PACAHWCPUID(r13) /* get our phys cpu from paca */
674 /* disable interrupts, we are overwriting kernel data next */
679 /* copy dest pages, flush whole dest image */
681 bl .kexec_copy_flush /* (image) */
686 /* clear out hardware hash page table and tlb */
687 ld r5,0(r27) /* deref function descriptor */
689 bctrl /* ppc_md.hash_clear_all(void); */
692 * kexec image calling is:
693 * the first 0x100 bytes of the entry point are copied to 0
695 * all slaves branch to slave = 0x60 (absolute)
696 * slave(phys_cpu_id);
698 * master goes to start = entry point
699 * start(phys_cpu_id, start, 0);
702 * a wrapper is needed to call existing kernels, here is an approximate
703 * description of one method:
706 * start will be near the boot_block (maybe 0x100 bytes before it?)
707 * it will have a 0x60, which will b to boot_block, where it will wait
708 * and 0 will store phys into struct boot-block and load r3 from there,
709 * copy kernel 0-0x100 and tell slaves to back down to 0x60 again
712 * boot block will have all cpus scanning device tree to see if they
713 * are the boot cpu ?????
714 * other device tree differences (prop sizes, va vs pa, etc)...
717 /* copy 0x100 bytes starting at start to 0 */
722 bl .copy_and_flush /* (dest, src, copy limit, start offset) */
723 1: /* assume normal blr return */
725 /* release other cpus to the new kernel secondary start at 0x60 */
728 stw r6,kexec_flag-1b(5)
729 mr r3,r25 # my phys cpu
730 mr r4,r30 # start, aka phys mem offset
733 blr /* image->start(physid, image->start, 0); */
734 #endif /* CONFIG_KEXEC */