git.oblomov.eu Git - linux-2.6/blob - drivers/gpu/drm/radeon/radeon_irq.c

   1 /* radeon_irq.c -- IRQ handling for radeon -*- linux-c -*- */
   2 /*
   3  * Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   4  *
   5  * The Weather Channel (TM) funded Tungsten Graphics to develop the
   6  * initial release of the Radeon 8500 driver under the XFree86 license.
   7  * This notice must be preserved.
   8  *
   9  * Permission is hereby granted, free of charge, to any person obtaining a
  10  * copy of this software and associated documentation files (the "Software"),
  11  * to deal in the Software without restriction, including without limitation
  12  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  13  * and/or sell copies of the Software, and to permit persons to whom the
  14  * Software is furnished to do so, subject to the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the next
  17  * paragraph) shall be included in all copies or substantial portions of the
  18  * Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  21  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  22  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  23  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  24  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  25  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  26  * DEALINGS IN THE SOFTWARE.
  27  *
  28  * Authors:
  29  *    Keith Whitwell <keith@tungstengraphics.com>
  30  *    Michel D�zer <michel@daenzer.net>
  31  */
  32
  33 #include "drmP.h"
  34 #include "drm.h"
  35 #include "radeon_drm.h"
  36 #include "radeon_drv.h"
  37
  38 void radeon_irq_set_state(struct drm_device *dev, u32 mask, int state)
  39 {
  40         drm_radeon_private_t *dev_priv = dev->dev_private;
  41
  42         if (state)
  43                 dev_priv->irq_enable_reg |= mask;
  44         else
  45                 dev_priv->irq_enable_reg &= ~mask;
  46
  47         RADEON_WRITE(RADEON_GEN_INT_CNTL, dev_priv->irq_enable_reg);
  48 }
  49
  50 static void r500_vbl_irq_set_state(struct drm_device *dev, u32 mask, int state)
  51 {
  52         drm_radeon_private_t *dev_priv = dev->dev_private;
  53
  54         if (state)
  55                 dev_priv->r500_disp_irq_reg |= mask;
  56         else
  57                 dev_priv->r500_disp_irq_reg &= ~mask;
  58
  59         RADEON_WRITE(R500_DxMODE_INT_MASK, dev_priv->r500_disp_irq_reg);
  60 }
  61
  62 int radeon_enable_vblank(struct drm_device *dev, int crtc)
  63 {
  64         drm_radeon_private_t *dev_priv = dev->dev_private;
  65
  66         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS690) {
  67                 switch (crtc) {
  68                 case 0:
  69                         r500_vbl_irq_set_state(dev, R500_D1MODE_INT_MASK, 1);
  70                         break;
  71                 case 1:
  72                         r500_vbl_irq_set_state(dev, R500_D2MODE_INT_MASK, 1);
  73                         break;
  74                 default:
  75                         DRM_ERROR("tried to enable vblank on non-existent crtc %d\n",
  76                                   crtc);
  77                         return EINVAL;
  78                 }
  79         } else {
  80                 switch (crtc) {
  81                 case 0:
  82                         radeon_irq_set_state(dev, RADEON_CRTC_VBLANK_MASK, 1);
  83                         break;
  84                 case 1:
  85                         radeon_irq_set_state(dev, RADEON_CRTC2_VBLANK_MASK, 1);
  86                         break;
  87                 default:
  88                         DRM_ERROR("tried to enable vblank on non-existent crtc %d\n",
  89                                   crtc);
  90                         return EINVAL;
  91                 }
  92         }
  93
  94         return 0;
  95 }
  96
  97 void radeon_disable_vblank(struct drm_device *dev, int crtc)
  98 {
  99         drm_radeon_private_t *dev_priv = dev->dev_private;
 100
 101         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS690) {
 102                 switch (crtc) {
 103                 case 0:
 104                         r500_vbl_irq_set_state(dev, R500_D1MODE_INT_MASK, 0);
 105                         break;
 106                 case 1:
 107                         r500_vbl_irq_set_state(dev, R500_D2MODE_INT_MASK, 0);
 108                         break;
 109                 default:
 110                         DRM_ERROR("tried to enable vblank on non-existent crtc %d\n",
 111                                   crtc);
 112                         break;
 113                 }
 114         } else {
 115                 switch (crtc) {
 116                 case 0:
 117                         radeon_irq_set_state(dev, RADEON_CRTC_VBLANK_MASK, 0);
 118                         break;
 119                 case 1:
 120                         radeon_irq_set_state(dev, RADEON_CRTC2_VBLANK_MASK, 0);
 121                         break;
 122                 default:
 123                         DRM_ERROR("tried to enable vblank on non-existent crtc %d\n",
 124                                   crtc);
 125                         break;
 126                 }
 127         }
 128 }
 129
 130 static inline u32 radeon_acknowledge_irqs(drm_radeon_private_t *dev_priv, u32 *r500_disp_int)
 131 {
 132         u32 irqs = RADEON_READ(RADEON_GEN_INT_STATUS);
 133         u32 irq_mask = RADEON_SW_INT_TEST;
 134
 135         *r500_disp_int = 0;
 136         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS690) {
 137                 /* vbl interrupts in a different place */
 138
 139                 if (irqs & R500_DISPLAY_INT_STATUS) {
 140                         /* if a display interrupt */
 141                         u32 disp_irq;
 142
 143                         disp_irq = RADEON_READ(R500_DISP_INTERRUPT_STATUS);
 144
 145                         *r500_disp_int = disp_irq;
 146                         if (disp_irq & R500_D1_VBLANK_INTERRUPT)
 147                                 RADEON_WRITE(R500_D1MODE_VBLANK_STATUS, R500_VBLANK_ACK);
 148                         if (disp_irq & R500_D2_VBLANK_INTERRUPT)
 149                                 RADEON_WRITE(R500_D2MODE_VBLANK_STATUS, R500_VBLANK_ACK);
 150                 }
 151                 irq_mask |= R500_DISPLAY_INT_STATUS;
 152         } else
 153                 irq_mask |= RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT;
 154
 155         irqs &= irq_mask;
 156
 157         if (irqs)
 158                 RADEON_WRITE(RADEON_GEN_INT_STATUS, irqs);
 159
 160         return irqs;
 161 }
 162
 163 /* Interrupts - Used for device synchronization and flushing in the
 164  * following circumstances:
 165  *
 166  * - Exclusive FB access with hw idle:
 167  *    - Wait for GUI Idle (?) interrupt, then do normal flush.
 168  *
 169  * - Frame throttling, NV_fence:
 170  *    - Drop marker irq's into command stream ahead of time.
 171  *    - Wait on irq's with lock *not held*
 172  *    - Check each for termination condition
 173  *
 174  * - Internally in cp_getbuffer, etc:
 175  *    - as above, but wait with lock held???
 176  *
 177  * NOTE: These functions are misleadingly named -- the irq's aren't
 178  * tied to dma at all, this is just a hangover from dri prehistory.
 179  */
 180
 181 irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS)
 182 {
 183         struct drm_device *dev = (struct drm_device *) arg;
 184         drm_radeon_private_t *dev_priv =
 185             (drm_radeon_private_t *) dev->dev_private;
 186         u32 stat;
 187         u32 r500_disp_int;
 188
 189         /* Only consider the bits we're interested in - others could be used
 190          * outside the DRM
 191          */
 192         stat = radeon_acknowledge_irqs(dev_priv, &r500_disp_int);
 193         if (!stat)
 194                 return IRQ_NONE;
 195
 196         stat &= dev_priv->irq_enable_reg;
 197
 198         /* SW interrupt */
 199         if (stat & RADEON_SW_INT_TEST)
 200                 DRM_WAKEUP(&dev_priv->swi_queue);
 201
 202         /* VBLANK interrupt */
 203         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS690) {
 204                 if (r500_disp_int & R500_D1_VBLANK_INTERRUPT)
 205                         drm_handle_vblank(dev, 0);
 206                 if (r500_disp_int & R500_D2_VBLANK_INTERRUPT)
 207                         drm_handle_vblank(dev, 1);
 208         } else {
 209                 if (stat & RADEON_CRTC_VBLANK_STAT)
 210                         drm_handle_vblank(dev, 0);
 211                 if (stat & RADEON_CRTC2_VBLANK_STAT)
 212                         drm_handle_vblank(dev, 1);
 213         }
 214         return IRQ_HANDLED;
 215 }
 216
 217 static int radeon_emit_irq(struct drm_device * dev)
 218 {
 219         drm_radeon_private_t *dev_priv = dev->dev_private;
 220         unsigned int ret;
 221         RING_LOCALS;
 222
 223         atomic_inc(&dev_priv->swi_emitted);
 224         ret = atomic_read(&dev_priv->swi_emitted);
 225
 226         BEGIN_RING(4);
 227         OUT_RING_REG(RADEON_LAST_SWI_REG, ret);
 228         OUT_RING_REG(RADEON_GEN_INT_STATUS, RADEON_SW_INT_FIRE);
 229         ADVANCE_RING();
 230         COMMIT_RING();
 231
 232         return ret;
 233 }
 234
 235 static int radeon_wait_irq(struct drm_device * dev, int swi_nr)
 236 {
 237         drm_radeon_private_t *dev_priv =
 238             (drm_radeon_private_t *) dev->dev_private;
 239         int ret = 0;
 240
 241         if (RADEON_READ(RADEON_LAST_SWI_REG) >= swi_nr)
 242                 return 0;
 243
 244         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 245
 246         DRM_WAIT_ON(ret, dev_priv->swi_queue, 3 * DRM_HZ,
 247                     RADEON_READ(RADEON_LAST_SWI_REG) >= swi_nr);
 248
 249         return ret;
 250 }
 251
 252 u32 radeon_get_vblank_counter(struct drm_device *dev, int crtc)
 253 {
 254         drm_radeon_private_t *dev_priv = dev->dev_private;
 255
 256         if (!dev_priv) {
 257                 DRM_ERROR("called with no initialization\n");
 258                 return -EINVAL;
 259         }
 260
 261         if (crtc < 0 || crtc > 1) {
 262                 DRM_ERROR("Invalid crtc %d\n", crtc);
 263                 return -EINVAL;
 264         }
 265
 266         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS690) {
 267                 if (crtc == 0)
 268                         return RADEON_READ(R500_D1CRTC_FRAME_COUNT);
 269                 else
 270                         return RADEON_READ(R500_D2CRTC_FRAME_COUNT);
 271         } else {
 272                 if (crtc == 0)
 273                         return RADEON_READ(RADEON_CRTC_CRNT_FRAME);
 274                 else
 275                         return RADEON_READ(RADEON_CRTC2_CRNT_FRAME);
 276         }
 277 }
 278
 279 /* Needs the lock as it touches the ring.
 280  */
 281 int radeon_irq_emit(struct drm_device *dev, void *data, struct drm_file *file_priv)
 282 {
 283         drm_radeon_private_t *dev_priv = dev->dev_private;
 284         drm_radeon_irq_emit_t *emit = data;
 285         int result;
 286
 287         LOCK_TEST_WITH_RETURN(dev, file_priv);
 288
 289         if (!dev_priv) {
 290                 DRM_ERROR("called with no initialization\n");
 291                 return -EINVAL;
 292         }
 293
 294         result = radeon_emit_irq(dev);
 295
 296         if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
 297                 DRM_ERROR("copy_to_user\n");
 298                 return -EFAULT;
 299         }
 300
 301         return 0;
 302 }
 303
 304 /* Doesn't need the hardware lock.
 305  */
 306 int radeon_irq_wait(struct drm_device *dev, void *data, struct drm_file *file_priv)
 307 {
 308         drm_radeon_private_t *dev_priv = dev->dev_private;
 309         drm_radeon_irq_wait_t *irqwait = data;
 310
 311         if (!dev_priv) {
 312                 DRM_ERROR("called with no initialization\n");
 313                 return -EINVAL;
 314         }
 315
 316         return radeon_wait_irq(dev, irqwait->irq_seq);
 317 }
 318
 319 /* drm_dma.h hooks
 320 */
 321 void radeon_driver_irq_preinstall(struct drm_device * dev)
 322 {
 323         drm_radeon_private_t *dev_priv =
 324             (drm_radeon_private_t *) dev->dev_private;
 325         u32 dummy;
 326
 327         /* Disable *all* interrupts */
 328         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS690)
 329                 RADEON_WRITE(R500_DxMODE_INT_MASK, 0);
 330         RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
 331
 332         /* Clear bits if they're already high */
 333         radeon_acknowledge_irqs(dev_priv, &dummy);
 334 }
 335
 336 int radeon_driver_irq_postinstall(struct drm_device *dev)
 337 {
 338         drm_radeon_private_t *dev_priv =
 339             (drm_radeon_private_t *) dev->dev_private;
 340         int ret;
 341
 342         atomic_set(&dev_priv->swi_emitted, 0);
 343         DRM_INIT_WAITQUEUE(&dev_priv->swi_queue);
 344
 345         ret = drm_vblank_init(dev, 2);
 346         if (ret)
 347                 return ret;
 348
 349         dev->max_vblank_count = 0x001fffff;
 350
 351         radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1);
 352
 353         return 0;
 354 }
 355
 356 void radeon_driver_irq_uninstall(struct drm_device * dev)
 357 {
 358         drm_radeon_private_t *dev_priv =
 359             (drm_radeon_private_t *) dev->dev_private;
 360         if (!dev_priv)
 361                 return;
 362
 363         dev_priv->irq_enabled = 0;
 364
 365         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS690)
 366                 RADEON_WRITE(R500_DxMODE_INT_MASK, 0);
 367         /* Disable *all* interrupts */
 368         RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
 369 }
 370
 371
 372 int radeon_vblank_crtc_get(struct drm_device *dev)
 373 {
 374         drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private;
 375
 376         return dev_priv->vblank_crtc;
 377 }
 378
 379 int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value)
 380 {
 381         drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private;
 382         if (value & ~(DRM_RADEON_VBLANK_CRTC1 | DRM_RADEON_VBLANK_CRTC2)) {
 383                 DRM_ERROR("called with invalid crtc 0x%x\n", (unsigned int)value);
 384                 return -EINVAL;
 385         }
 386         dev_priv->vblank_crtc = (unsigned int)value;
 387         return 0;
 388 }