4 * Support for VIA PadLock hardware crypto engine.
6 * Copyright (c) 2004 Michal Ludvig <michal@logix.cz>
8 * Key expansion routine taken from crypto/aes.c
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * ---------------------------------------------------------------------------
16 * Copyright (c) 2002, Dr Brian Gladman <brg@gladman.me.uk>, Worcester, UK.
17 * All rights reserved.
21 * The free distribution and use of this software in both source and binary
22 * form is allowed (with or without changes) provided that:
24 * 1. distributions of this source code include the above copyright
25 * notice, this list of conditions and the following disclaimer;
27 * 2. distributions in binary form include the above copyright
28 * notice, this list of conditions and the following disclaimer
29 * in the documentation and/or other associated materials;
31 * 3. the copyright holder's name is not used to endorse products
32 * built using this software without specific written permission.
34 * ALTERNATIVELY, provided that this notice is retained in full, this product
35 * may be distributed under the terms of the GNU General Public License (GPL),
36 * in which case the provisions of the GPL apply INSTEAD OF those given above.
40 * This software is provided 'as is' with no explicit or implied warranties
41 * in respect of its properties, including, but not limited to, correctness
42 * and/or fitness for purpose.
43 * ---------------------------------------------------------------------------
46 #include <linux/module.h>
47 #include <linux/init.h>
48 #include <linux/types.h>
49 #include <linux/errno.h>
50 #include <linux/crypto.h>
51 #include <linux/interrupt.h>
52 #include <linux/kernel.h>
53 #include <asm/byteorder.h>
56 #define AES_MIN_KEY_SIZE 16 /* in uint8_t units */
57 #define AES_MAX_KEY_SIZE 32 /* ditto */
58 #define AES_BLOCK_SIZE 16 /* ditto */
59 #define AES_EXTENDED_KEY_SIZE 64 /* in uint32_t units */
60 #define AES_EXTENDED_KEY_SIZE_B (AES_EXTENDED_KEY_SIZE * sizeof(uint32_t))
64 unsigned int __attribute__ ((__packed__))
71 } __attribute__ ((__aligned__(PADLOCK_ALIGNMENT)));
73 /* Whenever making any changes to the following
74 * structure *make sure* you keep E, d_data
75 * and cword aligned on 16 Bytes boundaries!!! */
83 u32 E[AES_EXTENDED_KEY_SIZE]
84 __attribute__ ((__aligned__(PADLOCK_ALIGNMENT)));
85 u32 d_data[AES_EXTENDED_KEY_SIZE]
86 __attribute__ ((__aligned__(PADLOCK_ALIGNMENT)));
89 /* ====== Key management routines ====== */
91 static inline uint32_t
92 generic_rotr32 (const uint32_t x, const unsigned bits)
94 const unsigned n = bits % 32;
95 return (x >> n) | (x << (32 - n));
98 static inline uint32_t
99 generic_rotl32 (const uint32_t x, const unsigned bits)
101 const unsigned n = bits % 32;
102 return (x << n) | (x >> (32 - n));
105 #define rotl generic_rotl32
106 #define rotr generic_rotr32
109 * #define byte(x, nr) ((unsigned char)((x) >> (nr*8)))
111 static inline uint8_t
112 byte(const uint32_t x, const unsigned n)
114 return x >> (n << 3);
120 static uint8_t pow_tab[256];
121 static uint8_t log_tab[256];
122 static uint8_t sbx_tab[256];
123 static uint8_t isb_tab[256];
124 static uint32_t rco_tab[10];
125 static uint32_t ft_tab[4][256];
126 static uint32_t it_tab[4][256];
128 static uint32_t fl_tab[4][256];
129 static uint32_t il_tab[4][256];
131 static inline uint8_t
132 f_mult (uint8_t a, uint8_t b)
134 uint8_t aa = log_tab[a], cc = aa + log_tab[b];
136 return pow_tab[cc + (cc < aa ? 1 : 0)];
139 #define ff_mult(a,b) (a && b ? f_mult(a, b) : 0)
141 #define f_rn(bo, bi, n, k) \
142 bo[n] = ft_tab[0][byte(bi[n],0)] ^ \
143 ft_tab[1][byte(bi[(n + 1) & 3],1)] ^ \
144 ft_tab[2][byte(bi[(n + 2) & 3],2)] ^ \
145 ft_tab[3][byte(bi[(n + 3) & 3],3)] ^ *(k + n)
147 #define i_rn(bo, bi, n, k) \
148 bo[n] = it_tab[0][byte(bi[n],0)] ^ \
149 it_tab[1][byte(bi[(n + 3) & 3],1)] ^ \
150 it_tab[2][byte(bi[(n + 2) & 3],2)] ^ \
151 it_tab[3][byte(bi[(n + 1) & 3],3)] ^ *(k + n)
154 ( fl_tab[0][byte(x, 0)] ^ \
155 fl_tab[1][byte(x, 1)] ^ \
156 fl_tab[2][byte(x, 2)] ^ \
157 fl_tab[3][byte(x, 3)] )
159 #define f_rl(bo, bi, n, k) \
160 bo[n] = fl_tab[0][byte(bi[n],0)] ^ \
161 fl_tab[1][byte(bi[(n + 1) & 3],1)] ^ \
162 fl_tab[2][byte(bi[(n + 2) & 3],2)] ^ \
163 fl_tab[3][byte(bi[(n + 3) & 3],3)] ^ *(k + n)
165 #define i_rl(bo, bi, n, k) \
166 bo[n] = il_tab[0][byte(bi[n],0)] ^ \
167 il_tab[1][byte(bi[(n + 3) & 3],1)] ^ \
168 il_tab[2][byte(bi[(n + 2) & 3],2)] ^ \
169 il_tab[3][byte(bi[(n + 1) & 3],3)] ^ *(k + n)
177 /* log and power tables for GF(2**8) finite field with
178 0x011b as modular polynomial - the simplest prmitive
179 root is 0x03, used here to generate the tables */
181 for (i = 0, p = 1; i < 256; ++i) {
182 pow_tab[i] = (uint8_t) p;
183 log_tab[p] = (uint8_t) i;
185 p ^= (p << 1) ^ (p & 0x80 ? 0x01b : 0);
190 for (i = 0, p = 1; i < 10; ++i) {
193 p = (p << 1) ^ (p & 0x80 ? 0x01b : 0);
196 for (i = 0; i < 256; ++i) {
197 p = (i ? pow_tab[255 - log_tab[i]] : 0);
198 q = ((p >> 7) | (p << 1)) ^ ((p >> 6) | (p << 2));
199 p ^= 0x63 ^ q ^ ((q >> 6) | (q << 2));
201 isb_tab[p] = (uint8_t) i;
204 for (i = 0; i < 256; ++i) {
209 fl_tab[1][i] = rotl (t, 8);
210 fl_tab[2][i] = rotl (t, 16);
211 fl_tab[3][i] = rotl (t, 24);
213 t = ((uint32_t) ff_mult (2, p)) |
214 ((uint32_t) p << 8) |
215 ((uint32_t) p << 16) | ((uint32_t) ff_mult (3, p) << 24);
218 ft_tab[1][i] = rotl (t, 8);
219 ft_tab[2][i] = rotl (t, 16);
220 ft_tab[3][i] = rotl (t, 24);
226 il_tab[1][i] = rotl (t, 8);
227 il_tab[2][i] = rotl (t, 16);
228 il_tab[3][i] = rotl (t, 24);
230 t = ((uint32_t) ff_mult (14, p)) |
231 ((uint32_t) ff_mult (9, p) << 8) |
232 ((uint32_t) ff_mult (13, p) << 16) |
233 ((uint32_t) ff_mult (11, p) << 24);
236 it_tab[1][i] = rotl (t, 8);
237 it_tab[2][i] = rotl (t, 16);
238 it_tab[3][i] = rotl (t, 24);
242 #define star_x(x) (((x) & 0x7f7f7f7f) << 1) ^ ((((x) & 0x80808080) >> 7) * 0x1b)
244 #define imix_col(y,x) \
250 (y) ^= rotr(u ^ t, 8) ^ \
254 /* initialise the key schedule from the user supplied key */
257 { t = rotr(t, 8); t = ls_box(t) ^ rco_tab[i]; \
258 t ^= E_KEY[4 * i]; E_KEY[4 * i + 4] = t; \
259 t ^= E_KEY[4 * i + 1]; E_KEY[4 * i + 5] = t; \
260 t ^= E_KEY[4 * i + 2]; E_KEY[4 * i + 6] = t; \
261 t ^= E_KEY[4 * i + 3]; E_KEY[4 * i + 7] = t; \
265 { t = rotr(t, 8); t = ls_box(t) ^ rco_tab[i]; \
266 t ^= E_KEY[6 * i]; E_KEY[6 * i + 6] = t; \
267 t ^= E_KEY[6 * i + 1]; E_KEY[6 * i + 7] = t; \
268 t ^= E_KEY[6 * i + 2]; E_KEY[6 * i + 8] = t; \
269 t ^= E_KEY[6 * i + 3]; E_KEY[6 * i + 9] = t; \
270 t ^= E_KEY[6 * i + 4]; E_KEY[6 * i + 10] = t; \
271 t ^= E_KEY[6 * i + 5]; E_KEY[6 * i + 11] = t; \
275 { t = rotr(t, 8); ; t = ls_box(t) ^ rco_tab[i]; \
276 t ^= E_KEY[8 * i]; E_KEY[8 * i + 8] = t; \
277 t ^= E_KEY[8 * i + 1]; E_KEY[8 * i + 9] = t; \
278 t ^= E_KEY[8 * i + 2]; E_KEY[8 * i + 10] = t; \
279 t ^= E_KEY[8 * i + 3]; E_KEY[8 * i + 11] = t; \
280 t = E_KEY[8 * i + 4] ^ ls_box(t); \
281 E_KEY[8 * i + 12] = t; \
282 t ^= E_KEY[8 * i + 5]; E_KEY[8 * i + 13] = t; \
283 t ^= E_KEY[8 * i + 6]; E_KEY[8 * i + 14] = t; \
284 t ^= E_KEY[8 * i + 7]; E_KEY[8 * i + 15] = t; \
287 /* Tells whether the ACE is capable to generate
288 the extended key for a given key_len. */
290 aes_hw_extkey_available(uint8_t key_len)
292 /* TODO: We should check the actual CPU model/stepping
293 as it's possible that the capability will be
294 added in the next CPU revisions. */
300 static inline struct aes_ctx *aes_ctx(struct crypto_tfm *tfm)
302 unsigned long addr = (unsigned long)crypto_tfm_ctx(tfm);
303 unsigned long align = PADLOCK_ALIGNMENT;
305 if (align <= crypto_tfm_ctx_alignment())
307 return (struct aes_ctx *)ALIGN(addr, align);
310 static int aes_set_key(struct crypto_tfm *tfm, const u8 *in_key,
311 unsigned int key_len)
313 struct aes_ctx *ctx = aes_ctx(tfm);
314 const __le32 *key = (const __le32 *)in_key;
315 u32 *flags = &tfm->crt_flags;
316 uint32_t i, t, u, v, w;
317 uint32_t P[AES_EXTENDED_KEY_SIZE];
321 *flags |= CRYPTO_TFM_RES_BAD_KEY_LEN;
325 ctx->key_length = key_len;
328 * If the hardware is capable of generating the extended key
329 * itself we must supply the plain key for both encryption
334 E_KEY[0] = le32_to_cpu(key[0]);
335 E_KEY[1] = le32_to_cpu(key[1]);
336 E_KEY[2] = le32_to_cpu(key[2]);
337 E_KEY[3] = le32_to_cpu(key[3]);
339 /* Prepare control words. */
340 memset(&ctx->cword, 0, sizeof(ctx->cword));
342 ctx->cword.decrypt.encdec = 1;
343 ctx->cword.encrypt.rounds = 10 + (key_len - 16) / 4;
344 ctx->cword.decrypt.rounds = ctx->cword.encrypt.rounds;
345 ctx->cword.encrypt.ksize = (key_len - 16) / 8;
346 ctx->cword.decrypt.ksize = ctx->cword.encrypt.ksize;
348 /* Don't generate extended keys if the hardware can do it. */
349 if (aes_hw_extkey_available(key_len))
352 ctx->D = ctx->d_data;
353 ctx->cword.encrypt.keygen = 1;
354 ctx->cword.decrypt.keygen = 1;
359 for (i = 0; i < 10; ++i)
364 E_KEY[4] = le32_to_cpu(key[4]);
365 t = E_KEY[5] = le32_to_cpu(key[5]);
366 for (i = 0; i < 8; ++i)
371 E_KEY[4] = le32_to_cpu(key[4]);
372 E_KEY[5] = le32_to_cpu(key[5]);
373 E_KEY[6] = le32_to_cpu(key[6]);
374 t = E_KEY[7] = le32_to_cpu(key[7]);
375 for (i = 0; i < 7; ++i)
385 for (i = 4; i < key_len + 24; ++i) {
386 imix_col (D_KEY[i], E_KEY[i]);
389 /* PadLock needs a different format of the decryption key. */
390 rounds = 10 + (key_len - 16) / 4;
392 for (i = 0; i < rounds; i++) {
393 P[((i + 1) * 4) + 0] = D_KEY[((rounds - i - 1) * 4) + 0];
394 P[((i + 1) * 4) + 1] = D_KEY[((rounds - i - 1) * 4) + 1];
395 P[((i + 1) * 4) + 2] = D_KEY[((rounds - i - 1) * 4) + 2];
396 P[((i + 1) * 4) + 3] = D_KEY[((rounds - i - 1) * 4) + 3];
399 P[0] = E_KEY[(rounds * 4) + 0];
400 P[1] = E_KEY[(rounds * 4) + 1];
401 P[2] = E_KEY[(rounds * 4) + 2];
402 P[3] = E_KEY[(rounds * 4) + 3];
404 memcpy(D_KEY, P, AES_EXTENDED_KEY_SIZE_B);
409 /* ====== Encryption/decryption routines ====== */
411 /* These are the real call to PadLock. */
412 static inline void padlock_xcrypt_ecb(const u8 *input, u8 *output, void *key,
413 void *control_word, u32 count)
415 asm volatile ("pushfl; popfl"); /* enforce key reload. */
416 asm volatile (".byte 0xf3,0x0f,0xa7,0xc8" /* rep xcryptecb */
417 : "+S"(input), "+D"(output)
418 : "d"(control_word), "b"(key), "c"(count));
421 static inline u8 *padlock_xcrypt_cbc(const u8 *input, u8 *output, void *key,
422 u8 *iv, void *control_word, u32 count)
424 /* Enforce key reload. */
425 asm volatile ("pushfl; popfl");
427 asm volatile (".byte 0xf3,0x0f,0xa7,0xd0"
428 : "+S" (input), "+D" (output), "+a" (iv)
429 : "d" (control_word), "b" (key), "c" (count));
433 static void aes_encrypt(struct crypto_tfm *tfm, u8 *out, const u8 *in)
435 struct aes_ctx *ctx = aes_ctx(tfm);
436 padlock_xcrypt_ecb(in, out, ctx->E, &ctx->cword.encrypt, 1);
439 static void aes_decrypt(struct crypto_tfm *tfm, u8 *out, const u8 *in)
441 struct aes_ctx *ctx = aes_ctx(tfm);
442 padlock_xcrypt_ecb(in, out, ctx->D, &ctx->cword.decrypt, 1);
445 static unsigned int aes_encrypt_ecb(const struct cipher_desc *desc, u8 *out,
446 const u8 *in, unsigned int nbytes)
448 struct aes_ctx *ctx = aes_ctx(desc->tfm);
449 padlock_xcrypt_ecb(in, out, ctx->E, &ctx->cword.encrypt,
450 nbytes / AES_BLOCK_SIZE);
451 return nbytes & ~(AES_BLOCK_SIZE - 1);
454 static unsigned int aes_decrypt_ecb(const struct cipher_desc *desc, u8 *out,
455 const u8 *in, unsigned int nbytes)
457 struct aes_ctx *ctx = aes_ctx(desc->tfm);
458 padlock_xcrypt_ecb(in, out, ctx->D, &ctx->cword.decrypt,
459 nbytes / AES_BLOCK_SIZE);
460 return nbytes & ~(AES_BLOCK_SIZE - 1);
463 static unsigned int aes_encrypt_cbc(const struct cipher_desc *desc, u8 *out,
464 const u8 *in, unsigned int nbytes)
466 struct aes_ctx *ctx = aes_ctx(desc->tfm);
469 iv = padlock_xcrypt_cbc(in, out, ctx->E, desc->info,
470 &ctx->cword.encrypt, nbytes / AES_BLOCK_SIZE);
471 memcpy(desc->info, iv, AES_BLOCK_SIZE);
473 return nbytes & ~(AES_BLOCK_SIZE - 1);
476 static unsigned int aes_decrypt_cbc(const struct cipher_desc *desc, u8 *out,
477 const u8 *in, unsigned int nbytes)
479 struct aes_ctx *ctx = aes_ctx(desc->tfm);
480 padlock_xcrypt_cbc(in, out, ctx->D, desc->info, &ctx->cword.decrypt,
481 nbytes / AES_BLOCK_SIZE);
482 return nbytes & ~(AES_BLOCK_SIZE - 1);
485 static struct crypto_alg aes_alg = {
487 .cra_driver_name = "aes-padlock",
488 .cra_priority = PADLOCK_CRA_PRIORITY,
489 .cra_flags = CRYPTO_ALG_TYPE_CIPHER,
490 .cra_blocksize = AES_BLOCK_SIZE,
491 .cra_ctxsize = sizeof(struct aes_ctx),
492 .cra_alignmask = PADLOCK_ALIGNMENT - 1,
493 .cra_module = THIS_MODULE,
494 .cra_list = LIST_HEAD_INIT(aes_alg.cra_list),
497 .cia_min_keysize = AES_MIN_KEY_SIZE,
498 .cia_max_keysize = AES_MAX_KEY_SIZE,
499 .cia_setkey = aes_set_key,
500 .cia_encrypt = aes_encrypt,
501 .cia_decrypt = aes_decrypt,
502 .cia_encrypt_ecb = aes_encrypt_ecb,
503 .cia_decrypt_ecb = aes_decrypt_ecb,
504 .cia_encrypt_cbc = aes_encrypt_cbc,
505 .cia_decrypt_cbc = aes_decrypt_cbc,
510 static int __init padlock_init(void)
514 if (!cpu_has_xcrypt) {
515 printk(KERN_ERR PFX "VIA PadLock not detected.\n");
519 if (!cpu_has_xcrypt_enabled) {
520 printk(KERN_ERR PFX "VIA PadLock detected, but not enabled. Hmm, strange...\n");
525 if ((ret = crypto_register_alg(&aes_alg))) {
526 printk(KERN_ERR PFX "VIA PadLock AES initialization failed.\n");
530 printk(KERN_NOTICE PFX "Using VIA PadLock ACE for AES algorithm.\n");
535 static void __exit padlock_fini(void)
537 crypto_unregister_alg(&aes_alg);
540 module_init(padlock_init);
541 module_exit(padlock_fini);
543 MODULE_DESCRIPTION("VIA PadLock AES algorithm support");
544 MODULE_LICENSE("GPL");
545 MODULE_AUTHOR("Michal Ludvig");
547 MODULE_ALIAS("aes-padlock");