Merge master.kernel.org:/home/rmk/linux-2.6-drvmodel
[linux-2.6] / drivers / i2c / busses / i2c-mpc.c
1 /*
2  * (C) Copyright 2003-2004
3  * Humboldt Solutions Ltd, adrian@humboldt.co.uk.
4
5  * This is a combined i2c adapter and algorithm driver for the
6  * MPC107/Tsi107 PowerPC northbridge and processors that include
7  * the same I2C unit (8240, 8245, 85xx).
8  *
9  * Release 0.8
10  *
11  * This file is licensed under the terms of the GNU General Public
12  * License version 2. This program is licensed "as is" without any
13  * warranty of any kind, whether express or implied.
14  */
15
16 #include <linux/config.h>
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/sched.h>
20 #include <linux/init.h>
21 #include <linux/pci.h>
22 #include <linux/platform_device.h>
23
24 #include <asm/io.h>
25 #include <linux/fsl_devices.h>
26 #include <linux/i2c.h>
27 #include <linux/interrupt.h>
28 #include <linux/delay.h>
29
30 #define MPC_I2C_ADDR  0x00
31 #define MPC_I2C_FDR     0x04
32 #define MPC_I2C_CR      0x08
33 #define MPC_I2C_SR      0x0c
34 #define MPC_I2C_DR      0x10
35 #define MPC_I2C_DFSRR 0x14
36 #define MPC_I2C_REGION 0x20
37
38 #define CCR_MEN  0x80
39 #define CCR_MIEN 0x40
40 #define CCR_MSTA 0x20
41 #define CCR_MTX  0x10
42 #define CCR_TXAK 0x08
43 #define CCR_RSTA 0x04
44
45 #define CSR_MCF  0x80
46 #define CSR_MAAS 0x40
47 #define CSR_MBB  0x20
48 #define CSR_MAL  0x10
49 #define CSR_SRW  0x04
50 #define CSR_MIF  0x02
51 #define CSR_RXAK 0x01
52
53 struct mpc_i2c {
54         void __iomem *base;
55         u32 interrupt;
56         wait_queue_head_t queue;
57         struct i2c_adapter adap;
58         int irq;
59         u32 flags;
60 };
61
62 static __inline__ void writeccr(struct mpc_i2c *i2c, u32 x)
63 {
64         writeb(x, i2c->base + MPC_I2C_CR);
65 }
66
67 static irqreturn_t mpc_i2c_isr(int irq, void *dev_id, struct pt_regs *regs)
68 {
69         struct mpc_i2c *i2c = dev_id;
70         if (readb(i2c->base + MPC_I2C_SR) & CSR_MIF) {
71                 /* Read again to allow register to stabilise */
72                 i2c->interrupt = readb(i2c->base + MPC_I2C_SR);
73                 writeb(0, i2c->base + MPC_I2C_SR);
74                 wake_up_interruptible(&i2c->queue);
75         }
76         return IRQ_HANDLED;
77 }
78
79 static int i2c_wait(struct mpc_i2c *i2c, unsigned timeout, int writing)
80 {
81         unsigned long orig_jiffies = jiffies;
82         u32 x;
83         int result = 0;
84
85         if (i2c->irq == 0)
86         {
87                 while (!(readb(i2c->base + MPC_I2C_SR) & CSR_MIF)) {
88                         schedule();
89                         if (time_after(jiffies, orig_jiffies + timeout)) {
90                                 pr_debug("I2C: timeout\n");
91                                 result = -EIO;
92                                 break;
93                         }
94                 }
95                 x = readb(i2c->base + MPC_I2C_SR);
96                 writeb(0, i2c->base + MPC_I2C_SR);
97         } else {
98                 /* Interrupt mode */
99                 result = wait_event_interruptible_timeout(i2c->queue,
100                         (i2c->interrupt & CSR_MIF), timeout * HZ);
101
102                 if (unlikely(result < 0))
103                         pr_debug("I2C: wait interrupted\n");
104                 else if (unlikely(!(i2c->interrupt & CSR_MIF))) {
105                         pr_debug("I2C: wait timeout\n");
106                         result = -ETIMEDOUT;
107                 }
108
109                 x = i2c->interrupt;
110                 i2c->interrupt = 0;
111         }
112
113         if (result < 0)
114                 return result;
115
116         if (!(x & CSR_MCF)) {
117                 pr_debug("I2C: unfinished\n");
118                 return -EIO;
119         }
120
121         if (x & CSR_MAL) {
122                 pr_debug("I2C: MAL\n");
123                 return -EIO;
124         }
125
126         if (writing && (x & CSR_RXAK)) {
127                 pr_debug("I2C: No RXAK\n");
128                 /* generate stop */
129                 writeccr(i2c, CCR_MEN);
130                 return -EIO;
131         }
132         return 0;
133 }
134
135 static void mpc_i2c_setclock(struct mpc_i2c *i2c)
136 {
137         /* Set clock and filters */
138         if (i2c->flags & FSL_I2C_DEV_SEPARATE_DFSRR) {
139                 writeb(0x31, i2c->base + MPC_I2C_FDR);
140                 writeb(0x10, i2c->base + MPC_I2C_DFSRR);
141         } else if (i2c->flags & FSL_I2C_DEV_CLOCK_5200)
142                 writeb(0x3f, i2c->base + MPC_I2C_FDR);
143         else
144                 writel(0x1031, i2c->base + MPC_I2C_FDR);
145 }
146
147 static void mpc_i2c_start(struct mpc_i2c *i2c)
148 {
149         /* Clear arbitration */
150         writeb(0, i2c->base + MPC_I2C_SR);
151         /* Start with MEN */
152         writeccr(i2c, CCR_MEN);
153 }
154
155 static void mpc_i2c_stop(struct mpc_i2c *i2c)
156 {
157         writeccr(i2c, CCR_MEN);
158 }
159
160 static int mpc_write(struct mpc_i2c *i2c, int target,
161                      const u8 * data, int length, int restart)
162 {
163         int i;
164         unsigned timeout = i2c->adap.timeout;
165         u32 flags = restart ? CCR_RSTA : 0;
166
167         /* Start with MEN */
168         if (!restart)
169                 writeccr(i2c, CCR_MEN);
170         /* Start as master */
171         writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_MTX | flags);
172         /* Write target byte */
173         writeb((target << 1), i2c->base + MPC_I2C_DR);
174
175         if (i2c_wait(i2c, timeout, 1) < 0)
176                 return -1;
177
178         for (i = 0; i < length; i++) {
179                 /* Write data byte */
180                 writeb(data[i], i2c->base + MPC_I2C_DR);
181
182                 if (i2c_wait(i2c, timeout, 1) < 0)
183                         return -1;
184         }
185
186         return 0;
187 }
188
189 static int mpc_read(struct mpc_i2c *i2c, int target,
190                     u8 * data, int length, int restart)
191 {
192         unsigned timeout = i2c->adap.timeout;
193         int i;
194         u32 flags = restart ? CCR_RSTA : 0;
195
196         /* Start with MEN */
197         if (!restart)
198                 writeccr(i2c, CCR_MEN);
199         /* Switch to read - restart */
200         writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_MTX | flags);
201         /* Write target address byte - this time with the read flag set */
202         writeb((target << 1) | 1, i2c->base + MPC_I2C_DR);
203
204         if (i2c_wait(i2c, timeout, 1) < 0)
205                 return -1;
206
207         if (length) {
208                 if (length == 1)
209                         writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_TXAK);
210                 else
211                         writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA);
212                 /* Dummy read */
213                 readb(i2c->base + MPC_I2C_DR);
214         }
215
216         for (i = 0; i < length; i++) {
217                 if (i2c_wait(i2c, timeout, 0) < 0)
218                         return -1;
219
220                 /* Generate txack on next to last byte */
221                 if (i == length - 2)
222                         writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_TXAK);
223                 /* Generate stop on last byte */
224                 if (i == length - 1)
225                         writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_TXAK);
226                 data[i] = readb(i2c->base + MPC_I2C_DR);
227         }
228
229         return length;
230 }
231
232 static int mpc_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
233 {
234         struct i2c_msg *pmsg;
235         int i;
236         int ret = 0;
237         unsigned long orig_jiffies = jiffies;
238         struct mpc_i2c *i2c = i2c_get_adapdata(adap);
239
240         mpc_i2c_start(i2c);
241
242         /* Allow bus up to 1s to become not busy */
243         while (readb(i2c->base + MPC_I2C_SR) & CSR_MBB) {
244                 if (signal_pending(current)) {
245                         pr_debug("I2C: Interrupted\n");
246                         return -EINTR;
247                 }
248                 if (time_after(jiffies, orig_jiffies + HZ)) {
249                         pr_debug("I2C: timeout\n");
250                         return -EIO;
251                 }
252                 schedule();
253         }
254
255         for (i = 0; ret >= 0 && i < num; i++) {
256                 pmsg = &msgs[i];
257                 pr_debug("Doing %s %d bytes to 0x%02x - %d of %d messages\n",
258                          pmsg->flags & I2C_M_RD ? "read" : "write",
259                          pmsg->len, pmsg->addr, i + 1, num);
260                 if (pmsg->flags & I2C_M_RD)
261                         ret =
262                             mpc_read(i2c, pmsg->addr, pmsg->buf, pmsg->len, i);
263                 else
264                         ret =
265                             mpc_write(i2c, pmsg->addr, pmsg->buf, pmsg->len, i);
266         }
267         mpc_i2c_stop(i2c);
268         return (ret < 0) ? ret : num;
269 }
270
271 static u32 mpc_functionality(struct i2c_adapter *adap)
272 {
273         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
274 }
275
276 static struct i2c_algorithm mpc_algo = {
277         .master_xfer = mpc_xfer,
278         .functionality = mpc_functionality,
279 };
280
281 static struct i2c_adapter mpc_ops = {
282         .owner = THIS_MODULE,
283         .name = "MPC adapter",
284         .id = I2C_HW_MPC107,
285         .algo = &mpc_algo,
286         .class = I2C_CLASS_HWMON,
287         .timeout = 1,
288         .retries = 1
289 };
290
291 static int fsl_i2c_probe(struct platform_device *pdev)
292 {
293         int result = 0;
294         struct mpc_i2c *i2c;
295         struct fsl_i2c_platform_data *pdata;
296         struct resource *r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
297
298         pdata = (struct fsl_i2c_platform_data *) pdev->dev.platform_data;
299
300         if (!(i2c = kzalloc(sizeof(*i2c), GFP_KERNEL))) {
301                 return -ENOMEM;
302         }
303
304         i2c->irq = platform_get_irq(pdev, 0);
305         i2c->flags = pdata->device_flags;
306         init_waitqueue_head(&i2c->queue);
307
308         i2c->base = ioremap((phys_addr_t)r->start, MPC_I2C_REGION);
309
310         if (!i2c->base) {
311                 printk(KERN_ERR "i2c-mpc - failed to map controller\n");
312                 result = -ENOMEM;
313                 goto fail_map;
314         }
315
316         if (i2c->irq != 0)
317                 if ((result = request_irq(i2c->irq, mpc_i2c_isr,
318                                           SA_SHIRQ, "i2c-mpc", i2c)) < 0) {
319                         printk(KERN_ERR
320                                "i2c-mpc - failed to attach interrupt\n");
321                         goto fail_irq;
322                 }
323
324         mpc_i2c_setclock(i2c);
325         platform_set_drvdata(pdev, i2c);
326
327         i2c->adap = mpc_ops;
328         i2c_set_adapdata(&i2c->adap, i2c);
329         i2c->adap.dev.parent = &pdev->dev;
330         if ((result = i2c_add_adapter(&i2c->adap)) < 0) {
331                 printk(KERN_ERR "i2c-mpc - failed to add adapter\n");
332                 goto fail_add;
333         }
334
335         return result;
336
337       fail_add:
338         if (i2c->irq != 0)
339                 free_irq(i2c->irq, NULL);
340       fail_irq:
341         iounmap(i2c->base);
342       fail_map:
343         kfree(i2c);
344         return result;
345 };
346
347 static int fsl_i2c_remove(struct platform_device *pdev)
348 {
349         struct mpc_i2c *i2c = platform_get_drvdata(pdev);
350
351         i2c_del_adapter(&i2c->adap);
352         platform_set_drvdata(pdev, NULL);
353
354         if (i2c->irq != 0)
355                 free_irq(i2c->irq, i2c);
356
357         iounmap(i2c->base);
358         kfree(i2c);
359         return 0;
360 };
361
362 /* Structure for a device driver */
363 static struct platform_driver fsl_i2c_driver = {
364         .probe = fsl_i2c_probe,
365         .remove = fsl_i2c_remove,
366         .driver = {
367                 .owner = THIS_MODULE,
368                 .name = "fsl-i2c",
369         },
370 };
371
372 static int __init fsl_i2c_init(void)
373 {
374         return platform_driver_register(&fsl_i2c_driver);
375 }
376
377 static void __exit fsl_i2c_exit(void)
378 {
379         platform_driver_unregister(&fsl_i2c_driver);
380 }
381
382 module_init(fsl_i2c_init);
383 module_exit(fsl_i2c_exit);
384
385 MODULE_AUTHOR("Adrian Cox <adrian@humboldt.co.uk>");
386 MODULE_DESCRIPTION
387     ("I2C-Bus adapter for MPC107 bridge and MPC824x/85xx/52xx processors");
388 MODULE_LICENSE("GPL");