Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/torvalds/linux-2.6
[linux-2.6] / drivers / net / wireless / ath5k / initvals.c
1 /*
2  * Initial register settings functions
3  *
4  * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
5  * Copyright (c) 2006-2007 Nick Kossifidis <mickflemm@gmail.com>
6  * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
7  *
8  * Permission to use, copy, modify, and distribute this software for any
9  * purpose with or without fee is hereby granted, provided that the above
10  * copyright notice and this permission notice appear in all copies.
11  *
12  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
13  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
14  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
15  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
16  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
17  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
18  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19  *
20  */
21
22 #include "ath5k.h"
23 #include "reg.h"
24 #include "debug.h"
25 #include "base.h"
26
27 /*
28  * Mode-independent initial register writes
29  */
30
31 struct ath5k_ini {
32         u16     ini_register;
33         u32     ini_value;
34
35         enum {
36                 AR5K_INI_WRITE = 0,     /* Default */
37                 AR5K_INI_READ = 1,      /* Cleared on read */
38         } ini_mode;
39 };
40
41 /*
42  * Mode specific initial register values
43  */
44
45 struct ath5k_ini_mode {
46         u16     mode_register;
47         u32     mode_value[5];
48 };
49
50 /* Initial register settings for AR5210 */
51 static const struct ath5k_ini ar5210_ini[] = {
52         /* PCU and MAC registers */
53         { AR5K_NOQCU_TXDP0,     0 },
54         { AR5K_NOQCU_TXDP1,     0 },
55         { AR5K_RXDP,            0 },
56         { AR5K_CR,              0 },
57         { AR5K_ISR,             0, AR5K_INI_READ },
58         { AR5K_IMR,             0 },
59         { AR5K_IER,             AR5K_IER_DISABLE },
60         { AR5K_BSR,             0, AR5K_INI_READ },
61         { AR5K_TXCFG,           AR5K_DMASIZE_128B },
62         { AR5K_RXCFG,           AR5K_DMASIZE_128B },
63         { AR5K_CFG,             AR5K_INIT_CFG },
64         { AR5K_TOPS,            8 },
65         { AR5K_RXNOFRM,         8 },
66         { AR5K_RPGTO,           0 },
67         { AR5K_TXNOFRM,         0 },
68         { AR5K_SFR,             0 },
69         { AR5K_MIBC,            0 },
70         { AR5K_MISC,            0 },
71         { AR5K_RX_FILTER_5210,  0 },
72         { AR5K_MCAST_FILTER0_5210, 0 },
73         { AR5K_MCAST_FILTER1_5210, 0 },
74         { AR5K_TX_MASK0,        0 },
75         { AR5K_TX_MASK1,        0 },
76         { AR5K_CLR_TMASK,       0 },
77         { AR5K_TRIG_LVL,        AR5K_TUNE_MIN_TX_FIFO_THRES },
78         { AR5K_DIAG_SW_5210,    0 },
79         { AR5K_RSSI_THR,        AR5K_TUNE_RSSI_THRES },
80         { AR5K_TSF_L32_5210,    0 },
81         { AR5K_TIMER0_5210,     0 },
82         { AR5K_TIMER1_5210,     0xffffffff },
83         { AR5K_TIMER2_5210,     0xffffffff },
84         { AR5K_TIMER3_5210,     1 },
85         { AR5K_CFP_DUR_5210,    0 },
86         { AR5K_CFP_PERIOD_5210, 0 },
87         /* PHY registers */
88         { AR5K_PHY(0),  0x00000047 },
89         { AR5K_PHY_AGC, 0x00000000 },
90         { AR5K_PHY(3),  0x09848ea6 },
91         { AR5K_PHY(4),  0x3d32e000 },
92         { AR5K_PHY(5),  0x0000076b },
93         { AR5K_PHY_ACT, AR5K_PHY_ACT_DISABLE },
94         { AR5K_PHY(8),  0x02020200 },
95         { AR5K_PHY(9),  0x00000e0e },
96         { AR5K_PHY(10), 0x0a020201 },
97         { AR5K_PHY(11), 0x00036ffc },
98         { AR5K_PHY(12), 0x00000000 },
99         { AR5K_PHY(13), 0x00000e0e },
100         { AR5K_PHY(14), 0x00000007 },
101         { AR5K_PHY(15), 0x00020100 },
102         { AR5K_PHY(16), 0x89630000 },
103         { AR5K_PHY(17), 0x1372169c },
104         { AR5K_PHY(18), 0x0018b633 },
105         { AR5K_PHY(19), 0x1284613c },
106         { AR5K_PHY(20), 0x0de8b8e0 },
107         { AR5K_PHY(21), 0x00074859 },
108         { AR5K_PHY(22), 0x7e80beba },
109         { AR5K_PHY(23), 0x313a665e },
110         { AR5K_PHY_AGCCTL, 0x00001d08 },
111         { AR5K_PHY(25), 0x0001ce00 },
112         { AR5K_PHY(26), 0x409a4190 },
113         { AR5K_PHY(28), 0x0000000f },
114         { AR5K_PHY(29), 0x00000080 },
115         { AR5K_PHY(30), 0x00000004 },
116         { AR5K_PHY(31), 0x00000018 },   /* 0x987c */
117         { AR5K_PHY(64), 0x00000000 },   /* 0x9900 */
118         { AR5K_PHY(65), 0x00000000 },
119         { AR5K_PHY(66), 0x00000000 },
120         { AR5K_PHY(67), 0x00800000 },
121         { AR5K_PHY(68), 0x00000003 },
122         /* BB gain table (64bytes) */
123         { AR5K_BB_GAIN(0), 0x00000000 },
124         { AR5K_BB_GAIN(1), 0x00000020 },
125         { AR5K_BB_GAIN(2), 0x00000010 },
126         { AR5K_BB_GAIN(3), 0x00000030 },
127         { AR5K_BB_GAIN(4), 0x00000008 },
128         { AR5K_BB_GAIN(5), 0x00000028 },
129         { AR5K_BB_GAIN(6), 0x00000028 },
130         { AR5K_BB_GAIN(7), 0x00000004 },
131         { AR5K_BB_GAIN(8), 0x00000024 },
132         { AR5K_BB_GAIN(9), 0x00000014 },
133         { AR5K_BB_GAIN(10), 0x00000034 },
134         { AR5K_BB_GAIN(11), 0x0000000c },
135         { AR5K_BB_GAIN(12), 0x0000002c },
136         { AR5K_BB_GAIN(13), 0x00000002 },
137         { AR5K_BB_GAIN(14), 0x00000022 },
138         { AR5K_BB_GAIN(15), 0x00000012 },
139         { AR5K_BB_GAIN(16), 0x00000032 },
140         { AR5K_BB_GAIN(17), 0x0000000a },
141         { AR5K_BB_GAIN(18), 0x0000002a },
142         { AR5K_BB_GAIN(19), 0x00000001 },
143         { AR5K_BB_GAIN(20), 0x00000021 },
144         { AR5K_BB_GAIN(21), 0x00000011 },
145         { AR5K_BB_GAIN(22), 0x00000031 },
146         { AR5K_BB_GAIN(23), 0x00000009 },
147         { AR5K_BB_GAIN(24), 0x00000029 },
148         { AR5K_BB_GAIN(25), 0x00000005 },
149         { AR5K_BB_GAIN(26), 0x00000025 },
150         { AR5K_BB_GAIN(27), 0x00000015 },
151         { AR5K_BB_GAIN(28), 0x00000035 },
152         { AR5K_BB_GAIN(29), 0x0000000d },
153         { AR5K_BB_GAIN(30), 0x0000002d },
154         { AR5K_BB_GAIN(31), 0x00000003 },
155         { AR5K_BB_GAIN(32), 0x00000023 },
156         { AR5K_BB_GAIN(33), 0x00000013 },
157         { AR5K_BB_GAIN(34), 0x00000033 },
158         { AR5K_BB_GAIN(35), 0x0000000b },
159         { AR5K_BB_GAIN(36), 0x0000002b },
160         { AR5K_BB_GAIN(37), 0x00000007 },
161         { AR5K_BB_GAIN(38), 0x00000027 },
162         { AR5K_BB_GAIN(39), 0x00000017 },
163         { AR5K_BB_GAIN(40), 0x00000037 },
164         { AR5K_BB_GAIN(41), 0x0000000f },
165         { AR5K_BB_GAIN(42), 0x0000002f },
166         { AR5K_BB_GAIN(43), 0x0000002f },
167         { AR5K_BB_GAIN(44), 0x0000002f },
168         { AR5K_BB_GAIN(45), 0x0000002f },
169         { AR5K_BB_GAIN(46), 0x0000002f },
170         { AR5K_BB_GAIN(47), 0x0000002f },
171         { AR5K_BB_GAIN(48), 0x0000002f },
172         { AR5K_BB_GAIN(49), 0x0000002f },
173         { AR5K_BB_GAIN(50), 0x0000002f },
174         { AR5K_BB_GAIN(51), 0x0000002f },
175         { AR5K_BB_GAIN(52), 0x0000002f },
176         { AR5K_BB_GAIN(53), 0x0000002f },
177         { AR5K_BB_GAIN(54), 0x0000002f },
178         { AR5K_BB_GAIN(55), 0x0000002f },
179         { AR5K_BB_GAIN(56), 0x0000002f },
180         { AR5K_BB_GAIN(57), 0x0000002f },
181         { AR5K_BB_GAIN(58), 0x0000002f },
182         { AR5K_BB_GAIN(59), 0x0000002f },
183         { AR5K_BB_GAIN(60), 0x0000002f },
184         { AR5K_BB_GAIN(61), 0x0000002f },
185         { AR5K_BB_GAIN(62), 0x0000002f },
186         { AR5K_BB_GAIN(63), 0x0000002f },
187         /* 5110 RF gain table (64btes) */
188         { AR5K_RF_GAIN(0), 0x0000001d },
189         { AR5K_RF_GAIN(1), 0x0000005d },
190         { AR5K_RF_GAIN(2), 0x0000009d },
191         { AR5K_RF_GAIN(3), 0x000000dd },
192         { AR5K_RF_GAIN(4), 0x0000011d },
193         { AR5K_RF_GAIN(5), 0x00000021 },
194         { AR5K_RF_GAIN(6), 0x00000061 },
195         { AR5K_RF_GAIN(7), 0x000000a1 },
196         { AR5K_RF_GAIN(8), 0x000000e1 },
197         { AR5K_RF_GAIN(9), 0x00000031 },
198         { AR5K_RF_GAIN(10), 0x00000071 },
199         { AR5K_RF_GAIN(11), 0x000000b1 },
200         { AR5K_RF_GAIN(12), 0x0000001c },
201         { AR5K_RF_GAIN(13), 0x0000005c },
202         { AR5K_RF_GAIN(14), 0x00000029 },
203         { AR5K_RF_GAIN(15), 0x00000069 },
204         { AR5K_RF_GAIN(16), 0x000000a9 },
205         { AR5K_RF_GAIN(17), 0x00000020 },
206         { AR5K_RF_GAIN(18), 0x00000019 },
207         { AR5K_RF_GAIN(19), 0x00000059 },
208         { AR5K_RF_GAIN(20), 0x00000099 },
209         { AR5K_RF_GAIN(21), 0x00000030 },
210         { AR5K_RF_GAIN(22), 0x00000005 },
211         { AR5K_RF_GAIN(23), 0x00000025 },
212         { AR5K_RF_GAIN(24), 0x00000065 },
213         { AR5K_RF_GAIN(25), 0x000000a5 },
214         { AR5K_RF_GAIN(26), 0x00000028 },
215         { AR5K_RF_GAIN(27), 0x00000068 },
216         { AR5K_RF_GAIN(28), 0x0000001f },
217         { AR5K_RF_GAIN(29), 0x0000001e },
218         { AR5K_RF_GAIN(30), 0x00000018 },
219         { AR5K_RF_GAIN(31), 0x00000058 },
220         { AR5K_RF_GAIN(32), 0x00000098 },
221         { AR5K_RF_GAIN(33), 0x00000003 },
222         { AR5K_RF_GAIN(34), 0x00000004 },
223         { AR5K_RF_GAIN(35), 0x00000044 },
224         { AR5K_RF_GAIN(36), 0x00000084 },
225         { AR5K_RF_GAIN(37), 0x00000013 },
226         { AR5K_RF_GAIN(38), 0x00000012 },
227         { AR5K_RF_GAIN(39), 0x00000052 },
228         { AR5K_RF_GAIN(40), 0x00000092 },
229         { AR5K_RF_GAIN(41), 0x000000d2 },
230         { AR5K_RF_GAIN(42), 0x0000002b },
231         { AR5K_RF_GAIN(43), 0x0000002a },
232         { AR5K_RF_GAIN(44), 0x0000006a },
233         { AR5K_RF_GAIN(45), 0x000000aa },
234         { AR5K_RF_GAIN(46), 0x0000001b },
235         { AR5K_RF_GAIN(47), 0x0000001a },
236         { AR5K_RF_GAIN(48), 0x0000005a },
237         { AR5K_RF_GAIN(49), 0x0000009a },
238         { AR5K_RF_GAIN(50), 0x000000da },
239         { AR5K_RF_GAIN(51), 0x00000006 },
240         { AR5K_RF_GAIN(52), 0x00000006 },
241         { AR5K_RF_GAIN(53), 0x00000006 },
242         { AR5K_RF_GAIN(54), 0x00000006 },
243         { AR5K_RF_GAIN(55), 0x00000006 },
244         { AR5K_RF_GAIN(56), 0x00000006 },
245         { AR5K_RF_GAIN(57), 0x00000006 },
246         { AR5K_RF_GAIN(58), 0x00000006 },
247         { AR5K_RF_GAIN(59), 0x00000006 },
248         { AR5K_RF_GAIN(60), 0x00000006 },
249         { AR5K_RF_GAIN(61), 0x00000006 },
250         { AR5K_RF_GAIN(62), 0x00000006 },
251         { AR5K_RF_GAIN(63), 0x00000006 },
252         /* PHY activation */
253         { AR5K_PHY(53), 0x00000020 },
254         { AR5K_PHY(51), 0x00000004 },
255         { AR5K_PHY(50), 0x00060106 },
256         { AR5K_PHY(39), 0x0000006d },
257         { AR5K_PHY(48), 0x00000000 },
258         { AR5K_PHY(52), 0x00000014 },
259         { AR5K_PHY_ACT, AR5K_PHY_ACT_ENABLE },
260 };
261
262 /* Initial register settings for AR5211 */
263 static const struct ath5k_ini ar5211_ini[] = {
264         { AR5K_RXDP,            0x00000000 },
265         { AR5K_RTSD0,           0x84849c9c },
266         { AR5K_RTSD1,           0x7c7c7c7c },
267         { AR5K_RXCFG,           0x00000005 },
268         { AR5K_MIBC,            0x00000000 },
269         { AR5K_TOPS,            0x00000008 },
270         { AR5K_RXNOFRM,         0x00000008 },
271         { AR5K_TXNOFRM,         0x00000010 },
272         { AR5K_RPGTO,           0x00000000 },
273         { AR5K_RFCNT,           0x0000001f },
274         { AR5K_QUEUE_TXDP(0),   0x00000000 },
275         { AR5K_QUEUE_TXDP(1),   0x00000000 },
276         { AR5K_QUEUE_TXDP(2),   0x00000000 },
277         { AR5K_QUEUE_TXDP(3),   0x00000000 },
278         { AR5K_QUEUE_TXDP(4),   0x00000000 },
279         { AR5K_QUEUE_TXDP(5),   0x00000000 },
280         { AR5K_QUEUE_TXDP(6),   0x00000000 },
281         { AR5K_QUEUE_TXDP(7),   0x00000000 },
282         { AR5K_QUEUE_TXDP(8),   0x00000000 },
283         { AR5K_QUEUE_TXDP(9),   0x00000000 },
284         { AR5K_DCU_FP,          0x00000000 },
285         { AR5K_STA_ID1,         0x00000000 },
286         { AR5K_BSS_ID0,         0x00000000 },
287         { AR5K_BSS_ID1,         0x00000000 },
288         { AR5K_RSSI_THR,        0x00000000 },
289         { AR5K_CFP_PERIOD_5211, 0x00000000 },
290         { AR5K_TIMER0_5211,     0x00000030 },
291         { AR5K_TIMER1_5211,     0x0007ffff },
292         { AR5K_TIMER2_5211,     0x01ffffff },
293         { AR5K_TIMER3_5211,     0x00000031 },
294         { AR5K_CFP_DUR_5211,    0x00000000 },
295         { AR5K_RX_FILTER_5211,  0x00000000 },
296         { AR5K_MCAST_FILTER0_5211, 0x00000000 },
297         { AR5K_MCAST_FILTER1_5211, 0x00000002 },
298         { AR5K_DIAG_SW_5211,    0x00000000 },
299         { AR5K_ADDAC_TEST,      0x00000000 },
300         { AR5K_DEFAULT_ANTENNA, 0x00000000 },
301         /* PHY registers */
302         { AR5K_PHY_AGC, 0x00000000 },
303         { AR5K_PHY(3),  0x2d849093 },
304         { AR5K_PHY(4),  0x7d32e000 },
305         { AR5K_PHY(5),  0x00000f6b },
306         { AR5K_PHY_ACT, 0x00000000 },
307         { AR5K_PHY(11), 0x00026ffe },
308         { AR5K_PHY(12), 0x00000000 },
309         { AR5K_PHY(15), 0x00020100 },
310         { AR5K_PHY(16), 0x206a017a },
311         { AR5K_PHY(19), 0x1284613c },
312         { AR5K_PHY(21), 0x00000859 },
313         { AR5K_PHY(26), 0x409a4190 },   /* 0x9868 */
314         { AR5K_PHY(27), 0x050cb081 },
315         { AR5K_PHY(28), 0x0000000f },
316         { AR5K_PHY(29), 0x00000080 },
317         { AR5K_PHY(30), 0x0000000c },
318         { AR5K_PHY(64), 0x00000000 },
319         { AR5K_PHY(65), 0x00000000 },
320         { AR5K_PHY(66), 0x00000000 },
321         { AR5K_PHY(67), 0x00800000 },
322         { AR5K_PHY(68), 0x00000001 },
323         { AR5K_PHY(71), 0x0000092a },
324         { AR5K_PHY_IQ,  0x00000000 },
325         { AR5K_PHY(73), 0x00058a05 },
326         { AR5K_PHY(74), 0x00000001 },
327         { AR5K_PHY(75), 0x00000000 },
328         { AR5K_PHY_PAPD_PROBE, 0x00000000 },
329         { AR5K_PHY(77), 0x00000000 },   /* 0x9934 */
330         { AR5K_PHY(78), 0x00000000 },   /* 0x9938 */
331         { AR5K_PHY(79), 0x0000003f },   /* 0x993c */
332         { AR5K_PHY(80), 0x00000004 },
333         { AR5K_PHY(82), 0x00000000 },
334         { AR5K_PHY(83), 0x00000000 },
335         { AR5K_PHY(84), 0x00000000 },
336         { AR5K_PHY_RADAR, 0x5d50f14c },
337         { AR5K_PHY(86), 0x00000018 },
338         { AR5K_PHY(87), 0x004b6a8e },
339         /* Initial Power table (32bytes)
340          * common on all cards/modes.
341          * Note: Table is rewritten during
342          * txpower setup later using calibration
343          * data etc. so next write is non-common
344         { AR5K_PHY_PCDAC_TXPOWER(1), 0x06ff05ff },
345         { AR5K_PHY_PCDAC_TXPOWER(2), 0x07ff07ff },
346         { AR5K_PHY_PCDAC_TXPOWER(3), 0x08ff08ff },
347         { AR5K_PHY_PCDAC_TXPOWER(4), 0x09ff09ff },
348         { AR5K_PHY_PCDAC_TXPOWER(5), 0x0aff0aff },
349         { AR5K_PHY_PCDAC_TXPOWER(6), 0x0bff0bff },
350         { AR5K_PHY_PCDAC_TXPOWER(7), 0x0cff0cff },
351         { AR5K_PHY_PCDAC_TXPOWER(8), 0x0dff0dff },
352         { AR5K_PHY_PCDAC_TXPOWER(9), 0x0fff0eff },
353         { AR5K_PHY_PCDAC_TXPOWER(10), 0x12ff12ff },
354         { AR5K_PHY_PCDAC_TXPOWER(11), 0x14ff13ff },
355         { AR5K_PHY_PCDAC_TXPOWER(12), 0x16ff15ff },
356         { AR5K_PHY_PCDAC_TXPOWER(13), 0x19ff17ff },
357         { AR5K_PHY_PCDAC_TXPOWER(14), 0x1bff1aff },
358         { AR5K_PHY_PCDAC_TXPOWER(15), 0x1eff1dff },
359         { AR5K_PHY_PCDAC_TXPOWER(16), 0x23ff20ff },
360         { AR5K_PHY_PCDAC_TXPOWER(17), 0x27ff25ff },
361         { AR5K_PHY_PCDAC_TXPOWER(18), 0x2cff29ff },
362         { AR5K_PHY_PCDAC_TXPOWER(19), 0x31ff2fff },
363         { AR5K_PHY_PCDAC_TXPOWER(20), 0x37ff34ff },
364         { AR5K_PHY_PCDAC_TXPOWER(21), 0x3aff3aff },
365         { AR5K_PHY_PCDAC_TXPOWER(22), 0x3aff3aff },
366         { AR5K_PHY_PCDAC_TXPOWER(23), 0x3aff3aff },
367         { AR5K_PHY_PCDAC_TXPOWER(24), 0x3aff3aff },
368         { AR5K_PHY_PCDAC_TXPOWER(25), 0x3aff3aff },
369         { AR5K_PHY_PCDAC_TXPOWER(26), 0x3aff3aff },
370         { AR5K_PHY_PCDAC_TXPOWER(27), 0x3aff3aff },
371         { AR5K_PHY_PCDAC_TXPOWER(28), 0x3aff3aff },
372         { AR5K_PHY_PCDAC_TXPOWER(29), 0x3aff3aff },
373         { AR5K_PHY_PCDAC_TXPOWER(30), 0x3aff3aff },
374         { AR5K_PHY_PCDAC_TXPOWER(31), 0x3aff3aff },*/
375         { AR5K_PHY_CCKTXCTL, 0x00000000 },
376         { AR5K_PHY(642), 0x503e4646 },
377         { AR5K_PHY_GAIN_2GHZ, 0x6480416c },
378         { AR5K_PHY(644), 0x0199a003 },
379         { AR5K_PHY(645), 0x044cd610 },
380         { AR5K_PHY(646), 0x13800040 },
381         { AR5K_PHY(647), 0x1be00060 },
382         { AR5K_PHY(648), 0x0c53800a },
383         { AR5K_PHY(649), 0x0014df3b },
384         { AR5K_PHY(650), 0x000001b5 },
385         { AR5K_PHY(651), 0x00000020 },
386 };
387
388 /* Initial mode-specific settings for AR5211
389  * XXX: how about g / gTurbo ? RF5111 supports it, how about AR5211 ?
390  * Maybe 5211 supports OFDM-only g but we need to test it !
391  */
392 static const struct ath5k_ini_mode ar5211_ini_mode[] = {
393         { AR5K_TXCFG,
394         /*        a           aTurbo      b             */
395                 { 0x00000015, 0x00000015, 0x0000001d } },
396         { AR5K_QUEUE_DFS_LOCAL_IFS(0),
397                 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f } },
398         { AR5K_QUEUE_DFS_LOCAL_IFS(1),
399                 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f } },
400         { AR5K_QUEUE_DFS_LOCAL_IFS(2),
401                 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f } },
402         { AR5K_QUEUE_DFS_LOCAL_IFS(3),
403                 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f } },
404         { AR5K_QUEUE_DFS_LOCAL_IFS(4),
405                 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f } },
406         { AR5K_QUEUE_DFS_LOCAL_IFS(5),
407                 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f } },
408         { AR5K_QUEUE_DFS_LOCAL_IFS(6),
409                 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f } },
410         { AR5K_QUEUE_DFS_LOCAL_IFS(7),
411                 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f } },
412         { AR5K_QUEUE_DFS_LOCAL_IFS(8),
413                 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f } },
414         { AR5K_QUEUE_DFS_LOCAL_IFS(9),
415                 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f } },
416         { AR5K_DCU_GBL_IFS_SLOT,
417                 { 0x00000168, 0x000001e0, 0x000001b8 } },
418         { AR5K_DCU_GBL_IFS_SIFS,
419                 { 0x00000230, 0x000001e0, 0x000000b0 } },
420         { AR5K_DCU_GBL_IFS_EIFS,
421                 { 0x00000d98, 0x00001180, 0x00001f48 } },
422         { AR5K_DCU_GBL_IFS_MISC,
423                 { 0x0000a0e0, 0x00014068, 0x00005880 } },
424         { AR5K_TIME_OUT,
425                 { 0x04000400, 0x08000800, 0x20003000 } },
426         { AR5K_USEC_5211,
427                 { 0x0e8d8fa7, 0x0e8d8fcf, 0x01608f95 } },
428         { AR5K_PHY_TURBO,
429                 { 0x00000000, 0x00000003, 0x00000000 } },
430         { AR5K_PHY(8),
431                 { 0x02020200, 0x02020200, 0x02010200 } },
432         { AR5K_PHY(9),
433                 { 0x00000e0e, 0x00000e0e, 0x00000707 } },
434         { AR5K_PHY(10),
435                 { 0x0a020001, 0x0a020001, 0x05010000 } },
436         { AR5K_PHY(13),
437                 { 0x00000e0e, 0x00000e0e, 0x00000e0e } },
438         { AR5K_PHY(14),
439                 { 0x00000007, 0x00000007, 0x0000000b } },
440         { AR5K_PHY(17),
441                 { 0x1372169c, 0x137216a5, 0x137216a8 } },
442         { AR5K_PHY(18),
443                 { 0x0018ba67, 0x0018ba67, 0x0018ba69 } },
444         { AR5K_PHY(20),
445                 { 0x0c28b4e0, 0x0c28b4e0, 0x0c28b4e0 } },
446         { AR5K_PHY_SIG,
447                 { 0x7e800d2e, 0x7e800d2e, 0x7ec00d2e } },
448         { AR5K_PHY_AGCCOARSE,
449                 { 0x31375d5e, 0x31375d5e, 0x313a5d5e } },
450         { AR5K_PHY_AGCCTL,
451                 { 0x0000bd10, 0x0000bd10, 0x0000bd38 } },
452         { AR5K_PHY_NF,
453                 { 0x0001ce00, 0x0001ce00, 0x0001ce00 } },
454         { AR5K_PHY_RX_DELAY,
455                 { 0x00002710, 0x00002710, 0x0000157c } },
456         { AR5K_PHY(70),
457                 { 0x00000190, 0x00000190, 0x00000084 } },
458         { AR5K_PHY_FRAME_CTL_5211,
459                 { 0x6fe01020, 0x6fe01020, 0x6fe00920 } },
460         { AR5K_PHY_PCDAC_TXPOWER_BASE_5211,
461                 { 0x05ff14ff, 0x05ff14ff, 0x05ff14ff } },
462         { AR5K_RF_BUFFER_CONTROL_4,
463                 { 0x00000010, 0x00000014, 0x00000010 } },
464 };
465
466 /* Initial register settings for AR5212 */
467 static const struct ath5k_ini ar5212_ini[] = {
468         { AR5K_RXDP,            0x00000000 },
469         { AR5K_RXCFG,           0x00000005 },
470         { AR5K_MIBC,            0x00000000 },
471         { AR5K_TOPS,            0x00000008 },
472         { AR5K_RXNOFRM,         0x00000008 },
473         { AR5K_TXNOFRM,         0x00000010 },
474         { AR5K_RPGTO,           0x00000000 },
475         { AR5K_RFCNT,           0x0000001f },
476         { AR5K_QUEUE_TXDP(0),   0x00000000 },
477         { AR5K_QUEUE_TXDP(1),   0x00000000 },
478         { AR5K_QUEUE_TXDP(2),   0x00000000 },
479         { AR5K_QUEUE_TXDP(3),   0x00000000 },
480         { AR5K_QUEUE_TXDP(4),   0x00000000 },
481         { AR5K_QUEUE_TXDP(5),   0x00000000 },
482         { AR5K_QUEUE_TXDP(6),   0x00000000 },
483         { AR5K_QUEUE_TXDP(7),   0x00000000 },
484         { AR5K_QUEUE_TXDP(8),   0x00000000 },
485         { AR5K_QUEUE_TXDP(9),   0x00000000 },
486         { AR5K_DCU_FP,          0x00000000 },
487         { AR5K_DCU_TXP,         0x00000000 },
488         { AR5K_DCU_TX_FILTER_0_BASE,    0x00000000 },
489         /* Unknown table */
490         { 0x1078, 0x00000000 },
491         { 0x10b8, 0x00000000 },
492         { 0x10f8, 0x00000000 },
493         { 0x1138, 0x00000000 },
494         { 0x1178, 0x00000000 },
495         { 0x11b8, 0x00000000 },
496         { 0x11f8, 0x00000000 },
497         { 0x1238, 0x00000000 },
498         { 0x1278, 0x00000000 },
499         { 0x12b8, 0x00000000 },
500         { 0x12f8, 0x00000000 },
501         { 0x1338, 0x00000000 },
502         { 0x1378, 0x00000000 },
503         { 0x13b8, 0x00000000 },
504         { 0x13f8, 0x00000000 },
505         { 0x1438, 0x00000000 },
506         { 0x1478, 0x00000000 },
507         { 0x14b8, 0x00000000 },
508         { 0x14f8, 0x00000000 },
509         { 0x1538, 0x00000000 },
510         { 0x1578, 0x00000000 },
511         { 0x15b8, 0x00000000 },
512         { 0x15f8, 0x00000000 },
513         { 0x1638, 0x00000000 },
514         { 0x1678, 0x00000000 },
515         { 0x16b8, 0x00000000 },
516         { 0x16f8, 0x00000000 },
517         { 0x1738, 0x00000000 },
518         { 0x1778, 0x00000000 },
519         { 0x17b8, 0x00000000 },
520         { 0x17f8, 0x00000000 },
521         { 0x103c, 0x00000000 },
522         { 0x107c, 0x00000000 },
523         { 0x10bc, 0x00000000 },
524         { 0x10fc, 0x00000000 },
525         { 0x113c, 0x00000000 },
526         { 0x117c, 0x00000000 },
527         { 0x11bc, 0x00000000 },
528         { 0x11fc, 0x00000000 },
529         { 0x123c, 0x00000000 },
530         { 0x127c, 0x00000000 },
531         { 0x12bc, 0x00000000 },
532         { 0x12fc, 0x00000000 },
533         { 0x133c, 0x00000000 },
534         { 0x137c, 0x00000000 },
535         { 0x13bc, 0x00000000 },
536         { 0x13fc, 0x00000000 },
537         { 0x143c, 0x00000000 },
538         { 0x147c, 0x00000000 },
539         { AR5K_DCU_TX_FILTER_CLR, 0x00000000 },
540         { AR5K_DCU_TX_FILTER_SET, 0x00000000 },
541         { AR5K_STA_ID1,         0x00000000 },
542         { AR5K_BSS_ID0,         0x00000000 },
543         { AR5K_BSS_ID1,         0x00000000 },
544         /*{ AR5K_RSSI_THR,      0x00000000 },*/ /* Found on SuperAG cards */
545         { AR5K_BEACON_5211,     0x00000000 },   /* Found on SuperAG cards */
546         { AR5K_CFP_PERIOD_5211, 0x00000000 },   /* Found on SuperAG cards */
547         { AR5K_TIMER0_5211,     0x00000030 },   /* Found on SuperAG cards */
548         { AR5K_TIMER1_5211,     0x0007ffff },   /* Found on SuperAG cards */
549         { AR5K_TIMER2_5211,     0x01ffffff },   /* Found on SuperAG cards */
550         { AR5K_TIMER3_5211,     0x00000031 },   /* Found on SuperAG cards */
551         { AR5K_CFP_DUR_5211,    0x00000000 },   /* Found on SuperAG cards */
552         { AR5K_RX_FILTER_5211,  0x00000000 },
553         { AR5K_DIAG_SW_5211,    0x00000000 },
554         { AR5K_ADDAC_TEST,      0x00000000 },
555         { AR5K_DEFAULT_ANTENNA, 0x00000000 },
556         { 0x8080, 0x00000000 },
557         /*{ 0x805c, 0xffffc7ff },*/ /* Old value */
558         { 0x805c, 0x000fc78f },
559         { AR5K_NAV_5211,        0x00000000 },   /* Not found on recent */
560         { AR5K_RTS_OK_5211,     0x00000000 },   /* dumps but it makes  */
561         { AR5K_RTS_FAIL_5211,   0x00000000 },   /* sense to reset counters */
562         { AR5K_ACK_FAIL_5211,   0x00000000 },   /* since pcu registers */
563         { AR5K_FCS_FAIL_5211,   0x00000000 },   /* are skiped during chan*/
564         { AR5K_BEACON_CNT_5211, 0x00000000 },   /* change */
565         { AR5K_XRMODE,          0x2a82301a },
566         { AR5K_XRDELAY,         0x05dc01e0 },
567         { AR5K_XRTIMEOUT,       0x1f402710 },
568         { AR5K_XRCHIRP,         0x01f40000 },
569         { AR5K_XRSTOMP,         0x00001e1c },
570         { AR5K_SLEEP0,          0x0002aaaa },   /* Found on SuperAG cards */
571         { AR5K_SLEEP1,          0x02005555 },   /* Found on SuperAG cards */
572         { AR5K_SLEEP2,          0x00000000 },   /* Found on SuperAG cards */
573         { AR5K_BSS_IDM0,        0xffffffff },
574         { AR5K_BSS_IDM1,        0x0000ffff },
575         { AR5K_TXPC,            0x00000000 },
576         { AR5K_PROFCNT_TX,      0x00000000 },
577         { AR5K_PROFCNT_RX,      0x00000000 },
578         { AR5K_PROFCNT_RXCLR,   0x00000000 },
579         { AR5K_PROFCNT_CYCLE,   0x00000000 },
580         { 0x80fc, 0x00000088 },
581         { AR5K_RATE_DUR(0),     0x00000000 },
582         { AR5K_RATE_DUR(1),     0x0000008c },
583         { AR5K_RATE_DUR(2),     0x000000e4 },
584         { AR5K_RATE_DUR(3),     0x000002d5 },
585         { AR5K_RATE_DUR(4),     0x00000000 },
586         { AR5K_RATE_DUR(5),     0x00000000 },
587         { AR5K_RATE_DUR(6),     0x000000a0 },
588         { AR5K_RATE_DUR(7),     0x000001c9 },
589         { AR5K_RATE_DUR(8),     0x0000002c },
590         { AR5K_RATE_DUR(9),     0x0000002c },
591         { AR5K_RATE_DUR(10),    0x00000030 },
592         { AR5K_RATE_DUR(11),    0x0000003c },
593         { AR5K_RATE_DUR(12),    0x0000002c },
594         { AR5K_RATE_DUR(13),    0x0000002c },
595         { AR5K_RATE_DUR(14),    0x00000030 },
596         { AR5K_RATE_DUR(15),    0x0000003c },
597         { AR5K_RATE_DUR(16),    0x00000000 },
598         { AR5K_RATE_DUR(17),    0x00000000 },
599         { AR5K_RATE_DUR(18),    0x00000000 },
600         { AR5K_RATE_DUR(19),    0x00000000 },
601         { AR5K_RATE_DUR(20),    0x00000000 },
602         { AR5K_RATE_DUR(21),    0x00000000 },
603         { AR5K_RATE_DUR(22),    0x00000000 },
604         { AR5K_RATE_DUR(23),    0x00000000 },
605         { AR5K_RATE_DUR(24),    0x000000d5 },
606         { AR5K_RATE_DUR(25),    0x000000df },
607         { AR5K_RATE_DUR(26),    0x00000102 },
608         { AR5K_RATE_DUR(27),    0x0000013a },
609         { AR5K_RATE_DUR(28),    0x00000075 },
610         { AR5K_RATE_DUR(29),    0x0000007f },
611         { AR5K_RATE_DUR(30),    0x000000a2 },
612         { AR5K_RATE_DUR(31),    0x00000000 },
613         { 0x8100, 0x00010002},
614         { AR5K_TSF_PARM,        0x00000001 },
615         { 0x8108, 0x000000c0 },
616         { AR5K_PHY_ERR_FIL,     0x00000000 },
617         { 0x8110, 0x00000168 },
618         { 0x8114, 0x00000000 },
619         /* Some kind of table
620          * also notice ...03<-02<-01<-00) */
621         { 0x87c0, 0x03020100 },
622         { 0x87c4, 0x07060504 },
623         { 0x87c8, 0x0b0a0908 },
624         { 0x87cc, 0x0f0e0d0c },
625         { 0x87d0, 0x13121110 },
626         { 0x87d4, 0x17161514 },
627         { 0x87d8, 0x1b1a1918 },
628         { 0x87dc, 0x1f1e1d1c },
629         /* loop ? */
630         { 0x87e0, 0x03020100 },
631         { 0x87e4, 0x07060504 },
632         { 0x87e8, 0x0b0a0908 },
633         { 0x87ec, 0x0f0e0d0c },
634         { 0x87f0, 0x13121110 },
635         { 0x87f4, 0x17161514 },
636         { 0x87f8, 0x1b1a1918 },
637         { 0x87fc, 0x1f1e1d1c },
638         /* PHY registers */
639         /*{ AR5K_PHY_AGC, 0x00000000 },*/
640         { AR5K_PHY(3),  0xad848e19 },
641         { AR5K_PHY(4),  0x7d28e000 },
642         { AR5K_PHY_TIMING_3, 0x9c0a9f6b },
643         { AR5K_PHY_ACT, 0x00000000 },
644         /*{ AR5K_PHY(11), 0x00022ffe },*/
645         /*{ AR5K_PHY(15), 0x00020100 },*/
646         { AR5K_PHY(16), 0x206a017a },
647         /*{ AR5K_PHY(19), 0x1284613c },*/
648         { AR5K_PHY(21), 0x00000859 },
649         { AR5K_PHY(64), 0x00000000 },
650         { AR5K_PHY(65), 0x00000000 },
651         { AR5K_PHY(66), 0x00000000 },
652         { AR5K_PHY(67), 0x00800000 },
653         { AR5K_PHY(68), 0x00000001 },
654         /*{ AR5K_PHY(71), 0x0000092a },*/ /* Old value */
655         { AR5K_PHY(71), 0x00000c80 },
656         { AR5K_PHY_IQ,  0x05100000 },
657         { AR5K_PHY(74), 0x00000001 },
658         { AR5K_PHY(75), 0x00000004 },
659         { AR5K_PHY_TXPOWER_RATE1, 0x1e1f2022 },
660         { AR5K_PHY_TXPOWER_RATE2, 0x0a0b0c0d },
661         { AR5K_PHY_TXPOWER_RATE_MAX, 0x0000003f },
662         /*{ AR5K_PHY(80), 0x00000004 },*/
663         { AR5K_PHY(82), 0x9280b212 },
664         { AR5K_PHY_RADAR, 0x5d50e188 },
665         /*{ AR5K_PHY(86), 0x000000ff },*/
666         { AR5K_PHY(87), 0x004b6a8e },
667         { AR5K_PHY(90), 0x000003ce },
668         { AR5K_PHY(92), 0x192fb515 },
669         /*{ AR5K_PHY(93), 0x00000000 },*/
670         { AR5K_PHY(94), 0x00000001 },
671         { AR5K_PHY(95), 0x00000000 },
672         /*{ AR5K_PHY(644), 0x0080a333 },*/ /* Old value */
673         /*{ AR5K_PHY(645), 0x00206c10 },*/ /* Old value */
674         { AR5K_PHY(644), 0x00806333 },
675         { AR5K_PHY(645), 0x00106c10 },
676         { AR5K_PHY(646), 0x009c4060 },
677         { AR5K_PHY(647), 0x1483800a },
678         /* { AR5K_PHY(648), 0x018830c6 },*/ /* 2413/2425 */
679         { AR5K_PHY(648), 0x01831061 },
680         { AR5K_PHY(649), 0x00000400 },
681         /*{ AR5K_PHY(650), 0x000001b5 },*/
682         { AR5K_PHY(651), 0x00000000 },
683         { AR5K_PHY_TXPOWER_RATE3, 0x20202020 },
684         { AR5K_PHY_TXPOWER_RATE2, 0x20202020 },
685         /*{ AR5K_PHY(655), 0x13c889af },*/
686         { AR5K_PHY(656), 0x38490a20 },
687         { AR5K_PHY(657), 0x00007bb6 },
688         { AR5K_PHY(658), 0x0fff3ffc },
689         /*{ AR5K_PHY_CCKTXCTL, 0x00000000 },*/
690 };
691
692 /* Initial mode-specific settings for AR5212 (Written before ar5212_ini) */
693 static const struct ath5k_ini_mode ar5212_ini_mode_start[] = {
694         { AR5K_PHY(640),
695         /*        a/XR        aTurbo      b           g (DYN)     gTurbo */
696                 { 0x00000008, 0x00000008, 0x0000000b, 0x0000000e, 0x0000000e } },
697         { AR5K_PHY(0),
698                 { 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 } },
699         { AR5K_QUEUE_DFS_LOCAL_IFS(0),
700                 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
701         { AR5K_QUEUE_DFS_LOCAL_IFS(1),
702                 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
703         { AR5K_QUEUE_DFS_LOCAL_IFS(2),
704                 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
705         { AR5K_QUEUE_DFS_LOCAL_IFS(3),
706                 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
707         { AR5K_QUEUE_DFS_LOCAL_IFS(4),
708                 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
709         { AR5K_QUEUE_DFS_LOCAL_IFS(5),
710                 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
711         { AR5K_QUEUE_DFS_LOCAL_IFS(6),
712                 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
713         { AR5K_QUEUE_DFS_LOCAL_IFS(7),
714                 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
715         { AR5K_QUEUE_DFS_LOCAL_IFS(8),
716                 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
717         { AR5K_QUEUE_DFS_LOCAL_IFS(9),
718                 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
719         { AR5K_DCU_GBL_IFS_SIFS,
720                 { 0x00000230, 0x000001e0, 0x000000b0, 0x00000160, 0x000001e0 } },
721         { AR5K_DCU_GBL_IFS_SLOT,
722                 { 0x00000168, 0x000001e0, 0x000001b8, 0x0000018c, 0x000001e0 } },
723         { AR5K_DCU_GBL_IFS_EIFS,
724                 { 0x00000e60, 0x00001180, 0x00001f1c, 0x00003e38, 0x00001180 } },
725         { AR5K_DCU_GBL_IFS_MISC,
726                 { 0x0000a0e0, 0x00014068, 0x00005880, 0x0000b0e0, 0x00014068 } },
727         { AR5K_TIME_OUT,
728                 { 0x03e803e8, 0x06e006e0, 0x04200420, 0x08400840, 0x06e006e0 } },
729         { AR5K_PHY_TURBO,
730                 { 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000003 } },
731         { AR5K_PHY(8),
732                 { 0x02020200, 0x02020200, 0x02010200, 0x02020200, 0x02020200 } },
733         { AR5K_PHY(9),
734                 { 0x00000e0e, 0x00000e0e, 0x00000707, 0x00000e0e, 0x00000e0e } },
735         { AR5K_PHY(17),
736                 { 0x1372161c, 0x13721c25, 0x13721722, 0x137216a2, 0x13721c25 } },
737         { AR5K_PHY_AGCCTL,
738                 { 0x00009d10, 0x00009d10, 0x00009d18, 0x00009d18, 0x00009d18 } },
739         { AR5K_PHY_NF,
740                 { 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 } },
741         { AR5K_PHY(26),
742                 { 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190 } },
743         { AR5K_PHY(70),
744                 { 0x000001b8, 0x000001b8, 0x00000084, 0x00000108, 0x000001b8 } },
745         { AR5K_PHY(73),
746                 { 0x10058a05, 0x10058a05, 0x10058a05, 0x10058a05, 0x10058a05 } },
747         { 0xa230,
748                 { 0x00000000, 0x00000000, 0x00000000, 0x00000108, 0x00000000 } },
749 };
750
751 /* Initial mode-specific settings for AR5212 + RF5111 (Written after ar5212_ini) */
752 /* New dump pending */
753 static const struct ath5k_ini_mode ar5212_rf5111_ini_mode_end[] = {
754         { AR5K_PHY(640), /* This one differs from ar5212_ini_mode_start ! */
755         /*        a/XR        aTurbo      b           g (DYN)     gTurbo */
756                 { 0x00000000, 0x00000000, 0x00000003, 0x00000006, 0x00000006 } },
757         { AR5K_TXCFG,
758                 { 0x00008015, 0x00008015, 0x00008015, 0x00008015, 0x00008015 } },
759         { AR5K_USEC_5211,
760                 { 0x128d8fa7, 0x09880fcf, 0x04e00f95, 0x12e00fab, 0x09880fcf } },
761         { AR5K_PHY(10),
762                 { 0x0a020001, 0x0a020001, 0x05010100, 0x0a020001, 0x0a020001 } },
763         { AR5K_PHY(13),
764                 { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } },
765         { AR5K_PHY(14),
766                 { 0x00000007, 0x00000007, 0x0000000b, 0x0000000b, 0x0000000b } },
767         { AR5K_PHY(18),
768                 { 0x0018da5a, 0x0018da5a, 0x0018ca69, 0x0018ca69, 0x0018ca69 } },
769         { AR5K_PHY(20),
770                 { 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0 } },
771         { AR5K_PHY_SIG,
772                 { 0x7e800d2e, 0x7e800d2e, 0x7ee84d2e, 0x7ee84d2e, 0x7e800d2e } },
773         { AR5K_PHY_AGCCOARSE,
774                 { 0x3137665e, 0x3137665e, 0x3137665e, 0x3137665e, 0x3137615e } },
775         { AR5K_PHY(27),
776                 { 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb080, 0x050cb080 } },
777         { AR5K_PHY_RX_DELAY,
778                 { 0x00002710, 0x00002710, 0x0000157c, 0x00002af8, 0x00002710 } },
779         { AR5K_PHY_FRAME_CTL_5211,
780                 { 0xf7b81020, 0xf7b81020, 0xf7b80d20, 0xf7b81020, 0xf7b81020 } },
781         { AR5K_PHY_GAIN_2GHZ,
782                 { 0x642c416a, 0x642c416a, 0x6440416a, 0x6440416a, 0x6440416a } },
783         { 0xa21c,
784                 { 0x1883800a, 0x1883800a, 0x1873800a, 0x1883800a, 0x1883800a } },
785         { AR5K_DCU_FP,
786                 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
787         { AR5K_PHY_AGC,
788                 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
789         { AR5K_PHY(11),
790                 { 0x00022ffe, 0x00022ffe, 0x00022ffe, 0x00022ffe, 0x00022ffe } },
791         { AR5K_PHY(15),
792                 { 0x00020100, 0x00020100, 0x00020100, 0x00020100, 0x00020100 } },
793         { AR5K_PHY(19),
794                 { 0x1284613c, 0x1284613c, 0x1284613c, 0x1284613c, 0x1284613c } },
795         { AR5K_PHY_PAPD_PROBE,
796                 { 0x00004883, 0x00004883, 0x00004883, 0x00004883, 0x00004883 } },
797         { AR5K_PHY(80),
798                 { 0x00000004, 0x00000004, 0x00000004, 0x00000004, 0x00000004 } },
799         { AR5K_PHY(86),
800                 { 0x000000ff, 0x000000ff, 0x000000ff, 0x000000ff, 0x000000ff } },
801         { AR5K_PHY(93),
802                 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
803         { AR5K_PHY_SPENDING,
804                 { 0x00000018, 0x00000018, 0x00000018, 0x00000018, 0x00000018 } },
805         { AR5K_PHY_CCKTXCTL,
806                 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
807         { AR5K_PHY(642),
808                 { 0xd03e6788, 0xd03e6788, 0xd03e6788, 0xd03e6788, 0xd03e6788 } },
809         { 0xa23c,
810                 { 0x13c889af, 0x13c889af, 0x13c889af, 0x13c889af, 0x13c889af } },
811 };
812
813 /* Initial mode-specific settings for AR5212 + RF5112 (Written after ar5212_ini) */
814 /* XXX: No dumps for turbog yet, but i found settings from old values so it should be ok */
815 static const struct ath5k_ini_mode ar5212_rf5112_ini_mode_end[] = {
816         { AR5K_TXCFG,
817         /*        a/XR        aTurbo      b           g (DYN)     gTurbo */
818                 { 0x00008015, 0x00008015, 0x00008015, 0x00008015, 0x00008015 } },
819         { AR5K_USEC_5211,
820                 { 0x128d93a7, 0x098813cf, 0x04e01395, 0x12e013ab, 0x098813cf } },
821         { AR5K_PHY(10),
822                 { 0x0a020001, 0x0a020001, 0x05020100, 0x0a020001, 0x0a020001 } },
823         { AR5K_PHY(13),
824                 { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } },
825         { AR5K_PHY(14),
826                 { 0x00000007, 0x00000007, 0x0000000b, 0x0000000b, 0x0000000b } },
827         { AR5K_PHY(18),
828                 { 0x0018da6d, 0x0018da6d, 0x0018ca75, 0x0018ca75, 0x0018ca75 } },
829         { AR5K_PHY(20),
830                 { 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0 } },
831         { AR5K_PHY_SIG,
832                 { 0x7e800d2e, 0x7e800d2e, 0x7ee80d2e, 0x7ee80d2e, 0x7ee80d2e } },
833         { AR5K_PHY_AGCCOARSE,
834                 { 0x3137665e, 0x3137665e, 0x3137665e, 0x3137665e, 0x3137665e } },
835         { AR5K_PHY(27),
836                 { 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 } },
837         { AR5K_PHY_RX_DELAY,
838                 { 0x000007d0, 0x000007d0, 0x0000044c, 0x00000898, 0x000007d0 } },
839         { AR5K_PHY_FRAME_CTL_5211,
840                 { 0xf7b81020, 0xf7b81020, 0xf7b80d10, 0xf7b81010, 0xf7b81010 } },
841         { AR5K_PHY_CCKTXCTL,
842                 { 0x00000000, 0x00000000, 0x00000008, 0x00000008, 0x00000008 } },
843         { AR5K_PHY(642),
844                 { 0xd6be6788, 0xd6be6788, 0xd03e6788, 0xd03e6788, 0xd03e6788 } },
845         { AR5K_PHY_GAIN_2GHZ,
846                 { 0x642c0140, 0x642c0140, 0x6442c160, 0x6442c160, 0x6442c160 } },
847         { 0xa21c,
848                 { 0x1883800a, 0x1883800a, 0x1873800a, 0x1883800a, 0x1883800a } },
849         { AR5K_DCU_FP,
850                 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
851         { AR5K_PHY_AGC,
852                 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
853         { AR5K_PHY(11),
854                 { 0x00022ffe, 0x00022ffe, 0x00022ffe, 0x00022ffe, 0x00022ffe } },
855         { AR5K_PHY(15),
856                 { 0x00020100, 0x00020100, 0x00020100, 0x00020100, 0x00020100 } },
857         { AR5K_PHY(19),
858                 { 0x1284613c, 0x1284613c, 0x1284613c, 0x1284613c, 0x1284613c } },
859         { AR5K_PHY_PAPD_PROBE,
860                 { 0x00004882, 0x00004882, 0x00004882, 0x00004882, 0x00004882 } },
861         { AR5K_PHY(80),
862                 { 0x00000004, 0x00000004, 0x00000004, 0x00000004, 0x00000004 } },
863         { AR5K_PHY(86),
864                 { 0x000000ff, 0x000000ff, 0x000000ff, 0x000000ff, 0x000000ff } },
865         { AR5K_PHY(93),
866                 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
867         { 0xa228,
868                 { 0x000001b5, 0x000001b5, 0x000001b5, 0x000001b5, 0x000001b5 } },
869         { 0xa23c,
870                 { 0x13c889af, 0x13c889af, 0x13c889af, 0x13c889af, 0x13c889af } },
871 };
872
873 /* Initial mode-specific settings for RF5413/5414 (Written after ar5212_ini) */
874 /* XXX: No dumps for turbog yet, so turbog is the same with g here with some
875  * minor tweaking based on dumps from other chips */
876 static const struct ath5k_ini_mode rf5413_ini_mode_end[] = {
877         { AR5K_TXCFG,
878         /*        a/XR        aTurbo      b           g           gTurbo */
879                 { 0x00000015, 0x00000015, 0x00000015, 0x00000015, 0x00000015 } },
880         { AR5K_USEC_5211,
881                 { 0x128d93a7, 0x098813cf, 0x04e01395, 0x12e013ab, 0x098813cf } },
882         { AR5K_PHY(10),
883                 { 0x0a020001, 0x0a020001, 0x05020100, 0x0a020001, 0x0a020001 } },
884         { AR5K_PHY(13),
885                 { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } },
886         { AR5K_PHY(14),
887                 { 0x00000007, 0x00000007, 0x0000000b, 0x0000000b, 0x0000000b } },
888         { AR5K_PHY(18),
889                 { 0x0018fa61, 0x0018fa61, 0x001a1a63, 0x001a1a63, 0x001a1a63 } },
890         { AR5K_PHY(20),
891                 { 0x0c98b4e0, 0x0c98b4e0, 0x0c98b0da, 0x0c98b0da, 0x0c98b0da } },
892         { AR5K_PHY_SIG,
893                 { 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e } },
894         { AR5K_PHY_AGCCOARSE,
895                 { 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e } },
896         { AR5K_PHY(27),
897                 { 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 } },
898         { AR5K_PHY_RX_DELAY,
899                 { 0x000007d0, 0x000007d0, 0x0000044c, 0x00000898, 0x000007d0 } },
900         { AR5K_PHY_FRAME_CTL_5211,
901                 { 0xf7b81000, 0xf7b81000, 0xf7b80d00, 0xf7b81000, 0xf7b81000 } },
902         { AR5K_PHY_CCKTXCTL,
903                 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
904         { AR5K_PHY(642),
905                 { 0xd6be6788, 0xd6be6788, 0xd03e6788, 0xd03e6788, 0xd03e6788 } },
906         { AR5K_PHY_GAIN_2GHZ,
907                 { 0x002ec1e0, 0x002ec1e0, 0x002ac120, 0x002ac120, 0x002ac120 } },
908         { 0xa21c,
909                 { 0x1883800a, 0x1883800a, 0x1863800a, 0x1883800a, 0x1883800a } },
910         { 0xa300,
911                 { 0x18010000, 0x18010000, 0x18010000, 0x18010000, 0x18010000 } },
912         { 0xa304,
913                 { 0x30032602, 0x30032602, 0x30032602, 0x30032602, 0x30032602 } },
914         { 0xa308,
915                 { 0x48073e06, 0x48073e06, 0x48073e06, 0x48073e06, 0x48073e06 } },
916         { 0xa30c,
917                 { 0x560b4c0a, 0x560b4c0a, 0x560b4c0a, 0x560b4c0a, 0x560b4c0a } },
918         { 0xa310,
919                 { 0x641a600f, 0x641a600f, 0x641a600f, 0x641a600f, 0x641a600f } },
920         { 0xa314,
921                 { 0x784f6e1b, 0x784f6e1b, 0x784f6e1b, 0x784f6e1b, 0x784f6e1b } },
922         { 0xa318,
923                 { 0x868f7c5a, 0x868f7c5a, 0x868f7c5a, 0x868f7c5a, 0x868f7c5a } },
924         { 0xa31c,
925                 { 0x90cf865b, 0x90cf865b, 0x8ecf865b, 0x8ecf865b, 0x8ecf865b } },
926         { 0xa320,
927                 { 0x9d4f970f, 0x9d4f970f, 0x9b4f970f, 0x9b4f970f, 0x9b4f970f } },
928         { 0xa324,
929                 { 0xa7cfa38f, 0xa7cfa38f, 0xa3cf9f8f, 0xa3cf9f8f, 0xa3cf9f8f } },
930         { 0xa328,
931                 { 0xb55faf1f, 0xb55faf1f, 0xb35faf1f, 0xb35faf1f, 0xb35faf1f } },
932         { 0xa32c,
933                 { 0xbddfb99f, 0xbddfb99f, 0xbbdfb99f, 0xbbdfb99f, 0xbbdfb99f } },
934         { 0xa330,
935                 { 0xcb7fc53f, 0xcb7fc53f, 0xcb7fc73f, 0xcb7fc73f, 0xcb7fc73f } },
936         { 0xa334,
937                 { 0xd5ffd1bf, 0xd5ffd1bf, 0xd3ffd1bf, 0xd3ffd1bf, 0xd3ffd1bf } },
938         { AR5K_DCU_FP,
939                 { 0x000003e0, 0x000003e0, 0x000003e0, 0x000003e0, 0x000003e0 } },
940         { 0x4068,
941                 { 0x00000010, 0x00000010, 0x00000010, 0x00000010, 0x00000010 } },
942         { 0x8060,
943                 { 0x0000000f, 0x0000000f, 0x0000000f, 0x0000000f, 0x0000000f } },
944         { 0x809c,
945                 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
946         { 0x80a0,
947                 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
948         { 0x8118,
949                 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
950         { 0x811c,
951                 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
952         { 0x8120,
953                 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
954         { 0x8124,
955                 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
956         { 0x8128,
957                 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
958         { 0x812c,
959                 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
960         { 0x8130,
961                 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
962         { 0x8134,
963                 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
964         { 0x8138,
965                 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
966         { 0x813c,
967                 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
968         { 0x8140,
969                 { 0x800003f9, 0x800003f9, 0x800003f9, 0x800003f9, 0x800003f9 } },
970         { 0x8144,
971                 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
972         { AR5K_PHY_AGC,
973                 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
974         { AR5K_PHY(11),
975                 { 0x0000a000, 0x0000a000, 0x0000a000, 0x0000a000, 0x0000a000 } },
976         { AR5K_PHY(15),
977                 { 0x00200400, 0x00200400, 0x00200400, 0x00200400, 0x00200400 } },
978         { AR5K_PHY(19),
979                 { 0x1284233c, 0x1284233c, 0x1284233c, 0x1284233c, 0x1284233c } },
980         { AR5K_PHY_SCR,
981                 { 0x0000001f, 0x0000001f, 0x0000001f, 0x0000001f, 0x0000001f } },
982         { AR5K_PHY_SLMT,
983                 { 0x00000080, 0x00000080, 0x00000080, 0x00000080, 0x00000080 } },
984         { AR5K_PHY_SCAL,
985                 { 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e } },
986         { AR5K_PHY(86),
987                 { 0x00081fff, 0x00081fff, 0x00081fff, 0x00081fff, 0x00081fff } },
988         { AR5K_PHY(96),
989                 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
990         { AR5K_PHY(97),
991                 { 0x02800000, 0x02800000, 0x02800000, 0x02800000, 0x02800000 } },
992         { AR5K_PHY(104),
993                 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
994         { AR5K_PHY(120),
995                 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
996         { AR5K_PHY(121),
997                 { 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa } },
998         { AR5K_PHY(122),
999                 { 0x3c466478, 0x3c466478, 0x3c466478, 0x3c466478, 0x3c466478 } },
1000         { AR5K_PHY(123),
1001                 { 0x000000aa, 0x000000aa, 0x000000aa, 0x000000aa, 0x000000aa } },
1002         { AR5K_PHY_SCLOCK,
1003                 { 0x0000000c, 0x0000000c, 0x0000000c, 0x0000000c, 0x0000000c } },
1004         { AR5K_PHY_SDELAY,
1005                 { 0x000000ff, 0x000000ff, 0x000000ff, 0x000000ff, 0x000000ff } },
1006         { AR5K_PHY_SPENDING,
1007                 { 0x00000014, 0x00000014, 0x00000014, 0x00000014, 0x00000014 } },
1008         { 0xa228,
1009                 { 0x000009b5, 0x000009b5, 0x000009b5, 0x000009b5, 0x000009b5 } },
1010         { 0xa23c,
1011                 { 0x93c889af, 0x93c889af, 0x93c889af, 0x93c889af, 0x93c889af } },
1012         { 0xa24c,
1013                 { 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001 } },
1014         { 0xa250,
1015                 { 0x0000a000, 0x0000a000, 0x0000a000, 0x0000a000, 0x0000a000 } },
1016         { 0xa254,
1017                 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
1018         { 0xa258,
1019                 { 0x0cc75380, 0x0cc75380, 0x0cc75380, 0x0cc75380, 0x0cc75380 } },
1020         { 0xa25c,
1021                 { 0x0f0f0f01, 0x0f0f0f01, 0x0f0f0f01, 0x0f0f0f01, 0x0f0f0f01 } },
1022         { 0xa260,
1023                 { 0x5f690f01, 0x5f690f01, 0x5f690f01, 0x5f690f01, 0x5f690f01 } },
1024         { 0xa264,
1025                 { 0x00418a11, 0x00418a11, 0x00418a11, 0x00418a11, 0x00418a11 } },
1026         { 0xa268,
1027                 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
1028         { 0xa26c,
1029                 { 0x0c30c16a, 0x0c30c16a, 0x0c30c16a, 0x0c30c16a, 0x0c30c16a } },
1030         { 0xa270,
1031                 { 0x00820820, 0x00820820, 0x00820820, 0x00820820, 0x00820820 } },
1032         { 0xa274,
1033                 { 0x081b7caa, 0x081b7caa, 0x081b7caa, 0x081b7caa, 0x081b7caa } },
1034         { 0xa278,
1035                 { 0x1ce739ce, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce } },
1036         { 0xa27c,
1037                 { 0x051701ce, 0x051701ce, 0x051701ce, 0x051701ce, 0x051701ce } },
1038         { 0xa338,
1039                 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
1040         { 0xa33c,
1041                 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
1042         { 0xa340,
1043                 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
1044         { 0xa344,
1045                 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
1046         { 0xa348,
1047                 { 0x3fffffff, 0x3fffffff, 0x3fffffff, 0x3fffffff, 0x3fffffff } },
1048         { 0xa34c,
1049                 { 0x3fffffff, 0x3fffffff, 0x3fffffff, 0x3fffffff, 0x3fffffff } },
1050         { 0xa350,
1051                 { 0x3fffffff, 0x3fffffff, 0x3fffffff, 0x3fffffff, 0x3fffffff } },
1052         { 0xa354,
1053                 { 0x0003ffff, 0x0003ffff, 0x0003ffff, 0x0003ffff, 0x0003ffff } },
1054         { 0xa358,
1055                 { 0x79a8aa1f, 0x79a8aa1f, 0x79a8aa1f, 0x79a8aa1f, 0x79a8aa1f } },
1056         { 0xa35c,
1057                 { 0x066c420f, 0x066c420f, 0x066c420f, 0x066c420f, 0x066c420f } },
1058         { 0xa360,
1059                 { 0x0f282207, 0x0f282207, 0x0f282207, 0x0f282207, 0x0f282207 } },
1060         { 0xa364,
1061                 { 0x17601685, 0x17601685, 0x17601685, 0x17601685, 0x17601685 } },
1062         { 0xa368,
1063                 { 0x1f801104, 0x1f801104, 0x1f801104, 0x1f801104, 0x1f801104 } },
1064         { 0xa36c,
1065                 { 0x37a00c03, 0x37a00c03, 0x37a00c03, 0x37a00c03, 0x37a00c03 } },
1066         { 0xa370,
1067                 { 0x3fc40883, 0x3fc40883, 0x3fc40883, 0x3fc40883, 0x3fc40883 } },
1068         { 0xa374,
1069                 { 0x57c00803, 0x57c00803, 0x57c00803, 0x57c00803, 0x57c00803 } },
1070         { 0xa378,
1071                 { 0x5fd80682, 0x5fd80682, 0x5fd80682, 0x5fd80682, 0x5fd80682 } },
1072         { 0xa37c,
1073                 { 0x7fe00482, 0x7fe00482, 0x7fe00482, 0x7fe00482, 0x7fe00482 } },
1074         { 0xa380,
1075                 { 0x7f3c7bba, 0x7f3c7bba, 0x7f3c7bba, 0x7f3c7bba, 0x7f3c7bba } },
1076         { 0xa384,
1077                 { 0xf3307ff0, 0xf3307ff0, 0xf3307ff0, 0xf3307ff0, 0xf3307ff0 } },
1078 };
1079
1080 /* Initial mode-specific settings for RF2413/2414 (Written after ar5212_ini) */
1081 /* XXX: No dumps for turbog yet, so turbog is the same with g here with some
1082  * minor tweaking based on dumps from other chips */
1083 static const struct ath5k_ini_mode rf2413_ini_mode_end[] = {
1084         { AR5K_TXCFG,
1085         /*            b         g           gTurbo */
1086                 { 0x00000015, 0x00000015, 0x00000015 } },
1087         { AR5K_USEC_5211,
1088                 { 0x04e01395, 0x12e013ab, 0x098813cf } },
1089         { AR5K_PHY(10),
1090                 { 0x05020000, 0x0a020001, 0x0a020001 } },
1091         { AR5K_PHY(13),
1092                 { 0x00000e00, 0x00000e00, 0x00000e00 } },
1093         { AR5K_PHY(14),
1094                 { 0x0000000a, 0x0000000a, 0x0000000a } },
1095         { AR5K_PHY(18),
1096                 { 0x001a6a64, 0x001a6a64, 0x001a6a64 } },
1097         { AR5K_PHY(20),
1098                 { 0x0de8b0da, 0x0c98b0da, 0x0c98b0da } },
1099         { AR5K_PHY_SIG,
1100                 { 0x7ee80d2e, 0x7ec80d2e, 0x7ec80d2e } },
1101         { AR5K_PHY_AGCCOARSE,
1102                 { 0x3137665e, 0x3139605e, 0x3139605e } },
1103         { AR5K_PHY(27),
1104                 { 0x050cb081, 0x050cb081, 0x050cb081 } },
1105         { AR5K_PHY_RX_DELAY,
1106                 { 0x0000044c, 0x00000898, 0x000007d0 } },
1107         { AR5K_PHY_FRAME_CTL_5211,
1108                 { 0xf7b80d00, 0xf7b81000, 0xf7b81000 } },
1109         { AR5K_PHY_CCKTXCTL,
1110                 { 0x00000000, 0x00000000, 0x00000000 } },
1111         { AR5K_PHY(642),
1112                 { 0xd03e6788, 0xd03e6788, 0xd03e6788 } },
1113         { AR5K_PHY_GAIN_2GHZ,
1114                 { 0x0042c140, 0x0042c140, 0x0042c140 } },
1115         { 0xa21c,
1116                 { 0x1863800a, 0x1883800a, 0x1883800a } },
1117         { AR5K_DCU_FP,
1118                 { 0x000003e0, 0x000003e0, 0x000003e0 } },
1119         { 0x8060,
1120                 { 0x0000000f, 0x0000000f, 0x0000000f } },
1121         { 0x8118,
1122                 { 0x00000000, 0x00000000, 0x00000000 } },
1123         { 0x811c,
1124                 { 0x00000000, 0x00000000, 0x00000000 } },
1125         { 0x8120,
1126                 { 0x00000000, 0x00000000, 0x00000000 } },
1127         { 0x8124,
1128                 { 0x00000000, 0x00000000, 0x00000000 } },
1129         { 0x8128,
1130                 { 0x00000000, 0x00000000, 0x00000000 } },
1131         { 0x812c,
1132                 { 0x00000000, 0x00000000, 0x00000000 } },
1133         { 0x8130,
1134                 { 0x00000000, 0x00000000, 0x00000000 } },
1135         { 0x8134,
1136                 { 0x00000000, 0x00000000, 0x00000000 } },
1137         { 0x8138,
1138                 { 0x00000000, 0x00000000, 0x00000000 } },
1139         { 0x813c,
1140                 { 0x00000000, 0x00000000, 0x00000000 } },
1141         { 0x8140,
1142                 { 0x800000a8, 0x800000a8, 0x800000a8 } },
1143         { 0x8144,
1144                 { 0x00000000, 0x00000000, 0x00000000 } },
1145         { AR5K_PHY_AGC,
1146                 { 0x00000000, 0x00000000, 0x00000000 } },
1147         { AR5K_PHY(11),
1148                 { 0x0000a000, 0x0000a000, 0x0000a000 } },
1149         { AR5K_PHY(15),
1150                 { 0x00200400, 0x00200400, 0x00200400 } },
1151         { AR5K_PHY(19),
1152                 { 0x1284233c, 0x1284233c, 0x1284233c } },
1153         { AR5K_PHY_SCR,
1154                 { 0x0000001f, 0x0000001f, 0x0000001f } },
1155         { AR5K_PHY_SLMT,
1156                 { 0x00000080, 0x00000080, 0x00000080 } },
1157         { AR5K_PHY_SCAL,
1158                 { 0x0000000e, 0x0000000e, 0x0000000e } },
1159         { AR5K_PHY(86),
1160                 { 0x000000ff, 0x000000ff, 0x000000ff } },
1161         { AR5K_PHY(96),
1162                 { 0x00000000, 0x00000000, 0x00000000 } },
1163         { AR5K_PHY(97),
1164                 { 0x02800000, 0x02800000, 0x02800000 } },
1165         { AR5K_PHY(104),
1166                 { 0x00000000, 0x00000000, 0x00000000 } },
1167         { AR5K_PHY(120),
1168                 { 0x00000000, 0x00000000, 0x00000000 } },
1169         { AR5K_PHY(121),
1170                 { 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa } },
1171         { AR5K_PHY(122),
1172                 { 0x3c466478, 0x3c466478, 0x3c466478 } },
1173         { AR5K_PHY(123),
1174                 { 0x000000aa, 0x000000aa, 0x000000aa } },
1175         { AR5K_PHY_SCLOCK,
1176                 { 0x0000000c, 0x0000000c, 0x0000000c } },
1177         { AR5K_PHY_SDELAY,
1178                 { 0x000000ff, 0x000000ff, 0x000000ff } },
1179         { AR5K_PHY_SPENDING,
1180                 { 0x00000014, 0x00000014, 0x00000014 } },
1181         { 0xa228,
1182                 { 0x000009b5, 0x000009b5, 0x000009b5 } },
1183         { 0xa23c,
1184                 { 0x93c889af, 0x93c889af, 0x93c889af } },
1185         { 0xa24c,
1186                 { 0x00000001, 0x00000001, 0x00000001 } },
1187         { 0xa250,
1188                 { 0x0000a000, 0x0000a000, 0x0000a000 } },
1189         { 0xa254,
1190                 { 0x00000000, 0x00000000, 0x00000000 } },
1191         { 0xa258,
1192                 { 0x0cc75380, 0x0cc75380, 0x0cc75380 } },
1193         { 0xa25c,
1194                 { 0x0f0f0f01, 0x0f0f0f01, 0x0f0f0f01 } },
1195         { 0xa260,
1196                 { 0x5f690f01, 0x5f690f01, 0x5f690f01 } },
1197         { 0xa264,
1198                 { 0x00418a11, 0x00418a11, 0x00418a11 } },
1199         { 0xa268,
1200                 { 0x00000000, 0x00000000, 0x00000000 } },
1201         { 0xa26c,
1202                 { 0x0c30c16a, 0x0c30c16a, 0x0c30c16a } },
1203         { 0xa270,
1204                 { 0x00820820, 0x00820820, 0x00820820 } },
1205         { 0xa274,
1206                 { 0x001b7caa, 0x001b7caa, 0x001b7caa } },
1207         { 0xa278,
1208                 { 0x1ce739ce, 0x1ce739ce, 0x1ce739ce } },
1209         { 0xa27c,
1210                 { 0x051701ce, 0x051701ce, 0x051701ce } },
1211         { 0xa300,
1212                 { 0x18010000, 0x18010000, 0x18010000 } },
1213         { 0xa304,
1214                 { 0x30032602, 0x30032602, 0x30032602 } },
1215         { 0xa308,
1216                 { 0x48073e06, 0x48073e06, 0x48073e06 } },
1217         { 0xa30c,
1218                 { 0x560b4c0a, 0x560b4c0a, 0x560b4c0a } },
1219         { 0xa310,
1220                 { 0x641a600f, 0x641a600f, 0x641a600f } },
1221         { 0xa314,
1222                 { 0x784f6e1b, 0x784f6e1b, 0x784f6e1b } },
1223         { 0xa318,
1224                 { 0x868f7c5a, 0x868f7c5a, 0x868f7c5a } },
1225         { 0xa31c,
1226                 { 0x8ecf865b, 0x8ecf865b, 0x8ecf865b } },
1227         { 0xa320,
1228                 { 0x9d4f970f, 0x9d4f970f, 0x9d4f970f } },
1229         { 0xa324,
1230                 { 0xa5cfa18f, 0xa5cfa18f, 0xa5cfa18f } },
1231         { 0xa328,
1232                 { 0xb55faf1f, 0xb55faf1f, 0xb55faf1f } },
1233         { 0xa32c,
1234                 { 0xbddfb99f, 0xbddfb99f, 0xbddfb99f } },
1235         { 0xa330,
1236                 { 0xcd7fc73f, 0xcd7fc73f, 0xcd7fc73f } },
1237         { 0xa334,
1238                 { 0xd5ffd1bf, 0xd5ffd1bf, 0xd5ffd1bf } },
1239         { 0xa338,
1240                 { 0x00000000, 0x00000000, 0x00000000 } },
1241         { 0xa33c,
1242                 { 0x00000000, 0x00000000, 0x00000000 } },
1243         { 0xa340,
1244                 { 0x00000000, 0x00000000, 0x00000000 } },
1245         { 0xa344,
1246                 { 0x00000000, 0x00000000, 0x00000000 } },
1247         { 0xa348,
1248                 { 0x3fffffff, 0x3fffffff, 0x3fffffff } },
1249         { 0xa34c,
1250                 { 0x3fffffff, 0x3fffffff, 0x3fffffff } },
1251         { 0xa350,
1252                 { 0x3fffffff, 0x3fffffff, 0x3fffffff } },
1253         { 0xa354,
1254                 { 0x0003ffff, 0x0003ffff, 0x0003ffff } },
1255         { 0xa358,
1256                 { 0x79a8aa1f, 0x79a8aa1f, 0x79a8aa1f } },
1257         { 0xa35c,
1258                 { 0x066c420f, 0x066c420f, 0x066c420f } },
1259         { 0xa360,
1260                 { 0x0f282207, 0x0f282207, 0x0f282207 } },
1261         { 0xa364,
1262                 { 0x17601685, 0x17601685, 0x17601685 } },
1263         { 0xa368,
1264                 { 0x1f801104, 0x1f801104, 0x1f801104 } },
1265         { 0xa36c,
1266                 { 0x37a00c03, 0x37a00c03, 0x37a00c03 } },
1267         { 0xa370,
1268                 { 0x3fc40883, 0x3fc40883, 0x3fc40883 } },
1269         { 0xa374,
1270                 { 0x57c00803, 0x57c00803, 0x57c00803 } },
1271         { 0xa378,
1272                 { 0x5fd80682, 0x5fd80682, 0x5fd80682 } },
1273         { 0xa37c,
1274                 { 0x7fe00482, 0x7fe00482, 0x7fe00482 } },
1275         { 0xa380,
1276                 { 0x7f3c7bba, 0x7f3c7bba, 0x7f3c7bba } },
1277         { 0xa384,
1278                 { 0xf3307ff0, 0xf3307ff0, 0xf3307ff0 } },
1279 };
1280
1281 /* Initial mode-specific settings for RF2425 (Written after ar5212_ini) */
1282 /* XXX: No dumps for turbog yet, so turbog is the same with g here with some
1283  * minor tweaking based on dumps from other chips */
1284 static const struct ath5k_ini_mode rf2425_ini_mode_end[] = {
1285         { AR5K_TXCFG,
1286         /*             g        gTurbo */
1287                 { 0x00000015, 0x00000015 } },
1288         { AR5K_USEC_5211,
1289                 { 0x12e013ab, 0x098813cf } },
1290         { AR5K_PHY_TURBO,
1291                 { 0x00000000, 0x00000003 } },
1292         { AR5K_PHY(10),
1293                 { 0x0a020001, 0x0a020001 } },
1294         { AR5K_PHY(13),
1295                 { 0x00000e0e, 0x00000e0e } },
1296         { AR5K_PHY(14),
1297                 { 0x0000000b, 0x0000000b } },
1298         { AR5K_PHY(17),
1299                 { 0x13721422, 0x13721422 } },
1300         { AR5K_PHY(18),
1301                 { 0x00199a65, 0x00199a65 } },
1302         { AR5K_PHY(20),
1303                 { 0x0c98b0da, 0x0c98b0da } },
1304         { AR5K_PHY_SIG,
1305                 { 0x7ec80d2e, 0x7ec80d2e } },
1306         { AR5K_PHY_AGCCOARSE,
1307                 { 0x3139605e, 0x3139605e } },
1308         { AR5K_PHY(27),
1309                 { 0x050cb081, 0x050cb081 } },
1310         { AR5K_PHY_RX_DELAY,
1311                 { 0x00000898, 0x000007d0 } },
1312         { AR5K_PHY_FRAME_CTL_5211,
1313                 { 0xf7b81000, 0xf7b81000 } },
1314         { AR5K_PHY_CCKTXCTL,
1315                 { 0x00000000, 0x00000000 } },
1316         { AR5K_PHY(642),
1317                 { 0xd03e6788, 0xd03e6788 } },
1318         { AR5K_PHY_GAIN_2GHZ,
1319                 { 0x0052c140, 0x0052c140 } },
1320         { 0xa21c,
1321                 { 0x1883800a, 0x1883800a } },
1322         { 0xa324,
1323                 { 0xa7cfa7cf, 0xa7cfa7cf } },
1324         { 0xa328,
1325                 { 0xa7cfa7cf, 0xa7cfa7cf } },
1326         { 0xa32c,
1327                 { 0xa7cfa7cf, 0xa7cfa7cf } },
1328         { 0xa330,
1329                 { 0xa7cfa7cf, 0xa7cfa7cf } },
1330         { 0xa334,
1331                 { 0xa7cfa7cf, 0xa7cfa7cf } },
1332         { AR5K_DCU_FP,
1333                 { 0x000003e0, 0x000003e0 } },
1334         { 0x8060,
1335                 { 0x0000000f, 0x0000000f } },
1336         { 0x809c,
1337                 { 0x00000000, 0x00000000 } },
1338         { 0x80a0,
1339                 { 0x00000000, 0x00000000 } },
1340         { 0x8118,
1341                 { 0x00000000, 0x00000000 } },
1342         { 0x811c,
1343                 { 0x00000000, 0x00000000 } },
1344         { 0x8120,
1345                 { 0x00000000, 0x00000000 } },
1346         { 0x8124,
1347                 { 0x00000000, 0x00000000 } },
1348         { 0x8128,
1349                 { 0x00000000, 0x00000000 } },
1350         { 0x812c,
1351                 { 0x00000000, 0x00000000 } },
1352         { 0x8130,
1353                 { 0x00000000, 0x00000000 } },
1354         { 0x8134,
1355                 { 0x00000000, 0x00000000 } },
1356         { 0x8138,
1357                 { 0x00000000, 0x00000000 } },
1358         { 0x813c,
1359                 { 0x00000000, 0x00000000 } },
1360         { 0x8140,
1361                 { 0x800003f9, 0x800003f9 } },
1362         { 0x8144,
1363                 { 0x00000000, 0x00000000 } },
1364         { AR5K_PHY_AGC,
1365                 { 0x00000000, 0x00000000 } },
1366         { AR5K_PHY(11),
1367                 { 0x0000a000, 0x0000a000 } },
1368         { AR5K_PHY(15),
1369                 { 0x00200400, 0x00200400 } },
1370         { AR5K_PHY(19),
1371                 { 0x1284233c, 0x1284233c } },
1372         { AR5K_PHY_SCR,
1373                 { 0x0000001f, 0x0000001f } },
1374         { AR5K_PHY_SLMT,
1375                 { 0x00000080, 0x00000080 } },
1376         { AR5K_PHY_SCAL,
1377                 { 0x0000000e, 0x0000000e } },
1378         { AR5K_PHY(86),
1379                 { 0x00081fff, 0x00081fff } },
1380         { AR5K_PHY(96),
1381                 { 0x00000000, 0x00000000 } },
1382         { AR5K_PHY(97),
1383                 { 0x02800000, 0x02800000 } },
1384         { AR5K_PHY(104),
1385                 { 0x00000000, 0x00000000 } },
1386         { AR5K_PHY(119),
1387                 { 0xfebadbe8, 0xfebadbe8 } },
1388         { AR5K_PHY(120),
1389                 { 0x00000000, 0x00000000 } },
1390         { AR5K_PHY(121),
1391                 { 0xaaaaaaaa, 0xaaaaaaaa } },
1392         { AR5K_PHY(122),
1393                 { 0x3c466478, 0x3c466478 } },
1394         { AR5K_PHY(123),
1395                 { 0x000000aa, 0x000000aa } },
1396         { AR5K_PHY_SCLOCK,
1397                 { 0x0000000c, 0x0000000c } },
1398         { AR5K_PHY_SDELAY,
1399                 { 0x000000ff, 0x000000ff } },
1400         { AR5K_PHY_SPENDING,
1401                 { 0x00000014, 0x00000014 } },
1402         { 0xa228,
1403                 { 0x000009b5, 0x000009b5 } },
1404         { AR5K_PHY_TXPOWER_RATE3,
1405                 { 0x20202020, 0x20202020 } },
1406         { AR5K_PHY_TXPOWER_RATE4,
1407                 { 0x20202020, 0x20202020 } },
1408         { 0xa23c,
1409                 { 0x93c889af, 0x93c889af } },
1410         { 0xa24c,
1411                 { 0x00000001, 0x00000001 } },
1412         { 0xa250,
1413                 { 0x0000a000, 0x0000a000 } },
1414         { 0xa254,
1415                 { 0x00000000, 0x00000000 } },
1416         { 0xa258,
1417                 { 0x0cc75380, 0x0cc75380 } },
1418         { 0xa25c,
1419                 { 0x0f0f0f01, 0x0f0f0f01 } },
1420         { 0xa260,
1421                 { 0x5f690f01, 0x5f690f01 } },
1422         { 0xa264,
1423                 { 0x00418a11, 0x00418a11 } },
1424         { 0xa268,
1425                 { 0x00000000, 0x00000000 } },
1426         { 0xa26c,
1427                 { 0x0c30c166, 0x0c30c166 } },
1428         { 0xa270,
1429                 { 0x00820820, 0x00820820 } },
1430         { 0xa274,
1431                 { 0x081a3caa, 0x081a3caa } },
1432         { 0xa278,
1433                 { 0x1ce739ce, 0x1ce739ce } },
1434         { 0xa27c,
1435                 { 0x051701ce, 0x051701ce } },
1436         { 0xa300,
1437                 { 0x16010000, 0x16010000 } },
1438         { 0xa304,
1439                 { 0x2c032402, 0x2c032402 } },
1440         { 0xa308,
1441                 { 0x48433e42, 0x48433e42 } },
1442         { 0xa30c,
1443                 { 0x5a0f500b, 0x5a0f500b } },
1444         { 0xa310,
1445                 { 0x6c4b624a, 0x6c4b624a } },
1446         { 0xa314,
1447                 { 0x7e8b748a, 0x7e8b748a } },
1448         { 0xa318,
1449                 { 0x96cf8ccb, 0x96cf8ccb } },
1450         { 0xa31c,
1451                 { 0xa34f9d0f, 0xa34f9d0f } },
1452         { 0xa320,
1453                 { 0xa7cfa58f, 0xa7cfa58f } },
1454         { 0xa348,
1455                 { 0x3fffffff, 0x3fffffff } },
1456         { 0xa34c,
1457                 { 0x3fffffff, 0x3fffffff } },
1458         { 0xa350,
1459                 { 0x3fffffff, 0x3fffffff } },
1460         { 0xa354,
1461                 { 0x0003ffff, 0x0003ffff } },
1462         { 0xa358,
1463                 { 0x79a8aa1f, 0x79a8aa1f } },
1464         { 0xa35c,
1465                 { 0x066c420f, 0x066c420f } },
1466         { 0xa360,
1467                 { 0x0f282207, 0x0f282207 } },
1468         { 0xa364,
1469                 { 0x17601685, 0x17601685 } },
1470         { 0xa368,
1471                 { 0x1f801104, 0x1f801104 } },
1472         { 0xa36c,
1473                 { 0x37a00c03, 0x37a00c03 } },
1474         { 0xa370,
1475                 { 0x3fc40883, 0x3fc40883 } },
1476         { 0xa374,
1477                 { 0x57c00803, 0x57c00803 } },
1478         { 0xa378,
1479                 { 0x5fd80682, 0x5fd80682 } },
1480         { 0xa37c,
1481                 { 0x7fe00482, 0x7fe00482 } },
1482         { 0xa380,
1483                 { 0x7f3c7bba, 0x7f3c7bba } },
1484         { 0xa384,
1485                 { 0xf3307ff0, 0xf3307ff0 } },
1486 };
1487
1488 /*
1489  * Initial BaseBand Gain settings for RF5111/5112 (AR5210 comes with
1490  * RF5110 only so initial BB Gain settings are included in AR5K_AR5210_INI)
1491  */
1492
1493 /* RF5111 Initial BaseBand Gain settings */
1494 static const struct ath5k_ini rf5111_ini_bbgain[] = {
1495         { AR5K_BB_GAIN(0), 0x00000000 },
1496         { AR5K_BB_GAIN(1), 0x00000020 },
1497         { AR5K_BB_GAIN(2), 0x00000010 },
1498         { AR5K_BB_GAIN(3), 0x00000030 },
1499         { AR5K_BB_GAIN(4), 0x00000008 },
1500         { AR5K_BB_GAIN(5), 0x00000028 },
1501         { AR5K_BB_GAIN(6), 0x00000004 },
1502         { AR5K_BB_GAIN(7), 0x00000024 },
1503         { AR5K_BB_GAIN(8), 0x00000014 },
1504         { AR5K_BB_GAIN(9), 0x00000034 },
1505         { AR5K_BB_GAIN(10), 0x0000000c },
1506         { AR5K_BB_GAIN(11), 0x0000002c },
1507         { AR5K_BB_GAIN(12), 0x00000002 },
1508         { AR5K_BB_GAIN(13), 0x00000022 },
1509         { AR5K_BB_GAIN(14), 0x00000012 },
1510         { AR5K_BB_GAIN(15), 0x00000032 },
1511         { AR5K_BB_GAIN(16), 0x0000000a },
1512         { AR5K_BB_GAIN(17), 0x0000002a },
1513         { AR5K_BB_GAIN(18), 0x00000006 },
1514         { AR5K_BB_GAIN(19), 0x00000026 },
1515         { AR5K_BB_GAIN(20), 0x00000016 },
1516         { AR5K_BB_GAIN(21), 0x00000036 },
1517         { AR5K_BB_GAIN(22), 0x0000000e },
1518         { AR5K_BB_GAIN(23), 0x0000002e },
1519         { AR5K_BB_GAIN(24), 0x00000001 },
1520         { AR5K_BB_GAIN(25), 0x00000021 },
1521         { AR5K_BB_GAIN(26), 0x00000011 },
1522         { AR5K_BB_GAIN(27), 0x00000031 },
1523         { AR5K_BB_GAIN(28), 0x00000009 },
1524         { AR5K_BB_GAIN(29), 0x00000029 },
1525         { AR5K_BB_GAIN(30), 0x00000005 },
1526         { AR5K_BB_GAIN(31), 0x00000025 },
1527         { AR5K_BB_GAIN(32), 0x00000015 },
1528         { AR5K_BB_GAIN(33), 0x00000035 },
1529         { AR5K_BB_GAIN(34), 0x0000000d },
1530         { AR5K_BB_GAIN(35), 0x0000002d },
1531         { AR5K_BB_GAIN(36), 0x00000003 },
1532         { AR5K_BB_GAIN(37), 0x00000023 },
1533         { AR5K_BB_GAIN(38), 0x00000013 },
1534         { AR5K_BB_GAIN(39), 0x00000033 },
1535         { AR5K_BB_GAIN(40), 0x0000000b },
1536         { AR5K_BB_GAIN(41), 0x0000002b },
1537         { AR5K_BB_GAIN(42), 0x0000002b },
1538         { AR5K_BB_GAIN(43), 0x0000002b },
1539         { AR5K_BB_GAIN(44), 0x0000002b },
1540         { AR5K_BB_GAIN(45), 0x0000002b },
1541         { AR5K_BB_GAIN(46), 0x0000002b },
1542         { AR5K_BB_GAIN(47), 0x0000002b },
1543         { AR5K_BB_GAIN(48), 0x0000002b },
1544         { AR5K_BB_GAIN(49), 0x0000002b },
1545         { AR5K_BB_GAIN(50), 0x0000002b },
1546         { AR5K_BB_GAIN(51), 0x0000002b },
1547         { AR5K_BB_GAIN(52), 0x0000002b },
1548         { AR5K_BB_GAIN(53), 0x0000002b },
1549         { AR5K_BB_GAIN(54), 0x0000002b },
1550         { AR5K_BB_GAIN(55), 0x0000002b },
1551         { AR5K_BB_GAIN(56), 0x0000002b },
1552         { AR5K_BB_GAIN(57), 0x0000002b },
1553         { AR5K_BB_GAIN(58), 0x0000002b },
1554         { AR5K_BB_GAIN(59), 0x0000002b },
1555         { AR5K_BB_GAIN(60), 0x0000002b },
1556         { AR5K_BB_GAIN(61), 0x0000002b },
1557         { AR5K_BB_GAIN(62), 0x00000002 },
1558         { AR5K_BB_GAIN(63), 0x00000016 },
1559 };
1560
1561 /* RF5112 Initial BaseBand Gain settings (Same for RF5413/5414) */
1562 static const struct ath5k_ini rf5112_ini_bbgain[] = {
1563         { AR5K_BB_GAIN(0), 0x00000000 },
1564         { AR5K_BB_GAIN(1), 0x00000001 },
1565         { AR5K_BB_GAIN(2), 0x00000002 },
1566         { AR5K_BB_GAIN(3), 0x00000003 },
1567         { AR5K_BB_GAIN(4), 0x00000004 },
1568         { AR5K_BB_GAIN(5), 0x00000005 },
1569         { AR5K_BB_GAIN(6), 0x00000008 },
1570         { AR5K_BB_GAIN(7), 0x00000009 },
1571         { AR5K_BB_GAIN(8), 0x0000000a },
1572         { AR5K_BB_GAIN(9), 0x0000000b },
1573         { AR5K_BB_GAIN(10), 0x0000000c },
1574         { AR5K_BB_GAIN(11), 0x0000000d },
1575         { AR5K_BB_GAIN(12), 0x00000010 },
1576         { AR5K_BB_GAIN(13), 0x00000011 },
1577         { AR5K_BB_GAIN(14), 0x00000012 },
1578         { AR5K_BB_GAIN(15), 0x00000013 },
1579         { AR5K_BB_GAIN(16), 0x00000014 },
1580         { AR5K_BB_GAIN(17), 0x00000015 },
1581         { AR5K_BB_GAIN(18), 0x00000018 },
1582         { AR5K_BB_GAIN(19), 0x00000019 },
1583         { AR5K_BB_GAIN(20), 0x0000001a },
1584         { AR5K_BB_GAIN(21), 0x0000001b },
1585         { AR5K_BB_GAIN(22), 0x0000001c },
1586         { AR5K_BB_GAIN(23), 0x0000001d },
1587         { AR5K_BB_GAIN(24), 0x00000020 },
1588         { AR5K_BB_GAIN(25), 0x00000021 },
1589         { AR5K_BB_GAIN(26), 0x00000022 },
1590         { AR5K_BB_GAIN(27), 0x00000023 },
1591         { AR5K_BB_GAIN(28), 0x00000024 },
1592         { AR5K_BB_GAIN(29), 0x00000025 },
1593         { AR5K_BB_GAIN(30), 0x00000028 },
1594         { AR5K_BB_GAIN(31), 0x00000029 },
1595         { AR5K_BB_GAIN(32), 0x0000002a },
1596         { AR5K_BB_GAIN(33), 0x0000002b },
1597         { AR5K_BB_GAIN(34), 0x0000002c },
1598         { AR5K_BB_GAIN(35), 0x0000002d },
1599         { AR5K_BB_GAIN(36), 0x00000030 },
1600         { AR5K_BB_GAIN(37), 0x00000031 },
1601         { AR5K_BB_GAIN(38), 0x00000032 },
1602         { AR5K_BB_GAIN(39), 0x00000033 },
1603         { AR5K_BB_GAIN(40), 0x00000034 },
1604         { AR5K_BB_GAIN(41), 0x00000035 },
1605         { AR5K_BB_GAIN(42), 0x00000035 },
1606         { AR5K_BB_GAIN(43), 0x00000035 },
1607         { AR5K_BB_GAIN(44), 0x00000035 },
1608         { AR5K_BB_GAIN(45), 0x00000035 },
1609         { AR5K_BB_GAIN(46), 0x00000035 },
1610         { AR5K_BB_GAIN(47), 0x00000035 },
1611         { AR5K_BB_GAIN(48), 0x00000035 },
1612         { AR5K_BB_GAIN(49), 0x00000035 },
1613         { AR5K_BB_GAIN(50), 0x00000035 },
1614         { AR5K_BB_GAIN(51), 0x00000035 },
1615         { AR5K_BB_GAIN(52), 0x00000035 },
1616         { AR5K_BB_GAIN(53), 0x00000035 },
1617         { AR5K_BB_GAIN(54), 0x00000035 },
1618         { AR5K_BB_GAIN(55), 0x00000035 },
1619         { AR5K_BB_GAIN(56), 0x00000035 },
1620         { AR5K_BB_GAIN(57), 0x00000035 },
1621         { AR5K_BB_GAIN(58), 0x00000035 },
1622         { AR5K_BB_GAIN(59), 0x00000035 },
1623         { AR5K_BB_GAIN(60), 0x00000035 },
1624         { AR5K_BB_GAIN(61), 0x00000035 },
1625         { AR5K_BB_GAIN(62), 0x00000010 },
1626         { AR5K_BB_GAIN(63), 0x0000001a },
1627 };
1628
1629
1630 /*
1631  * Write initial register dump
1632  */
1633 static void ath5k_hw_ini_registers(struct ath5k_hw *ah, unsigned int size,
1634                 const struct ath5k_ini *ini_regs, bool change_channel)
1635 {
1636         unsigned int i;
1637
1638         /* Write initial registers */
1639         for (i = 0; i < size; i++) {
1640                 /* On channel change there is
1641                  * no need to mess with PCU */
1642                 if (change_channel &&
1643                                 ini_regs[i].ini_register >= AR5K_PCU_MIN &&
1644                                 ini_regs[i].ini_register <= AR5K_PCU_MAX)
1645                         continue;
1646
1647                 switch (ini_regs[i].ini_mode) {
1648                 case AR5K_INI_READ:
1649                         /* Cleared on read */
1650                         ath5k_hw_reg_read(ah, ini_regs[i].ini_register);
1651                         break;
1652                 case AR5K_INI_WRITE:
1653                 default:
1654                         AR5K_REG_WAIT(i);
1655                         ath5k_hw_reg_write(ah, ini_regs[i].ini_value,
1656                                         ini_regs[i].ini_register);
1657                 }
1658         }
1659 }
1660
1661 static void ath5k_hw_ini_mode_registers(struct ath5k_hw *ah,
1662                 unsigned int size, const struct ath5k_ini_mode *ini_mode,
1663                 u8 mode)
1664 {
1665         unsigned int i;
1666
1667         for (i = 0; i < size; i++) {
1668                 AR5K_REG_WAIT(i);
1669                 ath5k_hw_reg_write(ah, ini_mode[i].mode_value[mode],
1670                         (u32)ini_mode[i].mode_register);
1671         }
1672
1673 }
1674
1675 int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool change_channel)
1676 {
1677         /*
1678          * Write initial register settings
1679          */
1680
1681         /* For AR5212 and combatible */
1682         if (ah->ah_version == AR5K_AR5212){
1683
1684                 /* First set of mode-specific settings */
1685                 ath5k_hw_ini_mode_registers(ah,
1686                         ARRAY_SIZE(ar5212_ini_mode_start),
1687                         ar5212_ini_mode_start, mode);
1688
1689                 /*
1690                  * Write initial settings common for all modes
1691                  */
1692                 ath5k_hw_ini_registers(ah, ARRAY_SIZE(ar5212_ini),
1693                                         ar5212_ini, change_channel);
1694
1695                 /* Second set of mode-specific settings */
1696                 if (ah->ah_radio == AR5K_RF5111){
1697
1698                         ath5k_hw_ini_mode_registers(ah,
1699                                         ARRAY_SIZE(ar5212_rf5111_ini_mode_end),
1700                                         ar5212_rf5111_ini_mode_end, mode);
1701
1702                         /* Baseband gain table */
1703                         ath5k_hw_ini_registers(ah,
1704                                         ARRAY_SIZE(rf5111_ini_bbgain),
1705                                         rf5111_ini_bbgain, change_channel);
1706
1707                 } else if (ah->ah_radio == AR5K_RF5112){
1708
1709                         ath5k_hw_ini_mode_registers(ah,
1710                                         ARRAY_SIZE(ar5212_rf5112_ini_mode_end),
1711                                         ar5212_rf5112_ini_mode_end, mode);
1712
1713                         ath5k_hw_ini_registers(ah,
1714                                         ARRAY_SIZE(rf5112_ini_bbgain),
1715                                         rf5112_ini_bbgain, change_channel);
1716
1717                 } else if (ah->ah_radio == AR5K_RF5413){
1718
1719                         ath5k_hw_ini_mode_registers(ah,
1720                                         ARRAY_SIZE(rf5413_ini_mode_end),
1721                                         rf5413_ini_mode_end, mode);
1722
1723                         ath5k_hw_ini_registers(ah,
1724                                         ARRAY_SIZE(rf5112_ini_bbgain),
1725                                         rf5112_ini_bbgain, change_channel);
1726
1727                 } else if (ah->ah_radio == AR5K_RF2413) {
1728
1729                         if (mode < 2) {
1730                                 ATH5K_ERR(ah->ah_sc,
1731                                         "unsupported channel mode: %d\n", mode);
1732                                 return -EINVAL;
1733                         }
1734                         mode = mode - 2;
1735
1736                         /* Override a setting from ar5212_ini */
1737                         ath5k_hw_reg_write(ah, 0x018830c6, AR5K_PHY(648));
1738
1739                         ath5k_hw_ini_mode_registers(ah,
1740                                         ARRAY_SIZE(rf2413_ini_mode_end),
1741                                         rf2413_ini_mode_end, mode);
1742
1743                         /* Baseband gain table */
1744                         ath5k_hw_ini_registers(ah,
1745                                         ARRAY_SIZE(rf5112_ini_bbgain),
1746                                         rf5112_ini_bbgain, change_channel);
1747
1748                 } else if (ah->ah_radio == AR5K_RF2425) {
1749
1750                         if (mode < 2) {
1751                                 ATH5K_ERR(ah->ah_sc,
1752                                         "unsupported channel mode: %d\n", mode);
1753                                 return -EINVAL;
1754                         }
1755
1756                         /* Map b to g */
1757                         if (mode == 2)
1758                                 mode = 0;
1759                         else
1760                                 mode = mode - 3;
1761
1762                         /* Override a setting from ar5212_ini */
1763                         ath5k_hw_reg_write(ah, 0x018830c6, AR5K_PHY(648));
1764
1765                         ath5k_hw_ini_mode_registers(ah,
1766                                         ARRAY_SIZE(rf2425_ini_mode_end),
1767                                         rf2425_ini_mode_end, mode);
1768
1769                         /* Baseband gain table */
1770                         ath5k_hw_ini_registers(ah,
1771                                         ARRAY_SIZE(rf5112_ini_bbgain),
1772                                         rf5112_ini_bbgain, change_channel);
1773
1774                 }
1775
1776         /* For AR5211 */
1777         } else if (ah->ah_version == AR5K_AR5211) {
1778
1779                 /* AR5K_MODE_11B */
1780                 if (mode > 2) {
1781                         ATH5K_ERR(ah->ah_sc,
1782                                 "unsupported channel mode: %d\n", mode);
1783                         return -EINVAL;
1784                 }
1785
1786                 /* Mode-specific settings */
1787                 ath5k_hw_ini_mode_registers(ah, ARRAY_SIZE(ar5211_ini_mode),
1788                                 ar5211_ini_mode, mode);
1789
1790                 /*
1791                  * Write initial settings common for all modes
1792                  */
1793                 ath5k_hw_ini_registers(ah, ARRAY_SIZE(ar5211_ini),
1794                                 ar5211_ini, change_channel);
1795
1796                 /* AR5211 only comes with 5111 */
1797
1798                 /* Baseband gain table */
1799                 ath5k_hw_ini_registers(ah, ARRAY_SIZE(rf5111_ini_bbgain),
1800                                 rf5111_ini_bbgain, change_channel);
1801         /* For AR5210 (for mode settings check out ath5k_hw_reset_tx_queue) */
1802         } else if (ah->ah_version == AR5K_AR5210) {
1803                 ath5k_hw_ini_registers(ah, ARRAY_SIZE(ar5210_ini),
1804                                 ar5210_ini, change_channel);
1805         }
1806
1807         return 0;
1808 }