V4L/DVB (9776): cx18: Change to per CX23418 device work queues for deferrable work...
[linux-2.6] / drivers / media / video / cx18 / cx18-mailbox.c
1 /*
2  *  cx18 mailbox functions
3  *
4  *  Copyright (C) 2007  Hans Verkuil <hverkuil@xs4all.nl>
5  *  Copyright (C) 2008  Andy Walls <awalls@radix.net>
6  *
7  *  This program is free software; you can redistribute it and/or modify
8  *  it under the terms of the GNU General Public License as published by
9  *  the Free Software Foundation; either version 2 of the License, or
10  *  (at your option) any later version.
11  *
12  *  This program is distributed in the hope that it will be useful,
13  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
14  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  *  GNU General Public License for more details.
16  *
17  *  You should have received a copy of the GNU General Public License
18  *  along with this program; if not, write to the Free Software
19  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
20  *  02111-1307  USA
21  */
22
23 #include <stdarg.h>
24
25 #include "cx18-driver.h"
26 #include "cx18-io.h"
27 #include "cx18-scb.h"
28 #include "cx18-irq.h"
29 #include "cx18-mailbox.h"
30 #include "cx18-queue.h"
31 #include "cx18-streams.h"
32
33 static const char *rpu_str[] = { "APU", "CPU", "EPU", "HPU" };
34
35 #define API_FAST (1 << 2) /* Short timeout */
36 #define API_SLOW (1 << 3) /* Additional 300ms timeout */
37
38 struct cx18_api_info {
39         u32 cmd;
40         u8 flags;               /* Flags, see above */
41         u8 rpu;                 /* Processing unit */
42         const char *name;       /* The name of the command */
43 };
44
45 #define API_ENTRY(rpu, x, f) { (x), (f), (rpu), #x }
46
47 static const struct cx18_api_info api_info[] = {
48         /* MPEG encoder API */
49         API_ENTRY(CPU, CX18_CPU_SET_CHANNEL_TYPE,               0),
50         API_ENTRY(CPU, CX18_EPU_DEBUG,                          0),
51         API_ENTRY(CPU, CX18_CREATE_TASK,                        0),
52         API_ENTRY(CPU, CX18_DESTROY_TASK,                       0),
53         API_ENTRY(CPU, CX18_CPU_CAPTURE_START,                  API_SLOW),
54         API_ENTRY(CPU, CX18_CPU_CAPTURE_STOP,                   API_SLOW),
55         API_ENTRY(CPU, CX18_CPU_CAPTURE_PAUSE,                  0),
56         API_ENTRY(CPU, CX18_CPU_CAPTURE_RESUME,                 0),
57         API_ENTRY(CPU, CX18_CPU_SET_CHANNEL_TYPE,               0),
58         API_ENTRY(CPU, CX18_CPU_SET_STREAM_OUTPUT_TYPE,         0),
59         API_ENTRY(CPU, CX18_CPU_SET_VIDEO_IN,                   0),
60         API_ENTRY(CPU, CX18_CPU_SET_VIDEO_RATE,                 0),
61         API_ENTRY(CPU, CX18_CPU_SET_VIDEO_RESOLUTION,           0),
62         API_ENTRY(CPU, CX18_CPU_SET_FILTER_PARAM,               0),
63         API_ENTRY(CPU, CX18_CPU_SET_SPATIAL_FILTER_TYPE,        0),
64         API_ENTRY(CPU, CX18_CPU_SET_MEDIAN_CORING,              0),
65         API_ENTRY(CPU, CX18_CPU_SET_INDEXTABLE,                 0),
66         API_ENTRY(CPU, CX18_CPU_SET_AUDIO_PARAMETERS,           0),
67         API_ENTRY(CPU, CX18_CPU_SET_VIDEO_MUTE,                 0),
68         API_ENTRY(CPU, CX18_CPU_SET_AUDIO_MUTE,                 0),
69         API_ENTRY(CPU, CX18_CPU_SET_MISC_PARAMETERS,            0),
70         API_ENTRY(CPU, CX18_CPU_SET_RAW_VBI_PARAM,              API_SLOW),
71         API_ENTRY(CPU, CX18_CPU_SET_CAPTURE_LINE_NO,            0),
72         API_ENTRY(CPU, CX18_CPU_SET_COPYRIGHT,                  0),
73         API_ENTRY(CPU, CX18_CPU_SET_AUDIO_PID,                  0),
74         API_ENTRY(CPU, CX18_CPU_SET_VIDEO_PID,                  0),
75         API_ENTRY(CPU, CX18_CPU_SET_VER_CROP_LINE,              0),
76         API_ENTRY(CPU, CX18_CPU_SET_GOP_STRUCTURE,              0),
77         API_ENTRY(CPU, CX18_CPU_SET_SCENE_CHANGE_DETECTION,     0),
78         API_ENTRY(CPU, CX18_CPU_SET_ASPECT_RATIO,               0),
79         API_ENTRY(CPU, CX18_CPU_SET_SKIP_INPUT_FRAME,           0),
80         API_ENTRY(CPU, CX18_CPU_SET_SLICED_VBI_PARAM,           0),
81         API_ENTRY(CPU, CX18_CPU_SET_USERDATA_PLACE_HOLDER,      0),
82         API_ENTRY(CPU, CX18_CPU_GET_ENC_PTS,                    0),
83         API_ENTRY(CPU, CX18_CPU_DE_SET_MDL_ACK,                 0),
84         API_ENTRY(CPU, CX18_CPU_DE_SET_MDL,                     API_FAST),
85         API_ENTRY(CPU, CX18_APU_RESETAI,                        API_FAST),
86         API_ENTRY(CPU, CX18_CPU_DE_RELEASE_MDL,                 API_SLOW),
87         API_ENTRY(0, 0,                                         0),
88 };
89
90 static const struct cx18_api_info *find_api_info(u32 cmd)
91 {
92         int i;
93
94         for (i = 0; api_info[i].cmd; i++)
95                 if (api_info[i].cmd == cmd)
96                         return &api_info[i];
97         return NULL;
98 }
99
100 static void dump_mb(struct cx18 *cx, struct cx18_mailbox *mb, char *name)
101 {
102         char argstr[MAX_MB_ARGUMENTS*11+1];
103         char *p;
104         int i;
105
106         if (!(cx18_debug & CX18_DBGFLG_API))
107                 return;
108
109         for (i = 0, p = argstr; i < MAX_MB_ARGUMENTS; i++, p += 11) {
110                 /* kernel snprintf() appends '\0' always */
111                 snprintf(p, 12, " %#010x", mb->args[i]);
112         }
113         CX18_DEBUG_API("%s: req %#010x ack %#010x cmd %#010x err %#010x args%s"
114                 "\n", name, mb->request, mb->ack, mb->cmd, mb->error, argstr);
115 }
116
117
118 /*
119  * Functions that run in a work_queue work handling context
120  */
121
122 static void epu_dma_done(struct cx18 *cx, struct cx18_epu_work_order *order)
123 {
124         u32 handle, mdl_ack_count, id;
125         struct cx18_mailbox *mb;
126         struct cx18_mdl_ack *mdl_ack;
127         struct cx18_stream *s;
128         struct cx18_buffer *buf;
129         int i;
130
131         mb = &order->mb;
132         handle = mb->args[0];
133         s = cx18_handle_to_stream(cx, handle);
134
135         if (s == NULL) {
136                 CX18_WARN("Got DMA done notification for unknown/inactive"
137                           " handle %d, %s mailbox seq no %d\n", handle,
138                           (order->flags & CX18_F_EWO_MB_STALE_UPON_RECEIPT) ?
139                           "stale" : "good", mb->request);
140                 return;
141         }
142
143         mdl_ack_count = mb->args[2];
144         mdl_ack = order->mdl_ack;
145         for (i = 0; i < mdl_ack_count; i++, mdl_ack++) {
146                 id = mdl_ack->id;
147                 /*
148                  * Simple integrity check for processing a stale (and possibly
149                  * inconsistent mailbox): make sure the buffer id is in the
150                  * valid range for the stream.
151                  *
152                  * We go through the trouble of dealing with stale mailboxes
153                  * because most of the time, the mailbox data is still valid and
154                  * unchanged (and in practice the firmware ping-pongs the
155                  * two mdl_ack buffers so mdl_acks are not stale).
156                  *
157                  * There are occasions when we get a half changed mailbox,
158                  * which this check catches for a handle & id mismatch.  If the
159                  * handle and id do correspond, the worst case is that we
160                  * completely lost the old buffer, but pick up the new buffer
161                  * early (but the new mdl_ack is guaranteed to be good in this
162                  * case as the firmware wouldn't point us to a new mdl_ack until
163                  * it's filled in).
164                  *
165                  * cx18_queue_get buf() will detect the lost buffers
166                  * and put them back in rotation eventually.
167                  */
168                 if ((order->flags & CX18_F_EWO_MB_STALE_UPON_RECEIPT) &&
169                     !(id >= s->mdl_offset &&
170                       id < (s->mdl_offset + s->buffers))) {
171                         CX18_WARN("Fell behind! Ignoring stale mailbox with "
172                                   " inconsistent data. Lost buffer for mailbox "
173                                   "seq no %d\n", mb->request);
174                         break;
175                 }
176                 buf = cx18_queue_get_buf(s, id, mdl_ack->data_used);
177                 CX18_DEBUG_HI_DMA("DMA DONE for %s (buffer %d)\n", s->name, id);
178                 if (buf == NULL) {
179                         CX18_WARN("Could not find buf %d for stream %s\n",
180                                   id, s->name);
181                         continue;
182                 }
183
184                 cx18_buf_sync_for_cpu(s, buf);
185                 if (s->type == CX18_ENC_STREAM_TYPE_TS && s->dvb.enabled) {
186                         CX18_DEBUG_HI_DMA("TS recv bytesused = %d\n",
187                                           buf->bytesused);
188
189                         dvb_dmx_swfilter(&s->dvb.demux, buf->buf,
190                                          buf->bytesused);
191
192                         cx18_buf_sync_for_device(s, buf);
193                         cx18_enqueue(s, buf, &s->q_free);
194
195                         if (s->handle != CX18_INVALID_TASK_HANDLE &&
196                             test_bit(CX18_F_S_STREAMING, &s->s_flags))
197                                 cx18_vapi(cx,
198                                        CX18_CPU_DE_SET_MDL, 5, s->handle,
199                                        (void __iomem *)
200                                        &cx->scb->cpu_mdl[buf->id] - cx->enc_mem,
201                                        1, buf->id, s->buf_size);
202                 } else
203                         set_bit(CX18_F_B_NEED_BUF_SWAP, &buf->b_flags);
204         }
205         wake_up(&cx->dma_waitq);
206         if (s->id != -1)
207                 wake_up(&s->waitq);
208 }
209
210 static void epu_debug(struct cx18 *cx, struct cx18_epu_work_order *order)
211 {
212         char *p;
213         char *str = order->str;
214
215         CX18_DEBUG_INFO("%x %s\n", order->mb.args[0], str);
216         p = strchr(str, '.');
217         if (!test_bit(CX18_F_I_LOADED_FW, &cx->i_flags) && p && p > str)
218                 CX18_INFO("FW version: %s\n", p - 1);
219 }
220
221 static void epu_cmd(struct cx18 *cx, struct cx18_epu_work_order *order)
222 {
223         switch (order->rpu) {
224         case CPU:
225         {
226                 switch (order->mb.cmd) {
227                 case CX18_EPU_DMA_DONE:
228                         epu_dma_done(cx, order);
229                         break;
230                 case CX18_EPU_DEBUG:
231                         epu_debug(cx, order);
232                         break;
233                 default:
234                         CX18_WARN("Unknown CPU to EPU mailbox command %#0x\n",
235                                   order->mb.cmd);
236                         break;
237                 }
238                 break;
239         }
240         case APU:
241                 CX18_WARN("Unknown APU to EPU mailbox command %#0x\n",
242                           order->mb.cmd);
243                 break;
244         default:
245                 break;
246         }
247 }
248
249 static
250 void free_epu_work_order(struct cx18 *cx, struct cx18_epu_work_order *order)
251 {
252         atomic_set(&order->pending, 0);
253 }
254
255 void cx18_epu_work_handler(struct work_struct *work)
256 {
257         struct cx18_epu_work_order *order =
258                         container_of(work, struct cx18_epu_work_order, work);
259         struct cx18 *cx = order->cx;
260         epu_cmd(cx, order);
261         free_epu_work_order(cx, order);
262 }
263
264
265 /*
266  * Functions that run in an interrupt handling context
267  */
268
269 static void mb_ack_irq(struct cx18 *cx, struct cx18_epu_work_order *order)
270 {
271         struct cx18_mailbox __iomem *ack_mb;
272         u32 ack_irq, req;
273
274         switch (order->rpu) {
275         case APU:
276                 ack_irq = IRQ_EPU_TO_APU_ACK;
277                 ack_mb = &cx->scb->apu2epu_mb;
278                 break;
279         case CPU:
280                 ack_irq = IRQ_EPU_TO_CPU_ACK;
281                 ack_mb = &cx->scb->cpu2epu_mb;
282                 break;
283         default:
284                 CX18_WARN("Unhandled RPU (%d) for command %x ack\n",
285                           order->rpu, order->mb.cmd);
286                 return;
287         }
288
289         req = order->mb.request;
290         /* Don't ack if the RPU has gotten impatient and timed us out */
291         if (req != cx18_readl(cx, &ack_mb->request) ||
292             req == cx18_readl(cx, &ack_mb->ack)) {
293                 CX18_DEBUG_WARN("Possibly falling behind: %s self-ack'ed our "
294                                 "incoming %s to EPU mailbox (sequence no. %u) "
295                                 "while processing\n",
296                                 rpu_str[order->rpu], rpu_str[order->rpu], req);
297                 order->flags |= CX18_F_EWO_MB_STALE_WHILE_PROC;
298                 return;
299         }
300         cx18_writel(cx, req, &ack_mb->ack);
301         cx18_write_reg_expect(cx, ack_irq, SW2_INT_SET, ack_irq, ack_irq);
302         return;
303 }
304
305 static int epu_dma_done_irq(struct cx18 *cx, struct cx18_epu_work_order *order)
306 {
307         u32 handle, mdl_ack_offset, mdl_ack_count;
308         struct cx18_mailbox *mb;
309
310         mb = &order->mb;
311         handle = mb->args[0];
312         mdl_ack_offset = mb->args[1];
313         mdl_ack_count = mb->args[2];
314
315         if (handle == CX18_INVALID_TASK_HANDLE ||
316             mdl_ack_count == 0 || mdl_ack_count > CX18_MAX_MDL_ACKS) {
317                 if ((order->flags & CX18_F_EWO_MB_STALE) == 0)
318                         mb_ack_irq(cx, order);
319                 return -1;
320         }
321
322         cx18_memcpy_fromio(cx, order->mdl_ack, cx->enc_mem + mdl_ack_offset,
323                            sizeof(struct cx18_mdl_ack) * mdl_ack_count);
324
325         if ((order->flags & CX18_F_EWO_MB_STALE) == 0)
326                 mb_ack_irq(cx, order);
327         return 1;
328 }
329
330 static
331 int epu_debug_irq(struct cx18 *cx, struct cx18_epu_work_order *order)
332 {
333         u32 str_offset;
334         char *str = order->str;
335
336         str[0] = '\0';
337         str_offset = order->mb.args[1];
338         if (str_offset) {
339                 cx18_setup_page(cx, str_offset);
340                 cx18_memcpy_fromio(cx, str, cx->enc_mem + str_offset, 252);
341                 str[252] = '\0';
342                 cx18_setup_page(cx, SCB_OFFSET);
343         }
344
345         if ((order->flags & CX18_F_EWO_MB_STALE) == 0)
346                 mb_ack_irq(cx, order);
347
348         return str_offset ? 1 : 0;
349 }
350
351 static inline
352 int epu_cmd_irq(struct cx18 *cx, struct cx18_epu_work_order *order)
353 {
354         int ret = -1;
355
356         switch (order->rpu) {
357         case CPU:
358         {
359                 switch (order->mb.cmd) {
360                 case CX18_EPU_DMA_DONE:
361                         ret = epu_dma_done_irq(cx, order);
362                         break;
363                 case CX18_EPU_DEBUG:
364                         ret = epu_debug_irq(cx, order);
365                         break;
366                 default:
367                         CX18_WARN("Unknown CPU to EPU mailbox command %#0x\n",
368                                   order->mb.cmd);
369                         break;
370                 }
371                 break;
372         }
373         case APU:
374                 CX18_WARN("Unknown APU to EPU mailbox command %#0x\n",
375                           order->mb.cmd);
376                 break;
377         default:
378                 break;
379         }
380         return ret;
381 }
382
383 static inline
384 struct cx18_epu_work_order *alloc_epu_work_order_irq(struct cx18 *cx)
385 {
386         int i;
387         struct cx18_epu_work_order *order = NULL;
388
389         for (i = 0; i < CX18_MAX_EPU_WORK_ORDERS; i++) {
390                 /*
391                  * We only need "pending" atomic to inspect its contents,
392                  * and need not do a check and set because:
393                  * 1. Any work handler thread only clears "pending" and only
394                  * on one, particular work order at a time, per handler thread.
395                  * 2. "pending" is only set here, and we're serialized because
396                  * we're called in an IRQ handler context.
397                  */
398                 if (atomic_read(&cx->epu_work_order[i].pending) == 0) {
399                         order = &cx->epu_work_order[i];
400                         atomic_set(&order->pending, 1);
401                         break;
402                 }
403         }
404         return order;
405 }
406
407 void cx18_api_epu_cmd_irq(struct cx18 *cx, int rpu)
408 {
409         struct cx18_mailbox __iomem *mb;
410         struct cx18_mailbox *order_mb;
411         struct cx18_epu_work_order *order;
412         int submit;
413
414         switch (rpu) {
415         case CPU:
416                 mb = &cx->scb->cpu2epu_mb;
417                 break;
418         case APU:
419                 mb = &cx->scb->apu2epu_mb;
420                 break;
421         default:
422                 return;
423         }
424
425         order = alloc_epu_work_order_irq(cx);
426         if (order == NULL) {
427                 CX18_WARN("Unable to find blank work order form to schedule "
428                           "incoming mailbox command processing\n");
429                 return;
430         }
431
432         order->flags = 0;
433         order->rpu = rpu;
434         order_mb = &order->mb;
435
436         /* mb->cmd and mb->args[0] through mb->args[2] */
437         cx18_memcpy_fromio(cx, &order_mb->cmd, &mb->cmd, 4 * sizeof(u32));
438         /* mb->request and mb->ack.  N.B. we want to read mb->ack last */
439         cx18_memcpy_fromio(cx, &order_mb->request, &mb->request,
440                            2 * sizeof(u32));
441
442         if (order_mb->request == order_mb->ack) {
443                 CX18_DEBUG_WARN("Possibly falling behind: %s self-ack'ed our "
444                                 "incoming %s to EPU mailbox (sequence no. %u)"
445                                 "\n",
446                                 rpu_str[rpu], rpu_str[rpu], order_mb->request);
447                 dump_mb(cx, order_mb, "incoming");
448                 order->flags = CX18_F_EWO_MB_STALE_UPON_RECEIPT;
449         }
450
451         /*
452          * Individual EPU command processing is responsible for ack-ing
453          * a non-stale mailbox as soon as possible
454          */
455         submit = epu_cmd_irq(cx, order);
456         if (submit > 0) {
457                 queue_work(cx->work_queue, &order->work);
458         }
459 }
460
461
462 /*
463  * Functions called from a non-interrupt, non work_queue context
464  */
465
466 static int cx18_api_call(struct cx18 *cx, u32 cmd, int args, u32 data[])
467 {
468         const struct cx18_api_info *info = find_api_info(cmd);
469         u32 state, irq, req, ack, err;
470         struct cx18_mailbox __iomem *mb;
471         u32 __iomem *xpu_state;
472         wait_queue_head_t *waitq;
473         struct mutex *mb_lock;
474         long int timeout, ret;
475         int i;
476
477         if (info == NULL) {
478                 CX18_WARN("unknown cmd %x\n", cmd);
479                 return -EINVAL;
480         }
481
482         if (cmd == CX18_CPU_DE_SET_MDL)
483                 CX18_DEBUG_HI_API("%s\n", info->name);
484         else
485                 CX18_DEBUG_API("%s\n", info->name);
486
487         switch (info->rpu) {
488         case APU:
489                 waitq = &cx->mb_apu_waitq;
490                 mb_lock = &cx->epu2apu_mb_lock;
491                 irq = IRQ_EPU_TO_APU;
492                 mb = &cx->scb->epu2apu_mb;
493                 xpu_state = &cx->scb->apu_state;
494                 break;
495         case CPU:
496                 waitq = &cx->mb_cpu_waitq;
497                 mb_lock = &cx->epu2cpu_mb_lock;
498                 irq = IRQ_EPU_TO_CPU;
499                 mb = &cx->scb->epu2cpu_mb;
500                 xpu_state = &cx->scb->cpu_state;
501                 break;
502         default:
503                 CX18_WARN("Unknown RPU (%d) for API call\n", info->rpu);
504                 return -EINVAL;
505         }
506
507         mutex_lock(mb_lock);
508         /*
509          * Wait for an in-use mailbox to complete
510          *
511          * If the XPU is responding with Ack's, the mailbox shouldn't be in
512          * a busy state, since we serialize access to it on our end.
513          *
514          * If the wait for ack after sending a previous command was interrupted
515          * by a signal, we may get here and find a busy mailbox.  After waiting,
516          * mark it "not busy" from our end, if the XPU hasn't ack'ed it still.
517          */
518         state = cx18_readl(cx, xpu_state);
519         req = cx18_readl(cx, &mb->request);
520         timeout = msecs_to_jiffies(10);
521         ret = wait_event_timeout(*waitq,
522                                  (ack = cx18_readl(cx, &mb->ack)) == req,
523                                  timeout);
524         if (req != ack) {
525                 /* waited long enough, make the mbox "not busy" from our end */
526                 cx18_writel(cx, req, &mb->ack);
527                 CX18_ERR("mbox was found stuck busy when setting up for %s; "
528                          "clearing busy and trying to proceed\n", info->name);
529         } else if (ret != timeout)
530                 CX18_DEBUG_API("waited %u msecs for busy mbox to be acked\n",
531                                jiffies_to_msecs(timeout-ret));
532
533         /* Build the outgoing mailbox */
534         req = ((req & 0xfffffffe) == 0xfffffffe) ? 1 : req + 1;
535
536         cx18_writel(cx, cmd, &mb->cmd);
537         for (i = 0; i < args; i++)
538                 cx18_writel(cx, data[i], &mb->args[i]);
539         cx18_writel(cx, 0, &mb->error);
540         cx18_writel(cx, req, &mb->request);
541         cx18_writel(cx, req - 1, &mb->ack); /* ensure ack & req are distinct */
542
543         /*
544          * Notify the XPU and wait for it to send an Ack back
545          */
546         timeout = msecs_to_jiffies((info->flags & API_FAST) ? 10 : 20);
547
548         CX18_DEBUG_HI_IRQ("sending interrupt SW1: %x to send %s\n",
549                           irq, info->name);
550         cx18_write_reg_expect(cx, irq, SW1_INT_SET, irq, irq);
551
552         ret = wait_event_timeout(
553                        *waitq,
554                        cx18_readl(cx, &mb->ack) == cx18_readl(cx, &mb->request),
555                        timeout);
556
557         if (ret == 0) {
558                 /* Timed out */
559                 mutex_unlock(mb_lock);
560                 CX18_DEBUG_WARN("sending %s timed out waiting %d msecs for RPU "
561                                 "acknowledgement\n",
562                                 info->name, jiffies_to_msecs(timeout));
563                 return -EINVAL;
564         }
565
566         if (ret != timeout)
567                 CX18_DEBUG_HI_API("waited %u msecs for %s to be acked\n",
568                                   jiffies_to_msecs(timeout-ret), info->name);
569
570         /* Collect data returned by the XPU */
571         for (i = 0; i < MAX_MB_ARGUMENTS; i++)
572                 data[i] = cx18_readl(cx, &mb->args[i]);
573         err = cx18_readl(cx, &mb->error);
574         mutex_unlock(mb_lock);
575
576         /*
577          * Wait for XPU to perform extra actions for the caller in some cases.
578          * e.g. CX18_CPU_DE_RELEASE_MDL will cause the CPU to send all buffers
579          * back in a burst shortly thereafter
580          */
581         if (info->flags & API_SLOW)
582                 cx18_msleep_timeout(300, 0);
583
584         if (err)
585                 CX18_DEBUG_API("mailbox error %08x for command %s\n", err,
586                                 info->name);
587         return err ? -EIO : 0;
588 }
589
590 int cx18_api(struct cx18 *cx, u32 cmd, int args, u32 data[])
591 {
592         return cx18_api_call(cx, cmd, args, data);
593 }
594
595 static int cx18_set_filter_param(struct cx18_stream *s)
596 {
597         struct cx18 *cx = s->cx;
598         u32 mode;
599         int ret;
600
601         mode = (cx->filter_mode & 1) ? 2 : (cx->spatial_strength ? 1 : 0);
602         ret = cx18_vapi(cx, CX18_CPU_SET_FILTER_PARAM, 4,
603                         s->handle, 1, mode, cx->spatial_strength);
604         mode = (cx->filter_mode & 2) ? 2 : (cx->temporal_strength ? 1 : 0);
605         ret = ret ? ret : cx18_vapi(cx, CX18_CPU_SET_FILTER_PARAM, 4,
606                         s->handle, 0, mode, cx->temporal_strength);
607         ret = ret ? ret : cx18_vapi(cx, CX18_CPU_SET_FILTER_PARAM, 4,
608                         s->handle, 2, cx->filter_mode >> 2, 0);
609         return ret;
610 }
611
612 int cx18_api_func(void *priv, u32 cmd, int in, int out,
613                 u32 data[CX2341X_MBOX_MAX_DATA])
614 {
615         struct cx18 *cx = priv;
616         struct cx18_stream *s = &cx->streams[CX18_ENC_STREAM_TYPE_MPG];
617
618         switch (cmd) {
619         case CX2341X_ENC_SET_OUTPUT_PORT:
620                 return 0;
621         case CX2341X_ENC_SET_FRAME_RATE:
622                 return cx18_vapi(cx, CX18_CPU_SET_VIDEO_IN, 6,
623                                 s->handle, 0, 0, 0, 0, data[0]);
624         case CX2341X_ENC_SET_FRAME_SIZE:
625                 return cx18_vapi(cx, CX18_CPU_SET_VIDEO_RESOLUTION, 3,
626                                 s->handle, data[1], data[0]);
627         case CX2341X_ENC_SET_STREAM_TYPE:
628                 return cx18_vapi(cx, CX18_CPU_SET_STREAM_OUTPUT_TYPE, 2,
629                                 s->handle, data[0]);
630         case CX2341X_ENC_SET_ASPECT_RATIO:
631                 return cx18_vapi(cx, CX18_CPU_SET_ASPECT_RATIO, 2,
632                                 s->handle, data[0]);
633
634         case CX2341X_ENC_SET_GOP_PROPERTIES:
635                 return cx18_vapi(cx, CX18_CPU_SET_GOP_STRUCTURE, 3,
636                                 s->handle, data[0], data[1]);
637         case CX2341X_ENC_SET_GOP_CLOSURE:
638                 return 0;
639         case CX2341X_ENC_SET_AUDIO_PROPERTIES:
640                 return cx18_vapi(cx, CX18_CPU_SET_AUDIO_PARAMETERS, 2,
641                                 s->handle, data[0]);
642         case CX2341X_ENC_MUTE_AUDIO:
643                 return cx18_vapi(cx, CX18_CPU_SET_AUDIO_MUTE, 2,
644                                 s->handle, data[0]);
645         case CX2341X_ENC_SET_BIT_RATE:
646                 return cx18_vapi(cx, CX18_CPU_SET_VIDEO_RATE, 5,
647                                 s->handle, data[0], data[1], data[2], data[3]);
648         case CX2341X_ENC_MUTE_VIDEO:
649                 return cx18_vapi(cx, CX18_CPU_SET_VIDEO_MUTE, 2,
650                                 s->handle, data[0]);
651         case CX2341X_ENC_SET_FRAME_DROP_RATE:
652                 return cx18_vapi(cx, CX18_CPU_SET_SKIP_INPUT_FRAME, 2,
653                                 s->handle, data[0]);
654         case CX2341X_ENC_MISC:
655                 return cx18_vapi(cx, CX18_CPU_SET_MISC_PARAMETERS, 4,
656                                 s->handle, data[0], data[1], data[2]);
657         case CX2341X_ENC_SET_DNR_FILTER_MODE:
658                 cx->filter_mode = (data[0] & 3) | (data[1] << 2);
659                 return cx18_set_filter_param(s);
660         case CX2341X_ENC_SET_DNR_FILTER_PROPS:
661                 cx->spatial_strength = data[0];
662                 cx->temporal_strength = data[1];
663                 return cx18_set_filter_param(s);
664         case CX2341X_ENC_SET_SPATIAL_FILTER_TYPE:
665                 return cx18_vapi(cx, CX18_CPU_SET_SPATIAL_FILTER_TYPE, 3,
666                                 s->handle, data[0], data[1]);
667         case CX2341X_ENC_SET_CORING_LEVELS:
668                 return cx18_vapi(cx, CX18_CPU_SET_MEDIAN_CORING, 5,
669                                 s->handle, data[0], data[1], data[2], data[3]);
670         }
671         CX18_WARN("Unknown cmd %x\n", cmd);
672         return 0;
673 }
674
675 int cx18_vapi_result(struct cx18 *cx, u32 data[MAX_MB_ARGUMENTS],
676                 u32 cmd, int args, ...)
677 {
678         va_list ap;
679         int i;
680
681         va_start(ap, args);
682         for (i = 0; i < args; i++)
683                 data[i] = va_arg(ap, u32);
684         va_end(ap);
685         return cx18_api(cx, cmd, args, data);
686 }
687
688 int cx18_vapi(struct cx18 *cx, u32 cmd, int args, ...)
689 {
690         u32 data[MAX_MB_ARGUMENTS];
691         va_list ap;
692         int i;
693
694         if (cx == NULL) {
695                 CX18_ERR("cx == NULL (cmd=%x)\n", cmd);
696                 return 0;
697         }
698         if (args > MAX_MB_ARGUMENTS) {
699                 CX18_ERR("args too big (cmd=%x)\n", cmd);
700                 args = MAX_MB_ARGUMENTS;
701         }
702         va_start(ap, args);
703         for (i = 0; i < args; i++)
704                 data[i] = va_arg(ap, u32);
705         va_end(ap);
706         return cx18_api(cx, cmd, args, data);
707 }