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   1 #ifndef _ASM_IA64_PAL_H
   2 #define _ASM_IA64_PAL_H
   3
   4 /*
   5  * Processor Abstraction Layer definitions.
   6  *
   7  * This is based on Intel IA-64 Architecture Software Developer's Manual rev 1.0
   8  * chapter 11 IA-64 Processor Abstraction Layer
   9  *
  10  * Copyright (C) 1998-2001 Hewlett-Packard Co
  11  *      David Mosberger-Tang <davidm@hpl.hp.com>
  12  *      Stephane Eranian <eranian@hpl.hp.com>
  13  * Copyright (C) 1999 VA Linux Systems
  14  * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
  15  * Copyright (C) 1999 Srinivasa Prasad Thirumalachar <sprasad@sprasad.engr.sgi.com>
  16  *
  17  * 99/10/01     davidm  Make sure we pass zero for reserved parameters.
  18  * 00/03/07     davidm  Updated pal_cache_flush() to be in sync with PAL v2.6.
  19  * 00/03/23     cfleck  Modified processor min-state save area to match updated PAL & SAL info
  20  * 00/05/24     eranian Updated to latest PAL spec, fix structures bugs, added
  21  * 00/05/25     eranian Support for stack calls, and static physical calls
  22  * 00/06/18     eranian Support for stacked physical calls
  23  */
  24
  25 /*
  26  * Note that some of these calls use a static-register only calling
  27  * convention which has nothing to do with the regular calling
  28  * convention.
  29  */
  30 #define PAL_CACHE_FLUSH         1       /* flush i/d cache */
  31 #define PAL_CACHE_INFO          2       /* get detailed i/d cache info */
  32 #define PAL_CACHE_INIT          3       /* initialize i/d cache */
  33 #define PAL_CACHE_SUMMARY       4       /* get summary of cache heirarchy */
  34 #define PAL_MEM_ATTRIB          5       /* list supported memory attributes */
  35 #define PAL_PTCE_INFO           6       /* purge TLB info */
  36 #define PAL_VM_INFO             7       /* return supported virtual memory features */
  37 #define PAL_VM_SUMMARY          8       /* return summary on supported vm features */
  38 #define PAL_BUS_GET_FEATURES    9       /* return processor bus interface features settings */
  39 #define PAL_BUS_SET_FEATURES    10      /* set processor bus features */
  40 #define PAL_DEBUG_INFO          11      /* get number of debug registers */
  41 #define PAL_FIXED_ADDR          12      /* get fixed component of processors's directed address */
  42 #define PAL_FREQ_BASE           13      /* base frequency of the platform */
  43 #define PAL_FREQ_RATIOS         14      /* ratio of processor, bus and ITC frequency */
  44 #define PAL_PERF_MON_INFO       15      /* return performance monitor info */
  45 #define PAL_PLATFORM_ADDR       16      /* set processor interrupt block and IO port space addr */
  46 #define PAL_PROC_GET_FEATURES   17      /* get configurable processor features & settings */
  47 #define PAL_PROC_SET_FEATURES   18      /* enable/disable configurable processor features */
  48 #define PAL_RSE_INFO            19      /* return rse information */
  49 #define PAL_VERSION             20      /* return version of PAL code */
  50 #define PAL_MC_CLEAR_LOG        21      /* clear all processor log info */
  51 #define PAL_MC_DRAIN            22      /* drain operations which could result in an MCA */
  52 #define PAL_MC_EXPECTED         23      /* set/reset expected MCA indicator */
  53 #define PAL_MC_DYNAMIC_STATE    24      /* get processor dynamic state */
  54 #define PAL_MC_ERROR_INFO       25      /* get processor MCA info and static state */
  55 #define PAL_MC_RESUME           26      /* Return to interrupted process */
  56 #define PAL_MC_REGISTER_MEM     27      /* Register memory for PAL to use during MCAs and inits */
  57 #define PAL_HALT                28      /* enter the low power HALT state */
  58 #define PAL_HALT_LIGHT          29      /* enter the low power light halt state*/
  59 #define PAL_COPY_INFO           30      /* returns info needed to relocate PAL */
  60 #define PAL_CACHE_LINE_INIT     31      /* init tags & data of cache line */
  61 #define PAL_PMI_ENTRYPOINT      32      /* register PMI memory entry points with the processor */
  62 #define PAL_ENTER_IA_32_ENV     33      /* enter IA-32 system environment */
  63 #define PAL_VM_PAGE_SIZE        34      /* return vm TC and page walker page sizes */
  64
  65 #define PAL_MEM_FOR_TEST        37      /* get amount of memory needed for late processor test */
  66 #define PAL_CACHE_PROT_INFO     38      /* get i/d cache protection info */
  67 #define PAL_REGISTER_INFO       39      /* return AR and CR register information*/
  68 #define PAL_SHUTDOWN            40      /* enter processor shutdown state */
  69 #define PAL_PREFETCH_VISIBILITY 41      /* Make Processor Prefetches Visible */
  70 #define PAL_LOGICAL_TO_PHYSICAL 42      /* returns information on logical to physical processor mapping */
  71 #define PAL_CACHE_SHARED_INFO   43      /* returns information on caches shared by logical processor */
  72
  73 #define PAL_COPY_PAL            256     /* relocate PAL procedures and PAL PMI */
  74 #define PAL_HALT_INFO           257     /* return the low power capabilities of processor */
  75 #define PAL_TEST_PROC           258     /* perform late processor self-test */
  76 #define PAL_CACHE_READ          259     /* read tag & data of cacheline for diagnostic testing */
  77 #define PAL_CACHE_WRITE         260     /* write tag & data of cacheline for diagnostic testing */
  78 #define PAL_VM_TR_READ          261     /* read contents of translation register */
  79 #define PAL_GET_PSTATE          262     /* get the current P-state */
  80 #define PAL_SET_PSTATE          263     /* set the P-state */
  81
  82 #ifndef __ASSEMBLY__
  83
  84 #include <linux/types.h>
  85 #include <asm/fpu.h>
  86
  87 /*
  88  * Data types needed to pass information into PAL procedures and
  89  * interpret information returned by them.
  90  */
  91
  92 /* Return status from the PAL procedure */
  93 typedef s64                             pal_status_t;
  94
  95 #define PAL_STATUS_SUCCESS              0       /* No error */
  96 #define PAL_STATUS_UNIMPLEMENTED        (-1)    /* Unimplemented procedure */
  97 #define PAL_STATUS_EINVAL               (-2)    /* Invalid argument */
  98 #define PAL_STATUS_ERROR                (-3)    /* Error */
  99 #define PAL_STATUS_CACHE_INIT_FAIL      (-4)    /* Could not initialize the
 100                                                  * specified level and type of
 101                                                  * cache without sideeffects
 102                                                  * and "restrict" was 1
 103                                                  */
 104
 105 /* Processor cache level in the heirarchy */
 106 typedef u64                             pal_cache_level_t;
 107 #define PAL_CACHE_LEVEL_L0              0       /* L0 */
 108 #define PAL_CACHE_LEVEL_L1              1       /* L1 */
 109 #define PAL_CACHE_LEVEL_L2              2       /* L2 */
 110
 111
 112 /* Processor cache type at a particular level in the heirarchy */
 113
 114 typedef u64                             pal_cache_type_t;
 115 #define PAL_CACHE_TYPE_INSTRUCTION      1       /* Instruction cache */
 116 #define PAL_CACHE_TYPE_DATA             2       /* Data or unified cache */
 117 #define PAL_CACHE_TYPE_INSTRUCTION_DATA 3       /* Both Data & Instruction */
 118
 119
 120 #define PAL_CACHE_FLUSH_INVALIDATE      1       /* Invalidate clean lines */
 121 #define PAL_CACHE_FLUSH_CHK_INTRS       2       /* check for interrupts/mc while flushing */
 122
 123 /* Processor cache line size in bytes  */
 124 typedef int                             pal_cache_line_size_t;
 125
 126 /* Processor cache line state */
 127 typedef u64                             pal_cache_line_state_t;
 128 #define PAL_CACHE_LINE_STATE_INVALID    0       /* Invalid */
 129 #define PAL_CACHE_LINE_STATE_SHARED     1       /* Shared */
 130 #define PAL_CACHE_LINE_STATE_EXCLUSIVE  2       /* Exclusive */
 131 #define PAL_CACHE_LINE_STATE_MODIFIED   3       /* Modified */
 132
 133 typedef struct pal_freq_ratio {
 134         u32 den, num;           /* numerator & denominator */
 135 } itc_ratio, proc_ratio;
 136
 137 typedef union  pal_cache_config_info_1_s {
 138         struct {
 139                 u64             u               : 1,    /* 0 Unified cache ? */
 140                                 at              : 2,    /* 2-1 Cache mem attr*/
 141                                 reserved        : 5,    /* 7-3 Reserved */
 142                                 associativity   : 8,    /* 16-8 Associativity*/
 143                                 line_size       : 8,    /* 23-17 Line size */
 144                                 stride          : 8,    /* 31-24 Stride */
 145                                 store_latency   : 8,    /*39-32 Store latency*/
 146                                 load_latency    : 8,    /* 47-40 Load latency*/
 147                                 store_hints     : 8,    /* 55-48 Store hints*/
 148                                 load_hints      : 8;    /* 63-56 Load hints */
 149         } pcci1_bits;
 150         u64                     pcci1_data;
 151 } pal_cache_config_info_1_t;
 152
 153 typedef union  pal_cache_config_info_2_s {
 154         struct {
 155                 u32             cache_size;             /*cache size in bytes*/
 156
 157
 158                 u32             alias_boundary  : 8,    /* 39-32 aliased addr
 159                                                          * separation for max
 160                                                          * performance.
 161                                                          */
 162                                 tag_ls_bit      : 8,    /* 47-40 LSb of addr*/
 163                                 tag_ms_bit      : 8,    /* 55-48 MSb of addr*/
 164                                 reserved        : 8;    /* 63-56 Reserved */
 165         } pcci2_bits;
 166         u64                     pcci2_data;
 167 } pal_cache_config_info_2_t;
 168
 169
 170 typedef struct pal_cache_config_info_s {
 171         pal_status_t                    pcci_status;
 172         pal_cache_config_info_1_t       pcci_info_1;
 173         pal_cache_config_info_2_t       pcci_info_2;
 174         u64                             pcci_reserved;
 175 } pal_cache_config_info_t;
 176
 177 #define pcci_ld_hints           pcci_info_1.pcci1_bits.load_hints
 178 #define pcci_st_hints           pcci_info_1.pcci1_bits.store_hints
 179 #define pcci_ld_latency         pcci_info_1.pcci1_bits.load_latency
 180 #define pcci_st_latency         pcci_info_1.pcci1_bits.store_latency
 181 #define pcci_stride             pcci_info_1.pcci1_bits.stride
 182 #define pcci_line_size          pcci_info_1.pcci1_bits.line_size
 183 #define pcci_assoc              pcci_info_1.pcci1_bits.associativity
 184 #define pcci_cache_attr         pcci_info_1.pcci1_bits.at
 185 #define pcci_unified            pcci_info_1.pcci1_bits.u
 186 #define pcci_tag_msb            pcci_info_2.pcci2_bits.tag_ms_bit
 187 #define pcci_tag_lsb            pcci_info_2.pcci2_bits.tag_ls_bit
 188 #define pcci_alias_boundary     pcci_info_2.pcci2_bits.alias_boundary
 189 #define pcci_cache_size         pcci_info_2.pcci2_bits.cache_size
 190
 191
 192
 193 /* Possible values for cache attributes */
 194
 195 #define PAL_CACHE_ATTR_WT               0       /* Write through cache */
 196 #define PAL_CACHE_ATTR_WB               1       /* Write back cache */
 197 #define PAL_CACHE_ATTR_WT_OR_WB         2       /* Either write thru or write
 198                                                  * back depending on TLB
 199                                                  * memory attributes
 200                                                  */
 201
 202
 203 /* Possible values for cache hints */
 204
 205 #define PAL_CACHE_HINT_TEMP_1           0       /* Temporal level 1 */
 206 #define PAL_CACHE_HINT_NTEMP_1          1       /* Non-temporal level 1 */
 207 #define PAL_CACHE_HINT_NTEMP_ALL        3       /* Non-temporal all levels */
 208
 209 /* Processor cache protection  information */
 210 typedef union pal_cache_protection_element_u {
 211         u32                     pcpi_data;
 212         struct {
 213                 u32             data_bits       : 8, /* # data bits covered by
 214                                                       * each unit of protection
 215                                                       */
 216
 217                                 tagprot_lsb     : 6, /* Least -do- */
 218                                 tagprot_msb     : 6, /* Most Sig. tag address
 219                                                       * bit that this
 220                                                       * protection covers.
 221                                                       */
 222                                 prot_bits       : 6, /* # of protection bits */
 223                                 method          : 4, /* Protection method */
 224                                 t_d             : 2; /* Indicates which part
 225                                                       * of the cache this
 226                                                       * protection encoding
 227                                                       * applies.
 228                                                       */
 229         } pcp_info;
 230 } pal_cache_protection_element_t;
 231
 232 #define pcpi_cache_prot_part    pcp_info.t_d
 233 #define pcpi_prot_method        pcp_info.method
 234 #define pcpi_prot_bits          pcp_info.prot_bits
 235 #define pcpi_tagprot_msb        pcp_info.tagprot_msb
 236 #define pcpi_tagprot_lsb        pcp_info.tagprot_lsb
 237 #define pcpi_data_bits          pcp_info.data_bits
 238
 239 /* Processor cache part encodings */
 240 #define PAL_CACHE_PROT_PART_DATA        0       /* Data protection  */
 241 #define PAL_CACHE_PROT_PART_TAG         1       /* Tag  protection */
 242 #define PAL_CACHE_PROT_PART_TAG_DATA    2       /* Tag+data protection (tag is
 243                                                  * more significant )
 244                                                  */
 245 #define PAL_CACHE_PROT_PART_DATA_TAG    3       /* Data+tag protection (data is
 246                                                  * more significant )
 247                                                  */
 248 #define PAL_CACHE_PROT_PART_MAX         6
 249
 250
 251 typedef struct pal_cache_protection_info_s {
 252         pal_status_t                    pcpi_status;
 253         pal_cache_protection_element_t  pcp_info[PAL_CACHE_PROT_PART_MAX];
 254 } pal_cache_protection_info_t;
 255
 256
 257 /* Processor cache protection method encodings */
 258 #define PAL_CACHE_PROT_METHOD_NONE              0       /* No protection */
 259 #define PAL_CACHE_PROT_METHOD_ODD_PARITY        1       /* Odd parity */
 260 #define PAL_CACHE_PROT_METHOD_EVEN_PARITY       2       /* Even parity */
 261 #define PAL_CACHE_PROT_METHOD_ECC               3       /* ECC protection */
 262
 263
 264 /* Processor cache line identification in the heirarchy */
 265 typedef union pal_cache_line_id_u {
 266         u64                     pclid_data;
 267         struct {
 268                 u64             cache_type      : 8,    /* 7-0 cache type */
 269                                 level           : 8,    /* 15-8 level of the
 270                                                          * cache in the
 271                                                          * heirarchy.
 272                                                          */
 273                                 way             : 8,    /* 23-16 way in the set
 274                                                          */
 275                                 part            : 8,    /* 31-24 part of the
 276                                                          * cache
 277                                                          */
 278                                 reserved        : 32;   /* 63-32 is reserved*/
 279         } pclid_info_read;
 280         struct {
 281                 u64             cache_type      : 8,    /* 7-0 cache type */
 282                                 level           : 8,    /* 15-8 level of the
 283                                                          * cache in the
 284                                                          * heirarchy.
 285                                                          */
 286                                 way             : 8,    /* 23-16 way in the set
 287                                                          */
 288                                 part            : 8,    /* 31-24 part of the
 289                                                          * cache
 290                                                          */
 291                                 mesi            : 8,    /* 39-32 cache line
 292                                                          * state
 293                                                          */
 294                                 start           : 8,    /* 47-40 lsb of data to
 295                                                          * invert
 296                                                          */
 297                                 length          : 8,    /* 55-48 #bits to
 298                                                          * invert
 299                                                          */
 300                                 trigger         : 8;    /* 63-56 Trigger error
 301                                                          * by doing a load
 302                                                          * after the write
 303                                                          */
 304
 305         } pclid_info_write;
 306 } pal_cache_line_id_u_t;
 307
 308 #define pclid_read_part         pclid_info_read.part
 309 #define pclid_read_way          pclid_info_read.way
 310 #define pclid_read_level        pclid_info_read.level
 311 #define pclid_read_cache_type   pclid_info_read.cache_type
 312
 313 #define pclid_write_trigger     pclid_info_write.trigger
 314 #define pclid_write_length      pclid_info_write.length
 315 #define pclid_write_start       pclid_info_write.start
 316 #define pclid_write_mesi        pclid_info_write.mesi
 317 #define pclid_write_part        pclid_info_write.part
 318 #define pclid_write_way         pclid_info_write.way
 319 #define pclid_write_level       pclid_info_write.level
 320 #define pclid_write_cache_type  pclid_info_write.cache_type
 321
 322 /* Processor cache line part encodings */
 323 #define PAL_CACHE_LINE_ID_PART_DATA             0       /* Data */
 324 #define PAL_CACHE_LINE_ID_PART_TAG              1       /* Tag */
 325 #define PAL_CACHE_LINE_ID_PART_DATA_PROT        2       /* Data protection */
 326 #define PAL_CACHE_LINE_ID_PART_TAG_PROT         3       /* Tag protection */
 327 #define PAL_CACHE_LINE_ID_PART_DATA_TAG_PROT    4       /* Data+tag
 328                                                          * protection
 329                                                          */
 330 typedef struct pal_cache_line_info_s {
 331         pal_status_t            pcli_status;            /* Return status of the read cache line
 332                                                          * info call.
 333                                                          */
 334         u64                     pcli_data;              /* 64-bit data, tag, protection bits .. */
 335         u64                     pcli_data_len;          /* data length in bits */
 336         pal_cache_line_state_t  pcli_cache_line_state;  /* mesi state */
 337
 338 } pal_cache_line_info_t;
 339
 340
 341 /* Machine Check related crap */
 342
 343 /* Pending event status bits  */
 344 typedef u64                                     pal_mc_pending_events_t;
 345
 346 #define PAL_MC_PENDING_MCA                      (1 << 0)
 347 #define PAL_MC_PENDING_INIT                     (1 << 1)
 348
 349 /* Error information type */
 350 typedef u64                                     pal_mc_info_index_t;
 351
 352 #define PAL_MC_INFO_PROCESSOR                   0       /* Processor */
 353 #define PAL_MC_INFO_CACHE_CHECK                 1       /* Cache check */
 354 #define PAL_MC_INFO_TLB_CHECK                   2       /* Tlb check */
 355 #define PAL_MC_INFO_BUS_CHECK                   3       /* Bus check */
 356 #define PAL_MC_INFO_REQ_ADDR                    4       /* Requestor address */
 357 #define PAL_MC_INFO_RESP_ADDR                   5       /* Responder address */
 358 #define PAL_MC_INFO_TARGET_ADDR                 6       /* Target address */
 359 #define PAL_MC_INFO_IMPL_DEP                    7       /* Implementation
 360                                                          * dependent
 361                                                          */
 362
 363
 364 typedef struct pal_process_state_info_s {
 365         u64             reserved1       : 2,
 366                         rz              : 1,    /* PAL_CHECK processor
 367                                                  * rendezvous
 368                                                  * successful.
 369                                                  */
 370
 371                         ra              : 1,    /* PAL_CHECK attempted
 372                                                  * a rendezvous.
 373                                                  */
 374                         me              : 1,    /* Distinct multiple
 375                                                  * errors occurred
 376                                                  */
 377
 378                         mn              : 1,    /* Min. state save
 379                                                  * area has been
 380                                                  * registered with PAL
 381                                                  */
 382
 383                         sy              : 1,    /* Storage integrity
 384                                                  * synched
 385                                                  */
 386
 387
 388                         co              : 1,    /* Continuable */
 389                         ci              : 1,    /* MC isolated */
 390                         us              : 1,    /* Uncontained storage
 391                                                  * damage.
 392                                                  */
 393
 394
 395                         hd              : 1,    /* Non-essential hw
 396                                                  * lost (no loss of
 397                                                  * functionality)
 398                                                  * causing the
 399                                                  * processor to run in
 400                                                  * degraded mode.
 401                                                  */
 402
 403                         tl              : 1,    /* 1 => MC occurred
 404                                                  * after an instr was
 405                                                  * executed but before
 406                                                  * the trap that
 407                                                  * resulted from instr
 408                                                  * execution was
 409                                                  * generated.
 410                                                  * (Trap Lost )
 411                                                  */
 412                         mi              : 1,    /* More information available
 413                                                  * call PAL_MC_ERROR_INFO
 414                                                  */
 415                         pi              : 1,    /* Precise instruction pointer */
 416                         pm              : 1,    /* Precise min-state save area */
 417
 418                         dy              : 1,    /* Processor dynamic
 419                                                  * state valid
 420                                                  */
 421
 422
 423                         in              : 1,    /* 0 = MC, 1 = INIT */
 424                         rs              : 1,    /* RSE valid */
 425                         cm              : 1,    /* MC corrected */
 426                         ex              : 1,    /* MC is expected */
 427                         cr              : 1,    /* Control regs valid*/
 428                         pc              : 1,    /* Perf cntrs valid */
 429                         dr              : 1,    /* Debug regs valid */
 430                         tr              : 1,    /* Translation regs
 431                                                  * valid
 432                                                  */
 433                         rr              : 1,    /* Region regs valid */
 434                         ar              : 1,    /* App regs valid */
 435                         br              : 1,    /* Branch regs valid */
 436                         pr              : 1,    /* Predicate registers
 437                                                  * valid
 438                                                  */
 439
 440                         fp              : 1,    /* fp registers valid*/
 441                         b1              : 1,    /* Preserved bank one
 442                                                  * general registers
 443                                                  * are valid
 444                                                  */
 445                         b0              : 1,    /* Preserved bank zero
 446                                                  * general registers
 447                                                  * are valid
 448                                                  */
 449                         gr              : 1,    /* General registers
 450                                                  * are valid
 451                                                  * (excl. banked regs)
 452                                                  */
 453                         dsize           : 16,   /* size of dynamic
 454                                                  * state returned
 455                                                  * by the processor
 456                                                  */
 457
 458                         reserved2       : 11,
 459                         cc              : 1,    /* Cache check */
 460                         tc              : 1,    /* TLB check */
 461                         bc              : 1,    /* Bus check */
 462                         rc              : 1,    /* Register file check */
 463                         uc              : 1;    /* Uarch check */
 464
 465 } pal_processor_state_info_t;
 466
 467 typedef struct pal_cache_check_info_s {
 468         u64             op              : 4,    /* Type of cache
 469                                                  * operation that
 470                                                  * caused the machine
 471                                                  * check.
 472                                                  */
 473                         level           : 2,    /* Cache level */
 474                         reserved1       : 2,
 475                         dl              : 1,    /* Failure in data part
 476                                                  * of cache line
 477                                                  */
 478                         tl              : 1,    /* Failure in tag part
 479                                                  * of cache line
 480                                                  */
 481                         dc              : 1,    /* Failure in dcache */
 482                         ic              : 1,    /* Failure in icache */
 483                         mesi            : 3,    /* Cache line state */
 484                         mv              : 1,    /* mesi valid */
 485                         way             : 5,    /* Way in which the
 486                                                  * error occurred
 487                                                  */
 488                         wiv             : 1,    /* Way field valid */
 489                         reserved2       : 10,
 490
 491                         index           : 20,   /* Cache line index */
 492                         reserved3       : 2,
 493
 494                         is              : 1,    /* instruction set (1 == ia32) */
 495                         iv              : 1,    /* instruction set field valid */
 496                         pl              : 2,    /* privilege level */
 497                         pv              : 1,    /* privilege level field valid */
 498                         mcc             : 1,    /* Machine check corrected */
 499                         tv              : 1,    /* Target address
 500                                                  * structure is valid
 501                                                  */
 502                         rq              : 1,    /* Requester identifier
 503                                                  * structure is valid
 504                                                  */
 505                         rp              : 1,    /* Responder identifier
 506                                                  * structure is valid
 507                                                  */
 508                         pi              : 1;    /* Precise instruction pointer
 509                                                  * structure is valid
 510                                                  */
 511 } pal_cache_check_info_t;
 512
 513 typedef struct pal_tlb_check_info_s {
 514
 515         u64             tr_slot         : 8,    /* Slot# of TR where
 516                                                  * error occurred
 517                                                  */
 518                         trv             : 1,    /* tr_slot field is valid */
 519                         reserved1       : 1,
 520                         level           : 2,    /* TLB level where failure occurred */
 521                         reserved2       : 4,
 522                         dtr             : 1,    /* Fail in data TR */
 523                         itr             : 1,    /* Fail in inst TR */
 524                         dtc             : 1,    /* Fail in data TC */
 525                         itc             : 1,    /* Fail in inst. TC */
 526                         op              : 4,    /* Cache operation */
 527                         reserved3       : 30,
 528
 529                         is              : 1,    /* instruction set (1 == ia32) */
 530                         iv              : 1,    /* instruction set field valid */
 531                         pl              : 2,    /* privilege level */
 532                         pv              : 1,    /* privilege level field valid */
 533                         mcc             : 1,    /* Machine check corrected */
 534                         tv              : 1,    /* Target address
 535                                                  * structure is valid
 536                                                  */
 537                         rq              : 1,    /* Requester identifier
 538                                                  * structure is valid
 539                                                  */
 540                         rp              : 1,    /* Responder identifier
 541                                                  * structure is valid
 542                                                  */
 543                         pi              : 1;    /* Precise instruction pointer
 544                                                  * structure is valid
 545                                                  */
 546 } pal_tlb_check_info_t;
 547
 548 typedef struct pal_bus_check_info_s {
 549         u64             size            : 5,    /* Xaction size */
 550                         ib              : 1,    /* Internal bus error */
 551                         eb              : 1,    /* External bus error */
 552                         cc              : 1,    /* Error occurred
 553                                                  * during cache-cache
 554                                                  * transfer.
 555                                                  */
 556                         type            : 8,    /* Bus xaction type*/
 557                         sev             : 5,    /* Bus error severity*/
 558                         hier            : 2,    /* Bus hierarchy level */
 559                         reserved1       : 1,
 560                         bsi             : 8,    /* Bus error status
 561                                                  * info
 562                                                  */
 563                         reserved2       : 22,
 564
 565                         is              : 1,    /* instruction set (1 == ia32) */
 566                         iv              : 1,    /* instruction set field valid */
 567                         pl              : 2,    /* privilege level */
 568                         pv              : 1,    /* privilege level field valid */
 569                         mcc             : 1,    /* Machine check corrected */
 570                         tv              : 1,    /* Target address
 571                                                  * structure is valid
 572                                                  */
 573                         rq              : 1,    /* Requester identifier
 574                                                  * structure is valid
 575                                                  */
 576                         rp              : 1,    /* Responder identifier
 577                                                  * structure is valid
 578                                                  */
 579                         pi              : 1;    /* Precise instruction pointer
 580                                                  * structure is valid
 581                                                  */
 582 } pal_bus_check_info_t;
 583
 584 typedef struct pal_reg_file_check_info_s {
 585         u64             id              : 4,    /* Register file identifier */
 586                         op              : 4,    /* Type of register
 587                                                  * operation that
 588                                                  * caused the machine
 589                                                  * check.
 590                                                  */
 591                         reg_num         : 7,    /* Register number */
 592                         rnv             : 1,    /* reg_num valid */
 593                         reserved2       : 38,
 594
 595                         is              : 1,    /* instruction set (1 == ia32) */
 596                         iv              : 1,    /* instruction set field valid */
 597                         pl              : 2,    /* privilege level */
 598                         pv              : 1,    /* privilege level field valid */
 599                         mcc             : 1,    /* Machine check corrected */
 600                         reserved3       : 3,
 601                         pi              : 1;    /* Precise instruction pointer
 602                                                  * structure is valid
 603                                                  */
 604 } pal_reg_file_check_info_t;
 605
 606 typedef struct pal_uarch_check_info_s {
 607         u64             sid             : 5,    /* Structure identification */
 608                         level           : 3,    /* Level of failure */
 609                         array_id        : 4,    /* Array identification */
 610                         op              : 4,    /* Type of
 611                                                  * operation that
 612                                                  * caused the machine
 613                                                  * check.
 614                                                  */
 615                         way             : 6,    /* Way of structure */
 616                         wv              : 1,    /* way valid */
 617                         xv              : 1,    /* index valid */
 618                         reserved1       : 8,
 619                         index           : 8,    /* Index or set of the uarch
 620                                                  * structure that failed.
 621                                                  */
 622                         reserved2       : 24,
 623
 624                         is              : 1,    /* instruction set (1 == ia32) */
 625                         iv              : 1,    /* instruction set field valid */
 626                         pl              : 2,    /* privilege level */
 627                         pv              : 1,    /* privilege level field valid */
 628                         mcc             : 1,    /* Machine check corrected */
 629                         tv              : 1,    /* Target address
 630                                                  * structure is valid
 631                                                  */
 632                         rq              : 1,    /* Requester identifier
 633                                                  * structure is valid
 634                                                  */
 635                         rp              : 1,    /* Responder identifier
 636                                                  * structure is valid
 637                                                  */
 638                         pi              : 1;    /* Precise instruction pointer
 639                                                  * structure is valid
 640                                                  */
 641 } pal_uarch_check_info_t;
 642
 643 typedef union pal_mc_error_info_u {
 644         u64                             pmei_data;
 645         pal_processor_state_info_t      pme_processor;
 646         pal_cache_check_info_t          pme_cache;
 647         pal_tlb_check_info_t            pme_tlb;
 648         pal_bus_check_info_t            pme_bus;
 649         pal_reg_file_check_info_t       pme_reg_file;
 650         pal_uarch_check_info_t          pme_uarch;
 651 } pal_mc_error_info_t;
 652
 653 #define pmci_proc_unknown_check                 pme_processor.uc
 654 #define pmci_proc_bus_check                     pme_processor.bc
 655 #define pmci_proc_tlb_check                     pme_processor.tc
 656 #define pmci_proc_cache_check                   pme_processor.cc
 657 #define pmci_proc_dynamic_state_size            pme_processor.dsize
 658 #define pmci_proc_gpr_valid                     pme_processor.gr
 659 #define pmci_proc_preserved_bank0_gpr_valid     pme_processor.b0
 660 #define pmci_proc_preserved_bank1_gpr_valid     pme_processor.b1
 661 #define pmci_proc_fp_valid                      pme_processor.fp
 662 #define pmci_proc_predicate_regs_valid          pme_processor.pr
 663 #define pmci_proc_branch_regs_valid             pme_processor.br
 664 #define pmci_proc_app_regs_valid                pme_processor.ar
 665 #define pmci_proc_region_regs_valid             pme_processor.rr
 666 #define pmci_proc_translation_regs_valid        pme_processor.tr
 667 #define pmci_proc_debug_regs_valid              pme_processor.dr
 668 #define pmci_proc_perf_counters_valid           pme_processor.pc
 669 #define pmci_proc_control_regs_valid            pme_processor.cr
 670 #define pmci_proc_machine_check_expected        pme_processor.ex
 671 #define pmci_proc_machine_check_corrected       pme_processor.cm
 672 #define pmci_proc_rse_valid                     pme_processor.rs
 673 #define pmci_proc_machine_check_or_init         pme_processor.in
 674 #define pmci_proc_dynamic_state_valid           pme_processor.dy
 675 #define pmci_proc_operation                     pme_processor.op
 676 #define pmci_proc_trap_lost                     pme_processor.tl
 677 #define pmci_proc_hardware_damage               pme_processor.hd
 678 #define pmci_proc_uncontained_storage_damage    pme_processor.us
 679 #define pmci_proc_machine_check_isolated        pme_processor.ci
 680 #define pmci_proc_continuable                   pme_processor.co
 681 #define pmci_proc_storage_intergrity_synced     pme_processor.sy
 682 #define pmci_proc_min_state_save_area_regd      pme_processor.mn
 683 #define pmci_proc_distinct_multiple_errors      pme_processor.me
 684 #define pmci_proc_pal_attempted_rendezvous      pme_processor.ra
 685 #define pmci_proc_pal_rendezvous_complete       pme_processor.rz
 686
 687
 688 #define pmci_cache_level                        pme_cache.level
 689 #define pmci_cache_line_state                   pme_cache.mesi
 690 #define pmci_cache_line_state_valid             pme_cache.mv
 691 #define pmci_cache_line_index                   pme_cache.index
 692 #define pmci_cache_instr_cache_fail             pme_cache.ic
 693 #define pmci_cache_data_cache_fail              pme_cache.dc
 694 #define pmci_cache_line_tag_fail                pme_cache.tl
 695 #define pmci_cache_line_data_fail               pme_cache.dl
 696 #define pmci_cache_operation                    pme_cache.op
 697 #define pmci_cache_way_valid                    pme_cache.wv
 698 #define pmci_cache_target_address_valid         pme_cache.tv
 699 #define pmci_cache_way                          pme_cache.way
 700 #define pmci_cache_mc                           pme_cache.mc
 701
 702 #define pmci_tlb_instr_translation_cache_fail   pme_tlb.itc
 703 #define pmci_tlb_data_translation_cache_fail    pme_tlb.dtc
 704 #define pmci_tlb_instr_translation_reg_fail     pme_tlb.itr
 705 #define pmci_tlb_data_translation_reg_fail      pme_tlb.dtr
 706 #define pmci_tlb_translation_reg_slot           pme_tlb.tr_slot
 707 #define pmci_tlb_mc                             pme_tlb.mc
 708
 709 #define pmci_bus_status_info                    pme_bus.bsi
 710 #define pmci_bus_req_address_valid              pme_bus.rq
 711 #define pmci_bus_resp_address_valid             pme_bus.rp
 712 #define pmci_bus_target_address_valid           pme_bus.tv
 713 #define pmci_bus_error_severity                 pme_bus.sev
 714 #define pmci_bus_transaction_type               pme_bus.type
 715 #define pmci_bus_cache_cache_transfer           pme_bus.cc
 716 #define pmci_bus_transaction_size               pme_bus.size
 717 #define pmci_bus_internal_error                 pme_bus.ib
 718 #define pmci_bus_external_error                 pme_bus.eb
 719 #define pmci_bus_mc                             pme_bus.mc
 720
 721 /*
 722  * NOTE: this min_state_save area struct only includes the 1KB
 723  * architectural state save area.  The other 3 KB is scratch space
 724  * for PAL.
 725  */
 726
 727 typedef struct pal_min_state_area_s {
 728         u64     pmsa_nat_bits;          /* nat bits for saved GRs  */
 729         u64     pmsa_gr[15];            /* GR1  - GR15             */
 730         u64     pmsa_bank0_gr[16];      /* GR16 - GR31             */
 731         u64     pmsa_bank1_gr[16];      /* GR16 - GR31             */
 732         u64     pmsa_pr;                /* predicate registers     */
 733         u64     pmsa_br0;               /* branch register 0       */
 734         u64     pmsa_rsc;               /* ar.rsc                  */
 735         u64     pmsa_iip;               /* cr.iip                  */
 736         u64     pmsa_ipsr;              /* cr.ipsr                 */
 737         u64     pmsa_ifs;               /* cr.ifs                  */
 738         u64     pmsa_xip;               /* previous iip            */
 739         u64     pmsa_xpsr;              /* previous psr            */
 740         u64     pmsa_xfs;               /* previous ifs            */
 741         u64     pmsa_br1;               /* branch register 1       */
 742         u64     pmsa_reserved[70];      /* pal_min_state_area should total to 1KB */
 743 } pal_min_state_area_t;
 744
 745
 746 struct ia64_pal_retval {
 747         /*
 748          * A zero status value indicates call completed without error.
 749          * A negative status value indicates reason of call failure.
 750          * A positive status value indicates success but an
 751          * informational value should be printed (e.g., "reboot for
 752          * change to take effect").
 753          */
 754         s64 status;
 755         u64 v0;
 756         u64 v1;
 757         u64 v2;
 758 };
 759
 760 /*
 761  * Note: Currently unused PAL arguments are generally labeled
 762  * "reserved" so the value specified in the PAL documentation
 763  * (generally 0) MUST be passed.  Reserved parameters are not optional
 764  * parameters.
 765  */
 766 extern struct ia64_pal_retval ia64_pal_call_static (u64, u64, u64, u64, u64);
 767 extern struct ia64_pal_retval ia64_pal_call_stacked (u64, u64, u64, u64);
 768 extern struct ia64_pal_retval ia64_pal_call_phys_static (u64, u64, u64, u64);
 769 extern struct ia64_pal_retval ia64_pal_call_phys_stacked (u64, u64, u64, u64);
 770 extern void ia64_save_scratch_fpregs (struct ia64_fpreg *);
 771 extern void ia64_load_scratch_fpregs (struct ia64_fpreg *);
 772
 773 #define PAL_CALL(iprv,a0,a1,a2,a3) do {                 \
 774         struct ia64_fpreg fr[6];                        \
 775         ia64_save_scratch_fpregs(fr);                   \
 776         iprv = ia64_pal_call_static(a0, a1, a2, a3, 0); \
 777         ia64_load_scratch_fpregs(fr);                   \
 778 } while (0)
 779
 780 #define PAL_CALL_IC_OFF(iprv,a0,a1,a2,a3) do {          \
 781         struct ia64_fpreg fr[6];                        \
 782         ia64_save_scratch_fpregs(fr);                   \
 783         iprv = ia64_pal_call_static(a0, a1, a2, a3, 1); \
 784         ia64_load_scratch_fpregs(fr);                   \
 785 } while (0)
 786
 787 #define PAL_CALL_STK(iprv,a0,a1,a2,a3) do {             \
 788         struct ia64_fpreg fr[6];                        \
 789         ia64_save_scratch_fpregs(fr);                   \
 790         iprv = ia64_pal_call_stacked(a0, a1, a2, a3);   \
 791         ia64_load_scratch_fpregs(fr);                   \
 792 } while (0)
 793
 794 #define PAL_CALL_PHYS(iprv,a0,a1,a2,a3) do {                    \
 795         struct ia64_fpreg fr[6];                                \
 796         ia64_save_scratch_fpregs(fr);                           \
 797         iprv = ia64_pal_call_phys_static(a0, a1, a2, a3);       \
 798         ia64_load_scratch_fpregs(fr);                           \
 799 } while (0)
 800
 801 #define PAL_CALL_PHYS_STK(iprv,a0,a1,a2,a3) do {                \
 802         struct ia64_fpreg fr[6];                                \
 803         ia64_save_scratch_fpregs(fr);                           \
 804         iprv = ia64_pal_call_phys_stacked(a0, a1, a2, a3);      \
 805         ia64_load_scratch_fpregs(fr);                           \
 806 } while (0)
 807
 808 typedef int (*ia64_pal_handler) (u64, ...);
 809 extern ia64_pal_handler ia64_pal;
 810 extern void ia64_pal_handler_init (void *);
 811
 812 extern ia64_pal_handler ia64_pal;
 813
 814 extern pal_cache_config_info_t          l0d_cache_config_info;
 815 extern pal_cache_config_info_t          l0i_cache_config_info;
 816 extern pal_cache_config_info_t          l1_cache_config_info;
 817 extern pal_cache_config_info_t          l2_cache_config_info;
 818
 819 extern pal_cache_protection_info_t      l0d_cache_protection_info;
 820 extern pal_cache_protection_info_t      l0i_cache_protection_info;
 821 extern pal_cache_protection_info_t      l1_cache_protection_info;
 822 extern pal_cache_protection_info_t      l2_cache_protection_info;
 823
 824 extern pal_cache_config_info_t          pal_cache_config_info_get(pal_cache_level_t,
 825                                                                   pal_cache_type_t);
 826
 827 extern pal_cache_protection_info_t      pal_cache_protection_info_get(pal_cache_level_t,
 828                                                                       pal_cache_type_t);
 829
 830
 831 extern void                             pal_error(int);
 832
 833
 834 /* Useful wrappers for the current list of pal procedures */
 835
 836 typedef union pal_bus_features_u {
 837         u64     pal_bus_features_val;
 838         struct {
 839                 u64     pbf_reserved1                           :       29;
 840                 u64     pbf_req_bus_parking                     :       1;
 841                 u64     pbf_bus_lock_mask                       :       1;
 842                 u64     pbf_enable_half_xfer_rate               :       1;
 843                 u64     pbf_reserved2                           :       22;
 844                 u64     pbf_disable_xaction_queueing            :       1;
 845                 u64     pbf_disable_resp_err_check              :       1;
 846                 u64     pbf_disable_berr_check                  :       1;
 847                 u64     pbf_disable_bus_req_internal_err_signal :       1;
 848                 u64     pbf_disable_bus_req_berr_signal         :       1;
 849                 u64     pbf_disable_bus_init_event_check        :       1;
 850                 u64     pbf_disable_bus_init_event_signal       :       1;
 851                 u64     pbf_disable_bus_addr_err_check          :       1;
 852                 u64     pbf_disable_bus_addr_err_signal         :       1;
 853                 u64     pbf_disable_bus_data_err_check          :       1;
 854         } pal_bus_features_s;
 855 } pal_bus_features_u_t;
 856
 857 extern void pal_bus_features_print (u64);
 858
 859 /* Provide information about configurable processor bus features */
 860 static inline s64
 861 ia64_pal_bus_get_features (pal_bus_features_u_t *features_avail,
 862                            pal_bus_features_u_t *features_status,
 863                            pal_bus_features_u_t *features_control)
 864 {
 865         struct ia64_pal_retval iprv;
 866         PAL_CALL_PHYS(iprv, PAL_BUS_GET_FEATURES, 0, 0, 0);
 867         if (features_avail)
 868                 features_avail->pal_bus_features_val = iprv.v0;
 869         if (features_status)
 870                 features_status->pal_bus_features_val = iprv.v1;
 871         if (features_control)
 872                 features_control->pal_bus_features_val = iprv.v2;
 873         return iprv.status;
 874 }
 875
 876 /* Enables/disables specific processor bus features */
 877 static inline s64
 878 ia64_pal_bus_set_features (pal_bus_features_u_t feature_select)
 879 {
 880         struct ia64_pal_retval iprv;
 881         PAL_CALL_PHYS(iprv, PAL_BUS_SET_FEATURES, feature_select.pal_bus_features_val, 0, 0);
 882         return iprv.status;
 883 }
 884
 885 /* Get detailed cache information */
 886 static inline s64
 887 ia64_pal_cache_config_info (u64 cache_level, u64 cache_type, pal_cache_config_info_t *conf)
 888 {
 889         struct ia64_pal_retval iprv;
 890
 891         PAL_CALL(iprv, PAL_CACHE_INFO, cache_level, cache_type, 0);
 892
 893         if (iprv.status == 0) {
 894                 conf->pcci_status                 = iprv.status;
 895                 conf->pcci_info_1.pcci1_data      = iprv.v0;
 896                 conf->pcci_info_2.pcci2_data      = iprv.v1;
 897                 conf->pcci_reserved               = iprv.v2;
 898         }
 899         return iprv.status;
 900
 901 }
 902
 903 /* Get detailed cche protection information */
 904 static inline s64
 905 ia64_pal_cache_prot_info (u64 cache_level, u64 cache_type, pal_cache_protection_info_t *prot)
 906 {
 907         struct ia64_pal_retval iprv;
 908
 909         PAL_CALL(iprv, PAL_CACHE_PROT_INFO, cache_level, cache_type, 0);
 910
 911         if (iprv.status == 0) {
 912                 prot->pcpi_status           = iprv.status;
 913                 prot->pcp_info[0].pcpi_data = iprv.v0 & 0xffffffff;
 914                 prot->pcp_info[1].pcpi_data = iprv.v0 >> 32;
 915                 prot->pcp_info[2].pcpi_data = iprv.v1 & 0xffffffff;
 916                 prot->pcp_info[3].pcpi_data = iprv.v1 >> 32;
 917                 prot->pcp_info[4].pcpi_data = iprv.v2 & 0xffffffff;
 918                 prot->pcp_info[5].pcpi_data = iprv.v2 >> 32;
 919         }
 920         return iprv.status;
 921 }
 922
 923 /*
 924  * Flush the processor instruction or data caches.  *PROGRESS must be
 925  * initialized to zero before calling this for the first time..
 926  */
 927 static inline s64
 928 ia64_pal_cache_flush (u64 cache_type, u64 invalidate, u64 *progress, u64 *vector)
 929 {
 930         struct ia64_pal_retval iprv;
 931         PAL_CALL(iprv, PAL_CACHE_FLUSH, cache_type, invalidate, *progress);
 932         if (vector)
 933                 *vector = iprv.v0;
 934         *progress = iprv.v1;
 935         return iprv.status;
 936 }
 937
 938
 939 /* Initialize the processor controlled caches */
 940 static inline s64
 941 ia64_pal_cache_init (u64 level, u64 cache_type, u64 rest)
 942 {
 943         struct ia64_pal_retval iprv;
 944         PAL_CALL(iprv, PAL_CACHE_INIT, level, cache_type, rest);
 945         return iprv.status;
 946 }
 947
 948 /* Initialize the tags and data of a data or unified cache line of
 949  * processor controlled cache to known values without the availability
 950  * of backing memory.
 951  */
 952 static inline s64
 953 ia64_pal_cache_line_init (u64 physical_addr, u64 data_value)
 954 {
 955         struct ia64_pal_retval iprv;
 956         PAL_CALL(iprv, PAL_CACHE_LINE_INIT, physical_addr, data_value, 0);
 957         return iprv.status;
 958 }
 959
 960
 961 /* Read the data and tag of a processor controlled cache line for diags */
 962 static inline s64
 963 ia64_pal_cache_read (pal_cache_line_id_u_t line_id, u64 physical_addr)
 964 {
 965         struct ia64_pal_retval iprv;
 966         PAL_CALL(iprv, PAL_CACHE_READ, line_id.pclid_data, physical_addr, 0);
 967         return iprv.status;
 968 }
 969
 970 /* Return summary information about the heirarchy of caches controlled by the processor */
 971 static inline s64
 972 ia64_pal_cache_summary (u64 *cache_levels, u64 *unique_caches)
 973 {
 974         struct ia64_pal_retval iprv;
 975         PAL_CALL(iprv, PAL_CACHE_SUMMARY, 0, 0, 0);
 976         if (cache_levels)
 977                 *cache_levels = iprv.v0;
 978         if (unique_caches)
 979                 *unique_caches = iprv.v1;
 980         return iprv.status;
 981 }
 982
 983 /* Write the data and tag of a processor-controlled cache line for diags */
 984 static inline s64
 985 ia64_pal_cache_write (pal_cache_line_id_u_t line_id, u64 physical_addr, u64 data)
 986 {
 987         struct ia64_pal_retval iprv;
 988         PAL_CALL(iprv, PAL_CACHE_WRITE, line_id.pclid_data, physical_addr, data);
 989         return iprv.status;
 990 }
 991
 992
 993 /* Return the parameters needed to copy relocatable PAL procedures from ROM to memory */
 994 static inline s64
 995 ia64_pal_copy_info (u64 copy_type, u64 num_procs, u64 num_iopics,
 996                     u64 *buffer_size, u64 *buffer_align)
 997 {
 998         struct ia64_pal_retval iprv;
 999         PAL_CALL(iprv, PAL_COPY_INFO, copy_type, num_procs, num_iopics);
1000         if (buffer_size)
1001                 *buffer_size = iprv.v0;
1002         if (buffer_align)
1003                 *buffer_align = iprv.v1;
1004         return iprv.status;
1005 }
1006
1007 /* Copy relocatable PAL procedures from ROM to memory */
1008 static inline s64
1009 ia64_pal_copy_pal (u64 target_addr, u64 alloc_size, u64 processor, u64 *pal_proc_offset)
1010 {
1011         struct ia64_pal_retval iprv;
1012         PAL_CALL(iprv, PAL_COPY_PAL, target_addr, alloc_size, processor);
1013         if (pal_proc_offset)
1014                 *pal_proc_offset = iprv.v0;
1015         return iprv.status;
1016 }
1017
1018 /* Return the number of instruction and data debug register pairs */
1019 static inline s64
1020 ia64_pal_debug_info (u64 *inst_regs,  u64 *data_regs)
1021 {
1022         struct ia64_pal_retval iprv;
1023         PAL_CALL(iprv, PAL_DEBUG_INFO, 0, 0, 0);
1024         if (inst_regs)
1025                 *inst_regs = iprv.v0;
1026         if (data_regs)
1027                 *data_regs = iprv.v1;
1028
1029         return iprv.status;
1030 }
1031
1032 #ifdef TBD
1033 /* Switch from IA64-system environment to IA-32 system environment */
1034 static inline s64
1035 ia64_pal_enter_ia32_env (ia32_env1, ia32_env2, ia32_env3)
1036 {
1037         struct ia64_pal_retval iprv;
1038         PAL_CALL(iprv, PAL_ENTER_IA_32_ENV, ia32_env1, ia32_env2, ia32_env3);
1039         return iprv.status;
1040 }
1041 #endif
1042
1043 /* Get unique geographical address of this processor on its bus */
1044 static inline s64
1045 ia64_pal_fixed_addr (u64 *global_unique_addr)
1046 {
1047         struct ia64_pal_retval iprv;
1048         PAL_CALL(iprv, PAL_FIXED_ADDR, 0, 0, 0);
1049         if (global_unique_addr)
1050                 *global_unique_addr = iprv.v0;
1051         return iprv.status;
1052 }
1053
1054 /* Get base frequency of the platform if generated by the processor */
1055 static inline s64
1056 ia64_pal_freq_base (u64 *platform_base_freq)
1057 {
1058         struct ia64_pal_retval iprv;
1059         PAL_CALL(iprv, PAL_FREQ_BASE, 0, 0, 0);
1060         if (platform_base_freq)
1061                 *platform_base_freq = iprv.v0;
1062         return iprv.status;
1063 }
1064
1065 /*
1066  * Get the ratios for processor frequency, bus frequency and interval timer to
1067  * to base frequency of the platform
1068  */
1069 static inline s64
1070 ia64_pal_freq_ratios (struct pal_freq_ratio *proc_ratio, struct pal_freq_ratio *bus_ratio,
1071                       struct pal_freq_ratio *itc_ratio)
1072 {
1073         struct ia64_pal_retval iprv;
1074         PAL_CALL(iprv, PAL_FREQ_RATIOS, 0, 0, 0);
1075         if (proc_ratio)
1076                 *(u64 *)proc_ratio = iprv.v0;
1077         if (bus_ratio)
1078                 *(u64 *)bus_ratio = iprv.v1;
1079         if (itc_ratio)
1080                 *(u64 *)itc_ratio = iprv.v2;
1081         return iprv.status;
1082 }
1083
1084 /* Make the processor enter HALT or one of the implementation dependent low
1085  * power states where prefetching and execution are suspended and cache and
1086  * TLB coherency is not maintained.
1087  */
1088 static inline s64
1089 ia64_pal_halt (u64 halt_state)
1090 {
1091         struct ia64_pal_retval iprv;
1092         PAL_CALL(iprv, PAL_HALT, halt_state, 0, 0);
1093         return iprv.status;
1094 }
1095
1096 typedef union pal_power_mgmt_info_u {
1097         u64                     ppmi_data;
1098         struct {
1099                u64              exit_latency            : 16,
1100                                 entry_latency           : 16,
1101                                 power_consumption       : 28,
1102                                 im                      : 1,
1103                                 co                      : 1,
1104                                 reserved                : 2;
1105         } pal_power_mgmt_info_s;
1106 } pal_power_mgmt_info_u_t;
1107
1108 /* Return information about processor's optional power management capabilities. */
1109 static inline s64
1110 ia64_pal_halt_info (pal_power_mgmt_info_u_t *power_buf)
1111 {
1112         struct ia64_pal_retval iprv;
1113         PAL_CALL_STK(iprv, PAL_HALT_INFO, (unsigned long) power_buf, 0, 0);
1114         return iprv.status;
1115 }
1116
1117 /* Get the current P-state information */
1118 static inline s64
1119 ia64_pal_get_pstate (u64 *pstate_index)
1120 {
1121         struct ia64_pal_retval iprv;
1122         PAL_CALL_STK(iprv, PAL_GET_PSTATE, 0, 0, 0);
1123         *pstate_index = iprv.v0;
1124         return iprv.status;
1125 }
1126
1127 /* Set the P-state */
1128 static inline s64
1129 ia64_pal_set_pstate (u64 pstate_index)
1130 {
1131         struct ia64_pal_retval iprv;
1132         PAL_CALL_STK(iprv, PAL_SET_PSTATE, pstate_index, 0, 0);
1133         return iprv.status;
1134 }
1135
1136 /* Cause the processor to enter LIGHT HALT state, where prefetching and execution are
1137  * suspended, but cache and TLB coherency is maintained.
1138  */
1139 static inline s64
1140 ia64_pal_halt_light (void)
1141 {
1142         struct ia64_pal_retval iprv;
1143         PAL_CALL(iprv, PAL_HALT_LIGHT, 0, 0, 0);
1144         return iprv.status;
1145 }
1146
1147 /* Clear all the processor error logging   registers and reset the indicator that allows
1148  * the error logging registers to be written. This procedure also checks the pending
1149  * machine check bit and pending INIT bit and reports their states.
1150  */
1151 static inline s64
1152 ia64_pal_mc_clear_log (u64 *pending_vector)
1153 {
1154         struct ia64_pal_retval iprv;
1155         PAL_CALL(iprv, PAL_MC_CLEAR_LOG, 0, 0, 0);
1156         if (pending_vector)
1157                 *pending_vector = iprv.v0;
1158         return iprv.status;
1159 }
1160
1161 /* Ensure that all outstanding transactions in a processor are completed or that any
1162  * MCA due to thes outstanding transaction is taken.
1163  */
1164 static inline s64
1165 ia64_pal_mc_drain (void)
1166 {
1167         struct ia64_pal_retval iprv;
1168         PAL_CALL(iprv, PAL_MC_DRAIN, 0, 0, 0);
1169         return iprv.status;
1170 }
1171
1172 /* Return the machine check dynamic processor state */
1173 static inline s64
1174 ia64_pal_mc_dynamic_state (u64 offset, u64 *size, u64 *pds)
1175 {
1176         struct ia64_pal_retval iprv;
1177         PAL_CALL(iprv, PAL_MC_DYNAMIC_STATE, offset, 0, 0);
1178         if (size)
1179                 *size = iprv.v0;
1180         if (pds)
1181                 *pds = iprv.v1;
1182         return iprv.status;
1183 }
1184
1185 /* Return processor machine check information */
1186 static inline s64
1187 ia64_pal_mc_error_info (u64 info_index, u64 type_index, u64 *size, u64 *error_info)
1188 {
1189         struct ia64_pal_retval iprv;
1190         PAL_CALL(iprv, PAL_MC_ERROR_INFO, info_index, type_index, 0);
1191         if (size)
1192                 *size = iprv.v0;
1193         if (error_info)
1194                 *error_info = iprv.v1;
1195         return iprv.status;
1196 }
1197
1198 /* Inform PALE_CHECK whether a machine check is expected so that PALE_CHECK willnot
1199  * attempt to correct any expected machine checks.
1200  */
1201 static inline s64
1202 ia64_pal_mc_expected (u64 expected, u64 *previous)
1203 {
1204         struct ia64_pal_retval iprv;
1205         PAL_CALL(iprv, PAL_MC_EXPECTED, expected, 0, 0);
1206         if (previous)
1207                 *previous = iprv.v0;
1208         return iprv.status;
1209 }
1210
1211 /* Register a platform dependent location with PAL to which it can save
1212  * minimal processor state in the event of a machine check or initialization
1213  * event.
1214  */
1215 static inline s64
1216 ia64_pal_mc_register_mem (u64 physical_addr)
1217 {
1218         struct ia64_pal_retval iprv;
1219         PAL_CALL(iprv, PAL_MC_REGISTER_MEM, physical_addr, 0, 0);
1220         return iprv.status;
1221 }
1222
1223 /* Restore minimal architectural processor state, set CMC interrupt if necessary
1224  * and resume execution
1225  */
1226 static inline s64
1227 ia64_pal_mc_resume (u64 set_cmci, u64 save_ptr)
1228 {
1229         struct ia64_pal_retval iprv;
1230         PAL_CALL(iprv, PAL_MC_RESUME, set_cmci, save_ptr, 0);
1231         return iprv.status;
1232 }
1233
1234 /* Return the memory attributes implemented by the processor */
1235 static inline s64
1236 ia64_pal_mem_attrib (u64 *mem_attrib)
1237 {
1238         struct ia64_pal_retval iprv;
1239         PAL_CALL(iprv, PAL_MEM_ATTRIB, 0, 0, 0);
1240         if (mem_attrib)
1241                 *mem_attrib = iprv.v0 & 0xff;
1242         return iprv.status;
1243 }
1244
1245 /* Return the amount of memory needed for second phase of processor
1246  * self-test and the required alignment of memory.
1247  */
1248 static inline s64
1249 ia64_pal_mem_for_test (u64 *bytes_needed, u64 *alignment)
1250 {
1251         struct ia64_pal_retval iprv;
1252         PAL_CALL(iprv, PAL_MEM_FOR_TEST, 0, 0, 0);
1253         if (bytes_needed)
1254                 *bytes_needed = iprv.v0;
1255         if (alignment)
1256                 *alignment = iprv.v1;
1257         return iprv.status;
1258 }
1259
1260 typedef union pal_perf_mon_info_u {
1261         u64                       ppmi_data;
1262         struct {
1263                u64              generic         : 8,
1264                                 width           : 8,
1265                                 cycles          : 8,
1266                                 retired         : 8,
1267                                 reserved        : 32;
1268         } pal_perf_mon_info_s;
1269 } pal_perf_mon_info_u_t;
1270
1271 /* Return the performance monitor information about what can be counted
1272  * and how to configure the monitors to count the desired events.
1273  */
1274 static inline s64
1275 ia64_pal_perf_mon_info (u64 *pm_buffer, pal_perf_mon_info_u_t *pm_info)
1276 {
1277         struct ia64_pal_retval iprv;
1278         PAL_CALL(iprv, PAL_PERF_MON_INFO, (unsigned long) pm_buffer, 0, 0);
1279         if (pm_info)
1280                 pm_info->ppmi_data = iprv.v0;
1281         return iprv.status;
1282 }
1283
1284 /* Specifies the physical address of the processor interrupt block
1285  * and I/O port space.
1286  */
1287 static inline s64
1288 ia64_pal_platform_addr (u64 type, u64 physical_addr)
1289 {
1290         struct ia64_pal_retval iprv;
1291         PAL_CALL(iprv, PAL_PLATFORM_ADDR, type, physical_addr, 0);
1292         return iprv.status;
1293 }
1294
1295 /* Set the SAL PMI entrypoint in memory */
1296 static inline s64
1297 ia64_pal_pmi_entrypoint (u64 sal_pmi_entry_addr)
1298 {
1299         struct ia64_pal_retval iprv;
1300         PAL_CALL(iprv, PAL_PMI_ENTRYPOINT, sal_pmi_entry_addr, 0, 0);
1301         return iprv.status;
1302 }
1303
1304 struct pal_features_s;
1305 /* Provide information about configurable processor features */
1306 static inline s64
1307 ia64_pal_proc_get_features (u64 *features_avail,
1308                             u64 *features_status,
1309                             u64 *features_control)
1310 {
1311         struct ia64_pal_retval iprv;
1312         PAL_CALL_PHYS(iprv, PAL_PROC_GET_FEATURES, 0, 0, 0);
1313         if (iprv.status == 0) {
1314                 *features_avail   = iprv.v0;
1315                 *features_status  = iprv.v1;
1316                 *features_control = iprv.v2;
1317         }
1318         return iprv.status;
1319 }
1320
1321 /* Enable/disable processor dependent features */
1322 static inline s64
1323 ia64_pal_proc_set_features (u64 feature_select)
1324 {
1325         struct ia64_pal_retval iprv;
1326         PAL_CALL_PHYS(iprv, PAL_PROC_SET_FEATURES, feature_select, 0, 0);
1327         return iprv.status;
1328 }
1329
1330 /*
1331  * Put everything in a struct so we avoid the global offset table whenever
1332  * possible.
1333  */
1334 typedef struct ia64_ptce_info_s {
1335         u64             base;
1336         u32             count[2];
1337         u32             stride[2];
1338 } ia64_ptce_info_t;
1339
1340 /* Return the information required for the architected loop used to purge
1341  * (initialize) the entire TC
1342  */
1343 static inline s64
1344 ia64_get_ptce (ia64_ptce_info_t *ptce)
1345 {
1346         struct ia64_pal_retval iprv;
1347
1348         if (!ptce)
1349                 return -1;
1350
1351         PAL_CALL(iprv, PAL_PTCE_INFO, 0, 0, 0);
1352         if (iprv.status == 0) {
1353                 ptce->base = iprv.v0;
1354                 ptce->count[0] = iprv.v1 >> 32;
1355                 ptce->count[1] = iprv.v1 & 0xffffffff;
1356                 ptce->stride[0] = iprv.v2 >> 32;
1357                 ptce->stride[1] = iprv.v2 & 0xffffffff;
1358         }
1359         return iprv.status;
1360 }
1361
1362 /* Return info about implemented application and control registers. */
1363 static inline s64
1364 ia64_pal_register_info (u64 info_request, u64 *reg_info_1, u64 *reg_info_2)
1365 {
1366         struct ia64_pal_retval iprv;
1367         PAL_CALL(iprv, PAL_REGISTER_INFO, info_request, 0, 0);
1368         if (reg_info_1)
1369                 *reg_info_1 = iprv.v0;
1370         if (reg_info_2)
1371                 *reg_info_2 = iprv.v1;
1372         return iprv.status;
1373 }
1374
1375 typedef union pal_hints_u {
1376         u64                     ph_data;
1377         struct {
1378                u64              si              : 1,
1379                                 li              : 1,
1380                                 reserved        : 62;
1381         } pal_hints_s;
1382 } pal_hints_u_t;
1383
1384 /* Return information about the register stack and RSE for this processor
1385  * implementation.
1386  */
1387 static inline s64
1388 ia64_pal_rse_info (u64 *num_phys_stacked, pal_hints_u_t *hints)
1389 {
1390         struct ia64_pal_retval iprv;
1391         PAL_CALL(iprv, PAL_RSE_INFO, 0, 0, 0);
1392         if (num_phys_stacked)
1393                 *num_phys_stacked = iprv.v0;
1394         if (hints)
1395                 hints->ph_data = iprv.v1;
1396         return iprv.status;
1397 }
1398
1399 /* Cause the processor to enter SHUTDOWN state, where prefetching and execution are
1400  * suspended, but cause cache and TLB coherency to be maintained.
1401  * This is usually called in IA-32 mode.
1402  */
1403 static inline s64
1404 ia64_pal_shutdown (void)
1405 {
1406         struct ia64_pal_retval iprv;
1407         PAL_CALL(iprv, PAL_SHUTDOWN, 0, 0, 0);
1408         return iprv.status;
1409 }
1410
1411 /* Perform the second phase of processor self-test. */
1412 static inline s64
1413 ia64_pal_test_proc (u64 test_addr, u64 test_size, u64 attributes, u64 *self_test_state)
1414 {
1415         struct ia64_pal_retval iprv;
1416         PAL_CALL(iprv, PAL_TEST_PROC, test_addr, test_size, attributes);
1417         if (self_test_state)
1418                 *self_test_state = iprv.v0;
1419         return iprv.status;
1420 }
1421
1422 typedef union  pal_version_u {
1423         u64     pal_version_val;
1424         struct {
1425                 u64     pv_pal_b_rev            :       8;
1426                 u64     pv_pal_b_model          :       8;
1427                 u64     pv_reserved1            :       8;
1428                 u64     pv_pal_vendor           :       8;
1429                 u64     pv_pal_a_rev            :       8;
1430                 u64     pv_pal_a_model          :       8;
1431                 u64     pv_reserved2            :       16;
1432         } pal_version_s;
1433 } pal_version_u_t;
1434
1435
1436 /* Return PAL version information */
1437 static inline s64
1438 ia64_pal_version (pal_version_u_t *pal_min_version, pal_version_u_t *pal_cur_version)
1439 {
1440         struct ia64_pal_retval iprv;
1441         PAL_CALL_PHYS(iprv, PAL_VERSION, 0, 0, 0);
1442         if (pal_min_version)
1443                 pal_min_version->pal_version_val = iprv.v0;
1444
1445         if (pal_cur_version)
1446                 pal_cur_version->pal_version_val = iprv.v1;
1447
1448         return iprv.status;
1449 }
1450
1451 typedef union pal_tc_info_u {
1452         u64                     pti_val;
1453         struct {
1454                u64              num_sets        :       8,
1455                                 associativity   :       8,
1456                                 num_entries     :       16,
1457                                 pf              :       1,
1458                                 unified         :       1,
1459                                 reduce_tr       :       1,
1460                                 reserved        :       29;
1461         } pal_tc_info_s;
1462 } pal_tc_info_u_t;
1463
1464 #define tc_reduce_tr            pal_tc_info_s.reduce_tr
1465 #define tc_unified              pal_tc_info_s.unified
1466 #define tc_pf                   pal_tc_info_s.pf
1467 #define tc_num_entries          pal_tc_info_s.num_entries
1468 #define tc_associativity        pal_tc_info_s.associativity
1469 #define tc_num_sets             pal_tc_info_s.num_sets
1470
1471
1472 /* Return information about the virtual memory characteristics of the processor
1473  * implementation.
1474  */
1475 static inline s64
1476 ia64_pal_vm_info (u64 tc_level, u64 tc_type,  pal_tc_info_u_t *tc_info, u64 *tc_pages)
1477 {
1478         struct ia64_pal_retval iprv;
1479         PAL_CALL(iprv, PAL_VM_INFO, tc_level, tc_type, 0);
1480         if (tc_info)
1481                 tc_info->pti_val = iprv.v0;
1482         if (tc_pages)
1483                 *tc_pages = iprv.v1;
1484         return iprv.status;
1485 }
1486
1487 /* Get page size information about the virtual memory characteristics of the processor
1488  * implementation.
1489  */
1490 static inline s64
1491 ia64_pal_vm_page_size (u64 *tr_pages, u64 *vw_pages)
1492 {
1493         struct ia64_pal_retval iprv;
1494         PAL_CALL(iprv, PAL_VM_PAGE_SIZE, 0, 0, 0);
1495         if (tr_pages)
1496                 *tr_pages = iprv.v0;
1497         if (vw_pages)
1498                 *vw_pages = iprv.v1;
1499         return iprv.status;
1500 }
1501
1502 typedef union pal_vm_info_1_u {
1503         u64                     pvi1_val;
1504         struct {
1505                 u64             vw              : 1,
1506                                 phys_add_size   : 7,
1507                                 key_size        : 8,
1508                                 max_pkr         : 8,
1509                                 hash_tag_id     : 8,
1510                                 max_dtr_entry   : 8,
1511                                 max_itr_entry   : 8,
1512                                 max_unique_tcs  : 8,
1513                                 num_tc_levels   : 8;
1514         } pal_vm_info_1_s;
1515 } pal_vm_info_1_u_t;
1516
1517 typedef union pal_vm_info_2_u {
1518         u64                     pvi2_val;
1519         struct {
1520                 u64             impl_va_msb     : 8,
1521                                 rid_size        : 8,
1522                                 reserved        : 48;
1523         } pal_vm_info_2_s;
1524 } pal_vm_info_2_u_t;
1525
1526 /* Get summary information about the virtual memory characteristics of the processor
1527  * implementation.
1528  */
1529 static inline s64
1530 ia64_pal_vm_summary (pal_vm_info_1_u_t *vm_info_1, pal_vm_info_2_u_t *vm_info_2)
1531 {
1532         struct ia64_pal_retval iprv;
1533         PAL_CALL(iprv, PAL_VM_SUMMARY, 0, 0, 0);
1534         if (vm_info_1)
1535                 vm_info_1->pvi1_val = iprv.v0;
1536         if (vm_info_2)
1537                 vm_info_2->pvi2_val = iprv.v1;
1538         return iprv.status;
1539 }
1540
1541 typedef union pal_itr_valid_u {
1542         u64                     piv_val;
1543         struct {
1544                u64              access_rights_valid     : 1,
1545                                 priv_level_valid        : 1,
1546                                 dirty_bit_valid         : 1,
1547                                 mem_attr_valid          : 1,
1548                                 reserved                : 60;
1549         } pal_tr_valid_s;
1550 } pal_tr_valid_u_t;
1551
1552 /* Read a translation register */
1553 static inline s64
1554 ia64_pal_tr_read (u64 reg_num, u64 tr_type, u64 *tr_buffer, pal_tr_valid_u_t *tr_valid)
1555 {
1556         struct ia64_pal_retval iprv;
1557         PAL_CALL_PHYS_STK(iprv, PAL_VM_TR_READ, reg_num, tr_type,(u64)ia64_tpa(tr_buffer));
1558         if (tr_valid)
1559                 tr_valid->piv_val = iprv.v0;
1560         return iprv.status;
1561 }
1562
1563 /*
1564  * PAL_PREFETCH_VISIBILITY transaction types
1565  */
1566 #define PAL_VISIBILITY_VIRTUAL          0
1567 #define PAL_VISIBILITY_PHYSICAL         1
1568
1569 /*
1570  * PAL_PREFETCH_VISIBILITY return codes
1571  */
1572 #define PAL_VISIBILITY_OK               1
1573 #define PAL_VISIBILITY_OK_REMOTE_NEEDED 0
1574 #define PAL_VISIBILITY_INVAL_ARG        -2
1575 #define PAL_VISIBILITY_ERROR            -3
1576
1577 static inline s64
1578 ia64_pal_prefetch_visibility (s64 trans_type)
1579 {
1580         struct ia64_pal_retval iprv;
1581         PAL_CALL(iprv, PAL_PREFETCH_VISIBILITY, trans_type, 0, 0);
1582         return iprv.status;
1583 }
1584
1585 /* data structure for getting information on logical to physical mappings */
1586 typedef union pal_log_overview_u {
1587         struct {
1588                 u64     num_log         :16,    /* Total number of logical
1589                                                  * processors on this die
1590                                                  */
1591                         tpc             :8,     /* Threads per core */
1592                         reserved3       :8,     /* Reserved */
1593                         cpp             :8,     /* Cores per processor */
1594                         reserved2       :8,     /* Reserved */
1595                         ppid            :8,     /* Physical processor ID */
1596                         reserved1       :8;     /* Reserved */
1597         } overview_bits;
1598         u64 overview_data;
1599 } pal_log_overview_t;
1600
1601 typedef union pal_proc_n_log_info1_u{
1602         struct {
1603                 u64     tid             :16,    /* Thread id */
1604                         reserved2       :16,    /* Reserved */
1605                         cid             :16,    /* Core id */
1606                         reserved1       :16;    /* Reserved */
1607         } ppli1_bits;
1608         u64     ppli1_data;
1609 } pal_proc_n_log_info1_t;
1610
1611 typedef union pal_proc_n_log_info2_u {
1612         struct {
1613                 u64     la              :16,    /* Logical address */
1614                         reserved        :48;    /* Reserved */
1615         } ppli2_bits;
1616         u64     ppli2_data;
1617 } pal_proc_n_log_info2_t;
1618
1619 typedef struct pal_logical_to_physical_s
1620 {
1621         pal_log_overview_t overview;
1622         pal_proc_n_log_info1_t ppli1;
1623         pal_proc_n_log_info2_t ppli2;
1624 } pal_logical_to_physical_t;
1625
1626 #define overview_num_log        overview.overview_bits.num_log
1627 #define overview_tpc            overview.overview_bits.tpc
1628 #define overview_cpp            overview.overview_bits.cpp
1629 #define overview_ppid           overview.overview_bits.ppid
1630 #define log1_tid                ppli1.ppli1_bits.tid
1631 #define log1_cid                ppli1.ppli1_bits.cid
1632 #define log2_la                 ppli2.ppli2_bits.la
1633
1634 /* Get information on logical to physical processor mappings. */
1635 static inline s64
1636 ia64_pal_logical_to_phys(u64 proc_number, pal_logical_to_physical_t *mapping)
1637 {
1638         struct ia64_pal_retval iprv;
1639
1640         PAL_CALL(iprv, PAL_LOGICAL_TO_PHYSICAL, proc_number, 0, 0);
1641
1642         if (iprv.status == PAL_STATUS_SUCCESS)
1643         {
1644                 mapping->overview.overview_data = iprv.v0;
1645                 mapping->ppli1.ppli1_data = iprv.v1;
1646                 mapping->ppli2.ppli2_data = iprv.v2;
1647         }
1648
1649         return iprv.status;
1650 }
1651
1652 typedef struct pal_cache_shared_info_s
1653 {
1654         u64 num_shared;
1655         pal_proc_n_log_info1_t ppli1;
1656         pal_proc_n_log_info2_t ppli2;
1657 } pal_cache_shared_info_t;
1658
1659 /* Get information on logical to physical processor mappings. */
1660 static inline s64
1661 ia64_pal_cache_shared_info(u64 level,
1662                 u64 type,
1663                 u64 proc_number,
1664                 pal_cache_shared_info_t *info)
1665 {
1666         struct ia64_pal_retval iprv;
1667
1668         PAL_CALL(iprv, PAL_CACHE_SHARED_INFO, level, type, proc_number);
1669
1670         if (iprv.status == PAL_STATUS_SUCCESS) {
1671                 info->num_shared = iprv.v0;
1672                 info->ppli1.ppli1_data = iprv.v1;
1673                 info->ppli2.ppli2_data = iprv.v2;
1674         }
1675
1676         return iprv.status;
1677 }
1678 #endif /* __ASSEMBLY__ */
1679
1680 #endif /* _ASM_IA64_PAL_H */