Merge branch 'merge'
[linux-2.6] / arch / powerpc / platforms / 85xx / mpc85xx_ads.c
1 /*
2  * MPC85xx setup and early boot code plus other random bits.
3  *
4  * Maintained by Kumar Gala (see MAINTAINERS for contact information)
5  *
6  * Copyright 2005 Freescale Semiconductor Inc.
7  *
8  * This program is free software; you can redistribute  it and/or modify it
9  * under  the terms of  the GNU General  Public License as published by the
10  * Free Software Foundation;  either version 2 of the  License, or (at your
11  * option) any later version.
12  */
13
14 #include <linux/stddef.h>
15 #include <linux/kernel.h>
16 #include <linux/pci.h>
17 #include <linux/kdev_t.h>
18 #include <linux/delay.h>
19 #include <linux/seq_file.h>
20 #include <linux/root_dev.h>
21
22 #include <asm/system.h>
23 #include <asm/time.h>
24 #include <asm/machdep.h>
25 #include <asm/pci-bridge.h>
26 #include <asm/mpc85xx.h>
27 #include <asm/prom.h>
28 #include <asm/mpic.h>
29 #include <mm/mmu_decl.h>
30 #include <asm/udbg.h>
31
32 #include <sysdev/fsl_soc.h>
33 #include "mpc85xx.h"
34
35 #ifndef CONFIG_PCI
36 unsigned long isa_io_base = 0;
37 unsigned long isa_mem_base = 0;
38 #endif
39
40 /*
41  * Internal interrupts are all Level Sensitive, and Positive Polarity
42  *
43  * Note:  Likely, this table and the following function should be
44  *        obtained and derived from the OF Device Tree.
45  */
46 static u_char mpc85xx_ads_openpic_initsenses[] __initdata = {
47         MPC85XX_INTERNAL_IRQ_SENSES,
48         0x0,                    /* External  0: */
49 #if defined(CONFIG_PCI)
50         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* Ext 1: PCI slot 0 */
51         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* Ext 2: PCI slot 1 */
52         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* Ext 3: PCI slot 2 */
53         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* Ext 4: PCI slot 3 */
54 #else
55         0x0,                    /* External  1: */
56         0x0,                    /* External  2: */
57         0x0,                    /* External  3: */
58         0x0,                    /* External  4: */
59 #endif
60         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* External 5: PHY */
61         0x0,                    /* External  6: */
62         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* External 7: PHY */
63         0x0,                    /* External  8: */
64         0x0,                    /* External  9: */
65         0x0,                    /* External 10: */
66         0x0,                    /* External 11: */
67 };
68
69 #ifdef CONFIG_PCI
70 /*
71  * interrupt routing
72  */
73
74 int
75 mpc85xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
76 {
77         static char pci_irq_table[][4] =
78             /*
79              * This is little evil, but works around the fact
80              * that revA boards have IDSEL starting at 18
81              * and others boards (older) start at 12
82              *
83              *      PCI IDSEL/INTPIN->INTLINE
84              *       A      B      C      D
85              */
86         {
87                 {PIRQA, PIRQB, PIRQC, PIRQD},   /* IDSEL 2 */
88                 {PIRQD, PIRQA, PIRQB, PIRQC},
89                 {PIRQC, PIRQD, PIRQA, PIRQB},
90                 {PIRQB, PIRQC, PIRQD, PIRQA},   /* IDSEL 5 */
91                 {0, 0, 0, 0},   /* -- */
92                 {0, 0, 0, 0},   /* -- */
93                 {0, 0, 0, 0},   /* -- */
94                 {0, 0, 0, 0},   /* -- */
95                 {0, 0, 0, 0},   /* -- */
96                 {0, 0, 0, 0},   /* -- */
97                 {PIRQA, PIRQB, PIRQC, PIRQD},   /* IDSEL 12 */
98                 {PIRQD, PIRQA, PIRQB, PIRQC},
99                 {PIRQC, PIRQD, PIRQA, PIRQB},
100                 {PIRQB, PIRQC, PIRQD, PIRQA},   /* IDSEL 15 */
101                 {0, 0, 0, 0},   /* -- */
102                 {0, 0, 0, 0},   /* -- */
103                 {PIRQA, PIRQB, PIRQC, PIRQD},   /* IDSEL 18 */
104                 {PIRQD, PIRQA, PIRQB, PIRQC},
105                 {PIRQC, PIRQD, PIRQA, PIRQB},
106                 {PIRQB, PIRQC, PIRQD, PIRQA},   /* IDSEL 21 */
107         };
108
109         const long min_idsel = 2, max_idsel = 21, irqs_per_slot = 4;
110         return PCI_IRQ_TABLE_LOOKUP;
111 }
112
113 int
114 mpc85xx_exclude_device(u_char bus, u_char devfn)
115 {
116         if (bus == 0 && PCI_SLOT(devfn) == 0)
117                 return PCIBIOS_DEVICE_NOT_FOUND;
118         else
119                 return PCIBIOS_SUCCESSFUL;
120 }
121
122 #endif /* CONFIG_PCI */
123
124
125 void __init mpc85xx_ads_pic_init(void)
126 {
127         struct mpic *mpic1;
128         phys_addr_t OpenPIC_PAddr;
129
130         /* Determine the Physical Address of the OpenPIC regs */
131         OpenPIC_PAddr = get_immrbase() + MPC85xx_OPENPIC_OFFSET;
132
133         mpic1 = mpic_alloc(OpenPIC_PAddr,
134                            MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
135                            4, MPC85xx_OPENPIC_IRQ_OFFSET, 0, 250,
136                            mpc85xx_ads_openpic_initsenses,
137                            sizeof(mpc85xx_ads_openpic_initsenses),
138                            " OpenPIC  ");
139         BUG_ON(mpic1 == NULL);
140         mpic_assign_isu(mpic1, 0, OpenPIC_PAddr + 0x10200);
141         mpic_assign_isu(mpic1, 1, OpenPIC_PAddr + 0x10280);
142         mpic_assign_isu(mpic1, 2, OpenPIC_PAddr + 0x10300);
143         mpic_assign_isu(mpic1, 3, OpenPIC_PAddr + 0x10380);
144         mpic_assign_isu(mpic1, 4, OpenPIC_PAddr + 0x10400);
145         mpic_assign_isu(mpic1, 5, OpenPIC_PAddr + 0x10480);
146         mpic_assign_isu(mpic1, 6, OpenPIC_PAddr + 0x10500);
147         mpic_assign_isu(mpic1, 7, OpenPIC_PAddr + 0x10580);
148
149         /* dummy mappings to get to 48 */
150         mpic_assign_isu(mpic1, 8, OpenPIC_PAddr + 0x10600);
151         mpic_assign_isu(mpic1, 9, OpenPIC_PAddr + 0x10680);
152         mpic_assign_isu(mpic1, 10, OpenPIC_PAddr + 0x10700);
153         mpic_assign_isu(mpic1, 11, OpenPIC_PAddr + 0x10780);
154
155         /* External ints */
156         mpic_assign_isu(mpic1, 12, OpenPIC_PAddr + 0x10000);
157         mpic_assign_isu(mpic1, 13, OpenPIC_PAddr + 0x10080);
158         mpic_assign_isu(mpic1, 14, OpenPIC_PAddr + 0x10100);
159         mpic_init(mpic1);
160 }
161
162 /*
163  * Setup the architecture
164  */
165 static void __init mpc85xx_ads_setup_arch(void)
166 {
167         struct device_node *cpu;
168         struct device_node *np;
169
170         if (ppc_md.progress)
171                 ppc_md.progress("mpc85xx_ads_setup_arch()", 0);
172
173         cpu = of_find_node_by_type(NULL, "cpu");
174         if (cpu != 0) {
175                 const unsigned int *fp;
176
177                 fp = get_property(cpu, "clock-frequency", NULL);
178                 if (fp != 0)
179                         loops_per_jiffy = *fp / HZ;
180                 else
181                         loops_per_jiffy = 50000000 / HZ;
182                 of_node_put(cpu);
183         }
184
185 #ifdef CONFIG_PCI
186         for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;)
187                 add_bridge(np);
188
189         ppc_md.pci_swizzle = common_swizzle;
190         ppc_md.pci_map_irq = mpc85xx_map_irq;
191         ppc_md.pci_exclude_device = mpc85xx_exclude_device;
192 #endif
193
194 #ifdef  CONFIG_ROOT_NFS
195         ROOT_DEV = Root_NFS;
196 #else
197         ROOT_DEV = Root_HDA1;
198 #endif
199 }
200
201 void mpc85xx_ads_show_cpuinfo(struct seq_file *m)
202 {
203         uint pvid, svid, phid1;
204         uint memsize = total_memory;
205
206         pvid = mfspr(SPRN_PVR);
207         svid = mfspr(SPRN_SVR);
208
209         seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
210         seq_printf(m, "Machine\t\t: mpc85xx\n");
211         seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
212         seq_printf(m, "SVR\t\t: 0x%x\n", svid);
213
214         /* Display cpu Pll setting */
215         phid1 = mfspr(SPRN_HID1);
216         seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
217
218         /* Display the amount of memory */
219         seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
220 }
221
222 /*
223  * Called very early, device-tree isn't unflattened
224  */
225 static int __init mpc85xx_ads_probe(void)
226 {
227         /* We always match for now, eventually we should look at the flat
228            dev tree to ensure this is the board we are suppose to run on
229         */
230         return 1;
231 }
232
233 define_machine(mpc85xx_ads) {
234         .name                   = "MPC85xx ADS",
235         .probe                  = mpc85xx_ads_probe,
236         .setup_arch             = mpc85xx_ads_setup_arch,
237         .init_IRQ               = mpc85xx_ads_pic_init,
238         .show_cpuinfo           = mpc85xx_ads_show_cpuinfo,
239         .get_irq                = mpic_get_irq,
240         .restart                = mpc85xx_restart,
241         .calibrate_decr         = generic_calibrate_decr,
242         .progress               = udbg_progress,
243 };