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   1 /* $Id: pci_sabre.c,v 1.42 2002/01/23 11:27:32 davem Exp $
   2  * pci_sabre.c: Sabre specific PCI controller support.
   3  *
   4  * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@caipfs.rutgers.edu)
   5  * Copyright (C) 1998, 1999 Eddie C. Dost   (ecd@skynet.be)
   6  * Copyright (C) 1999 Jakub Jelinek   (jakub@redhat.com)
   7  */
   8
   9 #include <linux/kernel.h>
  10 #include <linux/types.h>
  11 #include <linux/pci.h>
  12 #include <linux/init.h>
  13 #include <linux/slab.h>
  14 #include <linux/interrupt.h>
  15
  16 #include <asm/apb.h>
  17 #include <asm/pbm.h>
  18 #include <asm/iommu.h>
  19 #include <asm/irq.h>
  20 #include <asm/smp.h>
  21 #include <asm/oplib.h>
  22 #include <asm/prom.h>
  23
  24 #include "pci_impl.h"
  25 #include "iommu_common.h"
  26
  27 /* All SABRE registers are 64-bits.  The following accessor
  28  * routines are how they are accessed.  The REG parameter
  29  * is a physical address.
  30  */
  31 #define sabre_read(__reg) \
  32 ({      u64 __ret; \
  33         __asm__ __volatile__("ldxa [%1] %2, %0" \
  34                              : "=r" (__ret) \
  35                              : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
  36                              : "memory"); \
  37         __ret; \
  38 })
  39 #define sabre_write(__reg, __val) \
  40         __asm__ __volatile__("stxa %0, [%1] %2" \
  41                              : /* no outputs */ \
  42                              : "r" (__val), "r" (__reg), \
  43                                "i" (ASI_PHYS_BYPASS_EC_E) \
  44                              : "memory")
  45
  46 /* SABRE PCI controller register offsets and definitions. */
  47 #define SABRE_UE_AFSR           0x0030UL
  48 #define  SABRE_UEAFSR_PDRD       0x4000000000000000UL   /* Primary PCI DMA Read */
  49 #define  SABRE_UEAFSR_PDWR       0x2000000000000000UL   /* Primary PCI DMA Write */
  50 #define  SABRE_UEAFSR_SDRD       0x0800000000000000UL   /* Secondary PCI DMA Read */
  51 #define  SABRE_UEAFSR_SDWR       0x0400000000000000UL   /* Secondary PCI DMA Write */
  52 #define  SABRE_UEAFSR_SDTE       0x0200000000000000UL   /* Secondary DMA Translation Error */
  53 #define  SABRE_UEAFSR_PDTE       0x0100000000000000UL   /* Primary DMA Translation Error */
  54 #define  SABRE_UEAFSR_BMSK       0x0000ffff00000000UL   /* Bytemask */
  55 #define  SABRE_UEAFSR_OFF        0x00000000e0000000UL   /* Offset (AFAR bits [5:3] */
  56 #define  SABRE_UEAFSR_BLK        0x0000000000800000UL   /* Was block operation */
  57 #define SABRE_UECE_AFAR         0x0038UL
  58 #define SABRE_CE_AFSR           0x0040UL
  59 #define  SABRE_CEAFSR_PDRD       0x4000000000000000UL   /* Primary PCI DMA Read */
  60 #define  SABRE_CEAFSR_PDWR       0x2000000000000000UL   /* Primary PCI DMA Write */
  61 #define  SABRE_CEAFSR_SDRD       0x0800000000000000UL   /* Secondary PCI DMA Read */
  62 #define  SABRE_CEAFSR_SDWR       0x0400000000000000UL   /* Secondary PCI DMA Write */
  63 #define  SABRE_CEAFSR_ESYND      0x00ff000000000000UL   /* ECC Syndrome */
  64 #define  SABRE_CEAFSR_BMSK       0x0000ffff00000000UL   /* Bytemask */
  65 #define  SABRE_CEAFSR_OFF        0x00000000e0000000UL   /* Offset */
  66 #define  SABRE_CEAFSR_BLK        0x0000000000800000UL   /* Was block operation */
  67 #define SABRE_UECE_AFAR_ALIAS   0x0048UL        /* Aliases to 0x0038 */
  68 #define SABRE_IOMMU_CONTROL     0x0200UL
  69 #define  SABRE_IOMMUCTRL_ERRSTS  0x0000000006000000UL   /* Error status bits */
  70 #define  SABRE_IOMMUCTRL_ERR     0x0000000001000000UL   /* Error present in IOTLB */
  71 #define  SABRE_IOMMUCTRL_LCKEN   0x0000000000800000UL   /* IOTLB lock enable */
  72 #define  SABRE_IOMMUCTRL_LCKPTR  0x0000000000780000UL   /* IOTLB lock pointer */
  73 #define  SABRE_IOMMUCTRL_TSBSZ   0x0000000000070000UL   /* TSB Size */
  74 #define  SABRE_IOMMU_TSBSZ_1K   0x0000000000000000
  75 #define  SABRE_IOMMU_TSBSZ_2K   0x0000000000010000
  76 #define  SABRE_IOMMU_TSBSZ_4K   0x0000000000020000
  77 #define  SABRE_IOMMU_TSBSZ_8K   0x0000000000030000
  78 #define  SABRE_IOMMU_TSBSZ_16K  0x0000000000040000
  79 #define  SABRE_IOMMU_TSBSZ_32K  0x0000000000050000
  80 #define  SABRE_IOMMU_TSBSZ_64K  0x0000000000060000
  81 #define  SABRE_IOMMU_TSBSZ_128K 0x0000000000070000
  82 #define  SABRE_IOMMUCTRL_TBWSZ   0x0000000000000004UL   /* TSB assumed page size */
  83 #define  SABRE_IOMMUCTRL_DENAB   0x0000000000000002UL   /* Diagnostic Mode Enable */
  84 #define  SABRE_IOMMUCTRL_ENAB    0x0000000000000001UL   /* IOMMU Enable */
  85 #define SABRE_IOMMU_TSBBASE     0x0208UL
  86 #define SABRE_IOMMU_FLUSH       0x0210UL
  87 #define SABRE_IMAP_A_SLOT0      0x0c00UL
  88 #define SABRE_IMAP_B_SLOT0      0x0c20UL
  89 #define SABRE_IMAP_SCSI         0x1000UL
  90 #define SABRE_IMAP_ETH          0x1008UL
  91 #define SABRE_IMAP_BPP          0x1010UL
  92 #define SABRE_IMAP_AU_REC       0x1018UL
  93 #define SABRE_IMAP_AU_PLAY      0x1020UL
  94 #define SABRE_IMAP_PFAIL        0x1028UL
  95 #define SABRE_IMAP_KMS          0x1030UL
  96 #define SABRE_IMAP_FLPY         0x1038UL
  97 #define SABRE_IMAP_SHW          0x1040UL
  98 #define SABRE_IMAP_KBD          0x1048UL
  99 #define SABRE_IMAP_MS           0x1050UL
 100 #define SABRE_IMAP_SER          0x1058UL
 101 #define SABRE_IMAP_UE           0x1070UL
 102 #define SABRE_IMAP_CE           0x1078UL
 103 #define SABRE_IMAP_PCIERR       0x1080UL
 104 #define SABRE_IMAP_GFX          0x1098UL
 105 #define SABRE_IMAP_EUPA         0x10a0UL
 106 #define SABRE_ICLR_A_SLOT0      0x1400UL
 107 #define SABRE_ICLR_B_SLOT0      0x1480UL
 108 #define SABRE_ICLR_SCSI         0x1800UL
 109 #define SABRE_ICLR_ETH          0x1808UL
 110 #define SABRE_ICLR_BPP          0x1810UL
 111 #define SABRE_ICLR_AU_REC       0x1818UL
 112 #define SABRE_ICLR_AU_PLAY      0x1820UL
 113 #define SABRE_ICLR_PFAIL        0x1828UL
 114 #define SABRE_ICLR_KMS          0x1830UL
 115 #define SABRE_ICLR_FLPY         0x1838UL
 116 #define SABRE_ICLR_SHW          0x1840UL
 117 #define SABRE_ICLR_KBD          0x1848UL
 118 #define SABRE_ICLR_MS           0x1850UL
 119 #define SABRE_ICLR_SER          0x1858UL
 120 #define SABRE_ICLR_UE           0x1870UL
 121 #define SABRE_ICLR_CE           0x1878UL
 122 #define SABRE_ICLR_PCIERR       0x1880UL
 123 #define SABRE_WRSYNC            0x1c20UL
 124 #define SABRE_PCICTRL           0x2000UL
 125 #define  SABRE_PCICTRL_MRLEN     0x0000001000000000UL   /* Use MemoryReadLine for block loads/stores */
 126 #define  SABRE_PCICTRL_SERR      0x0000000400000000UL   /* Set when SERR asserted on PCI bus */
 127 #define  SABRE_PCICTRL_ARBPARK   0x0000000000200000UL   /* Bus Parking 0=Ultra-IIi 1=prev-bus-owner */
 128 #define  SABRE_PCICTRL_CPUPRIO   0x0000000000100000UL   /* Ultra-IIi granted every other bus cycle */
 129 #define  SABRE_PCICTRL_ARBPRIO   0x00000000000f0000UL   /* Slot which is granted every other bus cycle */
 130 #define  SABRE_PCICTRL_ERREN     0x0000000000000100UL   /* PCI Error Interrupt Enable */
 131 #define  SABRE_PCICTRL_RTRYWE    0x0000000000000080UL   /* DMA Flow Control 0=wait-if-possible 1=retry */
 132 #define  SABRE_PCICTRL_AEN       0x000000000000000fUL   /* Slot PCI arbitration enables */
 133 #define SABRE_PIOAFSR           0x2010UL
 134 #define  SABRE_PIOAFSR_PMA       0x8000000000000000UL   /* Primary Master Abort */
 135 #define  SABRE_PIOAFSR_PTA       0x4000000000000000UL   /* Primary Target Abort */
 136 #define  SABRE_PIOAFSR_PRTRY     0x2000000000000000UL   /* Primary Excessive Retries */
 137 #define  SABRE_PIOAFSR_PPERR     0x1000000000000000UL   /* Primary Parity Error */
 138 #define  SABRE_PIOAFSR_SMA       0x0800000000000000UL   /* Secondary Master Abort */
 139 #define  SABRE_PIOAFSR_STA       0x0400000000000000UL   /* Secondary Target Abort */
 140 #define  SABRE_PIOAFSR_SRTRY     0x0200000000000000UL   /* Secondary Excessive Retries */
 141 #define  SABRE_PIOAFSR_SPERR     0x0100000000000000UL   /* Secondary Parity Error */
 142 #define  SABRE_PIOAFSR_BMSK      0x0000ffff00000000UL   /* Byte Mask */
 143 #define  SABRE_PIOAFSR_BLK       0x0000000080000000UL   /* Was Block Operation */
 144 #define SABRE_PIOAFAR           0x2018UL
 145 #define SABRE_PCIDIAG           0x2020UL
 146 #define  SABRE_PCIDIAG_DRTRY     0x0000000000000040UL   /* Disable PIO Retry Limit */
 147 #define  SABRE_PCIDIAG_IPAPAR    0x0000000000000008UL   /* Invert PIO Address Parity */
 148 #define  SABRE_PCIDIAG_IPDPAR    0x0000000000000004UL   /* Invert PIO Data Parity */
 149 #define  SABRE_PCIDIAG_IDDPAR    0x0000000000000002UL   /* Invert DMA Data Parity */
 150 #define  SABRE_PCIDIAG_ELPBK     0x0000000000000001UL   /* Loopback Enable - not supported */
 151 #define SABRE_PCITASR           0x2028UL
 152 #define  SABRE_PCITASR_EF        0x0000000000000080UL   /* Respond to 0xe0000000-0xffffffff */
 153 #define  SABRE_PCITASR_CD        0x0000000000000040UL   /* Respond to 0xc0000000-0xdfffffff */
 154 #define  SABRE_PCITASR_AB        0x0000000000000020UL   /* Respond to 0xa0000000-0xbfffffff */
 155 #define  SABRE_PCITASR_89        0x0000000000000010UL   /* Respond to 0x80000000-0x9fffffff */
 156 #define  SABRE_PCITASR_67        0x0000000000000008UL   /* Respond to 0x60000000-0x7fffffff */
 157 #define  SABRE_PCITASR_45        0x0000000000000004UL   /* Respond to 0x40000000-0x5fffffff */
 158 #define  SABRE_PCITASR_23        0x0000000000000002UL   /* Respond to 0x20000000-0x3fffffff */
 159 #define  SABRE_PCITASR_01        0x0000000000000001UL   /* Respond to 0x00000000-0x1fffffff */
 160 #define SABRE_PIOBUF_DIAG       0x5000UL
 161 #define SABRE_DMABUF_DIAGLO     0x5100UL
 162 #define SABRE_DMABUF_DIAGHI     0x51c0UL
 163 #define SABRE_IMAP_GFX_ALIAS    0x6000UL        /* Aliases to 0x1098 */
 164 #define SABRE_IMAP_EUPA_ALIAS   0x8000UL        /* Aliases to 0x10a0 */
 165 #define SABRE_IOMMU_VADIAG      0xa400UL
 166 #define SABRE_IOMMU_TCDIAG      0xa408UL
 167 #define SABRE_IOMMU_TAG         0xa580UL
 168 #define  SABRE_IOMMUTAG_ERRSTS   0x0000000001800000UL   /* Error status bits */
 169 #define  SABRE_IOMMUTAG_ERR      0x0000000000400000UL   /* Error present */
 170 #define  SABRE_IOMMUTAG_WRITE    0x0000000000200000UL   /* Page is writable */
 171 #define  SABRE_IOMMUTAG_STREAM   0x0000000000100000UL   /* Streamable bit - unused */
 172 #define  SABRE_IOMMUTAG_SIZE     0x0000000000080000UL   /* 0=8k 1=16k */
 173 #define  SABRE_IOMMUTAG_VPN      0x000000000007ffffUL   /* Virtual Page Number [31:13] */
 174 #define SABRE_IOMMU_DATA        0xa600UL
 175 #define SABRE_IOMMUDATA_VALID    0x0000000040000000UL   /* Valid */
 176 #define SABRE_IOMMUDATA_USED     0x0000000020000000UL   /* Used (for LRU algorithm) */
 177 #define SABRE_IOMMUDATA_CACHE    0x0000000010000000UL   /* Cacheable */
 178 #define SABRE_IOMMUDATA_PPN      0x00000000001fffffUL   /* Physical Page Number [33:13] */
 179 #define SABRE_PCI_IRQSTATE      0xa800UL
 180 #define SABRE_OBIO_IRQSTATE     0xa808UL
 181 #define SABRE_FFBCFG            0xf000UL
 182 #define  SABRE_FFBCFG_SPRQS      0x000000000f000000     /* Slave P_RQST queue size */
 183 #define  SABRE_FFBCFG_ONEREAD    0x0000000000004000     /* Slave supports one outstanding read */
 184 #define SABRE_MCCTRL0           0xf010UL
 185 #define  SABRE_MCCTRL0_RENAB     0x0000000080000000     /* Refresh Enable */
 186 #define  SABRE_MCCTRL0_EENAB     0x0000000010000000     /* Enable all ECC functions */
 187 #define  SABRE_MCCTRL0_11BIT     0x0000000000001000     /* Enable 11-bit column addressing */
 188 #define  SABRE_MCCTRL0_DPP       0x0000000000000f00     /* DIMM Pair Present Bits */
 189 #define  SABRE_MCCTRL0_RINTVL    0x00000000000000ff     /* Refresh Interval */
 190 #define SABRE_MCCTRL1           0xf018UL
 191 #define  SABRE_MCCTRL1_AMDC      0x0000000038000000     /* Advance Memdata Clock */
 192 #define  SABRE_MCCTRL1_ARDC      0x0000000007000000     /* Advance DRAM Read Data Clock */
 193 #define  SABRE_MCCTRL1_CSR       0x0000000000e00000     /* CAS to RAS delay for CBR refresh */
 194 #define  SABRE_MCCTRL1_CASRW     0x00000000001c0000     /* CAS length for read/write */
 195 #define  SABRE_MCCTRL1_RCD       0x0000000000038000     /* RAS to CAS delay */
 196 #define  SABRE_MCCTRL1_CP        0x0000000000007000     /* CAS Precharge */
 197 #define  SABRE_MCCTRL1_RP        0x0000000000000e00     /* RAS Precharge */
 198 #define  SABRE_MCCTRL1_RAS       0x00000000000001c0     /* Length of RAS for refresh */
 199 #define  SABRE_MCCTRL1_CASRW2    0x0000000000000038     /* Must be same as CASRW */
 200 #define  SABRE_MCCTRL1_RSC       0x0000000000000007     /* RAS after CAS hold time */
 201 #define SABRE_RESETCTRL         0xf020UL
 202
 203 #define SABRE_CONFIGSPACE       0x001000000UL
 204 #define SABRE_IOSPACE           0x002000000UL
 205 #define SABRE_IOSPACE_SIZE      0x000ffffffUL
 206 #define SABRE_MEMSPACE          0x100000000UL
 207 #define SABRE_MEMSPACE_SIZE     0x07fffffffUL
 208
 209 /* UltraSparc-IIi Programmer's Manual, page 325, PCI
 210  * configuration space address format:
 211  *
 212  *  32             24 23 16 15    11 10       8 7   2  1 0
 213  * ---------------------------------------------------------
 214  * |0 0 0 0 0 0 0 0 1| bus | device | function | reg | 0 0 |
 215  * ---------------------------------------------------------
 216  */
 217 #define SABRE_CONFIG_BASE(PBM)  \
 218         ((PBM)->config_space | (1UL << 24))
 219 #define SABRE_CONFIG_ENCODE(BUS, DEVFN, REG)    \
 220         (((unsigned long)(BUS)   << 16) |       \
 221          ((unsigned long)(DEVFN) << 8)  |       \
 222          ((unsigned long)(REG)))
 223
 224 static int hummingbird_p;
 225 static struct pci_bus *sabre_root_bus;
 226
 227 static void *sabre_pci_config_mkaddr(struct pci_pbm_info *pbm,
 228                                      unsigned char bus,
 229                                      unsigned int devfn,
 230                                      int where)
 231 {
 232         if (!pbm)
 233                 return NULL;
 234         return (void *)
 235                 (SABRE_CONFIG_BASE(pbm) |
 236                  SABRE_CONFIG_ENCODE(bus, devfn, where));
 237 }
 238
 239 static int sabre_out_of_range(unsigned char devfn)
 240 {
 241         if (hummingbird_p)
 242                 return 0;
 243
 244         return (((PCI_SLOT(devfn) == 0) && (PCI_FUNC(devfn) > 0)) ||
 245                 ((PCI_SLOT(devfn) == 1) && (PCI_FUNC(devfn) > 1)) ||
 246                 (PCI_SLOT(devfn) > 1));
 247 }
 248
 249 static int __sabre_out_of_range(struct pci_pbm_info *pbm,
 250                                 unsigned char bus,
 251                                 unsigned char devfn)
 252 {
 253         if (hummingbird_p)
 254                 return 0;
 255
 256         return ((pbm->parent == 0) ||
 257                 ((pbm == &pbm->parent->pbm_B) &&
 258                  (bus == pbm->pci_first_busno) &&
 259                  PCI_SLOT(devfn) > 8) ||
 260                 ((pbm == &pbm->parent->pbm_A) &&
 261                  (bus == pbm->pci_first_busno) &&
 262                  PCI_SLOT(devfn) > 8));
 263 }
 264
 265 static int __sabre_read_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
 266                                 int where, int size, u32 *value)
 267 {
 268         struct pci_pbm_info *pbm = bus_dev->sysdata;
 269         unsigned char bus = bus_dev->number;
 270         u32 *addr;
 271         u16 tmp16;
 272         u8 tmp8;
 273
 274         switch (size) {
 275         case 1:
 276                 *value = 0xff;
 277                 break;
 278         case 2:
 279                 *value = 0xffff;
 280                 break;
 281         case 4:
 282                 *value = 0xffffffff;
 283                 break;
 284         }
 285
 286         addr = sabre_pci_config_mkaddr(pbm, bus, devfn, where);
 287         if (!addr)
 288                 return PCIBIOS_SUCCESSFUL;
 289
 290         if (__sabre_out_of_range(pbm, bus, devfn))
 291                 return PCIBIOS_SUCCESSFUL;
 292
 293         switch (size) {
 294         case 1:
 295                 pci_config_read8((u8 *) addr, &tmp8);
 296                 *value = tmp8;
 297                 break;
 298
 299         case 2:
 300                 if (where & 0x01) {
 301                         printk("pci_read_config_word: misaligned reg [%x]\n",
 302                                where);
 303                         return PCIBIOS_SUCCESSFUL;
 304                 }
 305                 pci_config_read16((u16 *) addr, &tmp16);
 306                 *value = tmp16;
 307                 break;
 308
 309         case 4:
 310                 if (where & 0x03) {
 311                         printk("pci_read_config_dword: misaligned reg [%x]\n",
 312                                where);
 313                         return PCIBIOS_SUCCESSFUL;
 314                 }
 315                 pci_config_read32(addr, value);
 316                 break;
 317         }
 318
 319         return PCIBIOS_SUCCESSFUL;
 320 }
 321
 322 static int sabre_read_pci_cfg(struct pci_bus *bus, unsigned int devfn,
 323                               int where, int size, u32 *value)
 324 {
 325         if (!bus->number && sabre_out_of_range(devfn)) {
 326                 switch (size) {
 327                 case 1:
 328                         *value = 0xff;
 329                         break;
 330                 case 2:
 331                         *value = 0xffff;
 332                         break;
 333                 case 4:
 334                         *value = 0xffffffff;
 335                         break;
 336                 }
 337                 return PCIBIOS_SUCCESSFUL;
 338         }
 339
 340         if (bus->number || PCI_SLOT(devfn))
 341                 return __sabre_read_pci_cfg(bus, devfn, where, size, value);
 342
 343         /* When accessing PCI config space of the PCI controller itself (bus
 344          * 0, device slot 0, function 0) there are restrictions.  Each
 345          * register must be accessed as it's natural size.  Thus, for example
 346          * the Vendor ID must be accessed as a 16-bit quantity.
 347          */
 348
 349         switch (size) {
 350         case 1:
 351                 if (where < 8) {
 352                         u32 tmp32;
 353                         u16 tmp16;
 354
 355                         __sabre_read_pci_cfg(bus, devfn, where & ~1, 2, &tmp32);
 356                         tmp16 = (u16) tmp32;
 357                         if (where & 1)
 358                                 *value = tmp16 >> 8;
 359                         else
 360                                 *value = tmp16 & 0xff;
 361                 } else
 362                         return __sabre_read_pci_cfg(bus, devfn, where, 1, value);
 363                 break;
 364
 365         case 2:
 366                 if (where < 8)
 367                         return __sabre_read_pci_cfg(bus, devfn, where, 2, value);
 368                 else {
 369                         u32 tmp32;
 370                         u8 tmp8;
 371
 372                         __sabre_read_pci_cfg(bus, devfn, where, 1, &tmp32);
 373                         tmp8 = (u8) tmp32;
 374                         *value = tmp8;
 375                         __sabre_read_pci_cfg(bus, devfn, where + 1, 1, &tmp32);
 376                         tmp8 = (u8) tmp32;
 377                         *value |= tmp8 << 8;
 378                 }
 379                 break;
 380
 381         case 4: {
 382                 u32 tmp32;
 383                 u16 tmp16;
 384
 385                 sabre_read_pci_cfg(bus, devfn, where, 2, &tmp32);
 386                 tmp16 = (u16) tmp32;
 387                 *value = tmp16;
 388                 sabre_read_pci_cfg(bus, devfn, where + 2, 2, &tmp32);
 389                 tmp16 = (u16) tmp32;
 390                 *value |= tmp16 << 16;
 391                 break;
 392         }
 393         }
 394         return PCIBIOS_SUCCESSFUL;
 395 }
 396
 397 static int __sabre_write_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
 398                                  int where, int size, u32 value)
 399 {
 400         struct pci_pbm_info *pbm = bus_dev->sysdata;
 401         unsigned char bus = bus_dev->number;
 402         u32 *addr;
 403
 404         addr = sabre_pci_config_mkaddr(pbm, bus, devfn, where);
 405         if (!addr)
 406                 return PCIBIOS_SUCCESSFUL;
 407
 408         if (__sabre_out_of_range(pbm, bus, devfn))
 409                 return PCIBIOS_SUCCESSFUL;
 410
 411         switch (size) {
 412         case 1:
 413                 pci_config_write8((u8 *) addr, value);
 414                 break;
 415
 416         case 2:
 417                 if (where & 0x01) {
 418                         printk("pci_write_config_word: misaligned reg [%x]\n",
 419                                where);
 420                         return PCIBIOS_SUCCESSFUL;
 421                 }
 422                 pci_config_write16((u16 *) addr, value);
 423                 break;
 424
 425         case 4:
 426                 if (where & 0x03) {
 427                         printk("pci_write_config_dword: misaligned reg [%x]\n",
 428                                where);
 429                         return PCIBIOS_SUCCESSFUL;
 430                 }
 431                 pci_config_write32(addr, value);
 432                 break;
 433         }
 434
 435         return PCIBIOS_SUCCESSFUL;
 436 }
 437
 438 static int sabre_write_pci_cfg(struct pci_bus *bus, unsigned int devfn,
 439                                int where, int size, u32 value)
 440 {
 441         if (bus->number)
 442                 return __sabre_write_pci_cfg(bus, devfn, where, size, value);
 443
 444         if (sabre_out_of_range(devfn))
 445                 return PCIBIOS_SUCCESSFUL;
 446
 447         switch (size) {
 448         case 1:
 449                 if (where < 8) {
 450                         u32 tmp32;
 451                         u16 tmp16;
 452
 453                         __sabre_read_pci_cfg(bus, devfn, where & ~1, 2, &tmp32);
 454                         tmp16 = (u16) tmp32;
 455                         if (where & 1) {
 456                                 value &= 0x00ff;
 457                                 value |= tmp16 << 8;
 458                         } else {
 459                                 value &= 0xff00;
 460                                 value |= tmp16;
 461                         }
 462                         tmp32 = (u32) tmp16;
 463                         return __sabre_write_pci_cfg(bus, devfn, where & ~1, 2, tmp32);
 464                 } else
 465                         return __sabre_write_pci_cfg(bus, devfn, where, 1, value);
 466                 break;
 467         case 2:
 468                 if (where < 8)
 469                         return __sabre_write_pci_cfg(bus, devfn, where, 2, value);
 470                 else {
 471                         __sabre_write_pci_cfg(bus, devfn, where, 1, value & 0xff);
 472                         __sabre_write_pci_cfg(bus, devfn, where + 1, 1, value >> 8);
 473                 }
 474                 break;
 475         case 4:
 476                 sabre_write_pci_cfg(bus, devfn, where, 2, value & 0xffff);
 477                 sabre_write_pci_cfg(bus, devfn, where + 2, 2, value >> 16);
 478                 break;
 479         }
 480         return PCIBIOS_SUCCESSFUL;
 481 }
 482
 483 static struct pci_ops sabre_ops = {
 484         .read =         sabre_read_pci_cfg,
 485         .write =        sabre_write_pci_cfg,
 486 };
 487
 488 /* SABRE error handling support. */
 489 static void sabre_check_iommu_error(struct pci_controller_info *p,
 490                                     unsigned long afsr,
 491                                     unsigned long afar)
 492 {
 493         struct pci_iommu *iommu = p->pbm_A.iommu;
 494         unsigned long iommu_tag[16];
 495         unsigned long iommu_data[16];
 496         unsigned long flags;
 497         u64 control;
 498         int i;
 499
 500         spin_lock_irqsave(&iommu->lock, flags);
 501         control = sabre_read(iommu->iommu_control);
 502         if (control & SABRE_IOMMUCTRL_ERR) {
 503                 char *type_string;
 504
 505                 /* Clear the error encountered bit.
 506                  * NOTE: On Sabre this is write 1 to clear,
 507                  *       which is different from Psycho.
 508                  */
 509                 sabre_write(iommu->iommu_control, control);
 510                 switch((control & SABRE_IOMMUCTRL_ERRSTS) >> 25UL) {
 511                 case 1:
 512                         type_string = "Invalid Error";
 513                         break;
 514                 case 3:
 515                         type_string = "ECC Error";
 516                         break;
 517                 default:
 518                         type_string = "Unknown";
 519                         break;
 520                 };
 521                 printk("SABRE%d: IOMMU Error, type[%s]\n",
 522                        p->index, type_string);
 523
 524                 /* Enter diagnostic mode and probe for error'd
 525                  * entries in the IOTLB.
 526                  */
 527                 control &= ~(SABRE_IOMMUCTRL_ERRSTS | SABRE_IOMMUCTRL_ERR);
 528                 sabre_write(iommu->iommu_control,
 529                             (control | SABRE_IOMMUCTRL_DENAB));
 530                 for (i = 0; i < 16; i++) {
 531                         unsigned long base = p->pbm_A.controller_regs;
 532
 533                         iommu_tag[i] =
 534                                 sabre_read(base + SABRE_IOMMU_TAG + (i * 8UL));
 535                         iommu_data[i] =
 536                                 sabre_read(base + SABRE_IOMMU_DATA + (i * 8UL));
 537                         sabre_write(base + SABRE_IOMMU_TAG + (i * 8UL), 0);
 538                         sabre_write(base + SABRE_IOMMU_DATA + (i * 8UL), 0);
 539                 }
 540                 sabre_write(iommu->iommu_control, control);
 541
 542                 for (i = 0; i < 16; i++) {
 543                         unsigned long tag, data;
 544
 545                         tag = iommu_tag[i];
 546                         if (!(tag & SABRE_IOMMUTAG_ERR))
 547                                 continue;
 548
 549                         data = iommu_data[i];
 550                         switch((tag & SABRE_IOMMUTAG_ERRSTS) >> 23UL) {
 551                         case 1:
 552                                 type_string = "Invalid Error";
 553                                 break;
 554                         case 3:
 555                                 type_string = "ECC Error";
 556                                 break;
 557                         default:
 558                                 type_string = "Unknown";
 559                                 break;
 560                         };
 561                         printk("SABRE%d: IOMMU TAG(%d)[RAW(%016lx)error(%s)wr(%d)sz(%dK)vpg(%08lx)]\n",
 562                                p->index, i, tag, type_string,
 563                                ((tag & SABRE_IOMMUTAG_WRITE) ? 1 : 0),
 564                                ((tag & SABRE_IOMMUTAG_SIZE) ? 64 : 8),
 565                                ((tag & SABRE_IOMMUTAG_VPN) << IOMMU_PAGE_SHIFT));
 566                         printk("SABRE%d: IOMMU DATA(%d)[RAW(%016lx)valid(%d)used(%d)cache(%d)ppg(%016lx)\n",
 567                                p->index, i, data,
 568                                ((data & SABRE_IOMMUDATA_VALID) ? 1 : 0),
 569                                ((data & SABRE_IOMMUDATA_USED) ? 1 : 0),
 570                                ((data & SABRE_IOMMUDATA_CACHE) ? 1 : 0),
 571                                ((data & SABRE_IOMMUDATA_PPN) << IOMMU_PAGE_SHIFT));
 572                 }
 573         }
 574         spin_unlock_irqrestore(&iommu->lock, flags);
 575 }
 576
 577 static irqreturn_t sabre_ue_intr(int irq, void *dev_id, struct pt_regs *regs)
 578 {
 579         struct pci_controller_info *p = dev_id;
 580         unsigned long afsr_reg = p->pbm_A.controller_regs + SABRE_UE_AFSR;
 581         unsigned long afar_reg = p->pbm_A.controller_regs + SABRE_UECE_AFAR;
 582         unsigned long afsr, afar, error_bits;
 583         int reported;
 584
 585         /* Latch uncorrectable error status. */
 586         afar = sabre_read(afar_reg);
 587         afsr = sabre_read(afsr_reg);
 588
 589         /* Clear the primary/secondary error status bits. */
 590         error_bits = afsr &
 591                 (SABRE_UEAFSR_PDRD | SABRE_UEAFSR_PDWR |
 592                  SABRE_UEAFSR_SDRD | SABRE_UEAFSR_SDWR |
 593                  SABRE_UEAFSR_SDTE | SABRE_UEAFSR_PDTE);
 594         if (!error_bits)
 595                 return IRQ_NONE;
 596         sabre_write(afsr_reg, error_bits);
 597
 598         /* Log the error. */
 599         printk("SABRE%d: Uncorrectable Error, primary error type[%s%s]\n",
 600                p->index,
 601                ((error_bits & SABRE_UEAFSR_PDRD) ?
 602                 "DMA Read" :
 603                 ((error_bits & SABRE_UEAFSR_PDWR) ?
 604                  "DMA Write" : "???")),
 605                ((error_bits & SABRE_UEAFSR_PDTE) ?
 606                 ":Translation Error" : ""));
 607         printk("SABRE%d: bytemask[%04lx] dword_offset[%lx] was_block(%d)\n",
 608                p->index,
 609                (afsr & SABRE_UEAFSR_BMSK) >> 32UL,
 610                (afsr & SABRE_UEAFSR_OFF) >> 29UL,
 611                ((afsr & SABRE_UEAFSR_BLK) ? 1 : 0));
 612         printk("SABRE%d: UE AFAR [%016lx]\n", p->index, afar);
 613         printk("SABRE%d: UE Secondary errors [", p->index);
 614         reported = 0;
 615         if (afsr & SABRE_UEAFSR_SDRD) {
 616                 reported++;
 617                 printk("(DMA Read)");
 618         }
 619         if (afsr & SABRE_UEAFSR_SDWR) {
 620                 reported++;
 621                 printk("(DMA Write)");
 622         }
 623         if (afsr & SABRE_UEAFSR_SDTE) {
 624                 reported++;
 625                 printk("(Translation Error)");
 626         }
 627         if (!reported)
 628                 printk("(none)");
 629         printk("]\n");
 630
 631         /* Interrogate IOMMU for error status. */
 632         sabre_check_iommu_error(p, afsr, afar);
 633
 634         return IRQ_HANDLED;
 635 }
 636
 637 static irqreturn_t sabre_ce_intr(int irq, void *dev_id, struct pt_regs *regs)
 638 {
 639         struct pci_controller_info *p = dev_id;
 640         unsigned long afsr_reg = p->pbm_A.controller_regs + SABRE_CE_AFSR;
 641         unsigned long afar_reg = p->pbm_A.controller_regs + SABRE_UECE_AFAR;
 642         unsigned long afsr, afar, error_bits;
 643         int reported;
 644
 645         /* Latch error status. */
 646         afar = sabre_read(afar_reg);
 647         afsr = sabre_read(afsr_reg);
 648
 649         /* Clear primary/secondary error status bits. */
 650         error_bits = afsr &
 651                 (SABRE_CEAFSR_PDRD | SABRE_CEAFSR_PDWR |
 652                  SABRE_CEAFSR_SDRD | SABRE_CEAFSR_SDWR);
 653         if (!error_bits)
 654                 return IRQ_NONE;
 655         sabre_write(afsr_reg, error_bits);
 656
 657         /* Log the error. */
 658         printk("SABRE%d: Correctable Error, primary error type[%s]\n",
 659                p->index,
 660                ((error_bits & SABRE_CEAFSR_PDRD) ?
 661                 "DMA Read" :
 662                 ((error_bits & SABRE_CEAFSR_PDWR) ?
 663                  "DMA Write" : "???")));
 664
 665         /* XXX Use syndrome and afar to print out module string just like
 666          * XXX UDB CE trap handler does... -DaveM
 667          */
 668         printk("SABRE%d: syndrome[%02lx] bytemask[%04lx] dword_offset[%lx] "
 669                "was_block(%d)\n",
 670                p->index,
 671                (afsr & SABRE_CEAFSR_ESYND) >> 48UL,
 672                (afsr & SABRE_CEAFSR_BMSK) >> 32UL,
 673                (afsr & SABRE_CEAFSR_OFF) >> 29UL,
 674                ((afsr & SABRE_CEAFSR_BLK) ? 1 : 0));
 675         printk("SABRE%d: CE AFAR [%016lx]\n", p->index, afar);
 676         printk("SABRE%d: CE Secondary errors [", p->index);
 677         reported = 0;
 678         if (afsr & SABRE_CEAFSR_SDRD) {
 679                 reported++;
 680                 printk("(DMA Read)");
 681         }
 682         if (afsr & SABRE_CEAFSR_SDWR) {
 683                 reported++;
 684                 printk("(DMA Write)");
 685         }
 686         if (!reported)
 687                 printk("(none)");
 688         printk("]\n");
 689
 690         return IRQ_HANDLED;
 691 }
 692
 693 static irqreturn_t sabre_pcierr_intr_other(struct pci_controller_info *p)
 694 {
 695         unsigned long csr_reg, csr, csr_error_bits;
 696         irqreturn_t ret = IRQ_NONE;
 697         u16 stat;
 698
 699         csr_reg = p->pbm_A.controller_regs + SABRE_PCICTRL;
 700         csr = sabre_read(csr_reg);
 701         csr_error_bits =
 702                 csr & SABRE_PCICTRL_SERR;
 703         if (csr_error_bits) {
 704                 /* Clear the errors.  */
 705                 sabre_write(csr_reg, csr);
 706
 707                 /* Log 'em.  */
 708                 if (csr_error_bits & SABRE_PCICTRL_SERR)
 709                         printk("SABRE%d: PCI SERR signal asserted.\n",
 710                                p->index);
 711                 ret = IRQ_HANDLED;
 712         }
 713         pci_read_config_word(sabre_root_bus->self,
 714                              PCI_STATUS, &stat);
 715         if (stat & (PCI_STATUS_PARITY |
 716                     PCI_STATUS_SIG_TARGET_ABORT |
 717                     PCI_STATUS_REC_TARGET_ABORT |
 718                     PCI_STATUS_REC_MASTER_ABORT |
 719                     PCI_STATUS_SIG_SYSTEM_ERROR)) {
 720                 printk("SABRE%d: PCI bus error, PCI_STATUS[%04x]\n",
 721                        p->index, stat);
 722                 pci_write_config_word(sabre_root_bus->self,
 723                                       PCI_STATUS, 0xffff);
 724                 ret = IRQ_HANDLED;
 725         }
 726         return ret;
 727 }
 728
 729 static irqreturn_t sabre_pcierr_intr(int irq, void *dev_id, struct pt_regs *regs)
 730 {
 731         struct pci_controller_info *p = dev_id;
 732         unsigned long afsr_reg, afar_reg;
 733         unsigned long afsr, afar, error_bits;
 734         int reported;
 735
 736         afsr_reg = p->pbm_A.controller_regs + SABRE_PIOAFSR;
 737         afar_reg = p->pbm_A.controller_regs + SABRE_PIOAFAR;
 738
 739         /* Latch error status. */
 740         afar = sabre_read(afar_reg);
 741         afsr = sabre_read(afsr_reg);
 742
 743         /* Clear primary/secondary error status bits. */
 744         error_bits = afsr &
 745                 (SABRE_PIOAFSR_PMA | SABRE_PIOAFSR_PTA |
 746                  SABRE_PIOAFSR_PRTRY | SABRE_PIOAFSR_PPERR |
 747                  SABRE_PIOAFSR_SMA | SABRE_PIOAFSR_STA |
 748                  SABRE_PIOAFSR_SRTRY | SABRE_PIOAFSR_SPERR);
 749         if (!error_bits)
 750                 return sabre_pcierr_intr_other(p);
 751         sabre_write(afsr_reg, error_bits);
 752
 753         /* Log the error. */
 754         printk("SABRE%d: PCI Error, primary error type[%s]\n",
 755                p->index,
 756                (((error_bits & SABRE_PIOAFSR_PMA) ?
 757                  "Master Abort" :
 758                  ((error_bits & SABRE_PIOAFSR_PTA) ?
 759                   "Target Abort" :
 760                   ((error_bits & SABRE_PIOAFSR_PRTRY) ?
 761                    "Excessive Retries" :
 762                    ((error_bits & SABRE_PIOAFSR_PPERR) ?
 763                     "Parity Error" : "???"))))));
 764         printk("SABRE%d: bytemask[%04lx] was_block(%d)\n",
 765                p->index,
 766                (afsr & SABRE_PIOAFSR_BMSK) >> 32UL,
 767                (afsr & SABRE_PIOAFSR_BLK) ? 1 : 0);
 768         printk("SABRE%d: PCI AFAR [%016lx]\n", p->index, afar);
 769         printk("SABRE%d: PCI Secondary errors [", p->index);
 770         reported = 0;
 771         if (afsr & SABRE_PIOAFSR_SMA) {
 772                 reported++;
 773                 printk("(Master Abort)");
 774         }
 775         if (afsr & SABRE_PIOAFSR_STA) {
 776                 reported++;
 777                 printk("(Target Abort)");
 778         }
 779         if (afsr & SABRE_PIOAFSR_SRTRY) {
 780                 reported++;
 781                 printk("(Excessive Retries)");
 782         }
 783         if (afsr & SABRE_PIOAFSR_SPERR) {
 784                 reported++;
 785                 printk("(Parity Error)");
 786         }
 787         if (!reported)
 788                 printk("(none)");
 789         printk("]\n");
 790
 791         /* For the error types shown, scan both PCI buses for devices
 792          * which have logged that error type.
 793          */
 794
 795         /* If we see a Target Abort, this could be the result of an
 796          * IOMMU translation error of some sort.  It is extremely
 797          * useful to log this information as usually it indicates
 798          * a bug in the IOMMU support code or a PCI device driver.
 799          */
 800         if (error_bits & (SABRE_PIOAFSR_PTA | SABRE_PIOAFSR_STA)) {
 801                 sabre_check_iommu_error(p, afsr, afar);
 802                 pci_scan_for_target_abort(p, &p->pbm_A, p->pbm_A.pci_bus);
 803                 pci_scan_for_target_abort(p, &p->pbm_B, p->pbm_B.pci_bus);
 804         }
 805         if (error_bits & (SABRE_PIOAFSR_PMA | SABRE_PIOAFSR_SMA)) {
 806                 pci_scan_for_master_abort(p, &p->pbm_A, p->pbm_A.pci_bus);
 807                 pci_scan_for_master_abort(p, &p->pbm_B, p->pbm_B.pci_bus);
 808         }
 809         /* For excessive retries, SABRE/PBM will abort the device
 810          * and there is no way to specifically check for excessive
 811          * retries in the config space status registers.  So what
 812          * we hope is that we'll catch it via the master/target
 813          * abort events.
 814          */
 815
 816         if (error_bits & (SABRE_PIOAFSR_PPERR | SABRE_PIOAFSR_SPERR)) {
 817                 pci_scan_for_parity_error(p, &p->pbm_A, p->pbm_A.pci_bus);
 818                 pci_scan_for_parity_error(p, &p->pbm_B, p->pbm_B.pci_bus);
 819         }
 820
 821         return IRQ_HANDLED;
 822 }
 823
 824 static void sabre_register_error_handlers(struct pci_controller_info *p)
 825 {
 826         struct pci_pbm_info *pbm = &p->pbm_A; /* arbitrary */
 827         struct device_node *dp = pbm->prom_node;
 828         struct of_device *op;
 829         unsigned long base = pbm->controller_regs;
 830         u64 tmp;
 831
 832         if (pbm->chip_type == PBM_CHIP_TYPE_SABRE)
 833                 dp = dp->parent;
 834
 835         op = of_find_device_by_node(dp);
 836         if (!op)
 837                 return;
 838
 839         /* Sabre/Hummingbird IRQ property layout is:
 840          * 0: PCI ERR
 841          * 1: UE ERR
 842          * 2: CE ERR
 843          * 3: POWER FAIL
 844          */
 845         if (op->num_irqs < 4)
 846                 return;
 847
 848         /* We clear the error bits in the appropriate AFSR before
 849          * registering the handler so that we don't get spurious
 850          * interrupts.
 851          */
 852         sabre_write(base + SABRE_UE_AFSR,
 853                     (SABRE_UEAFSR_PDRD | SABRE_UEAFSR_PDWR |
 854                      SABRE_UEAFSR_SDRD | SABRE_UEAFSR_SDWR |
 855                      SABRE_UEAFSR_SDTE | SABRE_UEAFSR_PDTE));
 856
 857         request_irq(op->irqs[1], sabre_ue_intr, IRQF_SHARED, "SABRE UE", p);
 858
 859         sabre_write(base + SABRE_CE_AFSR,
 860                     (SABRE_CEAFSR_PDRD | SABRE_CEAFSR_PDWR |
 861                      SABRE_CEAFSR_SDRD | SABRE_CEAFSR_SDWR));
 862
 863         request_irq(op->irqs[2], sabre_ce_intr, IRQF_SHARED, "SABRE CE", p);
 864         request_irq(op->irqs[0], sabre_pcierr_intr, IRQF_SHARED,
 865                     "SABRE PCIERR", p);
 866
 867         tmp = sabre_read(base + SABRE_PCICTRL);
 868         tmp |= SABRE_PCICTRL_ERREN;
 869         sabre_write(base + SABRE_PCICTRL, tmp);
 870 }
 871
 872 static void sabre_resource_adjust(struct pci_dev *pdev,
 873                                   struct resource *res,
 874                                   struct resource *root)
 875 {
 876         struct pci_pbm_info *pbm = pdev->bus->sysdata;
 877         unsigned long base;
 878
 879         if (res->flags & IORESOURCE_IO)
 880                 base = pbm->controller_regs + SABRE_IOSPACE;
 881         else
 882                 base = pbm->controller_regs + SABRE_MEMSPACE;
 883
 884         res->start += base;
 885         res->end += base;
 886 }
 887
 888 static void sabre_base_address_update(struct pci_dev *pdev, int resource)
 889 {
 890         struct pcidev_cookie *pcp = pdev->sysdata;
 891         struct pci_pbm_info *pbm = pcp->pbm;
 892         struct resource *res;
 893         unsigned long base;
 894         u32 reg;
 895         int where, size, is_64bit;
 896
 897         res = &pdev->resource[resource];
 898         if (resource < 6) {
 899                 where = PCI_BASE_ADDRESS_0 + (resource * 4);
 900         } else if (resource == PCI_ROM_RESOURCE) {
 901                 where = pdev->rom_base_reg;
 902         } else {
 903                 /* Somebody might have asked allocation of a non-standard resource */
 904                 return;
 905         }
 906
 907         is_64bit = 0;
 908         if (res->flags & IORESOURCE_IO)
 909                 base = pbm->controller_regs + SABRE_IOSPACE;
 910         else {
 911                 base = pbm->controller_regs + SABRE_MEMSPACE;
 912                 if ((res->flags & PCI_BASE_ADDRESS_MEM_TYPE_MASK)
 913                     == PCI_BASE_ADDRESS_MEM_TYPE_64)
 914                         is_64bit = 1;
 915         }
 916
 917         size = res->end - res->start;
 918         pci_read_config_dword(pdev, where, &reg);
 919         reg = ((reg & size) |
 920                (((u32)(res->start - base)) & ~size));
 921         if (resource == PCI_ROM_RESOURCE) {
 922                 reg |= PCI_ROM_ADDRESS_ENABLE;
 923                 res->flags |= IORESOURCE_ROM_ENABLE;
 924         }
 925         pci_write_config_dword(pdev, where, reg);
 926
 927         /* This knows that the upper 32-bits of the address
 928          * must be zero.  Our PCI common layer enforces this.
 929          */
 930         if (is_64bit)
 931                 pci_write_config_dword(pdev, where + 4, 0);
 932 }
 933
 934 static void apb_init(struct pci_controller_info *p, struct pci_bus *sabre_bus)
 935 {
 936         struct pci_dev *pdev;
 937
 938         list_for_each_entry(pdev, &sabre_bus->devices, bus_list) {
 939
 940                 if (pdev->vendor == PCI_VENDOR_ID_SUN &&
 941                     pdev->device == PCI_DEVICE_ID_SUN_SIMBA) {
 942                         u32 word32;
 943                         u16 word16;
 944
 945                         sabre_read_pci_cfg(pdev->bus, pdev->devfn,
 946                                            PCI_COMMAND, 2, &word32);
 947                         word16 = (u16) word32;
 948                         word16 |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY |
 949                                 PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY |
 950                                 PCI_COMMAND_IO;
 951                         word32 = (u32) word16;
 952                         sabre_write_pci_cfg(pdev->bus, pdev->devfn,
 953                                             PCI_COMMAND, 2, word32);
 954
 955                         /* Status register bits are "write 1 to clear". */
 956                         sabre_write_pci_cfg(pdev->bus, pdev->devfn,
 957                                             PCI_STATUS, 2, 0xffff);
 958                         sabre_write_pci_cfg(pdev->bus, pdev->devfn,
 959                                             PCI_SEC_STATUS, 2, 0xffff);
 960
 961                         /* Use a primary/seconday latency timer value
 962                          * of 64.
 963                          */
 964                         sabre_write_pci_cfg(pdev->bus, pdev->devfn,
 965                                             PCI_LATENCY_TIMER, 1, 64);
 966                         sabre_write_pci_cfg(pdev->bus, pdev->devfn,
 967                                             PCI_SEC_LATENCY_TIMER, 1, 64);
 968
 969                         /* Enable reporting/forwarding of master aborts,
 970                          * parity, and SERR.
 971                          */
 972                         sabre_write_pci_cfg(pdev->bus, pdev->devfn,
 973                                             PCI_BRIDGE_CONTROL, 1,
 974                                             (PCI_BRIDGE_CTL_PARITY |
 975                                              PCI_BRIDGE_CTL_SERR |
 976                                              PCI_BRIDGE_CTL_MASTER_ABORT));
 977                 }
 978         }
 979 }
 980
 981 static struct pcidev_cookie *alloc_bridge_cookie(struct pci_pbm_info *pbm)
 982 {
 983         struct pcidev_cookie *cookie = kzalloc(sizeof(*cookie), GFP_KERNEL);
 984
 985         if (!cookie) {
 986                 prom_printf("SABRE: Critical allocation failure.\n");
 987                 prom_halt();
 988         }
 989
 990         /* All we care about is the PBM. */
 991         cookie->pbm = pbm;
 992
 993         return cookie;
 994 }
 995
 996 static void sabre_scan_bus(struct pci_controller_info *p)
 997 {
 998         static int once;
 999         struct pci_bus *sabre_bus, *pbus;
1000         struct pci_pbm_info *pbm;
1001         struct pcidev_cookie *cookie;
1002         int sabres_scanned;
1003
1004         /* The APB bridge speaks to the Sabre host PCI bridge
1005          * at 66Mhz, but the front side of APB runs at 33Mhz
1006          * for both segments.
1007          */
1008         p->pbm_A.is_66mhz_capable = 0;
1009         p->pbm_B.is_66mhz_capable = 0;
1010
1011         /* This driver has not been verified to handle
1012          * multiple SABREs yet, so trap this.
1013          *
1014          * Also note that the SABRE host bridge is hardwired
1015          * to live at bus 0.
1016          */
1017         if (once != 0) {
1018                 prom_printf("SABRE: Multiple controllers unsupported.\n");
1019                 prom_halt();
1020         }
1021         once++;
1022
1023         cookie = alloc_bridge_cookie(&p->pbm_A);
1024
1025         sabre_bus = pci_scan_bus(p->pci_first_busno,
1026                                  p->pci_ops,
1027                                  &p->pbm_A);
1028         pci_fixup_host_bridge_self(sabre_bus);
1029         sabre_bus->self->sysdata = cookie;
1030
1031         sabre_root_bus = sabre_bus;
1032
1033         apb_init(p, sabre_bus);
1034
1035         sabres_scanned = 0;
1036
1037         list_for_each_entry(pbus, &sabre_bus->children, node) {
1038
1039                 if (pbus->number == p->pbm_A.pci_first_busno) {
1040                         pbm = &p->pbm_A;
1041                 } else if (pbus->number == p->pbm_B.pci_first_busno) {
1042                         pbm = &p->pbm_B;
1043                 } else
1044                         continue;
1045
1046                 cookie = alloc_bridge_cookie(pbm);
1047                 pbus->self->sysdata = cookie;
1048
1049                 sabres_scanned++;
1050
1051                 pbus->sysdata = pbm;
1052                 pbm->pci_bus = pbus;
1053                 pci_fill_in_pbm_cookies(pbus, pbm, pbm->prom_node);
1054                 pci_record_assignments(pbm, pbus);
1055                 pci_assign_unassigned(pbm, pbus);
1056                 pci_fixup_irq(pbm, pbus);
1057                 pci_determine_66mhz_disposition(pbm, pbus);
1058                 pci_setup_busmastering(pbm, pbus);
1059         }
1060
1061         if (!sabres_scanned) {
1062                 /* Hummingbird, no APBs. */
1063                 pbm = &p->pbm_A;
1064                 sabre_bus->sysdata = pbm;
1065                 pbm->pci_bus = sabre_bus;
1066                 pci_fill_in_pbm_cookies(sabre_bus, pbm, pbm->prom_node);
1067                 pci_record_assignments(pbm, sabre_bus);
1068                 pci_assign_unassigned(pbm, sabre_bus);
1069                 pci_fixup_irq(pbm, sabre_bus);
1070                 pci_determine_66mhz_disposition(pbm, sabre_bus);
1071                 pci_setup_busmastering(pbm, sabre_bus);
1072         }
1073
1074         sabre_register_error_handlers(p);
1075 }
1076
1077 static void sabre_iommu_init(struct pci_controller_info *p,
1078                              int tsbsize, unsigned long dvma_offset,
1079                              u32 dma_mask)
1080 {
1081         struct pci_iommu *iommu = p->pbm_A.iommu;
1082         unsigned long i;
1083         u64 control;
1084
1085         /* Register addresses. */
1086         iommu->iommu_control  = p->pbm_A.controller_regs + SABRE_IOMMU_CONTROL;
1087         iommu->iommu_tsbbase  = p->pbm_A.controller_regs + SABRE_IOMMU_TSBBASE;
1088         iommu->iommu_flush    = p->pbm_A.controller_regs + SABRE_IOMMU_FLUSH;
1089         iommu->write_complete_reg = p->pbm_A.controller_regs + SABRE_WRSYNC;
1090         /* Sabre's IOMMU lacks ctx flushing. */
1091         iommu->iommu_ctxflush = 0;
1092
1093         /* Invalidate TLB Entries. */
1094         control = sabre_read(p->pbm_A.controller_regs + SABRE_IOMMU_CONTROL);
1095         control |= SABRE_IOMMUCTRL_DENAB;
1096         sabre_write(p->pbm_A.controller_regs + SABRE_IOMMU_CONTROL, control);
1097
1098         for(i = 0; i < 16; i++) {
1099                 sabre_write(p->pbm_A.controller_regs + SABRE_IOMMU_TAG + (i * 8UL), 0);
1100                 sabre_write(p->pbm_A.controller_regs + SABRE_IOMMU_DATA + (i * 8UL), 0);
1101         }
1102
1103         /* Leave diag mode enabled for full-flushing done
1104          * in pci_iommu.c
1105          */
1106         pci_iommu_table_init(iommu, tsbsize * 1024 * 8, dvma_offset, dma_mask);
1107
1108         sabre_write(p->pbm_A.controller_regs + SABRE_IOMMU_TSBBASE,
1109                     __pa(iommu->page_table));
1110
1111         control = sabre_read(p->pbm_A.controller_regs + SABRE_IOMMU_CONTROL);
1112         control &= ~(SABRE_IOMMUCTRL_TSBSZ | SABRE_IOMMUCTRL_TBWSZ);
1113         control |= SABRE_IOMMUCTRL_ENAB;
1114         switch(tsbsize) {
1115         case 64:
1116                 control |= SABRE_IOMMU_TSBSZ_64K;
1117                 break;
1118         case 128:
1119                 control |= SABRE_IOMMU_TSBSZ_128K;
1120                 break;
1121         default:
1122                 prom_printf("iommu_init: Illegal TSB size %d\n", tsbsize);
1123                 prom_halt();
1124                 break;
1125         }
1126         sabre_write(p->pbm_A.controller_regs + SABRE_IOMMU_CONTROL, control);
1127 }
1128
1129 static void pbm_register_toplevel_resources(struct pci_controller_info *p,
1130                                             struct pci_pbm_info *pbm)
1131 {
1132         char *name = pbm->name;
1133         unsigned long ibase = p->pbm_A.controller_regs + SABRE_IOSPACE;
1134         unsigned long mbase = p->pbm_A.controller_regs + SABRE_MEMSPACE;
1135         unsigned int devfn;
1136         unsigned long first, last, i;
1137         u8 *addr, map;
1138
1139         sprintf(name, "SABRE%d PBM%c",
1140                 p->index,
1141                 (pbm == &p->pbm_A ? 'A' : 'B'));
1142         pbm->io_space.name = pbm->mem_space.name = name;
1143
1144         devfn = PCI_DEVFN(1, (pbm == &p->pbm_A) ? 0 : 1);
1145         addr = sabre_pci_config_mkaddr(pbm, 0, devfn, APB_IO_ADDRESS_MAP);
1146         map = 0;
1147         pci_config_read8(addr, &map);
1148
1149         first = 8;
1150         last = 0;
1151         for (i = 0; i < 8; i++) {
1152                 if ((map & (1 << i)) != 0) {
1153                         if (first > i)
1154                                 first = i;
1155                         if (last < i)
1156                                 last = i;
1157                 }
1158         }
1159         pbm->io_space.start = ibase + (first << 21UL);
1160         pbm->io_space.end   = ibase + (last << 21UL) + ((1 << 21UL) - 1);
1161         pbm->io_space.flags = IORESOURCE_IO;
1162
1163         addr = sabre_pci_config_mkaddr(pbm, 0, devfn, APB_MEM_ADDRESS_MAP);
1164         map = 0;
1165         pci_config_read8(addr, &map);
1166
1167         first = 8;
1168         last = 0;
1169         for (i = 0; i < 8; i++) {
1170                 if ((map & (1 << i)) != 0) {
1171                         if (first > i)
1172                                 first = i;
1173                         if (last < i)
1174                                 last = i;
1175                 }
1176         }
1177         pbm->mem_space.start = mbase + (first << 29UL);
1178         pbm->mem_space.end   = mbase + (last << 29UL) + ((1 << 29UL) - 1);
1179         pbm->mem_space.flags = IORESOURCE_MEM;
1180
1181         if (request_resource(&ioport_resource, &pbm->io_space) < 0) {
1182                 prom_printf("Cannot register PBM-%c's IO space.\n",
1183                             (pbm == &p->pbm_A ? 'A' : 'B'));
1184                 prom_halt();
1185         }
1186         if (request_resource(&iomem_resource, &pbm->mem_space) < 0) {
1187                 prom_printf("Cannot register PBM-%c's MEM space.\n",
1188                             (pbm == &p->pbm_A ? 'A' : 'B'));
1189                 prom_halt();
1190         }
1191
1192         /* Register legacy regions if this PBM covers that area. */
1193         if (pbm->io_space.start == ibase &&
1194             pbm->mem_space.start == mbase)
1195                 pci_register_legacy_regions(&pbm->io_space,
1196                                             &pbm->mem_space);
1197 }
1198
1199 static void sabre_pbm_init(struct pci_controller_info *p, struct device_node *dp, u32 dma_begin)
1200 {
1201         struct pci_pbm_info *pbm;
1202         struct device_node *node;
1203         struct property *prop;
1204         u32 *busrange;
1205         int len, simbas_found;
1206
1207         simbas_found = 0;
1208         node = dp->child;
1209         while (node != NULL) {
1210                 if (strcmp(node->name, "pci"))
1211                         goto next_pci;
1212
1213                 prop = of_find_property(node, "model", NULL);
1214                 if (!prop || strncmp(prop->value, "SUNW,simba", prop->length))
1215                         goto next_pci;
1216
1217                 simbas_found++;
1218
1219                 prop = of_find_property(node, "bus-range", NULL);
1220                 busrange = prop->value;
1221                 if (busrange[0] == 1)
1222                         pbm = &p->pbm_B;
1223                 else
1224                         pbm = &p->pbm_A;
1225
1226                 pbm->name = node->full_name;
1227                 printk("%s: SABRE PCI Bus Module\n", pbm->name);
1228
1229                 pbm->chip_type = PBM_CHIP_TYPE_SABRE;
1230                 pbm->parent = p;
1231                 pbm->prom_node = node;
1232                 pbm->pci_first_slot = 1;
1233                 pbm->pci_first_busno = busrange[0];
1234                 pbm->pci_last_busno = busrange[1];
1235
1236                 prop = of_find_property(node, "ranges", &len);
1237                 if (prop) {
1238                         pbm->pbm_ranges = prop->value;
1239                         pbm->num_pbm_ranges =
1240                                 (len / sizeof(struct linux_prom_pci_ranges));
1241                 } else {
1242                         pbm->num_pbm_ranges = 0;
1243                 }
1244
1245                 prop = of_find_property(node, "interrupt-map", &len);
1246                 if (prop) {
1247                         pbm->pbm_intmap = prop->value;
1248                         pbm->num_pbm_intmap =
1249                                 (len / sizeof(struct linux_prom_pci_intmap));
1250
1251                         prop = of_find_property(node, "interrupt-map-mask",
1252                                                 NULL);
1253                         pbm->pbm_intmask = prop->value;
1254                 } else {
1255                         pbm->num_pbm_intmap = 0;
1256                 }
1257
1258                 pbm_register_toplevel_resources(p, pbm);
1259
1260         next_pci:
1261                 node = node->sibling;
1262         }
1263         if (simbas_found == 0) {
1264                 /* No APBs underneath, probably this is a hummingbird
1265                  * system.
1266                  */
1267                 pbm = &p->pbm_A;
1268                 pbm->parent = p;
1269                 pbm->prom_node = dp;
1270                 pbm->pci_first_busno = p->pci_first_busno;
1271                 pbm->pci_last_busno = p->pci_last_busno;
1272
1273                 prop = of_find_property(dp, "ranges", &len);
1274                 if (prop) {
1275                         pbm->pbm_ranges = prop->value;
1276                         pbm->num_pbm_ranges =
1277                                 (len / sizeof(struct linux_prom_pci_ranges));
1278                 } else {
1279                         pbm->num_pbm_ranges = 0;
1280                 }
1281
1282                 prop = of_find_property(dp, "interrupt-map", &len);
1283                 if (prop) {
1284                         pbm->pbm_intmap = prop->value;
1285                         pbm->num_pbm_intmap =
1286                                 (len / sizeof(struct linux_prom_pci_intmap));
1287
1288                         prop = of_find_property(dp, "interrupt-map-mask",
1289                                                 NULL);
1290                         pbm->pbm_intmask = prop->value;
1291                 } else {
1292                         pbm->num_pbm_intmap = 0;
1293                 }
1294
1295                 pbm->name = dp->full_name;
1296                 printk("%s: SABRE PCI Bus Module\n", pbm->name);
1297
1298                 pbm->io_space.name = pbm->mem_space.name = pbm->name;
1299
1300                 /* Hack up top-level resources. */
1301                 pbm->io_space.start = p->pbm_A.controller_regs + SABRE_IOSPACE;
1302                 pbm->io_space.end   = pbm->io_space.start + (1UL << 24) - 1UL;
1303                 pbm->io_space.flags = IORESOURCE_IO;
1304
1305                 pbm->mem_space.start = p->pbm_A.controller_regs + SABRE_MEMSPACE;
1306                 pbm->mem_space.end   = pbm->mem_space.start + (unsigned long)dma_begin - 1UL;
1307                 pbm->mem_space.flags = IORESOURCE_MEM;
1308
1309                 if (request_resource(&ioport_resource, &pbm->io_space) < 0) {
1310                         prom_printf("Cannot register Hummingbird's IO space.\n");
1311                         prom_halt();
1312                 }
1313                 if (request_resource(&iomem_resource, &pbm->mem_space) < 0) {
1314                         prom_printf("Cannot register Hummingbird's MEM space.\n");
1315                         prom_halt();
1316                 }
1317
1318                 pci_register_legacy_regions(&pbm->io_space,
1319                                             &pbm->mem_space);
1320         }
1321 }
1322
1323 void sabre_init(struct device_node *dp, char *model_name)
1324 {
1325         struct linux_prom64_registers *pr_regs;
1326         struct pci_controller_info *p;
1327         struct pci_iommu *iommu;
1328         struct property *prop;
1329         int tsbsize;
1330         u32 *busrange;
1331         u32 *vdma;
1332         u32 upa_portid, dma_mask;
1333         u64 clear_irq;
1334
1335         hummingbird_p = 0;
1336         if (!strcmp(model_name, "pci108e,a001"))
1337                 hummingbird_p = 1;
1338         else if (!strcmp(model_name, "SUNW,sabre")) {
1339                 prop = of_find_property(dp, "compatible", NULL);
1340                 if (prop) {
1341                         const char *compat = prop->value;
1342
1343                         if (!strcmp(compat, "pci108e,a001"))
1344                                 hummingbird_p = 1;
1345                 }
1346                 if (!hummingbird_p) {
1347                         struct device_node *dp;
1348
1349                         /* Of course, Sun has to encode things a thousand
1350                          * different ways, inconsistently.
1351                          */
1352                         cpu_find_by_instance(0, &dp, NULL);
1353                         if (!strcmp(dp->name, "SUNW,UltraSPARC-IIe"))
1354                                 hummingbird_p = 1;
1355                 }
1356         }
1357
1358         p = kzalloc(sizeof(*p), GFP_ATOMIC);
1359         if (!p) {
1360                 prom_printf("SABRE: Error, kmalloc(pci_controller_info) failed.\n");
1361                 prom_halt();
1362         }
1363
1364         iommu = kzalloc(sizeof(*iommu), GFP_ATOMIC);
1365         if (!iommu) {
1366                 prom_printf("SABRE: Error, kmalloc(pci_iommu) failed.\n");
1367                 prom_halt();
1368         }
1369         p->pbm_A.iommu = p->pbm_B.iommu = iommu;
1370
1371         upa_portid = 0xff;
1372         prop = of_find_property(dp, "upa-portid", NULL);
1373         if (prop)
1374                 upa_portid = *(u32 *) prop->value;
1375
1376         p->next = pci_controller_root;
1377         pci_controller_root = p;
1378
1379         p->pbm_A.portid = upa_portid;
1380         p->pbm_B.portid = upa_portid;
1381         p->index = pci_num_controllers++;
1382         p->pbms_same_domain = 1;
1383         p->scan_bus = sabre_scan_bus;
1384         p->base_address_update = sabre_base_address_update;
1385         p->resource_adjust = sabre_resource_adjust;
1386         p->pci_ops = &sabre_ops;
1387
1388         /*
1389          * Map in SABRE register set and report the presence of this SABRE.
1390          */
1391
1392         prop = of_find_property(dp, "reg", NULL);
1393         pr_regs = prop->value;
1394
1395         /*
1396          * First REG in property is base of entire SABRE register space.
1397          */
1398         p->pbm_A.controller_regs = pr_regs[0].phys_addr;
1399         p->pbm_B.controller_regs = pr_regs[0].phys_addr;
1400
1401         /* Clear interrupts */
1402
1403         /* PCI first */
1404         for (clear_irq = SABRE_ICLR_A_SLOT0; clear_irq < SABRE_ICLR_B_SLOT0 + 0x80; clear_irq += 8)
1405                 sabre_write(p->pbm_A.controller_regs + clear_irq, 0x0UL);
1406
1407         /* Then OBIO */
1408         for (clear_irq = SABRE_ICLR_SCSI; clear_irq < SABRE_ICLR_SCSI + 0x80; clear_irq += 8)
1409                 sabre_write(p->pbm_A.controller_regs + clear_irq, 0x0UL);
1410
1411         /* Error interrupts are enabled later after the bus scan. */
1412         sabre_write(p->pbm_A.controller_regs + SABRE_PCICTRL,
1413                     (SABRE_PCICTRL_MRLEN   | SABRE_PCICTRL_SERR |
1414                      SABRE_PCICTRL_ARBPARK | SABRE_PCICTRL_AEN));
1415
1416         /* Now map in PCI config space for entire SABRE. */
1417         p->pbm_A.config_space = p->pbm_B.config_space =
1418                 (p->pbm_A.controller_regs + SABRE_CONFIGSPACE);
1419
1420         prop = of_find_property(dp, "virtual-dma", NULL);
1421         vdma = prop->value;
1422
1423         dma_mask = vdma[0];
1424         switch(vdma[1]) {
1425                 case 0x20000000:
1426                         dma_mask |= 0x1fffffff;
1427                         tsbsize = 64;
1428                         break;
1429                 case 0x40000000:
1430                         dma_mask |= 0x3fffffff;
1431                         tsbsize = 128;
1432                         break;
1433
1434                 case 0x80000000:
1435                         dma_mask |= 0x7fffffff;
1436                         tsbsize = 128;
1437                         break;
1438                 default:
1439                         prom_printf("SABRE: strange virtual-dma size.\n");
1440                         prom_halt();
1441         }
1442
1443         sabre_iommu_init(p, tsbsize, vdma[0], dma_mask);
1444
1445         prop = of_find_property(dp, "bus-range", NULL);
1446         busrange = prop->value;
1447         p->pci_first_busno = busrange[0];
1448         p->pci_last_busno = busrange[1];
1449
1450         /*
1451          * Look for APB underneath.
1452          */
1453         sabre_pbm_init(p, dp, vdma[0]);
1454 }