2 * Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com>
3 * Copyright (c) 1999-2000 Grant Erickson <grant@lcse.umn.edu>
6 * Architecture- / platform-specific boot-time initialization code for
7 * the IBM iSeries LPAR. Adapted from original code by Grant Erickson and
8 * code by Gary Thomas, Cort Dougan <cort@fsmlabs.com>, and Dan Malek
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version
14 * 2 of the License, or (at your option) any later version.
19 #include <linux/config.h>
20 #include <linux/init.h>
21 #include <linux/threads.h>
22 #include <linux/smp.h>
23 #include <linux/param.h>
24 #include <linux/string.h>
25 #include <linux/initrd.h>
26 #include <linux/seq_file.h>
27 #include <linux/kdev_t.h>
28 #include <linux/major.h>
29 #include <linux/root_dev.h>
30 #include <linux/kernel.h>
32 #include <asm/processor.h>
33 #include <asm/machdep.h>
36 #include <asm/pgtable.h>
37 #include <asm/mmu_context.h>
38 #include <asm/cputable.h>
39 #include <asm/sections.h>
40 #include <asm/iommu.h>
41 #include <asm/firmware.h>
42 #include <asm/system.h>
45 #include <asm/cache.h>
46 #include <asm/sections.h>
47 #include <asm/abs_addr.h>
48 #include <asm/iseries/hv_lp_config.h>
49 #include <asm/iseries/hv_call_event.h>
50 #include <asm/iseries/hv_call_xm.h>
51 #include <asm/iseries/it_lp_queue.h>
52 #include <asm/iseries/mf.h>
53 #include <asm/iseries/hv_lp_event.h>
54 #include <asm/iseries/lpar_map.h>
60 #include "vpd_areas.h"
61 #include "processor_vpd.h"
62 #include "main_store.h"
67 #define DBG(fmt...) udbg_printf(fmt)
72 /* Function Prototypes */
73 static unsigned long build_iSeries_Memory_Map(void);
74 static void iseries_shared_idle(void);
75 static void iseries_dedicated_idle(void);
77 extern void iSeries_pci_final_fixup(void);
79 static void iSeries_pci_final_fixup(void) { }
82 /* Global Variables */
83 int piranha_simulator;
85 extern int rd_size; /* Defined in drivers/block/rd.c */
86 extern unsigned long embedded_sysmap_start;
87 extern unsigned long embedded_sysmap_end;
89 extern unsigned long iSeries_recal_tb;
90 extern unsigned long iSeries_recal_titan;
92 static int mf_initialized;
94 static unsigned long cmd_mem_limit;
97 unsigned long absStart;
99 unsigned long logicalStart;
100 unsigned long logicalEnd;
104 * Process the main store vpd to determine where the holes in memory are
105 * and return the number of physical blocks and fill in the array of
108 static unsigned long iSeries_process_Condor_mainstore_vpd(
109 struct MemoryBlock *mb_array, unsigned long max_entries)
111 unsigned long holeFirstChunk, holeSizeChunks;
112 unsigned long numMemoryBlocks = 1;
113 struct IoHriMainStoreSegment4 *msVpd =
114 (struct IoHriMainStoreSegment4 *)xMsVpd;
115 unsigned long holeStart = msVpd->nonInterleavedBlocksStartAdr;
116 unsigned long holeEnd = msVpd->nonInterleavedBlocksEndAdr;
117 unsigned long holeSize = holeEnd - holeStart;
119 printk("Mainstore_VPD: Condor\n");
121 * Determine if absolute memory has any
122 * holes so that we can interpret the
123 * access map we get back from the hypervisor
126 mb_array[0].logicalStart = 0;
127 mb_array[0].logicalEnd = 0x100000000;
128 mb_array[0].absStart = 0;
129 mb_array[0].absEnd = 0x100000000;
133 holeStart = holeStart & 0x000fffffffffffff;
134 holeStart = addr_to_chunk(holeStart);
135 holeFirstChunk = holeStart;
136 holeSize = addr_to_chunk(holeSize);
137 holeSizeChunks = holeSize;
138 printk( "Main store hole: start chunk = %0lx, size = %0lx chunks\n",
139 holeFirstChunk, holeSizeChunks );
140 mb_array[0].logicalEnd = holeFirstChunk;
141 mb_array[0].absEnd = holeFirstChunk;
142 mb_array[1].logicalStart = holeFirstChunk;
143 mb_array[1].logicalEnd = 0x100000000 - holeSizeChunks;
144 mb_array[1].absStart = holeFirstChunk + holeSizeChunks;
145 mb_array[1].absEnd = 0x100000000;
147 return numMemoryBlocks;
150 #define MaxSegmentAreas 32
151 #define MaxSegmentAdrRangeBlocks 128
152 #define MaxAreaRangeBlocks 4
154 static unsigned long iSeries_process_Regatta_mainstore_vpd(
155 struct MemoryBlock *mb_array, unsigned long max_entries)
157 struct IoHriMainStoreSegment5 *msVpdP =
158 (struct IoHriMainStoreSegment5 *)xMsVpd;
159 unsigned long numSegmentBlocks = 0;
160 u32 existsBits = msVpdP->msAreaExists;
161 unsigned long area_num;
163 printk("Mainstore_VPD: Regatta\n");
165 for (area_num = 0; area_num < MaxSegmentAreas; ++area_num ) {
166 unsigned long numAreaBlocks;
167 struct IoHriMainStoreArea4 *currentArea;
169 if (existsBits & 0x80000000) {
170 unsigned long block_num;
172 currentArea = &msVpdP->msAreaArray[area_num];
173 numAreaBlocks = currentArea->numAdrRangeBlocks;
174 printk("ms_vpd: processing area %2ld blocks=%ld",
175 area_num, numAreaBlocks);
176 for (block_num = 0; block_num < numAreaBlocks;
178 /* Process an address range block */
179 struct MemoryBlock tempBlock;
183 (unsigned long)currentArea->xAdrRangeBlock[block_num].blockStart;
185 (unsigned long)currentArea->xAdrRangeBlock[block_num].blockEnd;
186 tempBlock.logicalStart = 0;
187 tempBlock.logicalEnd = 0;
188 printk("\n block %ld absStart=%016lx absEnd=%016lx",
189 block_num, tempBlock.absStart,
192 for (i = 0; i < numSegmentBlocks; ++i) {
193 if (mb_array[i].absStart ==
197 if (i == numSegmentBlocks) {
198 if (numSegmentBlocks == max_entries)
199 panic("iSeries_process_mainstore_vpd: too many memory blocks");
200 mb_array[numSegmentBlocks] = tempBlock;
203 printk(" (duplicate)");
209 /* Now sort the blocks found into ascending sequence */
210 if (numSegmentBlocks > 1) {
213 for (m = 0; m < numSegmentBlocks - 1; ++m) {
214 for (n = numSegmentBlocks - 1; m < n; --n) {
215 if (mb_array[n].absStart <
216 mb_array[n-1].absStart) {
217 struct MemoryBlock tempBlock;
219 tempBlock = mb_array[n];
220 mb_array[n] = mb_array[n-1];
221 mb_array[n-1] = tempBlock;
227 * Assign "logical" addresses to each block. These
228 * addresses correspond to the hypervisor "bitmap" space.
229 * Convert all addresses into units of 256K chunks.
232 unsigned long i, nextBitmapAddress;
234 printk("ms_vpd: %ld sorted memory blocks\n", numSegmentBlocks);
235 nextBitmapAddress = 0;
236 for (i = 0; i < numSegmentBlocks; ++i) {
237 unsigned long length = mb_array[i].absEnd -
238 mb_array[i].absStart;
240 mb_array[i].logicalStart = nextBitmapAddress;
241 mb_array[i].logicalEnd = nextBitmapAddress + length;
242 nextBitmapAddress += length;
243 printk(" Bitmap range: %016lx - %016lx\n"
244 " Absolute range: %016lx - %016lx\n",
245 mb_array[i].logicalStart,
246 mb_array[i].logicalEnd,
247 mb_array[i].absStart, mb_array[i].absEnd);
248 mb_array[i].absStart = addr_to_chunk(mb_array[i].absStart &
250 mb_array[i].absEnd = addr_to_chunk(mb_array[i].absEnd &
252 mb_array[i].logicalStart =
253 addr_to_chunk(mb_array[i].logicalStart);
254 mb_array[i].logicalEnd = addr_to_chunk(mb_array[i].logicalEnd);
258 return numSegmentBlocks;
261 static unsigned long iSeries_process_mainstore_vpd(struct MemoryBlock *mb_array,
262 unsigned long max_entries)
265 unsigned long mem_blocks = 0;
267 if (cpu_has_feature(CPU_FTR_SLB))
268 mem_blocks = iSeries_process_Regatta_mainstore_vpd(mb_array,
271 mem_blocks = iSeries_process_Condor_mainstore_vpd(mb_array,
274 printk("Mainstore_VPD: numMemoryBlocks = %ld \n", mem_blocks);
275 for (i = 0; i < mem_blocks; ++i) {
276 printk("Mainstore_VPD: block %3ld logical chunks %016lx - %016lx\n"
277 " abs chunks %016lx - %016lx\n",
278 i, mb_array[i].logicalStart, mb_array[i].logicalEnd,
279 mb_array[i].absStart, mb_array[i].absEnd);
284 static void __init iSeries_get_cmdline(void)
288 /* copy the command line parameter from the primary VSP */
289 HvCallEvent_dmaToSp(cmd_line, 2 * 64* 1024, 256,
290 HvLpDma_Direction_RemoteToLocal);
295 if (!*p || *p == '\n')
302 static void __init iSeries_init_early(void)
304 DBG(" -> iSeries_init_early()\n");
306 ppc64_interrupt_controller = IC_ISERIES;
308 #if defined(CONFIG_BLK_DEV_INITRD)
310 * If the init RAM disk has been configured and there is
311 * a non-zero starting address for it, set it up
314 initrd_start = (unsigned long)__va(naca.xRamDisk);
315 initrd_end = initrd_start + naca.xRamDiskSize * HW_PAGE_SIZE;
316 initrd_below_start_ok = 1; // ramdisk in kernel space
317 ROOT_DEV = Root_RAM0;
318 if (((rd_size * 1024) / HW_PAGE_SIZE) < naca.xRamDiskSize)
319 rd_size = (naca.xRamDiskSize * HW_PAGE_SIZE) / 1024;
321 #endif /* CONFIG_BLK_DEV_INITRD */
323 /* ROOT_DEV = MKDEV(VIODASD_MAJOR, 1); */
326 iSeries_recal_tb = get_tb();
327 iSeries_recal_titan = HvCallXm_loadTod();
330 * Initialize the hash table management pointers
335 * Initialize the DMA/TCE management
337 iommu_init_early_iSeries();
339 /* Initialize machine-dependency vectors */
343 if (itLpNaca.xPirEnvironMode == 0)
344 piranha_simulator = 1;
346 /* Associate Lp Event Queue 0 with processor 0 */
347 HvCallEvent_setLpEventQueueInterruptProc(0, 0);
353 /* If we were passed an initrd, set the ROOT_DEV properly if the values
354 * look sensible. If not, clear initrd reference.
356 #ifdef CONFIG_BLK_DEV_INITRD
357 if (initrd_start >= KERNELBASE && initrd_end >= KERNELBASE &&
358 initrd_end > initrd_start)
359 ROOT_DEV = Root_RAM0;
361 initrd_start = initrd_end = 0;
362 #endif /* CONFIG_BLK_DEV_INITRD */
364 DBG(" <- iSeries_init_early()\n");
367 struct mschunks_map mschunks_map = {
368 /* XXX We don't use these, but Piranha might need them. */
369 .chunk_size = MSCHUNKS_CHUNK_SIZE,
370 .chunk_shift = MSCHUNKS_CHUNK_SHIFT,
371 .chunk_mask = MSCHUNKS_OFFSET_MASK,
373 EXPORT_SYMBOL(mschunks_map);
375 void mschunks_alloc(unsigned long num_chunks)
377 klimit = _ALIGN(klimit, sizeof(u32));
378 mschunks_map.mapping = (u32 *)klimit;
379 klimit += num_chunks * sizeof(u32);
380 mschunks_map.num_chunks = num_chunks;
384 * The iSeries may have very large memories ( > 128 GB ) and a partition
385 * may get memory in "chunks" that may be anywhere in the 2**52 real
386 * address space. The chunks are 256K in size. To map this to the
387 * memory model Linux expects, the AS/400 specific code builds a
388 * translation table to translate what Linux thinks are "physical"
389 * addresses to the actual real addresses. This allows us to make
390 * it appear to Linux that we have contiguous memory starting at
391 * physical address zero while in fact this could be far from the truth.
392 * To avoid confusion, I'll let the words physical and/or real address
393 * apply to the Linux addresses while I'll use "absolute address" to
394 * refer to the actual hardware real address.
396 * build_iSeries_Memory_Map gets information from the Hypervisor and
397 * looks at the Main Store VPD to determine the absolute addresses
398 * of the memory that has been assigned to our partition and builds
399 * a table used to translate Linux's physical addresses to these
400 * absolute addresses. Absolute addresses are needed when
401 * communicating with the hypervisor (e.g. to build HPT entries)
403 * Returns the physical memory size
406 static unsigned long __init build_iSeries_Memory_Map(void)
408 u32 loadAreaFirstChunk, loadAreaLastChunk, loadAreaSize;
410 u32 hptFirstChunk, hptLastChunk, hptSizeChunks, hptSizePages;
411 u32 totalChunks,moreChunks;
412 u32 currChunk, thisChunk, absChunk;
416 struct MemoryBlock mb[32];
417 unsigned long numMemoryBlocks, curBlock;
419 /* Chunk size on iSeries is 256K bytes */
420 totalChunks = (u32)HvLpConfig_getMsChunks();
421 mschunks_alloc(totalChunks);
424 * Get absolute address of our load area
425 * and map it to physical address 0
426 * This guarantees that the loadarea ends up at physical 0
427 * otherwise, it might not be returned by PLIC as the first
431 loadAreaFirstChunk = (u32)addr_to_chunk(itLpNaca.xLoadAreaAddr);
432 loadAreaSize = itLpNaca.xLoadAreaChunks;
435 * Only add the pages already mapped here.
436 * Otherwise we might add the hpt pages
437 * The rest of the pages of the load area
438 * aren't in the HPT yet and can still
439 * be assigned an arbitrary physical address
441 if ((loadAreaSize * 64) > HvPagesToMap)
442 loadAreaSize = HvPagesToMap / 64;
444 loadAreaLastChunk = loadAreaFirstChunk + loadAreaSize - 1;
447 * TODO Do we need to do something if the HPT is in the 64MB load area?
448 * This would be required if the itLpNaca.xLoadAreaChunks includes
452 printk("Mapping load area - physical addr = 0000000000000000\n"
453 " absolute addr = %016lx\n",
454 chunk_to_addr(loadAreaFirstChunk));
455 printk("Load area size %dK\n", loadAreaSize * 256);
457 for (nextPhysChunk = 0; nextPhysChunk < loadAreaSize; ++nextPhysChunk)
458 mschunks_map.mapping[nextPhysChunk] =
459 loadAreaFirstChunk + nextPhysChunk;
462 * Get absolute address of our HPT and remember it so
463 * we won't map it to any physical address
465 hptFirstChunk = (u32)addr_to_chunk(HvCallHpt_getHptAddress());
466 hptSizePages = (u32)HvCallHpt_getHptPages();
467 hptSizeChunks = hptSizePages >>
468 (MSCHUNKS_CHUNK_SHIFT - HW_PAGE_SHIFT);
469 hptLastChunk = hptFirstChunk + hptSizeChunks - 1;
471 printk("HPT absolute addr = %016lx, size = %dK\n",
472 chunk_to_addr(hptFirstChunk), hptSizeChunks * 256);
475 * Determine if absolute memory has any
476 * holes so that we can interpret the
477 * access map we get back from the hypervisor
480 numMemoryBlocks = iSeries_process_mainstore_vpd(mb, 32);
483 * Process the main store access map from the hypervisor
484 * to build up our physical -> absolute translation table
489 moreChunks = totalChunks;
492 map = HvCallSm_get64BitsOfAccessMap(itLpNaca.xLpIndex,
494 thisChunk = currChunk;
496 chunkBit = map >> 63;
500 while (thisChunk >= mb[curBlock].logicalEnd) {
502 if (curBlock >= numMemoryBlocks)
503 panic("out of memory blocks");
505 if (thisChunk < mb[curBlock].logicalStart)
506 panic("memory block error");
508 absChunk = mb[curBlock].absStart +
509 (thisChunk - mb[curBlock].logicalStart);
510 if (((absChunk < hptFirstChunk) ||
511 (absChunk > hptLastChunk)) &&
512 ((absChunk < loadAreaFirstChunk) ||
513 (absChunk > loadAreaLastChunk))) {
514 mschunks_map.mapping[nextPhysChunk] =
526 * main store size (in chunks) is
527 * totalChunks - hptSizeChunks
528 * which should be equal to
531 return chunk_to_addr(nextPhysChunk);
537 static void __init iSeries_setup_arch(void)
539 if (get_lppaca()->shared_proc) {
540 ppc_md.idle_loop = iseries_shared_idle;
541 printk(KERN_INFO "Using shared processor idle loop\n");
543 ppc_md.idle_loop = iseries_dedicated_idle;
544 printk(KERN_INFO "Using dedicated idle loop\n");
547 /* Setup the Lp Event Queue */
548 setup_hvlpevent_queue();
550 printk("Max logical processors = %d\n",
551 itVpdAreas.xSlicMaxLogicalProcs);
552 printk("Max physical processors = %d\n",
553 itVpdAreas.xSlicMaxPhysicalProcs);
556 static void iSeries_show_cpuinfo(struct seq_file *m)
558 seq_printf(m, "machine\t\t: 64-bit iSeries Logical Partition\n");
564 static void iSeries_restart(char *cmd)
572 static void iSeries_power_off(void)
580 static void iSeries_halt(void)
585 static void __init iSeries_progress(char * st, unsigned short code)
587 printk("Progress: [%04x] - %s\n", (unsigned)code, st);
588 if (!piranha_simulator && mf_initialized) {
590 mf_display_progress(code);
596 static void __init iSeries_fixup_klimit(void)
599 * Change klimit to take into account any ram disk
600 * that may be included
603 klimit = KERNELBASE + (u64)naca.xRamDisk +
604 (naca.xRamDiskSize * HW_PAGE_SIZE);
607 * No ram disk was included - check and see if there
608 * was an embedded system map. Change klimit to take
609 * into account any embedded system map
611 if (embedded_sysmap_end)
612 klimit = KERNELBASE + ((embedded_sysmap_end + 4095) &
617 static int __init iSeries_src_init(void)
619 /* clear the progress line */
620 ppc_md.progress(" ", 0xffff);
624 late_initcall(iSeries_src_init);
626 static inline void process_iSeries_events(void)
628 asm volatile ("li 0,0x5555; sc" : : : "r0", "r3");
631 static void yield_shared_processor(void)
635 HvCall_setEnabledInterrupts(HvCall_MaskIPI |
641 /* Compute future tb value when yield should expire */
642 HvCall_yieldProcessor(HvCall_YieldTimed, tb+tb_ticks_per_jiffy);
645 * The decrementer stops during the yield. Force a fake decrementer
646 * here and let the timer_interrupt code sort out the actual time.
648 get_lppaca()->int_dword.fields.decr_int = 1;
650 process_iSeries_events();
653 static void iseries_shared_idle(void)
656 while (!need_resched() && !hvlpevent_is_pending()) {
658 ppc64_runlatch_off();
660 /* Recheck with irqs off */
661 if (!need_resched() && !hvlpevent_is_pending())
662 yield_shared_processor();
670 if (hvlpevent_is_pending())
671 process_iSeries_events();
673 preempt_enable_no_resched();
679 static void iseries_dedicated_idle(void)
681 set_thread_flag(TIF_POLLING_NRFLAG);
684 if (!need_resched()) {
685 while (!need_resched()) {
686 ppc64_runlatch_off();
689 if (hvlpevent_is_pending()) {
692 process_iSeries_events();
700 preempt_enable_no_resched();
707 void __init iSeries_init_IRQ(void) { }
710 static int __init iseries_probe(int platform)
712 if (PLATFORM_ISERIES_LPAR != platform)
715 ppc64_firmware_features |= FW_FEATURE_ISERIES;
716 ppc64_firmware_features |= FW_FEATURE_LPAR;
721 struct machdep_calls __initdata iseries_md = {
722 .setup_arch = iSeries_setup_arch,
723 .show_cpuinfo = iSeries_show_cpuinfo,
724 .init_IRQ = iSeries_init_IRQ,
725 .get_irq = iSeries_get_irq,
726 .init_early = iSeries_init_early,
727 .pcibios_fixup = iSeries_pci_final_fixup,
728 .restart = iSeries_restart,
729 .power_off = iSeries_power_off,
730 .halt = iSeries_halt,
731 .get_boot_time = iSeries_get_boot_time,
732 .set_rtc_time = iSeries_set_rtc_time,
733 .get_rtc_time = iSeries_get_rtc_time,
734 .calibrate_decr = generic_calibrate_decr,
735 .progress = iSeries_progress,
736 .probe = iseries_probe,
737 /* XXX Implement enable_pmcs for iSeries */
741 unsigned char data[PAGE_SIZE];
745 struct iseries_flat_dt {
746 struct boot_param_header header;
752 struct iseries_flat_dt iseries_dt;
754 void dt_init(struct iseries_flat_dt *dt)
756 dt->header.off_mem_rsvmap =
757 offsetof(struct iseries_flat_dt, reserve_map);
758 dt->header.off_dt_struct = offsetof(struct iseries_flat_dt, dt);
759 dt->header.off_dt_strings = offsetof(struct iseries_flat_dt, strings);
760 dt->header.totalsize = sizeof(struct iseries_flat_dt);
761 dt->header.dt_strings_size = sizeof(struct blob);
763 /* There is no notion of hardware cpu id on iSeries */
764 dt->header.boot_cpuid_phys = smp_processor_id();
766 dt->dt.next = (unsigned long)&dt->dt.data;
767 dt->strings.next = (unsigned long)&dt->strings.data;
769 dt->header.magic = OF_DT_HEADER;
770 dt->header.version = 0x10;
771 dt->header.last_comp_version = 0x10;
773 dt->reserve_map[0] = 0;
774 dt->reserve_map[1] = 0;
777 void dt_check_blob(struct blob *b)
779 if (b->next >= (unsigned long)&b->next) {
780 DBG("Ran out of space in flat device tree blob!\n");
785 void dt_push_u32(struct iseries_flat_dt *dt, u32 value)
787 *((u32*)dt->dt.next) = value;
788 dt->dt.next += sizeof(u32);
790 dt_check_blob(&dt->dt);
793 void dt_push_u64(struct iseries_flat_dt *dt, u64 value)
795 *((u64*)dt->dt.next) = value;
796 dt->dt.next += sizeof(u64);
798 dt_check_blob(&dt->dt);
801 unsigned long dt_push_bytes(struct blob *blob, char *data, int len)
803 unsigned long start = blob->next - (unsigned long)blob->data;
805 memcpy((char *)blob->next, data, len);
806 blob->next = _ALIGN(blob->next + len, 4);
813 void dt_start_node(struct iseries_flat_dt *dt, char *name)
815 dt_push_u32(dt, OF_DT_BEGIN_NODE);
816 dt_push_bytes(&dt->dt, name, strlen(name) + 1);
819 #define dt_end_node(dt) dt_push_u32(dt, OF_DT_END_NODE)
821 void dt_prop(struct iseries_flat_dt *dt, char *name, char *data, int len)
823 unsigned long offset;
825 dt_push_u32(dt, OF_DT_PROP);
827 /* Length of the data */
828 dt_push_u32(dt, len);
830 /* Put the property name in the string blob. */
831 offset = dt_push_bytes(&dt->strings, name, strlen(name) + 1);
833 /* The offset of the properties name in the string blob. */
834 dt_push_u32(dt, (u32)offset);
836 /* The actual data. */
837 dt_push_bytes(&dt->dt, data, len);
840 void dt_prop_str(struct iseries_flat_dt *dt, char *name, char *data)
842 dt_prop(dt, name, data, strlen(data) + 1); /* + 1 for NULL */
845 void dt_prop_u32(struct iseries_flat_dt *dt, char *name, u32 data)
847 dt_prop(dt, name, (char *)&data, sizeof(u32));
850 void dt_prop_u64(struct iseries_flat_dt *dt, char *name, u64 data)
852 dt_prop(dt, name, (char *)&data, sizeof(u64));
855 void dt_prop_u64_list(struct iseries_flat_dt *dt, char *name, u64 *data, int n)
857 dt_prop(dt, name, (char *)data, sizeof(u64) * n);
860 void dt_prop_u32_list(struct iseries_flat_dt *dt, char *name, u32 *data, int n)
862 dt_prop(dt, name, (char *)data, sizeof(u32) * n);
865 void dt_prop_empty(struct iseries_flat_dt *dt, char *name)
867 dt_prop(dt, name, NULL, 0);
870 void dt_cpus(struct iseries_flat_dt *dt)
872 unsigned char buf[32];
874 unsigned int i, index;
875 struct IoHriProcessorVpd *d;
879 snprintf(buf, 32, "PowerPC,%s", cur_cpu_spec->cpu_name);
880 p = strchr(buf, ' ');
881 if (!p) p = buf + strlen(buf);
883 dt_start_node(dt, "cpus");
884 dt_prop_u32(dt, "#address-cells", 1);
885 dt_prop_u32(dt, "#size-cells", 0);
887 pft_size[0] = 0; /* NUMA CEC cookie, 0 for non NUMA */
888 pft_size[1] = __ilog2(HvCallHpt_getHptPages() * HW_PAGE_SIZE);
890 for (i = 0; i < NR_CPUS; i++) {
891 if (lppaca[i].dyn_proc_status >= 2)
894 snprintf(p, 32 - (p - buf), "@%d", i);
895 dt_start_node(dt, buf);
897 dt_prop_str(dt, "device_type", "cpu");
899 index = lppaca[i].dyn_hv_phys_proc_index;
900 d = &xIoHriProcessorVpd[index];
902 dt_prop_u32(dt, "i-cache-size", d->xInstCacheSize * 1024);
903 dt_prop_u32(dt, "i-cache-line-size", d->xInstCacheOperandSize);
905 dt_prop_u32(dt, "d-cache-size", d->xDataL1CacheSizeKB * 1024);
906 dt_prop_u32(dt, "d-cache-line-size", d->xDataCacheOperandSize);
908 /* magic conversions to Hz copied from old code */
909 dt_prop_u32(dt, "clock-frequency",
910 ((1UL << 34) * 1000000) / d->xProcFreq);
911 dt_prop_u32(dt, "timebase-frequency",
912 ((1UL << 32) * 1000000) / d->xTimeBaseFreq);
914 dt_prop_u32(dt, "reg", i);
916 dt_prop_u32_list(dt, "ibm,pft-size", pft_size, 2);
924 void build_flat_dt(struct iseries_flat_dt *dt, unsigned long phys_mem_size)
930 dt_start_node(dt, "");
932 dt_prop_u32(dt, "#address-cells", 2);
933 dt_prop_u32(dt, "#size-cells", 2);
936 dt_start_node(dt, "memory@0");
937 dt_prop_str(dt, "name", "memory");
938 dt_prop_str(dt, "device_type", "memory");
940 tmp[1] = phys_mem_size;
941 dt_prop_u64_list(dt, "reg", tmp, 2);
945 dt_start_node(dt, "chosen");
946 dt_prop_u32(dt, "linux,platform", PLATFORM_ISERIES_LPAR);
948 dt_prop_u64(dt, "linux,memory-limit", cmd_mem_limit);
955 dt_push_u32(dt, OF_DT_END);
958 void * __init iSeries_early_setup(void)
960 unsigned long phys_mem_size;
962 iSeries_fixup_klimit();
965 * Initialize the table which translate Linux physical addresses to
966 * AS/400 absolute addresses
968 phys_mem_size = build_iSeries_Memory_Map();
970 iSeries_get_cmdline();
972 /* Save unparsed command line copy for /proc/cmdline */
973 strlcpy(saved_command_line, cmd_line, COMMAND_LINE_SIZE);
975 /* Parse early parameters, in particular mem=x */
978 build_flat_dt(&iseries_dt, phys_mem_size);
980 return (void *) __pa(&iseries_dt);
984 * On iSeries we just parse the mem=X option from the command line.
985 * On pSeries it's a bit more complicated, see prom_init_mem()
987 static int __init early_parsemem(char *p)
990 cmd_mem_limit = ALIGN(memparse(p, &p), PAGE_SIZE);
993 early_param("mem", early_parsemem);
995 static void hvputc(char c)
1000 HvCall_writeLogBuffer(&c, 1);
1003 void __init udbg_init_iseries(void)