2 * Copyright (C) 2003 - 2009 NetXen, Inc.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
20 * The full GNU General Public License is included in this distribution
21 * in the file called LICENSE.
23 * Contact Information:
27 * Cupertino, CA 95014-0701
31 #include "netxen_nic.h"
32 #include "netxen_nic_hw.h"
33 #include "netxen_nic_phan_reg.h"
35 #include <linux/firmware.h>
38 #define MASK(n) ((1ULL<<(n))-1)
39 #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff))
40 #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff))
41 #define MS_WIN(addr) (addr & 0x0ffc0000)
43 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
45 #define CRB_BLK(off) ((off >> 20) & 0x3f)
46 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
47 #define CRB_WINDOW_2M (0x130060)
48 #define CRB_HI(off) ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000))
49 #define CRB_INDIRECT_2M (0x1e0000UL)
52 static inline u64 readq(void __iomem *addr)
54 return readl(addr) | (((u64) readl(addr + 4)) << 32LL);
59 static inline void writeq(u64 val, void __iomem *addr)
61 writel(((u32) (val)), (addr));
62 writel(((u32) (val >> 32)), (addr + 4));
66 #define ADDR_IN_RANGE(addr, low, high) \
67 (((addr) < (high)) && ((addr) >= (low)))
69 #define PCI_OFFSET_FIRST_RANGE(adapter, off) \
70 ((adapter)->ahw.pci_base0 + (off))
71 #define PCI_OFFSET_SECOND_RANGE(adapter, off) \
72 ((adapter)->ahw.pci_base1 + (off) - SECOND_PAGE_GROUP_START)
73 #define PCI_OFFSET_THIRD_RANGE(adapter, off) \
74 ((adapter)->ahw.pci_base2 + (off) - THIRD_PAGE_GROUP_START)
76 static void __iomem *pci_base_offset(struct netxen_adapter *adapter,
79 if (ADDR_IN_RANGE(off, FIRST_PAGE_GROUP_START, FIRST_PAGE_GROUP_END))
80 return PCI_OFFSET_FIRST_RANGE(adapter, off);
82 if (ADDR_IN_RANGE(off, SECOND_PAGE_GROUP_START, SECOND_PAGE_GROUP_END))
83 return PCI_OFFSET_SECOND_RANGE(adapter, off);
85 if (ADDR_IN_RANGE(off, THIRD_PAGE_GROUP_START, THIRD_PAGE_GROUP_END))
86 return PCI_OFFSET_THIRD_RANGE(adapter, off);
91 #define CRB_WIN_LOCK_TIMEOUT 100000000
92 static crb_128M_2M_block_map_t
93 crb_128M_2M_map[64] __cacheline_aligned_in_smp = {
94 {{{0, 0, 0, 0} } }, /* 0: PCI */
95 {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */
96 {1, 0x0110000, 0x0120000, 0x130000},
97 {1, 0x0120000, 0x0122000, 0x124000},
98 {1, 0x0130000, 0x0132000, 0x126000},
99 {1, 0x0140000, 0x0142000, 0x128000},
100 {1, 0x0150000, 0x0152000, 0x12a000},
101 {1, 0x0160000, 0x0170000, 0x110000},
102 {1, 0x0170000, 0x0172000, 0x12e000},
103 {0, 0x0000000, 0x0000000, 0x000000},
104 {0, 0x0000000, 0x0000000, 0x000000},
105 {0, 0x0000000, 0x0000000, 0x000000},
106 {0, 0x0000000, 0x0000000, 0x000000},
107 {0, 0x0000000, 0x0000000, 0x000000},
108 {0, 0x0000000, 0x0000000, 0x000000},
109 {1, 0x01e0000, 0x01e0800, 0x122000},
110 {0, 0x0000000, 0x0000000, 0x000000} } },
111 {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
112 {{{0, 0, 0, 0} } }, /* 3: */
113 {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
114 {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */
115 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */
116 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */
117 {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */
118 {0, 0x0000000, 0x0000000, 0x000000},
119 {0, 0x0000000, 0x0000000, 0x000000},
120 {0, 0x0000000, 0x0000000, 0x000000},
121 {0, 0x0000000, 0x0000000, 0x000000},
122 {0, 0x0000000, 0x0000000, 0x000000},
123 {0, 0x0000000, 0x0000000, 0x000000},
124 {0, 0x0000000, 0x0000000, 0x000000},
125 {0, 0x0000000, 0x0000000, 0x000000},
126 {0, 0x0000000, 0x0000000, 0x000000},
127 {0, 0x0000000, 0x0000000, 0x000000},
128 {0, 0x0000000, 0x0000000, 0x000000},
129 {0, 0x0000000, 0x0000000, 0x000000},
130 {0, 0x0000000, 0x0000000, 0x000000},
131 {0, 0x0000000, 0x0000000, 0x000000},
132 {1, 0x08f0000, 0x08f2000, 0x172000} } },
133 {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/
134 {0, 0x0000000, 0x0000000, 0x000000},
135 {0, 0x0000000, 0x0000000, 0x000000},
136 {0, 0x0000000, 0x0000000, 0x000000},
137 {0, 0x0000000, 0x0000000, 0x000000},
138 {0, 0x0000000, 0x0000000, 0x000000},
139 {0, 0x0000000, 0x0000000, 0x000000},
140 {0, 0x0000000, 0x0000000, 0x000000},
141 {0, 0x0000000, 0x0000000, 0x000000},
142 {0, 0x0000000, 0x0000000, 0x000000},
143 {0, 0x0000000, 0x0000000, 0x000000},
144 {0, 0x0000000, 0x0000000, 0x000000},
145 {0, 0x0000000, 0x0000000, 0x000000},
146 {0, 0x0000000, 0x0000000, 0x000000},
147 {0, 0x0000000, 0x0000000, 0x000000},
148 {1, 0x09f0000, 0x09f2000, 0x176000} } },
149 {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/
150 {0, 0x0000000, 0x0000000, 0x000000},
151 {0, 0x0000000, 0x0000000, 0x000000},
152 {0, 0x0000000, 0x0000000, 0x000000},
153 {0, 0x0000000, 0x0000000, 0x000000},
154 {0, 0x0000000, 0x0000000, 0x000000},
155 {0, 0x0000000, 0x0000000, 0x000000},
156 {0, 0x0000000, 0x0000000, 0x000000},
157 {0, 0x0000000, 0x0000000, 0x000000},
158 {0, 0x0000000, 0x0000000, 0x000000},
159 {0, 0x0000000, 0x0000000, 0x000000},
160 {0, 0x0000000, 0x0000000, 0x000000},
161 {0, 0x0000000, 0x0000000, 0x000000},
162 {0, 0x0000000, 0x0000000, 0x000000},
163 {0, 0x0000000, 0x0000000, 0x000000},
164 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
165 {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/
166 {0, 0x0000000, 0x0000000, 0x000000},
167 {0, 0x0000000, 0x0000000, 0x000000},
168 {0, 0x0000000, 0x0000000, 0x000000},
169 {0, 0x0000000, 0x0000000, 0x000000},
170 {0, 0x0000000, 0x0000000, 0x000000},
171 {0, 0x0000000, 0x0000000, 0x000000},
172 {0, 0x0000000, 0x0000000, 0x000000},
173 {0, 0x0000000, 0x0000000, 0x000000},
174 {0, 0x0000000, 0x0000000, 0x000000},
175 {0, 0x0000000, 0x0000000, 0x000000},
176 {0, 0x0000000, 0x0000000, 0x000000},
177 {0, 0x0000000, 0x0000000, 0x000000},
178 {0, 0x0000000, 0x0000000, 0x000000},
179 {0, 0x0000000, 0x0000000, 0x000000},
180 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
181 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
182 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
183 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
184 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
185 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
186 {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
187 {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
188 {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
189 {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
190 {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
191 {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
192 {{{0, 0, 0, 0} } }, /* 23: */
193 {{{0, 0, 0, 0} } }, /* 24: */
194 {{{0, 0, 0, 0} } }, /* 25: */
195 {{{0, 0, 0, 0} } }, /* 26: */
196 {{{0, 0, 0, 0} } }, /* 27: */
197 {{{0, 0, 0, 0} } }, /* 28: */
198 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
199 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
200 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
201 {{{0} } }, /* 32: PCI */
202 {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */
203 {1, 0x2110000, 0x2120000, 0x130000},
204 {1, 0x2120000, 0x2122000, 0x124000},
205 {1, 0x2130000, 0x2132000, 0x126000},
206 {1, 0x2140000, 0x2142000, 0x128000},
207 {1, 0x2150000, 0x2152000, 0x12a000},
208 {1, 0x2160000, 0x2170000, 0x110000},
209 {1, 0x2170000, 0x2172000, 0x12e000},
210 {0, 0x0000000, 0x0000000, 0x000000},
211 {0, 0x0000000, 0x0000000, 0x000000},
212 {0, 0x0000000, 0x0000000, 0x000000},
213 {0, 0x0000000, 0x0000000, 0x000000},
214 {0, 0x0000000, 0x0000000, 0x000000},
215 {0, 0x0000000, 0x0000000, 0x000000},
216 {0, 0x0000000, 0x0000000, 0x000000},
217 {0, 0x0000000, 0x0000000, 0x000000} } },
218 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
224 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
225 {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
226 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
227 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
228 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
229 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
230 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
231 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
232 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
233 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
234 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
235 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
237 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
238 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
239 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
240 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
241 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
242 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
243 {{{0} } }, /* 59: I2C0 */
244 {{{0} } }, /* 60: I2C1 */
245 {{{1, 0x3d00000, 0x3d04000, 0x1d8000} } },/* 61: LPC */
246 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
247 {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */
251 * top 12 bits of crb internal address (hub, agent)
253 static unsigned crb_hub_agt[64] =
256 NETXEN_HW_CRB_HUB_AGT_ADR_PS,
257 NETXEN_HW_CRB_HUB_AGT_ADR_MN,
258 NETXEN_HW_CRB_HUB_AGT_ADR_MS,
260 NETXEN_HW_CRB_HUB_AGT_ADR_SRE,
261 NETXEN_HW_CRB_HUB_AGT_ADR_NIU,
262 NETXEN_HW_CRB_HUB_AGT_ADR_QMN,
263 NETXEN_HW_CRB_HUB_AGT_ADR_SQN0,
264 NETXEN_HW_CRB_HUB_AGT_ADR_SQN1,
265 NETXEN_HW_CRB_HUB_AGT_ADR_SQN2,
266 NETXEN_HW_CRB_HUB_AGT_ADR_SQN3,
267 NETXEN_HW_CRB_HUB_AGT_ADR_I2Q,
268 NETXEN_HW_CRB_HUB_AGT_ADR_TIMR,
269 NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB,
270 NETXEN_HW_CRB_HUB_AGT_ADR_PGN4,
271 NETXEN_HW_CRB_HUB_AGT_ADR_XDMA,
272 NETXEN_HW_CRB_HUB_AGT_ADR_PGN0,
273 NETXEN_HW_CRB_HUB_AGT_ADR_PGN1,
274 NETXEN_HW_CRB_HUB_AGT_ADR_PGN2,
275 NETXEN_HW_CRB_HUB_AGT_ADR_PGN3,
276 NETXEN_HW_CRB_HUB_AGT_ADR_PGND,
277 NETXEN_HW_CRB_HUB_AGT_ADR_PGNI,
278 NETXEN_HW_CRB_HUB_AGT_ADR_PGS0,
279 NETXEN_HW_CRB_HUB_AGT_ADR_PGS1,
280 NETXEN_HW_CRB_HUB_AGT_ADR_PGS2,
281 NETXEN_HW_CRB_HUB_AGT_ADR_PGS3,
283 NETXEN_HW_CRB_HUB_AGT_ADR_PGSI,
284 NETXEN_HW_CRB_HUB_AGT_ADR_SN,
286 NETXEN_HW_CRB_HUB_AGT_ADR_EG,
288 NETXEN_HW_CRB_HUB_AGT_ADR_PS,
289 NETXEN_HW_CRB_HUB_AGT_ADR_CAM,
295 NETXEN_HW_CRB_HUB_AGT_ADR_TIMR,
297 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX1,
298 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX2,
299 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX3,
300 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX4,
301 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX5,
302 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX6,
303 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX7,
304 NETXEN_HW_CRB_HUB_AGT_ADR_XDMA,
305 NETXEN_HW_CRB_HUB_AGT_ADR_I2Q,
306 NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB,
308 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX0,
309 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX8,
310 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX9,
311 NETXEN_HW_CRB_HUB_AGT_ADR_OCM0,
313 NETXEN_HW_CRB_HUB_AGT_ADR_SMB,
314 NETXEN_HW_CRB_HUB_AGT_ADR_I2C0,
315 NETXEN_HW_CRB_HUB_AGT_ADR_I2C1,
317 NETXEN_HW_CRB_HUB_AGT_ADR_PGNC,
321 /* PCI Windowing for DDR regions. */
323 #define NETXEN_WINDOW_ONE 0x2000000 /*CRB Window: bit 25 of CRB address */
325 int netxen_nic_set_mac(struct net_device *netdev, void *p)
327 struct netxen_adapter *adapter = netdev_priv(netdev);
328 struct sockaddr *addr = p;
330 if (netif_running(netdev))
333 if (!is_valid_ether_addr(addr->sa_data))
334 return -EADDRNOTAVAIL;
336 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
338 /* For P3, MAC addr is not set in NIU */
339 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
340 if (adapter->macaddr_set)
341 adapter->macaddr_set(adapter, addr->sa_data);
346 #define NETXEN_UNICAST_ADDR(port, index) \
347 (NETXEN_UNICAST_ADDR_BASE+(port*32)+(index*8))
348 #define NETXEN_MCAST_ADDR(port, index) \
349 (NETXEN_MULTICAST_ADDR_BASE+(port*0x80)+(index*8))
350 #define MAC_HI(addr) \
351 ((addr[2] << 16) | (addr[1] << 8) | (addr[0]))
352 #define MAC_LO(addr) \
353 ((addr[5] << 16) | (addr[4] << 8) | (addr[3]))
356 netxen_nic_enable_mcast_filter(struct netxen_adapter *adapter)
359 u16 port = adapter->physical_port;
360 u8 *addr = adapter->netdev->dev_addr;
362 if (adapter->mc_enabled)
365 val = NXRD32(adapter, NETXEN_MAC_ADDR_CNTL_REG);
366 val |= (1UL << (28+port));
367 NXWR32(adapter, NETXEN_MAC_ADDR_CNTL_REG, val);
369 /* add broadcast addr to filter */
371 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0), val);
372 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0)+4, val);
374 /* add station addr to filter */
376 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1), val);
378 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1)+4, val);
380 adapter->mc_enabled = 1;
385 netxen_nic_disable_mcast_filter(struct netxen_adapter *adapter)
388 u16 port = adapter->physical_port;
389 u8 *addr = adapter->netdev->dev_addr;
391 if (!adapter->mc_enabled)
394 val = NXRD32(adapter, NETXEN_MAC_ADDR_CNTL_REG);
395 val &= ~(1UL << (28+port));
396 NXWR32(adapter, NETXEN_MAC_ADDR_CNTL_REG, val);
399 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0), val);
401 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0)+4, val);
403 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1), 0);
404 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1)+4, 0);
406 adapter->mc_enabled = 0;
411 netxen_nic_set_mcast_addr(struct netxen_adapter *adapter,
415 u16 port = adapter->physical_port;
420 NXWR32(adapter, NETXEN_MCAST_ADDR(port, index), hi);
421 NXWR32(adapter, NETXEN_MCAST_ADDR(port, index)+4, lo);
426 void netxen_p2_nic_set_multi(struct net_device *netdev)
428 struct netxen_adapter *adapter = netdev_priv(netdev);
429 struct dev_mc_list *mc_ptr;
433 memset(null_addr, 0, 6);
435 if (netdev->flags & IFF_PROMISC) {
437 adapter->set_promisc(adapter,
438 NETXEN_NIU_PROMISC_MODE);
440 /* Full promiscuous mode */
441 netxen_nic_disable_mcast_filter(adapter);
446 if (netdev->mc_count == 0) {
447 adapter->set_promisc(adapter,
448 NETXEN_NIU_NON_PROMISC_MODE);
449 netxen_nic_disable_mcast_filter(adapter);
453 adapter->set_promisc(adapter, NETXEN_NIU_ALLMULTI_MODE);
454 if (netdev->flags & IFF_ALLMULTI ||
455 netdev->mc_count > adapter->max_mc_count) {
456 netxen_nic_disable_mcast_filter(adapter);
460 netxen_nic_enable_mcast_filter(adapter);
462 for (mc_ptr = netdev->mc_list; mc_ptr; mc_ptr = mc_ptr->next, index++)
463 netxen_nic_set_mcast_addr(adapter, index, mc_ptr->dmi_addr);
465 if (index != netdev->mc_count)
466 printk(KERN_WARNING "%s: %s multicast address count mismatch\n",
467 netxen_nic_driver_name, netdev->name);
469 /* Clear out remaining addresses */
470 for (; index < adapter->max_mc_count; index++)
471 netxen_nic_set_mcast_addr(adapter, index, null_addr);
474 static int nx_p3_nic_add_mac(struct netxen_adapter *adapter,
475 u8 *addr, nx_mac_list_t **add_list, nx_mac_list_t **del_list)
477 nx_mac_list_t *cur, *prev;
479 /* if in del_list, move it to adapter->mac_list */
480 for (cur = *del_list, prev = NULL; cur;) {
481 if (memcmp(addr, cur->mac_addr, ETH_ALEN) == 0) {
483 *del_list = cur->next;
485 prev->next = cur->next;
486 cur->next = adapter->mac_list;
487 adapter->mac_list = cur;
494 /* make sure to add each mac address only once */
495 for (cur = adapter->mac_list; cur; cur = cur->next) {
496 if (memcmp(addr, cur->mac_addr, ETH_ALEN) == 0)
499 /* not in del_list, create new entry and add to add_list */
500 cur = kmalloc(sizeof(*cur), in_atomic()? GFP_ATOMIC : GFP_KERNEL);
502 printk(KERN_ERR "%s: cannot allocate memory. MAC filtering may"
503 "not work properly from now.\n", __func__);
507 memcpy(cur->mac_addr, addr, ETH_ALEN);
508 cur->next = *add_list;
514 netxen_send_cmd_descs(struct netxen_adapter *adapter,
515 struct cmd_desc_type0 *cmd_desc_arr, int nr_desc)
517 u32 i, producer, consumer;
518 struct netxen_cmd_buffer *pbuf;
519 struct cmd_desc_type0 *cmd_desc;
520 struct nx_host_tx_ring *tx_ring;
524 tx_ring = &adapter->tx_ring;
525 netif_tx_lock_bh(adapter->netdev);
527 producer = tx_ring->producer;
528 consumer = tx_ring->sw_consumer;
530 if (nr_desc > find_diff_among(producer, consumer, tx_ring->num_desc)) {
531 netif_tx_unlock_bh(adapter->netdev);
536 cmd_desc = &cmd_desc_arr[i];
538 pbuf = &tx_ring->cmd_buf_arr[producer];
540 pbuf->frag_count = 0;
542 memcpy(&tx_ring->desc_head[producer],
543 &cmd_desc_arr[i], sizeof(struct cmd_desc_type0));
545 producer = get_next_index(producer, tx_ring->num_desc);
548 } while (i != nr_desc);
550 tx_ring->producer = producer;
552 netxen_nic_update_cmd_producer(adapter, tx_ring, producer);
554 netif_tx_unlock_bh(adapter->netdev);
559 static int nx_p3_sre_macaddr_change(struct net_device *dev,
560 u8 *addr, unsigned op)
562 struct netxen_adapter *adapter = netdev_priv(dev);
564 nx_mac_req_t *mac_req;
568 memset(&req, 0, sizeof(nx_nic_req_t));
569 req.qhdr = cpu_to_le64(NX_NIC_REQUEST << 23);
571 word = NX_MAC_EVENT | ((u64)adapter->portnum << 16);
572 req.req_hdr = cpu_to_le64(word);
574 mac_req = (nx_mac_req_t *)&req.words[0];
576 memcpy(mac_req->mac_addr, addr, 6);
578 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
580 printk(KERN_ERR "ERROR. Could not send mac update\n");
587 void netxen_p3_nic_set_multi(struct net_device *netdev)
589 struct netxen_adapter *adapter = netdev_priv(netdev);
590 nx_mac_list_t *cur, *next, *del_list, *add_list = NULL;
591 struct dev_mc_list *mc_ptr;
592 u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
593 u32 mode = VPORT_MISS_MODE_DROP;
595 del_list = adapter->mac_list;
596 adapter->mac_list = NULL;
598 nx_p3_nic_add_mac(adapter, netdev->dev_addr, &add_list, &del_list);
599 nx_p3_nic_add_mac(adapter, bcast_addr, &add_list, &del_list);
601 if (netdev->flags & IFF_PROMISC) {
602 mode = VPORT_MISS_MODE_ACCEPT_ALL;
606 if ((netdev->flags & IFF_ALLMULTI) ||
607 (netdev->mc_count > adapter->max_mc_count)) {
608 mode = VPORT_MISS_MODE_ACCEPT_MULTI;
612 if (netdev->mc_count > 0) {
613 for (mc_ptr = netdev->mc_list; mc_ptr;
614 mc_ptr = mc_ptr->next) {
615 nx_p3_nic_add_mac(adapter, mc_ptr->dmi_addr,
616 &add_list, &del_list);
621 adapter->set_promisc(adapter, mode);
622 for (cur = del_list; cur;) {
623 nx_p3_sre_macaddr_change(netdev, cur->mac_addr, NETXEN_MAC_DEL);
628 for (cur = add_list; cur;) {
629 nx_p3_sre_macaddr_change(netdev, cur->mac_addr, NETXEN_MAC_ADD);
631 cur->next = adapter->mac_list;
632 adapter->mac_list = cur;
637 int netxen_p3_nic_set_promisc(struct netxen_adapter *adapter, u32 mode)
642 memset(&req, 0, sizeof(nx_nic_req_t));
644 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
646 word = NX_NIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE |
647 ((u64)adapter->portnum << 16);
648 req.req_hdr = cpu_to_le64(word);
650 req.words[0] = cpu_to_le64(mode);
652 return netxen_send_cmd_descs(adapter,
653 (struct cmd_desc_type0 *)&req, 1);
656 void netxen_p3_free_mac_list(struct netxen_adapter *adapter)
658 nx_mac_list_t *cur, *next;
660 cur = adapter->mac_list;
669 #define NETXEN_CONFIG_INTR_COALESCE 3
672 * Send the interrupt coalescing parameter set by ethtool to the card.
674 int netxen_config_intr_coalesce(struct netxen_adapter *adapter)
680 memset(&req, 0, sizeof(nx_nic_req_t));
682 req.qhdr = cpu_to_le64(NX_NIC_REQUEST << 23);
684 word = NETXEN_CONFIG_INTR_COALESCE | ((u64)adapter->portnum << 16);
685 req.req_hdr = cpu_to_le64(word);
687 memcpy(&req.words[0], &adapter->coal, sizeof(adapter->coal));
689 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
691 printk(KERN_ERR "ERROR. Could not send "
692 "interrupt coalescing parameters\n");
698 #define RSS_HASHTYPE_IP_TCP 0x3
700 int netxen_config_rss(struct netxen_adapter *adapter, int enable)
706 u64 key[] = { 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL,
707 0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
708 0x255b0ec26d5a56daULL };
711 memset(&req, 0, sizeof(nx_nic_req_t));
712 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
714 word = NX_NIC_H2C_OPCODE_CONFIG_RSS | ((u64)adapter->portnum << 16);
715 req.req_hdr = cpu_to_le64(word);
719 * bits 3-0: hash_method
720 * 5-4: hash_type_ipv4
721 * 7-6: hash_type_ipv6
723 * 9: use indirection table
725 * 63-48: indirection table mask
727 word = ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 4) |
728 ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 6) |
729 ((u64)(enable & 0x1) << 8) |
731 req.words[0] = cpu_to_le64(word);
732 for (i = 0; i < 5; i++)
733 req.words[i+1] = cpu_to_le64(key[i]);
736 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
738 printk(KERN_ERR "%s: could not configure RSS\n",
739 adapter->netdev->name);
745 int netxen_linkevent_request(struct netxen_adapter *adapter, int enable)
751 memset(&req, 0, sizeof(nx_nic_req_t));
752 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
754 word = NX_NIC_H2C_OPCODE_GET_LINKEVENT | ((u64)adapter->portnum << 16);
755 req.req_hdr = cpu_to_le64(word);
756 req.words[0] = cpu_to_le64(enable);
758 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
760 printk(KERN_ERR "%s: could not configure link notification\n",
761 adapter->netdev->name);
768 * netxen_nic_change_mtu - Change the Maximum Transfer Unit
769 * @returns 0 on success, negative on failure
772 #define MTU_FUDGE_FACTOR 100
774 int netxen_nic_change_mtu(struct net_device *netdev, int mtu)
776 struct netxen_adapter *adapter = netdev_priv(netdev);
780 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
781 max_mtu = P3_MAX_MTU;
783 max_mtu = P2_MAX_MTU;
786 printk(KERN_ERR "%s: mtu > %d bytes unsupported\n",
787 netdev->name, max_mtu);
791 if (adapter->set_mtu)
792 rc = adapter->set_mtu(adapter, mtu);
800 static int netxen_get_flash_block(struct netxen_adapter *adapter, int base,
801 int size, __le32 * buf)
808 for (i = 0; i < size / sizeof(u32); i++) {
809 if (netxen_rom_fast_read(adapter, addr, &v) == -1)
811 *ptr32 = cpu_to_le32(v);
815 if ((char *)buf + size > (char *)ptr32) {
817 if (netxen_rom_fast_read(adapter, addr, &v) == -1)
819 local = cpu_to_le32(v);
820 memcpy(ptr32, &local, (char *)buf + size - (char *)ptr32);
826 int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, __le64 *mac)
828 __le32 *pmac = (__le32 *) mac;
831 offset = NETXEN_USER_START +
832 offsetof(struct netxen_new_user_info, mac_addr) +
833 adapter->portnum * sizeof(u64);
835 if (netxen_get_flash_block(adapter, offset, sizeof(u64), pmac) == -1)
838 if (*mac == cpu_to_le64(~0ULL)) {
840 offset = NETXEN_USER_START_OLD +
841 offsetof(struct netxen_user_old_info, mac_addr) +
842 adapter->portnum * sizeof(u64);
844 if (netxen_get_flash_block(adapter,
845 offset, sizeof(u64), pmac) == -1)
848 if (*mac == cpu_to_le64(~0ULL))
854 int netxen_p3_get_mac_addr(struct netxen_adapter *adapter, __le64 *mac)
856 uint32_t crbaddr, mac_hi, mac_lo;
857 int pci_func = adapter->ahw.pci_func;
859 crbaddr = CRB_MAC_BLOCK_START +
860 (4 * ((pci_func/2) * 3)) + (4 * (pci_func & 1));
862 mac_lo = NXRD32(adapter, crbaddr);
863 mac_hi = NXRD32(adapter, crbaddr+4);
866 *mac = le64_to_cpu((mac_lo >> 16) | ((u64)mac_hi << 16));
868 *mac = le64_to_cpu((u64)mac_lo | ((u64)mac_hi << 32));
873 #define CRB_WIN_LOCK_TIMEOUT 100000000
875 static int crb_win_lock(struct netxen_adapter *adapter)
877 int done = 0, timeout = 0;
880 /* acquire semaphore3 from PCI HW block */
881 done = NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM7_LOCK));
884 if (timeout >= CRB_WIN_LOCK_TIMEOUT)
889 NXWR32(adapter, NETXEN_CRB_WIN_LOCK_ID, adapter->portnum);
893 static void crb_win_unlock(struct netxen_adapter *adapter)
897 val = NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM7_UNLOCK));
901 * Changes the CRB window to the specified window.
904 netxen_nic_pci_change_crbwindow_128M(struct netxen_adapter *adapter, u32 wndw)
906 void __iomem *offset;
909 uint8_t func = adapter->ahw.pci_func;
911 if (adapter->curr_window == wndw)
914 * Move the CRB window.
915 * We need to write to the "direct access" region of PCI
916 * to avoid a race condition where the window register has
917 * not been successfully written across CRB before the target
918 * register address is received by PCI. The direct region bypasses
921 offset = PCI_OFFSET_SECOND_RANGE(adapter,
922 NETXEN_PCIX_PH_REG(PCIE_CRB_WINDOW_REG(func)));
925 wndw = NETXEN_WINDOW_ONE;
927 writel(wndw, offset);
929 /* MUST make sure window is set before we forge on... */
930 while ((tmp = readl(offset)) != wndw) {
931 printk(KERN_WARNING "%s: %s WARNING: CRB window value not "
932 "registered properly: 0x%08x.\n",
933 netxen_nic_driver_name, __func__, tmp);
940 if (wndw == NETXEN_WINDOW_ONE)
941 adapter->curr_window = 1;
943 adapter->curr_window = 0;
947 * Return -1 if off is not valid,
948 * 1 if window access is needed. 'off' is set to offset from
949 * CRB space in 128M pci map
950 * 0 if no window access is needed. 'off' is set to 2M addr
951 * In: 'off' is offset from base in 128M pci map
954 netxen_nic_pci_get_crb_addr_2M(struct netxen_adapter *adapter,
957 unsigned long end = *off + len;
958 crb_128M_2M_sub_block_map_t *m;
961 if (*off >= NETXEN_CRB_MAX)
964 if (*off >= NETXEN_PCI_CAMQM && (end <= NETXEN_PCI_CAMQM_2M_END)) {
965 *off = (*off - NETXEN_PCI_CAMQM) + NETXEN_PCI_CAMQM_2M_BASE +
966 (ulong)adapter->ahw.pci_base0;
970 if (*off < NETXEN_PCI_CRBSPACE)
973 *off -= NETXEN_PCI_CRBSPACE;
979 m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)];
981 if (m->valid && (m->start_128M <= *off) && (m->end_128M >= end)) {
982 *off = *off + m->start_2M - m->start_128M +
983 (ulong)adapter->ahw.pci_base0;
988 * Not in direct map, use crb window
994 * In: 'off' is offset from CRB space in 128M pci map
995 * Out: 'off' is 2M pci map addr
996 * side effect: lock crb window
999 netxen_nic_pci_set_crbwindow_2M(struct netxen_adapter *adapter, ulong *off)
1003 adapter->crb_win = CRB_HI(*off);
1004 writel(adapter->crb_win, (adapter->ahw.pci_base0 + CRB_WINDOW_2M));
1006 * Read back value to make sure write has gone through before trying
1009 win_read = readl(adapter->ahw.pci_base0 + CRB_WINDOW_2M);
1010 if (win_read != adapter->crb_win) {
1011 printk(KERN_ERR "%s: Written crbwin (0x%x) != "
1012 "Read crbwin (0x%x), off=0x%lx\n",
1013 __func__, adapter->crb_win, win_read, *off);
1015 *off = (*off & MASK(16)) + CRB_INDIRECT_2M +
1016 (ulong)adapter->ahw.pci_base0;
1020 netxen_do_load_firmware(struct netxen_adapter *adapter, const char *fwname,
1021 const struct firmware *fw)
1024 u32 i, flashaddr, size;
1025 struct pci_dev *pdev = adapter->pdev;
1028 dev_info(&pdev->dev, "loading firmware from file %s\n", fwname);
1030 dev_info(&pdev->dev, "loading firmware from flash\n");
1032 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
1033 NXWR32(adapter, NETXEN_ROMUSB_GLB_CAS_RST, 1);
1038 size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START) / 8;
1040 ptr64 = (u64 *)&fw->data[NETXEN_BOOTLD_START];
1041 flashaddr = NETXEN_BOOTLD_START;
1043 for (i = 0; i < size; i++) {
1044 data = cpu_to_le64(ptr64[i]);
1045 adapter->pci_mem_write(adapter, flashaddr, &data, 8);
1049 size = *(u32 *)&fw->data[NX_FW_SIZE_OFFSET];
1050 size = (__force u32)cpu_to_le32(size) / 8;
1052 ptr64 = (u64 *)&fw->data[NETXEN_IMAGE_START];
1053 flashaddr = NETXEN_IMAGE_START;
1055 for (i = 0; i < size; i++) {
1056 data = cpu_to_le64(ptr64[i]);
1058 if (adapter->pci_mem_write(adapter,
1059 flashaddr, &data, 8))
1067 size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START) / 4;
1068 flashaddr = NETXEN_BOOTLD_START;
1070 for (i = 0; i < size; i++) {
1071 if (netxen_rom_fast_read(adapter,
1072 flashaddr, (int *)&data) != 0)
1075 if (adapter->pci_mem_write(adapter,
1076 flashaddr, &data, 4))
1084 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
1085 NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0x80001d);
1087 NXWR32(adapter, NETXEN_ROMUSB_GLB_CHIP_CLK_CTRL, 0x3fff);
1088 NXWR32(adapter, NETXEN_ROMUSB_GLB_CAS_RST, 0);
1095 netxen_validate_firmware(struct netxen_adapter *adapter, const char *fwname,
1096 const struct firmware *fw)
1099 u32 major, minor, build, ver, min_ver, bios;
1100 struct pci_dev *pdev = adapter->pdev;
1102 if (fw->size < NX_FW_MIN_SIZE)
1105 val = cpu_to_le32(*(u32 *)&fw->data[NX_FW_MAGIC_OFFSET]);
1106 if ((__force u32)val != NETXEN_BDINFO_MAGIC)
1109 val = cpu_to_le32(*(u32 *)&fw->data[NX_FW_VERSION_OFFSET]);
1110 major = (__force u32)val & 0xff;
1111 minor = ((__force u32)val >> 8) & 0xff;
1112 build = (__force u32)val >> 16;
1114 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
1115 min_ver = NETXEN_VERSION_CODE(4, 0, 216);
1117 min_ver = NETXEN_VERSION_CODE(3, 4, 216);
1119 ver = NETXEN_VERSION_CODE(major, minor, build);
1121 if ((major > _NETXEN_NIC_LINUX_MAJOR) || (ver < min_ver)) {
1123 "%s: firmware version %d.%d.%d unsupported\n",
1124 fwname, major, minor, build);
1128 val = cpu_to_le32(*(u32 *)&fw->data[NX_BIOS_VERSION_OFFSET]);
1129 netxen_rom_fast_read(adapter, NX_BIOS_VERSION_OFFSET, (int *)&bios);
1130 if ((__force u32)val != bios) {
1131 dev_err(&pdev->dev, "%s: firmware bios is incompatible\n",
1136 /* check if flashed firmware is newer */
1137 if (netxen_rom_fast_read(adapter,
1138 NX_FW_VERSION_OFFSET, (int *)&val))
1140 major = (__force u32)val & 0xff;
1141 minor = ((__force u32)val >> 8) & 0xff;
1142 build = (__force u32)val >> 16;
1143 if (NETXEN_VERSION_CODE(major, minor, build) > ver)
1146 NXWR32(adapter, NETXEN_CAM_RAM(0x1fc), NETXEN_BDINFO_MAGIC);
1150 static char *fw_name[] = { "nxromimg.bin", "nx3fwct.bin", "nx3fwmn.bin" };
1152 int netxen_load_firmware(struct netxen_adapter *adapter)
1154 u32 capability, flashed_ver;
1155 const struct firmware *fw;
1157 struct pci_dev *pdev = adapter->pdev;
1160 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
1161 fw_type = NX_P2_MN_ROMIMAGE;
1164 fw_type = NX_P3_CT_ROMIMAGE;
1171 netxen_rom_fast_read(adapter,
1172 NX_FW_VERSION_OFFSET, (int *)&flashed_ver);
1173 if (flashed_ver >= NETXEN_VERSION_CODE(4, 0, 220)) {
1174 capability = NXRD32(adapter, NX_PEG_TUNE_CAPABILITY);
1175 if (capability & NX_PEG_TUNE_MN_PRESENT) {
1176 fw_type = NX_P3_MN_ROMIMAGE;
1182 rc = request_firmware(&fw, fw_name[fw_type], &pdev->dev);
1184 if (fw_type == NX_P3_CT_ROMIMAGE) {
1193 rc = netxen_validate_firmware(adapter, fw_name[fw_type], fw);
1195 release_firmware(fw);
1197 if (fw_type == NX_P3_CT_ROMIMAGE) {
1206 rc = netxen_do_load_firmware(adapter, fw_name[fw_type], fw);
1209 release_firmware(fw);
1214 netxen_nic_hw_write_wx_128M(struct netxen_adapter *adapter, ulong off, u32 data)
1218 if (ADDR_IN_WINDOW1(off)) {
1219 addr = NETXEN_CRB_NORMALIZE(adapter, off);
1220 } else { /* Window 0 */
1221 addr = pci_base_offset(adapter, off);
1222 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1226 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1232 if (!ADDR_IN_WINDOW1(off))
1233 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1239 netxen_nic_hw_read_wx_128M(struct netxen_adapter *adapter, ulong off)
1244 if (ADDR_IN_WINDOW1(off)) { /* Window 1 */
1245 addr = NETXEN_CRB_NORMALIZE(adapter, off);
1246 } else { /* Window 0 */
1247 addr = pci_base_offset(adapter, off);
1248 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1252 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1258 if (!ADDR_IN_WINDOW1(off))
1259 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1265 netxen_nic_hw_write_wx_2M(struct netxen_adapter *adapter, ulong off, u32 data)
1267 unsigned long flags = 0;
1270 rv = netxen_nic_pci_get_crb_addr_2M(adapter, &off, 4);
1273 printk(KERN_ERR "%s: invalid offset: 0x%016lx\n",
1280 write_lock_irqsave(&adapter->adapter_lock, flags);
1281 crb_win_lock(adapter);
1282 netxen_nic_pci_set_crbwindow_2M(adapter, &off);
1283 writel(data, (void __iomem *)off);
1284 crb_win_unlock(adapter);
1285 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1287 writel(data, (void __iomem *)off);
1294 netxen_nic_hw_read_wx_2M(struct netxen_adapter *adapter, ulong off)
1296 unsigned long flags = 0;
1300 rv = netxen_nic_pci_get_crb_addr_2M(adapter, &off, 4);
1303 printk(KERN_ERR "%s: invalid offset: 0x%016lx\n",
1310 write_lock_irqsave(&adapter->adapter_lock, flags);
1311 crb_win_lock(adapter);
1312 netxen_nic_pci_set_crbwindow_2M(adapter, &off);
1313 data = readl((void __iomem *)off);
1314 crb_win_unlock(adapter);
1315 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1317 data = readl((void __iomem *)off);
1323 * check memory access boundary.
1324 * used by test agent. support ddr access only for now
1326 static unsigned long
1327 netxen_nic_pci_mem_bound_check(struct netxen_adapter *adapter,
1328 unsigned long long addr, int size)
1330 if (!ADDR_IN_RANGE(addr,
1331 NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX) ||
1332 !ADDR_IN_RANGE(addr+size-1,
1333 NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX) ||
1334 ((size != 1) && (size != 2) && (size != 4) && (size != 8))) {
1341 static int netxen_pci_set_window_warning_count;
1344 netxen_nic_pci_set_window_128M(struct netxen_adapter *adapter,
1345 unsigned long long addr)
1347 void __iomem *offset;
1349 unsigned long long qdr_max;
1350 uint8_t func = adapter->ahw.pci_func;
1352 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
1353 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P2;
1355 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P3;
1358 if (ADDR_IN_RANGE(addr, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1359 /* DDR network side */
1360 addr -= NETXEN_ADDR_DDR_NET;
1361 window = (addr >> 25) & 0x3ff;
1362 if (adapter->ahw.ddr_mn_window != window) {
1363 adapter->ahw.ddr_mn_window = window;
1364 offset = PCI_OFFSET_SECOND_RANGE(adapter,
1365 NETXEN_PCIX_PH_REG(PCIE_MN_WINDOW_REG(func)));
1366 writel(window, offset);
1367 /* MUST make sure window is set before we forge on... */
1370 addr -= (window * NETXEN_WINDOW_ONE);
1371 addr += NETXEN_PCI_DDR_NET;
1372 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1373 addr -= NETXEN_ADDR_OCM0;
1374 addr += NETXEN_PCI_OCM0;
1375 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
1376 addr -= NETXEN_ADDR_OCM1;
1377 addr += NETXEN_PCI_OCM1;
1378 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_QDR_NET, qdr_max)) {
1379 /* QDR network side */
1380 addr -= NETXEN_ADDR_QDR_NET;
1381 window = (addr >> 22) & 0x3f;
1382 if (adapter->ahw.qdr_sn_window != window) {
1383 adapter->ahw.qdr_sn_window = window;
1384 offset = PCI_OFFSET_SECOND_RANGE(adapter,
1385 NETXEN_PCIX_PH_REG(PCIE_SN_WINDOW_REG(func)));
1386 writel((window << 22), offset);
1387 /* MUST make sure window is set before we forge on... */
1390 addr -= (window * 0x400000);
1391 addr += NETXEN_PCI_QDR_NET;
1394 * peg gdb frequently accesses memory that doesn't exist,
1395 * this limits the chit chat so debugging isn't slowed down.
1397 if ((netxen_pci_set_window_warning_count++ < 8)
1398 || (netxen_pci_set_window_warning_count % 64 == 0))
1399 printk("%s: Warning:netxen_nic_pci_set_window()"
1400 " Unknown address range!\n",
1401 netxen_nic_driver_name);
1408 * Note : only 32-bit writes!
1410 int netxen_nic_pci_write_immediate_128M(struct netxen_adapter *adapter,
1413 writel(data, (void __iomem *)(PCI_OFFSET_SECOND_RANGE(adapter, off)));
1417 u32 netxen_nic_pci_read_immediate_128M(struct netxen_adapter *adapter, u64 off)
1419 return readl((void __iomem *)(pci_base_offset(adapter, off)));
1423 netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter,
1424 unsigned long long addr)
1429 if (ADDR_IN_RANGE(addr, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1430 /* DDR network side */
1431 window = MN_WIN(addr);
1432 adapter->ahw.ddr_mn_window = window;
1433 NXWR32(adapter, adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1435 win_read = NXRD32(adapter,
1436 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE);
1437 if ((win_read << 17) != window) {
1438 printk(KERN_INFO "Written MNwin (0x%x) != "
1439 "Read MNwin (0x%x)\n", window, win_read);
1441 addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_DDR_NET;
1442 } else if (ADDR_IN_RANGE(addr,
1443 NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1444 if ((addr & 0x00ff800) == 0xff800) {
1445 printk("%s: QM access not handled.\n", __func__);
1449 window = OCM_WIN(addr);
1450 adapter->ahw.ddr_mn_window = window;
1451 NXWR32(adapter, adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1453 win_read = NXRD32(adapter,
1454 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE);
1455 if ((win_read >> 7) != window) {
1456 printk(KERN_INFO "%s: Written OCMwin (0x%x) != "
1457 "Read OCMwin (0x%x)\n",
1458 __func__, window, win_read);
1460 addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_OCM0_2M;
1462 } else if (ADDR_IN_RANGE(addr,
1463 NETXEN_ADDR_QDR_NET, NETXEN_ADDR_QDR_NET_MAX_P3)) {
1464 /* QDR network side */
1465 window = MS_WIN(addr);
1466 adapter->ahw.qdr_sn_window = window;
1467 NXWR32(adapter, adapter->ahw.ms_win_crb | NETXEN_PCI_CRBSPACE,
1469 win_read = NXRD32(adapter,
1470 adapter->ahw.ms_win_crb | NETXEN_PCI_CRBSPACE);
1471 if (win_read != window) {
1472 printk(KERN_INFO "%s: Written MSwin (0x%x) != "
1473 "Read MSwin (0x%x)\n",
1474 __func__, window, win_read);
1476 addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_QDR_NET;
1480 * peg gdb frequently accesses memory that doesn't exist,
1481 * this limits the chit chat so debugging isn't slowed down.
1483 if ((netxen_pci_set_window_warning_count++ < 8)
1484 || (netxen_pci_set_window_warning_count%64 == 0)) {
1485 printk("%s: Warning:%s Unknown address range!\n",
1486 __func__, netxen_nic_driver_name);
1493 static int netxen_nic_pci_is_same_window(struct netxen_adapter *adapter,
1494 unsigned long long addr)
1497 unsigned long long qdr_max;
1499 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
1500 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P2;
1502 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P3;
1504 if (ADDR_IN_RANGE(addr,
1505 NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1506 /* DDR network side */
1507 BUG(); /* MN access can not come here */
1508 } else if (ADDR_IN_RANGE(addr,
1509 NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1511 } else if (ADDR_IN_RANGE(addr,
1512 NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
1514 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_QDR_NET, qdr_max)) {
1515 /* QDR network side */
1516 window = ((addr - NETXEN_ADDR_QDR_NET) >> 22) & 0x3f;
1517 if (adapter->ahw.qdr_sn_window == window)
1524 static int netxen_nic_pci_mem_read_direct(struct netxen_adapter *adapter,
1525 u64 off, void *data, int size)
1527 unsigned long flags;
1528 void __iomem *addr, *mem_ptr = NULL;
1531 unsigned long mem_base;
1532 unsigned long mem_page;
1534 write_lock_irqsave(&adapter->adapter_lock, flags);
1537 * If attempting to access unknown address or straddle hw windows,
1540 start = adapter->pci_set_window(adapter, off);
1541 if ((start == -1UL) ||
1542 (netxen_nic_pci_is_same_window(adapter, off+size-1) == 0)) {
1543 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1544 printk(KERN_ERR "%s out of bound pci memory access. "
1545 "offset is 0x%llx\n", netxen_nic_driver_name,
1546 (unsigned long long)off);
1550 addr = pci_base_offset(adapter, start);
1552 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1553 mem_base = pci_resource_start(adapter->pdev, 0);
1554 mem_page = start & PAGE_MASK;
1555 /* Map two pages whenever user tries to access addresses in two
1558 if (mem_page != ((start + size - 1) & PAGE_MASK))
1559 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2);
1561 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
1562 if (mem_ptr == NULL) {
1563 *(uint8_t *)data = 0;
1567 addr += start & (PAGE_SIZE - 1);
1568 write_lock_irqsave(&adapter->adapter_lock, flags);
1573 *(uint8_t *)data = readb(addr);
1576 *(uint16_t *)data = readw(addr);
1579 *(uint32_t *)data = readl(addr);
1582 *(uint64_t *)data = readq(addr);
1588 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1596 netxen_nic_pci_mem_write_direct(struct netxen_adapter *adapter, u64 off,
1597 void *data, int size)
1599 unsigned long flags;
1600 void __iomem *addr, *mem_ptr = NULL;
1603 unsigned long mem_base;
1604 unsigned long mem_page;
1606 write_lock_irqsave(&adapter->adapter_lock, flags);
1609 * If attempting to access unknown address or straddle hw windows,
1612 start = adapter->pci_set_window(adapter, off);
1613 if ((start == -1UL) ||
1614 (netxen_nic_pci_is_same_window(adapter, off+size-1) == 0)) {
1615 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1616 printk(KERN_ERR "%s out of bound pci memory access. "
1617 "offset is 0x%llx\n", netxen_nic_driver_name,
1618 (unsigned long long)off);
1622 addr = pci_base_offset(adapter, start);
1624 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1625 mem_base = pci_resource_start(adapter->pdev, 0);
1626 mem_page = start & PAGE_MASK;
1627 /* Map two pages whenever user tries to access addresses in two
1628 * consecutive pages.
1630 if (mem_page != ((start + size - 1) & PAGE_MASK))
1631 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2);
1633 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
1634 if (mem_ptr == NULL)
1637 addr += start & (PAGE_SIZE - 1);
1638 write_lock_irqsave(&adapter->adapter_lock, flags);
1643 writeb(*(uint8_t *)data, addr);
1646 writew(*(uint16_t *)data, addr);
1649 writel(*(uint32_t *)data, addr);
1652 writeq(*(uint64_t *)data, addr);
1658 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1664 #define MAX_CTL_CHECK 1000
1667 netxen_nic_pci_mem_write_128M(struct netxen_adapter *adapter,
1668 u64 off, void *data, int size)
1670 unsigned long flags;
1671 int i, j, ret = 0, loop, sz[2], off0;
1673 uint64_t off8, tmpw, word[2] = {0, 0};
1674 void __iomem *mem_crb;
1677 * If not MN, go check for MS or invalid.
1679 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1680 return netxen_nic_pci_mem_write_direct(adapter,
1683 off8 = off & 0xfffffff8;
1685 sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1686 sz[1] = size - sz[0];
1687 loop = ((off0 + size - 1) >> 3) + 1;
1688 mem_crb = pci_base_offset(adapter, NETXEN_CRB_DDR_NET);
1690 if ((size != 8) || (off0 != 0)) {
1691 for (i = 0; i < loop; i++) {
1692 if (adapter->pci_mem_read(adapter,
1693 off8 + (i << 3), &word[i], 8))
1700 tmpw = *((uint8_t *)data);
1703 tmpw = *((uint16_t *)data);
1706 tmpw = *((uint32_t *)data);
1710 tmpw = *((uint64_t *)data);
1713 word[0] &= ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1714 word[0] |= tmpw << (off0 * 8);
1717 word[1] &= ~(~0ULL << (sz[1] * 8));
1718 word[1] |= tmpw >> (sz[0] * 8);
1721 write_lock_irqsave(&adapter->adapter_lock, flags);
1722 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1724 for (i = 0; i < loop; i++) {
1725 writel((uint32_t)(off8 + (i << 3)),
1726 (mem_crb+MIU_TEST_AGT_ADDR_LO));
1728 (mem_crb+MIU_TEST_AGT_ADDR_HI));
1729 writel(word[i] & 0xffffffff,
1730 (mem_crb+MIU_TEST_AGT_WRDATA_LO));
1731 writel((word[i] >> 32) & 0xffffffff,
1732 (mem_crb+MIU_TEST_AGT_WRDATA_HI));
1733 writel(MIU_TA_CTL_ENABLE|MIU_TA_CTL_WRITE,
1734 (mem_crb+MIU_TEST_AGT_CTRL));
1735 writel(MIU_TA_CTL_START|MIU_TA_CTL_ENABLE|MIU_TA_CTL_WRITE,
1736 (mem_crb+MIU_TEST_AGT_CTRL));
1738 for (j = 0; j < MAX_CTL_CHECK; j++) {
1740 (mem_crb+MIU_TEST_AGT_CTRL));
1741 if ((temp & MIU_TA_CTL_BUSY) == 0)
1745 if (j >= MAX_CTL_CHECK) {
1746 if (printk_ratelimit())
1747 dev_err(&adapter->pdev->dev,
1748 "failed to write through agent\n");
1754 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1755 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1760 netxen_nic_pci_mem_read_128M(struct netxen_adapter *adapter,
1761 u64 off, void *data, int size)
1763 unsigned long flags;
1764 int i, j = 0, k, start, end, loop, sz[2], off0[2];
1766 uint64_t off8, val, word[2] = {0, 0};
1767 void __iomem *mem_crb;
1771 * If not MN, go check for MS or invalid.
1773 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1774 return netxen_nic_pci_mem_read_direct(adapter, off, data, size);
1776 off8 = off & 0xfffffff8;
1777 off0[0] = off & 0x7;
1779 sz[0] = (size < (8 - off0[0])) ? size : (8 - off0[0]);
1780 sz[1] = size - sz[0];
1781 loop = ((off0[0] + size - 1) >> 3) + 1;
1782 mem_crb = pci_base_offset(adapter, NETXEN_CRB_DDR_NET);
1784 write_lock_irqsave(&adapter->adapter_lock, flags);
1785 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1787 for (i = 0; i < loop; i++) {
1788 writel((uint32_t)(off8 + (i << 3)),
1789 (mem_crb+MIU_TEST_AGT_ADDR_LO));
1791 (mem_crb+MIU_TEST_AGT_ADDR_HI));
1792 writel(MIU_TA_CTL_ENABLE,
1793 (mem_crb+MIU_TEST_AGT_CTRL));
1794 writel(MIU_TA_CTL_START|MIU_TA_CTL_ENABLE,
1795 (mem_crb+MIU_TEST_AGT_CTRL));
1797 for (j = 0; j < MAX_CTL_CHECK; j++) {
1799 (mem_crb+MIU_TEST_AGT_CTRL));
1800 if ((temp & MIU_TA_CTL_BUSY) == 0)
1804 if (j >= MAX_CTL_CHECK) {
1805 if (printk_ratelimit())
1806 dev_err(&adapter->pdev->dev,
1807 "failed to read through agent\n");
1811 start = off0[i] >> 2;
1812 end = (off0[i] + sz[i] - 1) >> 2;
1813 for (k = start; k <= end; k++) {
1814 word[i] |= ((uint64_t) readl(
1816 MIU_TEST_AGT_RDDATA(k))) << (32*k));
1820 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1821 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1823 if (j >= MAX_CTL_CHECK)
1829 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
1830 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
1835 *(uint8_t *)data = val;
1838 *(uint16_t *)data = val;
1841 *(uint32_t *)data = val;
1844 *(uint64_t *)data = val;
1851 netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter,
1852 u64 off, void *data, int size)
1854 int i, j, ret = 0, loop, sz[2], off0;
1856 uint64_t off8, mem_crb, tmpw, word[2] = {0, 0};
1859 * If not MN, go check for MS or invalid.
1861 if (off >= NETXEN_ADDR_QDR_NET && off <= NETXEN_ADDR_QDR_NET_MAX_P3)
1862 mem_crb = NETXEN_CRB_QDR_NET;
1864 mem_crb = NETXEN_CRB_DDR_NET;
1865 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1866 return netxen_nic_pci_mem_write_direct(adapter,
1870 off8 = off & 0xfffffff8;
1872 sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1873 sz[1] = size - sz[0];
1874 loop = ((off0 + size - 1) >> 3) + 1;
1876 if ((size != 8) || (off0 != 0)) {
1877 for (i = 0; i < loop; i++) {
1878 if (adapter->pci_mem_read(adapter, off8 + (i << 3),
1886 tmpw = *((uint8_t *)data);
1889 tmpw = *((uint16_t *)data);
1892 tmpw = *((uint32_t *)data);
1896 tmpw = *((uint64_t *)data);
1900 word[0] &= ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1901 word[0] |= tmpw << (off0 * 8);
1904 word[1] &= ~(~0ULL << (sz[1] * 8));
1905 word[1] |= tmpw >> (sz[0] * 8);
1909 * don't lock here - write_wx gets the lock if each time
1910 * write_lock_irqsave(&adapter->adapter_lock, flags);
1911 * netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1914 for (i = 0; i < loop; i++) {
1915 temp = off8 + (i << 3);
1916 NXWR32(adapter, mem_crb+MIU_TEST_AGT_ADDR_LO, temp);
1918 NXWR32(adapter, mem_crb+MIU_TEST_AGT_ADDR_HI, temp);
1919 temp = word[i] & 0xffffffff;
1920 NXWR32(adapter, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp);
1921 temp = (word[i] >> 32) & 0xffffffff;
1922 NXWR32(adapter, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp);
1923 temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1924 NXWR32(adapter, mem_crb+MIU_TEST_AGT_CTRL, temp);
1925 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1926 NXWR32(adapter, mem_crb+MIU_TEST_AGT_CTRL, temp);
1928 for (j = 0; j < MAX_CTL_CHECK; j++) {
1929 temp = NXRD32(adapter, mem_crb + MIU_TEST_AGT_CTRL);
1930 if ((temp & MIU_TA_CTL_BUSY) == 0)
1934 if (j >= MAX_CTL_CHECK) {
1935 if (printk_ratelimit())
1936 dev_err(&adapter->pdev->dev,
1937 "failed to write through agent\n");
1944 * netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1945 * write_unlock_irqrestore(&adapter->adapter_lock, flags);
1951 netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter,
1952 u64 off, void *data, int size)
1954 int i, j = 0, k, start, end, loop, sz[2], off0[2];
1956 uint64_t off8, val, mem_crb, word[2] = {0, 0};
1959 * If not MN, go check for MS or invalid.
1962 if (off >= NETXEN_ADDR_QDR_NET && off <= NETXEN_ADDR_QDR_NET_MAX_P3)
1963 mem_crb = NETXEN_CRB_QDR_NET;
1965 mem_crb = NETXEN_CRB_DDR_NET;
1966 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1967 return netxen_nic_pci_mem_read_direct(adapter,
1971 off8 = off & 0xfffffff8;
1972 off0[0] = off & 0x7;
1974 sz[0] = (size < (8 - off0[0])) ? size : (8 - off0[0]);
1975 sz[1] = size - sz[0];
1976 loop = ((off0[0] + size - 1) >> 3) + 1;
1979 * don't lock here - write_wx gets the lock if each time
1980 * write_lock_irqsave(&adapter->adapter_lock, flags);
1981 * netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1984 for (i = 0; i < loop; i++) {
1985 temp = off8 + (i << 3);
1986 NXWR32(adapter, mem_crb + MIU_TEST_AGT_ADDR_LO, temp);
1988 NXWR32(adapter, mem_crb + MIU_TEST_AGT_ADDR_HI, temp);
1989 temp = MIU_TA_CTL_ENABLE;
1990 NXWR32(adapter, mem_crb + MIU_TEST_AGT_CTRL, temp);
1991 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE;
1992 NXWR32(adapter, mem_crb + MIU_TEST_AGT_CTRL, temp);
1994 for (j = 0; j < MAX_CTL_CHECK; j++) {
1995 temp = NXRD32(adapter, mem_crb + MIU_TEST_AGT_CTRL);
1996 if ((temp & MIU_TA_CTL_BUSY) == 0)
2000 if (j >= MAX_CTL_CHECK) {
2001 if (printk_ratelimit())
2002 dev_err(&adapter->pdev->dev,
2003 "failed to read through agent\n");
2007 start = off0[i] >> 2;
2008 end = (off0[i] + sz[i] - 1) >> 2;
2009 for (k = start; k <= end; k++) {
2010 temp = NXRD32(adapter,
2011 mem_crb + MIU_TEST_AGT_RDDATA(k));
2012 word[i] |= ((uint64_t)temp << (32 * k));
2017 * netxen_nic_pci_change_crbwindow_128M(adapter, 1);
2018 * write_unlock_irqrestore(&adapter->adapter_lock, flags);
2021 if (j >= MAX_CTL_CHECK)
2027 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
2028 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
2033 *(uint8_t *)data = val;
2036 *(uint16_t *)data = val;
2039 *(uint32_t *)data = val;
2042 *(uint64_t *)data = val;
2049 * Note : only 32-bit writes!
2051 int netxen_nic_pci_write_immediate_2M(struct netxen_adapter *adapter,
2054 NXWR32(adapter, off, data);
2059 u32 netxen_nic_pci_read_immediate_2M(struct netxen_adapter *adapter, u64 off)
2061 return NXRD32(adapter, off);
2064 int netxen_nic_get_board_info(struct netxen_adapter *adapter)
2066 int offset, board_type, magic, header_version;
2067 struct pci_dev *pdev = adapter->pdev;
2069 offset = NETXEN_BRDCFG_START +
2070 offsetof(struct netxen_board_info, magic);
2071 if (netxen_rom_fast_read(adapter, offset, &magic))
2074 offset = NETXEN_BRDCFG_START +
2075 offsetof(struct netxen_board_info, header_version);
2076 if (netxen_rom_fast_read(adapter, offset, &header_version))
2079 if (magic != NETXEN_BDINFO_MAGIC ||
2080 header_version != NETXEN_BDINFO_VERSION) {
2082 "invalid board config, magic=%08x, version=%08x\n",
2083 magic, header_version);
2087 offset = NETXEN_BRDCFG_START +
2088 offsetof(struct netxen_board_info, board_type);
2089 if (netxen_rom_fast_read(adapter, offset, &board_type))
2092 adapter->ahw.board_type = board_type;
2094 if (board_type == NETXEN_BRDTYPE_P3_4_GB_MM) {
2095 u32 gpio = NXRD32(adapter, NETXEN_ROMUSB_GLB_PAD_GPIO_I);
2096 if ((gpio & 0x8000) == 0)
2097 board_type = NETXEN_BRDTYPE_P3_10G_TP;
2100 switch (board_type) {
2101 case NETXEN_BRDTYPE_P2_SB35_4G:
2102 adapter->ahw.port_type = NETXEN_NIC_GBE;
2104 case NETXEN_BRDTYPE_P2_SB31_10G:
2105 case NETXEN_BRDTYPE_P2_SB31_10G_IMEZ:
2106 case NETXEN_BRDTYPE_P2_SB31_10G_HMEZ:
2107 case NETXEN_BRDTYPE_P2_SB31_10G_CX4:
2108 case NETXEN_BRDTYPE_P3_HMEZ:
2109 case NETXEN_BRDTYPE_P3_XG_LOM:
2110 case NETXEN_BRDTYPE_P3_10G_CX4:
2111 case NETXEN_BRDTYPE_P3_10G_CX4_LP:
2112 case NETXEN_BRDTYPE_P3_IMEZ:
2113 case NETXEN_BRDTYPE_P3_10G_SFP_PLUS:
2114 case NETXEN_BRDTYPE_P3_10G_SFP_CT:
2115 case NETXEN_BRDTYPE_P3_10G_SFP_QT:
2116 case NETXEN_BRDTYPE_P3_10G_XFP:
2117 case NETXEN_BRDTYPE_P3_10000_BASE_T:
2118 adapter->ahw.port_type = NETXEN_NIC_XGBE;
2120 case NETXEN_BRDTYPE_P1_BD:
2121 case NETXEN_BRDTYPE_P1_SB:
2122 case NETXEN_BRDTYPE_P1_SMAX:
2123 case NETXEN_BRDTYPE_P1_SOCK:
2124 case NETXEN_BRDTYPE_P3_REF_QG:
2125 case NETXEN_BRDTYPE_P3_4_GB:
2126 case NETXEN_BRDTYPE_P3_4_GB_MM:
2127 adapter->ahw.port_type = NETXEN_NIC_GBE;
2129 case NETXEN_BRDTYPE_P3_10G_TP:
2130 adapter->ahw.port_type = (adapter->portnum < 2) ?
2131 NETXEN_NIC_XGBE : NETXEN_NIC_GBE;
2134 dev_err(&pdev->dev, "unknown board type %x\n", board_type);
2135 adapter->ahw.port_type = NETXEN_NIC_XGBE;
2142 /* NIU access sections */
2144 int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu)
2146 new_mtu += MTU_FUDGE_FACTOR;
2147 NXWR32(adapter, NETXEN_NIU_GB_MAX_FRAME_SIZE(adapter->physical_port),
2152 int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu)
2154 new_mtu += MTU_FUDGE_FACTOR;
2155 if (adapter->physical_port == 0)
2156 NXWR32(adapter, NETXEN_NIU_XGE_MAX_FRAME_SIZE, new_mtu);
2158 NXWR32(adapter, NETXEN_NIU_XG1_MAX_FRAME_SIZE, new_mtu);
2162 void netxen_nic_set_link_parameters(struct netxen_adapter *adapter)
2168 if (!netif_carrier_ok(adapter->netdev)) {
2169 adapter->link_speed = 0;
2170 adapter->link_duplex = -1;
2171 adapter->link_autoneg = AUTONEG_ENABLE;
2175 if (adapter->ahw.port_type == NETXEN_NIC_GBE) {
2176 port_mode = NXRD32(adapter, NETXEN_PORT_MODE_ADDR);
2177 if (port_mode == NETXEN_PORT_MODE_802_3_AP) {
2178 adapter->link_speed = SPEED_1000;
2179 adapter->link_duplex = DUPLEX_FULL;
2180 adapter->link_autoneg = AUTONEG_DISABLE;
2184 if (adapter->phy_read
2185 && adapter->phy_read(adapter,
2186 NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS,
2188 if (netxen_get_phy_link(status)) {
2189 switch (netxen_get_phy_speed(status)) {
2191 adapter->link_speed = SPEED_10;
2194 adapter->link_speed = SPEED_100;
2197 adapter->link_speed = SPEED_1000;
2200 adapter->link_speed = 0;
2203 switch (netxen_get_phy_duplex(status)) {
2205 adapter->link_duplex = DUPLEX_HALF;
2208 adapter->link_duplex = DUPLEX_FULL;
2211 adapter->link_duplex = -1;
2214 if (adapter->phy_read
2215 && adapter->phy_read(adapter,
2216 NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG,
2218 adapter->link_autoneg = autoneg;
2223 adapter->link_speed = 0;
2224 adapter->link_duplex = -1;
2229 void netxen_nic_get_firmware_info(struct netxen_adapter *adapter)
2231 u32 fw_major, fw_minor, fw_build;
2232 char brd_name[NETXEN_MAX_SHORT_NAME];
2233 char serial_num[32];
2236 struct pci_dev *pdev = adapter->pdev;
2238 adapter->driver_mismatch = 0;
2240 ptr32 = (int *)&serial_num;
2241 addr = NETXEN_USER_START +
2242 offsetof(struct netxen_new_user_info, serial_num);
2243 for (i = 0; i < 8; i++) {
2244 if (netxen_rom_fast_read(adapter, addr, &val) == -1) {
2245 dev_err(&pdev->dev, "error reading board info\n");
2246 adapter->driver_mismatch = 1;
2249 ptr32[i] = cpu_to_le32(val);
2250 addr += sizeof(u32);
2253 fw_major = NXRD32(adapter, NETXEN_FW_VERSION_MAJOR);
2254 fw_minor = NXRD32(adapter, NETXEN_FW_VERSION_MINOR);
2255 fw_build = NXRD32(adapter, NETXEN_FW_VERSION_SUB);
2257 adapter->fw_major = fw_major;
2258 adapter->fw_version = NETXEN_VERSION_CODE(fw_major, fw_minor, fw_build);
2260 if (adapter->portnum == 0) {
2261 get_brd_name_by_type(adapter->ahw.board_type, brd_name);
2263 printk(KERN_INFO "NetXen %s Board S/N %s Chip rev 0x%x\n",
2264 brd_name, serial_num, adapter->ahw.revision_id);
2267 if (adapter->fw_version < NETXEN_VERSION_CODE(3, 4, 216)) {
2268 adapter->driver_mismatch = 1;
2269 dev_warn(&pdev->dev, "firmware version %d.%d.%d unsupported\n",
2270 fw_major, fw_minor, fw_build);
2274 dev_info(&pdev->dev, "firmware version %d.%d.%d\n",
2275 fw_major, fw_minor, fw_build);
2277 if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
2278 i = NXRD32(adapter, NETXEN_MIU_MN_CONTROL);
2279 adapter->ahw.cut_through = (i & 0x4) ? 1 : 0;
2280 dev_info(&pdev->dev, "firmware running in %s mode\n",
2281 adapter->ahw.cut_through ? "cut-through" : "legacy");
2286 netxen_nic_wol_supported(struct netxen_adapter *adapter)
2290 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
2293 wol_cfg = NXRD32(adapter, NETXEN_WOL_CONFIG_NV);
2294 if (wol_cfg & (1UL << adapter->portnum)) {
2295 wol_cfg = NXRD32(adapter, NETXEN_WOL_CONFIG);
2296 if (wol_cfg & (1 << adapter->portnum))