2 * arch/ppc/platforms/85xx/mpc85xx_devices.c
4 * MPC85xx Device descriptions
6 * Maintainer: Kumar Gala <kumar.gala@freescale.com>
8 * Copyright 2005 Freescale Semiconductor Inc.
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
16 #include <linux/init.h>
17 #include <linux/module.h>
18 #include <linux/device.h>
19 #include <linux/serial_8250.h>
20 #include <linux/fsl_devices.h>
21 #include <asm/mpc85xx.h>
23 #include <asm/ppc_sys.h>
25 /* We use offsets for IORESOURCE_MEM since we do not know at compile time
26 * what CCSRBAR is, will get fixed up by mach_mpc85xx_fixup
29 static struct gianfar_platform_data mpc85xx_tsec1_pdata = {
30 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
31 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
32 FSL_GIANFAR_DEV_HAS_MULTI_INTR,
33 .phy_reg_addr = MPC85xx_ENET1_OFFSET,
36 static struct gianfar_platform_data mpc85xx_tsec2_pdata = {
37 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
38 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
39 FSL_GIANFAR_DEV_HAS_MULTI_INTR,
40 .phy_reg_addr = MPC85xx_ENET1_OFFSET,
43 static struct gianfar_platform_data mpc85xx_etsec1_pdata = {
44 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
45 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
46 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
47 FSL_GIANFAR_DEV_HAS_CSUM | FSL_GIANFAR_DEV_HAS_VLAN |
48 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH,
49 .phy_reg_addr = MPC85xx_ENET1_OFFSET,
52 static struct gianfar_platform_data mpc85xx_etsec2_pdata = {
53 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
54 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
55 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
56 FSL_GIANFAR_DEV_HAS_CSUM | FSL_GIANFAR_DEV_HAS_VLAN |
57 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH,
58 .phy_reg_addr = MPC85xx_ENET1_OFFSET,
61 static struct gianfar_platform_data mpc85xx_etsec3_pdata = {
62 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
63 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
64 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
65 FSL_GIANFAR_DEV_HAS_CSUM | FSL_GIANFAR_DEV_HAS_VLAN |
66 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH,
67 .phy_reg_addr = MPC85xx_ENET1_OFFSET,
70 static struct gianfar_platform_data mpc85xx_etsec4_pdata = {
71 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
72 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
73 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
74 FSL_GIANFAR_DEV_HAS_CSUM | FSL_GIANFAR_DEV_HAS_VLAN |
75 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH,
76 .phy_reg_addr = MPC85xx_ENET1_OFFSET,
79 static struct gianfar_platform_data mpc85xx_fec_pdata = {
80 .phy_reg_addr = MPC85xx_ENET1_OFFSET,
83 static struct fsl_i2c_platform_data mpc85xx_fsl_i2c_pdata = {
84 .device_flags = FSL_I2C_DEV_SEPARATE_DFSRR,
87 static struct fsl_i2c_platform_data mpc85xx_fsl_i2c2_pdata = {
88 .device_flags = FSL_I2C_DEV_SEPARATE_DFSRR,
91 static struct plat_serial8250_port serial_platform_data[] = {
94 .irq = MPC85xx_IRQ_DUART,
96 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_SHARE_IRQ,
100 .irq = MPC85xx_IRQ_DUART,
102 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_SHARE_IRQ,
107 struct platform_device ppc_sys_platform_devices[] = {
109 .name = "fsl-gianfar",
111 .dev.platform_data = &mpc85xx_tsec1_pdata,
113 .resource = (struct resource[]) {
115 .start = MPC85xx_ENET1_OFFSET,
116 .end = MPC85xx_ENET1_OFFSET +
117 MPC85xx_ENET1_SIZE - 1,
118 .flags = IORESOURCE_MEM,
122 .start = MPC85xx_IRQ_TSEC1_TX,
123 .end = MPC85xx_IRQ_TSEC1_TX,
124 .flags = IORESOURCE_IRQ,
128 .start = MPC85xx_IRQ_TSEC1_RX,
129 .end = MPC85xx_IRQ_TSEC1_RX,
130 .flags = IORESOURCE_IRQ,
134 .start = MPC85xx_IRQ_TSEC1_ERROR,
135 .end = MPC85xx_IRQ_TSEC1_ERROR,
136 .flags = IORESOURCE_IRQ,
141 .name = "fsl-gianfar",
143 .dev.platform_data = &mpc85xx_tsec2_pdata,
145 .resource = (struct resource[]) {
147 .start = MPC85xx_ENET2_OFFSET,
148 .end = MPC85xx_ENET2_OFFSET +
149 MPC85xx_ENET2_SIZE - 1,
150 .flags = IORESOURCE_MEM,
154 .start = MPC85xx_IRQ_TSEC2_TX,
155 .end = MPC85xx_IRQ_TSEC2_TX,
156 .flags = IORESOURCE_IRQ,
160 .start = MPC85xx_IRQ_TSEC2_RX,
161 .end = MPC85xx_IRQ_TSEC2_RX,
162 .flags = IORESOURCE_IRQ,
166 .start = MPC85xx_IRQ_TSEC2_ERROR,
167 .end = MPC85xx_IRQ_TSEC2_ERROR,
168 .flags = IORESOURCE_IRQ,
173 .name = "fsl-gianfar",
175 .dev.platform_data = &mpc85xx_fec_pdata,
177 .resource = (struct resource[]) {
179 .start = MPC85xx_ENET3_OFFSET,
180 .end = MPC85xx_ENET3_OFFSET +
181 MPC85xx_ENET3_SIZE - 1,
182 .flags = IORESOURCE_MEM,
186 .start = MPC85xx_IRQ_FEC,
187 .end = MPC85xx_IRQ_FEC,
188 .flags = IORESOURCE_IRQ,
195 .dev.platform_data = &mpc85xx_fsl_i2c_pdata,
197 .resource = (struct resource[]) {
199 .start = MPC85xx_IIC1_OFFSET,
200 .end = MPC85xx_IIC1_OFFSET +
201 MPC85xx_IIC1_SIZE - 1,
202 .flags = IORESOURCE_MEM,
205 .start = MPC85xx_IRQ_IIC1,
206 .end = MPC85xx_IRQ_IIC1,
207 .flags = IORESOURCE_IRQ,
215 .resource = (struct resource[]) {
217 .start = MPC85xx_DMA0_OFFSET,
218 .end = MPC85xx_DMA0_OFFSET +
219 MPC85xx_DMA0_SIZE - 1,
220 .flags = IORESOURCE_MEM,
223 .start = MPC85xx_IRQ_DMA0,
224 .end = MPC85xx_IRQ_DMA0,
225 .flags = IORESOURCE_IRQ,
233 .resource = (struct resource[]) {
235 .start = MPC85xx_DMA1_OFFSET,
236 .end = MPC85xx_DMA1_OFFSET +
237 MPC85xx_DMA1_SIZE - 1,
238 .flags = IORESOURCE_MEM,
241 .start = MPC85xx_IRQ_DMA1,
242 .end = MPC85xx_IRQ_DMA1,
243 .flags = IORESOURCE_IRQ,
251 .resource = (struct resource[]) {
253 .start = MPC85xx_DMA2_OFFSET,
254 .end = MPC85xx_DMA2_OFFSET +
255 MPC85xx_DMA2_SIZE - 1,
256 .flags = IORESOURCE_MEM,
259 .start = MPC85xx_IRQ_DMA2,
260 .end = MPC85xx_IRQ_DMA2,
261 .flags = IORESOURCE_IRQ,
269 .resource = (struct resource[]) {
271 .start = MPC85xx_DMA3_OFFSET,
272 .end = MPC85xx_DMA3_OFFSET +
273 MPC85xx_DMA3_SIZE - 1,
274 .flags = IORESOURCE_MEM,
277 .start = MPC85xx_IRQ_DMA3,
278 .end = MPC85xx_IRQ_DMA3,
279 .flags = IORESOURCE_IRQ,
284 .name = "serial8250",
285 .id = PLAT8250_DEV_PLATFORM,
286 .dev.platform_data = serial_platform_data,
288 [MPC85xx_PERFMON] = {
289 .name = "fsl-perfmon",
292 .resource = (struct resource[]) {
294 .start = MPC85xx_PERFMON_OFFSET,
295 .end = MPC85xx_PERFMON_OFFSET +
296 MPC85xx_PERFMON_SIZE - 1,
297 .flags = IORESOURCE_MEM,
300 .start = MPC85xx_IRQ_PERFMON,
301 .end = MPC85xx_IRQ_PERFMON,
302 .flags = IORESOURCE_IRQ,
310 .resource = (struct resource[]) {
312 .start = MPC85xx_SEC2_OFFSET,
313 .end = MPC85xx_SEC2_OFFSET +
314 MPC85xx_SEC2_SIZE - 1,
315 .flags = IORESOURCE_MEM,
318 .start = MPC85xx_IRQ_SEC2,
319 .end = MPC85xx_IRQ_SEC2,
320 .flags = IORESOURCE_IRQ,
324 [MPC85xx_CPM_FCC1] = {
325 .name = "fsl-cpm-fcc",
328 .resource = (struct resource[]) {
332 .flags = IORESOURCE_MEM,
337 .flags = IORESOURCE_MEM,
340 .start = SIU_INT_FCC1,
342 .flags = IORESOURCE_IRQ,
346 [MPC85xx_CPM_FCC2] = {
347 .name = "fsl-cpm-fcc",
350 .resource = (struct resource[]) {
354 .flags = IORESOURCE_MEM,
359 .flags = IORESOURCE_MEM,
362 .start = SIU_INT_FCC2,
364 .flags = IORESOURCE_IRQ,
368 [MPC85xx_CPM_FCC3] = {
369 .name = "fsl-cpm-fcc",
372 .resource = (struct resource[]) {
376 .flags = IORESOURCE_MEM,
381 .flags = IORESOURCE_MEM,
384 .start = SIU_INT_FCC3,
386 .flags = IORESOURCE_IRQ,
390 [MPC85xx_CPM_I2C] = {
391 .name = "fsl-cpm-i2c",
394 .resource = (struct resource[]) {
398 .flags = IORESOURCE_MEM,
401 .start = SIU_INT_I2C,
403 .flags = IORESOURCE_IRQ,
407 [MPC85xx_CPM_SCC1] = {
408 .name = "fsl-cpm-scc",
411 .resource = (struct resource[]) {
415 .flags = IORESOURCE_MEM,
418 .start = SIU_INT_SCC1,
420 .flags = IORESOURCE_IRQ,
424 [MPC85xx_CPM_SCC2] = {
425 .name = "fsl-cpm-scc",
428 .resource = (struct resource[]) {
432 .flags = IORESOURCE_MEM,
435 .start = SIU_INT_SCC2,
437 .flags = IORESOURCE_IRQ,
441 [MPC85xx_CPM_SCC3] = {
442 .name = "fsl-cpm-scc",
445 .resource = (struct resource[]) {
449 .flags = IORESOURCE_MEM,
452 .start = SIU_INT_SCC3,
454 .flags = IORESOURCE_IRQ,
458 [MPC85xx_CPM_SCC4] = {
459 .name = "fsl-cpm-scc",
462 .resource = (struct resource[]) {
466 .flags = IORESOURCE_MEM,
469 .start = SIU_INT_SCC4,
471 .flags = IORESOURCE_IRQ,
475 [MPC85xx_CPM_SPI] = {
476 .name = "fsl-cpm-spi",
479 .resource = (struct resource[]) {
483 .flags = IORESOURCE_MEM,
486 .start = SIU_INT_SPI,
488 .flags = IORESOURCE_IRQ,
492 [MPC85xx_CPM_MCC1] = {
493 .name = "fsl-cpm-mcc",
496 .resource = (struct resource[]) {
500 .flags = IORESOURCE_MEM,
503 .start = SIU_INT_MCC1,
505 .flags = IORESOURCE_IRQ,
509 [MPC85xx_CPM_MCC2] = {
510 .name = "fsl-cpm-mcc",
513 .resource = (struct resource[]) {
517 .flags = IORESOURCE_MEM,
520 .start = SIU_INT_MCC2,
522 .flags = IORESOURCE_IRQ,
526 [MPC85xx_CPM_SMC1] = {
527 .name = "fsl-cpm-smc",
530 .resource = (struct resource[]) {
534 .flags = IORESOURCE_MEM,
537 .start = SIU_INT_SMC1,
539 .flags = IORESOURCE_IRQ,
543 [MPC85xx_CPM_SMC2] = {
544 .name = "fsl-cpm-smc",
547 .resource = (struct resource[]) {
551 .flags = IORESOURCE_MEM,
554 .start = SIU_INT_SMC2,
556 .flags = IORESOURCE_IRQ,
560 [MPC85xx_CPM_USB] = {
561 .name = "fsl-cpm-usb",
564 .resource = (struct resource[]) {
568 .flags = IORESOURCE_MEM,
571 .start = SIU_INT_USB,
573 .flags = IORESOURCE_IRQ,
578 .name = "fsl-gianfar",
580 .dev.platform_data = &mpc85xx_etsec1_pdata,
582 .resource = (struct resource[]) {
584 .start = MPC85xx_ENET1_OFFSET,
585 .end = MPC85xx_ENET1_OFFSET +
586 MPC85xx_ENET1_SIZE - 1,
587 .flags = IORESOURCE_MEM,
591 .start = MPC85xx_IRQ_TSEC1_TX,
592 .end = MPC85xx_IRQ_TSEC1_TX,
593 .flags = IORESOURCE_IRQ,
597 .start = MPC85xx_IRQ_TSEC1_RX,
598 .end = MPC85xx_IRQ_TSEC1_RX,
599 .flags = IORESOURCE_IRQ,
603 .start = MPC85xx_IRQ_TSEC1_ERROR,
604 .end = MPC85xx_IRQ_TSEC1_ERROR,
605 .flags = IORESOURCE_IRQ,
610 .name = "fsl-gianfar",
612 .dev.platform_data = &mpc85xx_etsec2_pdata,
614 .resource = (struct resource[]) {
616 .start = MPC85xx_ENET2_OFFSET,
617 .end = MPC85xx_ENET2_OFFSET +
618 MPC85xx_ENET2_SIZE - 1,
619 .flags = IORESOURCE_MEM,
623 .start = MPC85xx_IRQ_TSEC2_TX,
624 .end = MPC85xx_IRQ_TSEC2_TX,
625 .flags = IORESOURCE_IRQ,
629 .start = MPC85xx_IRQ_TSEC2_RX,
630 .end = MPC85xx_IRQ_TSEC2_RX,
631 .flags = IORESOURCE_IRQ,
635 .start = MPC85xx_IRQ_TSEC2_ERROR,
636 .end = MPC85xx_IRQ_TSEC2_ERROR,
637 .flags = IORESOURCE_IRQ,
642 .name = "fsl-gianfar",
644 .dev.platform_data = &mpc85xx_etsec3_pdata,
646 .resource = (struct resource[]) {
648 .start = MPC85xx_ENET3_OFFSET,
649 .end = MPC85xx_ENET3_OFFSET +
650 MPC85xx_ENET3_SIZE - 1,
651 .flags = IORESOURCE_MEM,
655 .start = MPC85xx_IRQ_TSEC3_TX,
656 .end = MPC85xx_IRQ_TSEC3_TX,
657 .flags = IORESOURCE_IRQ,
661 .start = MPC85xx_IRQ_TSEC3_RX,
662 .end = MPC85xx_IRQ_TSEC3_RX,
663 .flags = IORESOURCE_IRQ,
667 .start = MPC85xx_IRQ_TSEC3_ERROR,
668 .end = MPC85xx_IRQ_TSEC3_ERROR,
669 .flags = IORESOURCE_IRQ,
674 .name = "fsl-gianfar",
676 .dev.platform_data = &mpc85xx_etsec4_pdata,
678 .resource = (struct resource[]) {
682 .flags = IORESOURCE_MEM,
686 .start = MPC85xx_IRQ_TSEC4_TX,
687 .end = MPC85xx_IRQ_TSEC4_TX,
688 .flags = IORESOURCE_IRQ,
692 .start = MPC85xx_IRQ_TSEC4_RX,
693 .end = MPC85xx_IRQ_TSEC4_RX,
694 .flags = IORESOURCE_IRQ,
698 .start = MPC85xx_IRQ_TSEC4_ERROR,
699 .end = MPC85xx_IRQ_TSEC4_ERROR,
700 .flags = IORESOURCE_IRQ,
707 .dev.platform_data = &mpc85xx_fsl_i2c2_pdata,
709 .resource = (struct resource[]) {
713 .flags = IORESOURCE_MEM,
716 .start = MPC85xx_IRQ_IIC1,
717 .end = MPC85xx_IRQ_IIC1,
718 .flags = IORESOURCE_IRQ,
724 static int __init mach_mpc85xx_fixup(struct platform_device *pdev)
726 ppc_sys_fixup_mem_resource(pdev, CCSRBAR);
730 static int __init mach_mpc85xx_init(void)
732 ppc_sys_device_fixup = mach_mpc85xx_fixup;
736 postcore_initcall(mach_mpc85xx_init);