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   1 /*
   2  * linux/drivers/ide/pci/serverworks.c          Version 0.9     Mar 4 2007
   3  *
   4  * Copyright (C) 1998-2000 Michel Aubry
   5  * Copyright (C) 1998-2000 Andrzej Krzysztofowicz
   6  * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
   7  * Copyright (C)      2007 Bartlomiej Zolnierkiewicz
   8  * Portions copyright (c) 2001 Sun Microsystems
   9  *
  10  *
  11  * RCC/ServerWorks IDE driver for Linux
  12  *
  13  *   OSB4: `Open South Bridge' IDE Interface (fn 1)
  14  *         supports UDMA mode 2 (33 MB/s)
  15  *
  16  *   CSB5: `Champion South Bridge' IDE Interface (fn 1)
  17  *         all revisions support UDMA mode 4 (66 MB/s)
  18  *         revision A2.0 and up support UDMA mode 5 (100 MB/s)
  19  *
  20  *         *** The CSB5 does not provide ANY register ***
  21  *         *** to detect 80-conductor cable presence. ***
  22  *
  23  *   CSB6: `Champion South Bridge' IDE Interface (optional: third channel)
  24  *
  25  *   HT1000: AKA BCM5785 - Hypertransport Southbridge for Opteron systems. IDE
  26  *   controller same as the CSB6. Single channel ATA100 only.
  27  *
  28  * Documentation:
  29  *      Available under NDA only. Errata info very hard to get.
  30  *
  31  */
  32
  33 #include <linux/types.h>
  34 #include <linux/module.h>
  35 #include <linux/kernel.h>
  36 #include <linux/ioport.h>
  37 #include <linux/pci.h>
  38 #include <linux/hdreg.h>
  39 #include <linux/ide.h>
  40 #include <linux/init.h>
  41 #include <linux/delay.h>
  42
  43 #include <asm/io.h>
  44
  45 #define SVWKS_CSB5_REVISION_NEW 0x92 /* min PCI_REVISION_ID for UDMA5 (A2.0) */
  46 #define SVWKS_CSB6_REVISION     0xa0 /* min PCI_REVISION_ID for UDMA4 (A1.0) */
  47
  48 /* Seagate Barracuda ATA IV Family drives in UDMA mode 5
  49  * can overrun their FIFOs when used with the CSB5 */
  50 static const char *svwks_bad_ata100[] = {
  51         "ST320011A",
  52         "ST340016A",
  53         "ST360021A",
  54         "ST380021A",
  55         NULL
  56 };
  57
  58 static u8 svwks_revision = 0;
  59 static struct pci_dev *isa_dev;
  60
  61 static int check_in_drive_lists (ide_drive_t *drive, const char **list)
  62 {
  63         while (*list)
  64                 if (!strcmp(*list++, drive->id->model))
  65                         return 1;
  66         return 0;
  67 }
  68
  69 static u8 svwks_udma_filter(ide_drive_t *drive)
  70 {
  71         struct pci_dev *dev     = HWIF(drive)->pci_dev;
  72         u8 mask = 0;
  73
  74         if (!svwks_revision)
  75                 pci_read_config_byte(dev, PCI_REVISION_ID, &svwks_revision);
  76
  77         if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE)
  78                 return 0x1f;
  79         if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
  80                 u32 reg = 0;
  81                 if (isa_dev)
  82                         pci_read_config_dword(isa_dev, 0x64, &reg);
  83
  84                 /*
  85                  *      Don't enable UDMA on disk devices for the moment
  86                  */
  87                 if(drive->media == ide_disk)
  88                         return 0;
  89                 /* Check the OSB4 DMA33 enable bit */
  90                 return ((reg & 0x00004000) == 0x00004000) ? 0x07 : 0;
  91         } else if (svwks_revision < SVWKS_CSB5_REVISION_NEW) {
  92                 return 0x07;
  93         } else if (svwks_revision >= SVWKS_CSB5_REVISION_NEW) {
  94                 u8 btr = 0, mode;
  95                 pci_read_config_byte(dev, 0x5A, &btr);
  96                 mode = btr & 0x3;
  97
  98                 /* If someone decides to do UDMA133 on CSB5 the same
  99                    issue will bite so be inclusive */
 100                 if (mode > 2 && check_in_drive_lists(drive, svwks_bad_ata100))
 101                         mode = 2;
 102
 103                 switch(mode) {
 104                 case 2:  mask = 0x1f; break;
 105                 case 1:  mask = 0x07; break;
 106                 default: mask = 0x00; break;
 107                 }
 108         }
 109         if (((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
 110              (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) &&
 111             (!(PCI_FUNC(dev->devfn) & 1)))
 112                 mask = 0x1f;
 113
 114         return mask;
 115 }
 116
 117 static u8 svwks_csb_check (struct pci_dev *dev)
 118 {
 119         switch (dev->device) {
 120                 case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE:
 121                 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE:
 122                 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2:
 123                 case PCI_DEVICE_ID_SERVERWORKS_HT1000IDE:
 124                         return 1;
 125                 default:
 126                         break;
 127         }
 128         return 0;
 129 }
 130 static int svwks_tune_chipset (ide_drive_t *drive, u8 xferspeed)
 131 {
 132         static const u8 udma_modes[]            = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05 };
 133         static const u8 dma_modes[]             = { 0x77, 0x21, 0x20 };
 134         static const u8 pio_modes[]             = { 0x5d, 0x47, 0x34, 0x22, 0x20 };
 135         static const u8 drive_pci[]             = { 0x41, 0x40, 0x43, 0x42 };
 136         static const u8 drive_pci2[]            = { 0x45, 0x44, 0x47, 0x46 };
 137
 138         ide_hwif_t *hwif        = HWIF(drive);
 139         struct pci_dev *dev     = hwif->pci_dev;
 140         u8 speed                = ide_rate_filter(drive, xferspeed);
 141         u8 pio                  = ide_get_best_pio_mode(drive, 255, 4, NULL);
 142         u8 unit                 = (drive->select.b.unit & 0x01);
 143         u8 csb5                 = svwks_csb_check(dev);
 144         u8 ultra_enable         = 0, ultra_timing = 0;
 145         u8 dma_timing           = 0, pio_timing = 0;
 146         u16 csb5_pio            = 0;
 147
 148         /* If we are about to put a disk into UDMA mode we screwed up.
 149            Our code assumes we never _ever_ do this on an OSB4 */
 150
 151         if(dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4 &&
 152                 drive->media == ide_disk && speed >= XFER_UDMA_0)
 153                         BUG();
 154
 155         pci_read_config_byte(dev, drive_pci[drive->dn], &pio_timing);
 156         pci_read_config_byte(dev, drive_pci2[drive->dn], &dma_timing);
 157         pci_read_config_byte(dev, (0x56|hwif->channel), &ultra_timing);
 158         pci_read_config_word(dev, 0x4A, &csb5_pio);
 159         pci_read_config_byte(dev, 0x54, &ultra_enable);
 160
 161         /* If we are in RAID mode (eg AMI MegaIDE) then we can't it
 162            turns out trust the firmware configuration */
 163
 164         if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE)
 165                 goto oem_setup_failed;
 166
 167         /* Per Specified Design by OEM, and ASIC Architect */
 168         if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
 169             (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) {
 170                 if (!drive->init_speed) {
 171                         u8 dma_stat = inb(hwif->dma_status);
 172
 173 dma_pio:
 174                         if (((ultra_enable << (7-drive->dn) & 0x80) == 0x80) &&
 175                             ((dma_stat & (1<<(5+unit))) == (1<<(5+unit)))) {
 176                                 drive->current_speed = drive->init_speed = XFER_UDMA_0 + udma_modes[(ultra_timing >> (4*unit)) & ~(0xF0)];
 177                                 return 0;
 178                         } else if ((dma_timing) &&
 179                                    ((dma_stat&(1<<(5+unit)))==(1<<(5+unit)))) {
 180                                 u8 dmaspeed = dma_timing;
 181
 182                                 dma_timing &= ~0xFFU;
 183                                 if ((dmaspeed & 0x20) == 0x20)
 184                                         dmaspeed = XFER_MW_DMA_2;
 185                                 else if ((dmaspeed & 0x21) == 0x21)
 186                                         dmaspeed = XFER_MW_DMA_1;
 187                                 else if ((dmaspeed & 0x77) == 0x77)
 188                                         dmaspeed = XFER_MW_DMA_0;
 189                                 else
 190                                         goto dma_pio;
 191                                 drive->current_speed = drive->init_speed = dmaspeed;
 192                                 return 0;
 193                         } else if (pio_timing) {
 194                                 u8 piospeed = pio_timing;
 195
 196                                 pio_timing &= ~0xFFU;
 197                                 if ((piospeed & 0x20) == 0x20)
 198                                         piospeed = XFER_PIO_4;
 199                                 else if ((piospeed & 0x22) == 0x22)
 200                                         piospeed = XFER_PIO_3;
 201                                 else if ((piospeed & 0x34) == 0x34)
 202                                         piospeed = XFER_PIO_2;
 203                                 else if ((piospeed & 0x47) == 0x47)
 204                                         piospeed = XFER_PIO_1;
 205                                 else if ((piospeed & 0x5d) == 0x5d)
 206                                         piospeed = XFER_PIO_0;
 207                                 else
 208                                         goto oem_setup_failed;
 209                                 drive->current_speed = drive->init_speed = piospeed;
 210                                 return 0;
 211                         }
 212                 }
 213         }
 214
 215 oem_setup_failed:
 216
 217         pio_timing      &= ~0xFFU;
 218         dma_timing      &= ~0xFFU;
 219         ultra_timing    &= ~(0x0F << (4*unit));
 220         ultra_enable    &= ~(0x01 << drive->dn);
 221         csb5_pio        &= ~(0x0F << (4*drive->dn));
 222
 223         switch(speed) {
 224                 case XFER_PIO_4:
 225                 case XFER_PIO_3:
 226                 case XFER_PIO_2:
 227                 case XFER_PIO_1:
 228                 case XFER_PIO_0:
 229                         pio_timing |= pio_modes[speed - XFER_PIO_0];
 230                         csb5_pio   |= ((speed - XFER_PIO_0) << (4*drive->dn));
 231                         break;
 232
 233                 case XFER_MW_DMA_2:
 234                 case XFER_MW_DMA_1:
 235                 case XFER_MW_DMA_0:
 236                         /*
 237                          * TODO: always setup PIO mode so this won't be needed
 238                          */
 239                         pio_timing |= pio_modes[pio];
 240                         csb5_pio   |= (pio << (4*drive->dn));
 241                         dma_timing |= dma_modes[speed - XFER_MW_DMA_0];
 242                         break;
 243
 244                 case XFER_UDMA_5:
 245                 case XFER_UDMA_4:
 246                 case XFER_UDMA_3:
 247                 case XFER_UDMA_2:
 248                 case XFER_UDMA_1:
 249                 case XFER_UDMA_0:
 250                         /*
 251                          * TODO: always setup PIO mode so this won't be needed
 252                          */
 253                         pio_timing   |= pio_modes[pio];
 254                         csb5_pio     |= (pio << (4*drive->dn));
 255                         dma_timing   |= dma_modes[2];
 256                         ultra_timing |= ((udma_modes[speed - XFER_UDMA_0]) << (4*unit));
 257                         ultra_enable |= (0x01 << drive->dn);
 258                 default:
 259                         break;
 260         }
 261
 262         pci_write_config_byte(dev, drive_pci[drive->dn], pio_timing);
 263         if (csb5)
 264                 pci_write_config_word(dev, 0x4A, csb5_pio);
 265
 266         pci_write_config_byte(dev, drive_pci2[drive->dn], dma_timing);
 267         pci_write_config_byte(dev, (0x56|hwif->channel), ultra_timing);
 268         pci_write_config_byte(dev, 0x54, ultra_enable);
 269
 270         return (ide_config_drive_speed(drive, speed));
 271 }
 272
 273 static void svwks_tune_drive (ide_drive_t *drive, u8 pio)
 274 {
 275         pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
 276         (void)svwks_tune_chipset(drive, XFER_PIO_0 + pio);
 277 }
 278
 279 static int svwks_config_drive_xfer_rate (ide_drive_t *drive)
 280 {
 281         drive->init_speed = 0;
 282
 283         if (ide_tune_dma(drive))
 284                 return 0;
 285
 286         if (ide_use_fast_pio(drive))
 287                 svwks_tune_drive(drive, 255);
 288
 289         return -1;
 290 }
 291
 292 static unsigned int __devinit init_chipset_svwks (struct pci_dev *dev, const char *name)
 293 {
 294         unsigned int reg;
 295         u8 btr;
 296
 297         /* save revision id to determine DMA capability */
 298         pci_read_config_byte(dev, PCI_REVISION_ID, &svwks_revision);
 299
 300         /* force Master Latency Timer value to 64 PCICLKs */
 301         pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x40);
 302
 303         /* OSB4 : South Bridge and IDE */
 304         if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
 305                 isa_dev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
 306                           PCI_DEVICE_ID_SERVERWORKS_OSB4, NULL);
 307                 if (isa_dev) {
 308                         pci_read_config_dword(isa_dev, 0x64, &reg);
 309                         reg &= ~0x00002000; /* disable 600ns interrupt mask */
 310                         if(!(reg & 0x00004000))
 311                                 printk(KERN_DEBUG "%s: UDMA not BIOS enabled.\n", name);
 312                         reg |=  0x00004000; /* enable UDMA/33 support */
 313                         pci_write_config_dword(isa_dev, 0x64, reg);
 314                 }
 315         }
 316
 317         /* setup CSB5/CSB6 : South Bridge and IDE option RAID */
 318         else if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE) ||
 319                  (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
 320                  (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) {
 321
 322                 /* Third Channel Test */
 323                 if (!(PCI_FUNC(dev->devfn) & 1)) {
 324                         struct pci_dev * findev = NULL;
 325                         u32 reg4c = 0;
 326                         findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
 327                                 PCI_DEVICE_ID_SERVERWORKS_CSB5, NULL);
 328                         if (findev) {
 329                                 pci_read_config_dword(findev, 0x4C, &reg4c);
 330                                 reg4c &= ~0x000007FF;
 331                                 reg4c |=  0x00000040;
 332                                 reg4c |=  0x00000020;
 333                                 pci_write_config_dword(findev, 0x4C, reg4c);
 334                                 pci_dev_put(findev);
 335                         }
 336                         outb_p(0x06, 0x0c00);
 337                         dev->irq = inb_p(0x0c01);
 338                 } else {
 339                         struct pci_dev * findev = NULL;
 340                         u8 reg41 = 0;
 341
 342                         findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
 343                                         PCI_DEVICE_ID_SERVERWORKS_CSB6, NULL);
 344                         if (findev) {
 345                                 pci_read_config_byte(findev, 0x41, &reg41);
 346                                 reg41 &= ~0x40;
 347                                 pci_write_config_byte(findev, 0x41, reg41);
 348                                 pci_dev_put(findev);
 349                         }
 350                         /*
 351                          * This is a device pin issue on CSB6.
 352                          * Since there will be a future raid mode,
 353                          * early versions of the chipset require the
 354                          * interrupt pin to be set, and it is a compatibility
 355                          * mode issue.
 356                          */
 357                         if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE)
 358                                 dev->irq = 0;
 359                 }
 360 //              pci_read_config_dword(dev, 0x40, &pioreg)
 361 //              pci_write_config_dword(dev, 0x40, 0x99999999);
 362 //              pci_read_config_dword(dev, 0x44, &dmareg);
 363 //              pci_write_config_dword(dev, 0x44, 0xFFFFFFFF);
 364                 /* setup the UDMA Control register
 365                  *
 366                  * 1. clear bit 6 to enable DMA
 367                  * 2. enable DMA modes with bits 0-1
 368                  *      00 : legacy
 369                  *      01 : udma2
 370                  *      10 : udma2/udma4
 371                  *      11 : udma2/udma4/udma5
 372                  */
 373                 pci_read_config_byte(dev, 0x5A, &btr);
 374                 btr &= ~0x40;
 375                 if (!(PCI_FUNC(dev->devfn) & 1))
 376                         btr |= 0x2;
 377                 else
 378                         btr |= (svwks_revision >= SVWKS_CSB5_REVISION_NEW) ? 0x3 : 0x2;
 379                 pci_write_config_byte(dev, 0x5A, btr);
 380         }
 381         /* Setup HT1000 SouthBridge Controller - Single Channel Only */
 382         else if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE) {
 383                 pci_read_config_byte(dev, 0x5A, &btr);
 384                 btr &= ~0x40;
 385                 btr |= 0x3;
 386                 pci_write_config_byte(dev, 0x5A, btr);
 387         }
 388
 389         return dev->irq;
 390 }
 391
 392 static unsigned int __devinit ata66_svwks_svwks (ide_hwif_t *hwif)
 393 {
 394         return 1;
 395 }
 396
 397 /* On Dell PowerEdge servers with a CSB5/CSB6, the top two bits
 398  * of the subsystem device ID indicate presence of an 80-pin cable.
 399  * Bit 15 clear = secondary IDE channel does not have 80-pin cable.
 400  * Bit 15 set   = secondary IDE channel has 80-pin cable.
 401  * Bit 14 clear = primary IDE channel does not have 80-pin cable.
 402  * Bit 14 set   = primary IDE channel has 80-pin cable.
 403  */
 404 static unsigned int __devinit ata66_svwks_dell (ide_hwif_t *hwif)
 405 {
 406         struct pci_dev *dev = hwif->pci_dev;
 407         if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
 408             dev->vendor == PCI_VENDOR_ID_SERVERWORKS &&
 409             (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE ||
 410              dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE))
 411                 return ((1 << (hwif->channel + 14)) &
 412                         dev->subsystem_device) ? 1 : 0;
 413         return 0;
 414 }
 415
 416 /* Sun Cobalt Alpine hardware avoids the 80-pin cable
 417  * detect issue by attaching the drives directly to the board.
 418  * This check follows the Dell precedent (how scary is that?!)
 419  *
 420  * WARNING: this only works on Alpine hardware!
 421  */
 422 static unsigned int __devinit ata66_svwks_cobalt (ide_hwif_t *hwif)
 423 {
 424         struct pci_dev *dev = hwif->pci_dev;
 425         if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN &&
 426             dev->vendor == PCI_VENDOR_ID_SERVERWORKS &&
 427             dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE)
 428                 return ((1 << (hwif->channel + 14)) &
 429                         dev->subsystem_device) ? 1 : 0;
 430         return 0;
 431 }
 432
 433 static unsigned int __devinit ata66_svwks (ide_hwif_t *hwif)
 434 {
 435         struct pci_dev *dev = hwif->pci_dev;
 436
 437         /* Server Works */
 438         if (dev->subsystem_vendor == PCI_VENDOR_ID_SERVERWORKS)
 439                 return ata66_svwks_svwks (hwif);
 440
 441         /* Dell PowerEdge */
 442         if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL)
 443                 return ata66_svwks_dell (hwif);
 444
 445         /* Cobalt Alpine */
 446         if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN)
 447                 return ata66_svwks_cobalt (hwif);
 448
 449         /* Per Specified Design by OEM, and ASIC Architect */
 450         if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
 451             (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2))
 452                 return 1;
 453
 454         return 0;
 455 }
 456
 457 static void __devinit init_hwif_svwks (ide_hwif_t *hwif)
 458 {
 459         u8 dma_stat = 0;
 460
 461         if (!hwif->irq)
 462                 hwif->irq = hwif->channel ? 15 : 14;
 463
 464         hwif->tuneproc = &svwks_tune_drive;
 465         hwif->speedproc = &svwks_tune_chipset;
 466         hwif->udma_filter = &svwks_udma_filter;
 467
 468         hwif->atapi_dma = 1;
 469
 470         if (hwif->pci_dev->device != PCI_DEVICE_ID_SERVERWORKS_OSB4IDE)
 471                 hwif->ultra_mask = 0x3f;
 472
 473         hwif->mwdma_mask = 0x07;
 474
 475         hwif->autodma = 0;
 476
 477         if (!hwif->dma_base) {
 478                 hwif->drives[0].autotune = 1;
 479                 hwif->drives[1].autotune = 1;
 480                 return;
 481         }
 482
 483         hwif->ide_dma_check = &svwks_config_drive_xfer_rate;
 484         if (hwif->pci_dev->device != PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
 485                 if (!hwif->udma_four)
 486                         hwif->udma_four = ata66_svwks(hwif);
 487         }
 488         if (!noautodma)
 489                 hwif->autodma = 1;
 490
 491         dma_stat = inb(hwif->dma_status);
 492         hwif->drives[0].autodma = (dma_stat & 0x20);
 493         hwif->drives[1].autodma = (dma_stat & 0x40);
 494         hwif->drives[0].autotune = (!(dma_stat & 0x20));
 495         hwif->drives[1].autotune = (!(dma_stat & 0x40));
 496 }
 497
 498 static int __devinit init_setup_svwks (struct pci_dev *dev, ide_pci_device_t *d)
 499 {
 500         return ide_setup_pci_device(dev, d);
 501 }
 502
 503 static int __devinit init_setup_csb6 (struct pci_dev *dev, ide_pci_device_t *d)
 504 {
 505         if (!(PCI_FUNC(dev->devfn) & 1)) {
 506                 d->bootable = NEVER_BOARD;
 507                 if (dev->resource[0].start == 0x01f1)
 508                         d->bootable = ON_BOARD;
 509         }
 510
 511         d->channels = ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE ||
 512                         dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2) &&
 513                        (!(PCI_FUNC(dev->devfn) & 1))) ? 1 : 2;
 514
 515         return ide_setup_pci_device(dev, d);
 516 }
 517
 518 static ide_pci_device_t serverworks_chipsets[] __devinitdata = {
 519         {       /* 0 */
 520                 .name           = "SvrWks OSB4",
 521                 .init_setup     = init_setup_svwks,
 522                 .init_chipset   = init_chipset_svwks,
 523                 .init_hwif      = init_hwif_svwks,
 524                 .channels       = 2,
 525                 .autodma        = AUTODMA,
 526                 .bootable       = ON_BOARD,
 527         },{     /* 1 */
 528                 .name           = "SvrWks CSB5",
 529                 .init_setup     = init_setup_svwks,
 530                 .init_chipset   = init_chipset_svwks,
 531                 .init_hwif      = init_hwif_svwks,
 532                 .channels       = 2,
 533                 .autodma        = AUTODMA,
 534                 .bootable       = ON_BOARD,
 535         },{     /* 2 */
 536                 .name           = "SvrWks CSB6",
 537                 .init_setup     = init_setup_csb6,
 538                 .init_chipset   = init_chipset_svwks,
 539                 .init_hwif      = init_hwif_svwks,
 540                 .channels       = 2,
 541                 .autodma        = AUTODMA,
 542                 .bootable       = ON_BOARD,
 543         },{     /* 3 */
 544                 .name           = "SvrWks CSB6",
 545                 .init_setup     = init_setup_csb6,
 546                 .init_chipset   = init_chipset_svwks,
 547                 .init_hwif      = init_hwif_svwks,
 548                 .channels       = 1,    /* 2 */
 549                 .autodma        = AUTODMA,
 550                 .bootable       = ON_BOARD,
 551         },{     /* 4 */
 552                 .name           = "SvrWks HT1000",
 553                 .init_setup     = init_setup_svwks,
 554                 .init_chipset   = init_chipset_svwks,
 555                 .init_hwif      = init_hwif_svwks,
 556                 .channels       = 1,    /* 2 */
 557                 .autodma        = AUTODMA,
 558                 .bootable       = ON_BOARD,
 559         }
 560 };
 561
 562 /**
 563  *      svwks_init_one  -       called when a OSB/CSB is found
 564  *      @dev: the svwks device
 565  *      @id: the matching pci id
 566  *
 567  *      Called when the PCI registration layer (or the IDE initialization)
 568  *      finds a device matching our IDE device tables.
 569  */
 570
 571 static int __devinit svwks_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 572 {
 573         ide_pci_device_t *d = &serverworks_chipsets[id->driver_data];
 574
 575         return d->init_setup(dev, d);
 576 }
 577
 578 static struct pci_device_id svwks_pci_tbl[] = {
 579         { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_OSB4IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
 580         { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
 581         { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
 582         { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
 583         { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
 584         { 0, },
 585 };
 586 MODULE_DEVICE_TABLE(pci, svwks_pci_tbl);
 587
 588 static struct pci_driver driver = {
 589         .name           = "Serverworks_IDE",
 590         .id_table       = svwks_pci_tbl,
 591         .probe          = svwks_init_one,
 592 };
 593
 594 static int __init svwks_ide_init(void)
 595 {
 596         return ide_pci_register_driver(&driver);
 597 }
 598
 599 module_init(svwks_ide_init);
 600
 601 MODULE_AUTHOR("Michael Aubry. Andrzej Krzysztofowicz, Andre Hedrick");
 602 MODULE_DESCRIPTION("PCI driver module for Serverworks OSB4/CSB5/CSB6 IDE");
 603 MODULE_LICENSE("GPL");