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   1 /*
   2  * linux/drivers/ide/pci/sis5513.c      Version 0.16ac+vp       Jun 18, 2003
   3  *
   4  * Copyright (C) 1999-2000      Andre Hedrick <andre@linux-ide.org>
   5  * Copyright (C) 2002           Lionel Bouton <Lionel.Bouton@inet6.fr>, Maintainer
   6  * Copyright (C) 2003           Vojtech Pavlik <vojtech@suse.cz>
   7  * May be copied or modified under the terms of the GNU General Public License
   8  *
   9  *
  10  * Thanks :
  11  *
  12  * SiS Taiwan           : for direct support and hardware.
  13  * Daniela Engert       : for initial ATA100 advices and numerous others.
  14  * John Fremlin, Manfred Spraul, Dave Morgan, Peter Kjellerstedt        :
  15  *                        for checking code correctness, providing patches.
  16  *
  17  *
  18  * Original tests and design on the SiS620 chipset.
  19  * ATA100 tests and design on the SiS735 chipset.
  20  * ATA16/33 support from specs
  21  * ATA133 support for SiS961/962 by L.C. Chang <lcchang@sis.com.tw>
  22  * ATA133 961/962/963 fixes by Vojtech Pavlik <vojtech@suse.cz>
  23  *
  24  * Documentation:
  25  *      SiS chipset documentation available under NDA to companies only
  26  *      (not to individuals).
  27  */
  28
  29 /*
  30  * The original SiS5513 comes from a SiS5511/55112/5513 chipset. The original
  31  * SiS5513 was also used in the SiS5596/5513 chipset. Thus if we see a SiS5511
  32  * or SiS5596, we can assume we see the first MWDMA-16 capable SiS5513 chip.
  33  *
  34  * Later SiS chipsets integrated the 5513 functionality into the NorthBridge,
  35  * starting with SiS5571 and up to SiS745. The PCI ID didn't change, though. We
  36  * can figure out that we have a more modern and more capable 5513 by looking
  37  * for the respective NorthBridge IDs.
  38  *
  39  * Even later (96x family) SiS chipsets use the MuTIOL link and place the 5513
  40  * into the SouthBrige. Here we cannot rely on looking up the NorthBridge PCI
  41  * ID, while the now ATA-133 capable 5513 still has the same PCI ID.
  42  * Fortunately the 5513 can be 'unmasked' by fiddling with some config space
  43  * bits, changing its device id to the true one - 5517 for 961 and 5518 for
  44  * 962/963.
  45  */
  46
  47 #include <linux/types.h>
  48 #include <linux/module.h>
  49 #include <linux/kernel.h>
  50 #include <linux/delay.h>
  51 #include <linux/timer.h>
  52 #include <linux/mm.h>
  53 #include <linux/ioport.h>
  54 #include <linux/blkdev.h>
  55 #include <linux/hdreg.h>
  56
  57 #include <linux/interrupt.h>
  58 #include <linux/pci.h>
  59 #include <linux/init.h>
  60 #include <linux/ide.h>
  61
  62 #include <asm/irq.h>
  63
  64 #include "ide-timing.h"
  65
  66 #define DISPLAY_SIS_TIMINGS
  67
  68 /* registers layout and init values are chipset family dependant */
  69
  70 #define ATA_16          0x01
  71 #define ATA_33          0x02
  72 #define ATA_66          0x03
  73 #define ATA_100a        0x04 // SiS730/SiS550 is ATA100 with ATA66 layout
  74 #define ATA_100         0x05
  75 #define ATA_133a        0x06 // SiS961b with 133 support
  76 #define ATA_133         0x07 // SiS962/963
  77
  78 static u8 chipset_family;
  79
  80 /*
  81  * Devices supported
  82  */
  83 static const struct {
  84         const char *name;
  85         u16 host_id;
  86         u8 chipset_family;
  87         u8 flags;
  88 } SiSHostChipInfo[] = {
  89         { "SiS968",     PCI_DEVICE_ID_SI_968,   ATA_133  },
  90         { "SiS966",     PCI_DEVICE_ID_SI_966,   ATA_133  },
  91         { "SiS965",     PCI_DEVICE_ID_SI_965,   ATA_133  },
  92         { "SiS745",     PCI_DEVICE_ID_SI_745,   ATA_100  },
  93         { "SiS735",     PCI_DEVICE_ID_SI_735,   ATA_100  },
  94         { "SiS733",     PCI_DEVICE_ID_SI_733,   ATA_100  },
  95         { "SiS635",     PCI_DEVICE_ID_SI_635,   ATA_100  },
  96         { "SiS633",     PCI_DEVICE_ID_SI_633,   ATA_100  },
  97
  98         { "SiS730",     PCI_DEVICE_ID_SI_730,   ATA_100a },
  99         { "SiS550",     PCI_DEVICE_ID_SI_550,   ATA_100a },
 100
 101         { "SiS640",     PCI_DEVICE_ID_SI_640,   ATA_66   },
 102         { "SiS630",     PCI_DEVICE_ID_SI_630,   ATA_66   },
 103         { "SiS620",     PCI_DEVICE_ID_SI_620,   ATA_66   },
 104         { "SiS540",     PCI_DEVICE_ID_SI_540,   ATA_66   },
 105         { "SiS530",     PCI_DEVICE_ID_SI_530,   ATA_66   },
 106
 107         { "SiS5600",    PCI_DEVICE_ID_SI_5600,  ATA_33   },
 108         { "SiS5598",    PCI_DEVICE_ID_SI_5598,  ATA_33   },
 109         { "SiS5597",    PCI_DEVICE_ID_SI_5597,  ATA_33   },
 110         { "SiS5591/2",  PCI_DEVICE_ID_SI_5591,  ATA_33   },
 111         { "SiS5582",    PCI_DEVICE_ID_SI_5582,  ATA_33   },
 112         { "SiS5581",    PCI_DEVICE_ID_SI_5581,  ATA_33   },
 113
 114         { "SiS5596",    PCI_DEVICE_ID_SI_5596,  ATA_16   },
 115         { "SiS5571",    PCI_DEVICE_ID_SI_5571,  ATA_16   },
 116         { "SiS5517",    PCI_DEVICE_ID_SI_5517,  ATA_16   },
 117         { "SiS551x",    PCI_DEVICE_ID_SI_5511,  ATA_16   },
 118 };
 119
 120 /* Cycle time bits and values vary across chip dma capabilities
 121    These three arrays hold the register layout and the values to set.
 122    Indexed by chipset_family and (dma_mode - XFER_UDMA_0) */
 123
 124 /* {0, ATA_16, ATA_33, ATA_66, ATA_100a, ATA_100, ATA_133} */
 125 static u8 cycle_time_offset[] = {0,0,5,4,4,0,0};
 126 static u8 cycle_time_range[] = {0,0,2,3,3,4,4};
 127 static u8 cycle_time_value[][XFER_UDMA_6 - XFER_UDMA_0 + 1] = {
 128         {0,0,0,0,0,0,0}, /* no udma */
 129         {0,0,0,0,0,0,0}, /* no udma */
 130         {3,2,1,0,0,0,0}, /* ATA_33 */
 131         {7,5,3,2,1,0,0}, /* ATA_66 */
 132         {7,5,3,2,1,0,0}, /* ATA_100a (730 specific), differences are on cycle_time range and offset */
 133         {11,7,5,4,2,1,0}, /* ATA_100 */
 134         {15,10,7,5,3,2,1}, /* ATA_133a (earliest 691 southbridges) */
 135         {15,10,7,5,3,2,1}, /* ATA_133 */
 136 };
 137 /* CRC Valid Setup Time vary across IDE clock setting 33/66/100/133
 138    See SiS962 data sheet for more detail */
 139 static u8 cvs_time_value[][XFER_UDMA_6 - XFER_UDMA_0 + 1] = {
 140         {0,0,0,0,0,0,0}, /* no udma */
 141         {0,0,0,0,0,0,0}, /* no udma */
 142         {2,1,1,0,0,0,0},
 143         {4,3,2,1,0,0,0},
 144         {4,3,2,1,0,0,0},
 145         {6,4,3,1,1,1,0},
 146         {9,6,4,2,2,2,2},
 147         {9,6,4,2,2,2,2},
 148 };
 149 /* Initialize time, Active time, Recovery time vary across
 150    IDE clock settings. These 3 arrays hold the register value
 151    for PIO0/1/2/3/4 and DMA0/1/2 mode in order */
 152 static u8 ini_time_value[][8] = {
 153         {0,0,0,0,0,0,0,0},
 154         {0,0,0,0,0,0,0,0},
 155         {2,1,0,0,0,1,0,0},
 156         {4,3,1,1,1,3,1,1},
 157         {4,3,1,1,1,3,1,1},
 158         {6,4,2,2,2,4,2,2},
 159         {9,6,3,3,3,6,3,3},
 160         {9,6,3,3,3,6,3,3},
 161 };
 162 static u8 act_time_value[][8] = {
 163         {0,0,0,0,0,0,0,0},
 164         {0,0,0,0,0,0,0,0},
 165         {9,9,9,2,2,7,2,2},
 166         {19,19,19,5,4,14,5,4},
 167         {19,19,19,5,4,14,5,4},
 168         {28,28,28,7,6,21,7,6},
 169         {38,38,38,10,9,28,10,9},
 170         {38,38,38,10,9,28,10,9},
 171 };
 172 static u8 rco_time_value[][8] = {
 173         {0,0,0,0,0,0,0,0},
 174         {0,0,0,0,0,0,0,0},
 175         {9,2,0,2,0,7,1,1},
 176         {19,5,1,5,2,16,3,2},
 177         {19,5,1,5,2,16,3,2},
 178         {30,9,3,9,4,25,6,4},
 179         {40,12,4,12,5,34,12,5},
 180         {40,12,4,12,5,34,12,5},
 181 };
 182
 183 /*
 184  * Printing configuration
 185  */
 186 /* Used for chipset type printing at boot time */
 187 static char* chipset_capability[] = {
 188         "ATA", "ATA 16",
 189         "ATA 33", "ATA 66",
 190         "ATA 100 (1st gen)", "ATA 100 (2nd gen)",
 191         "ATA 133 (1st gen)", "ATA 133 (2nd gen)"
 192 };
 193
 194 #if defined(DISPLAY_SIS_TIMINGS) && defined(CONFIG_IDE_PROC_FS)
 195 #include <linux/stat.h>
 196 #include <linux/proc_fs.h>
 197
 198 static u8 sis_proc = 0;
 199
 200 static struct pci_dev *bmide_dev;
 201
 202 static char* cable_type[] = {
 203         "80 pins",
 204         "40 pins"
 205 };
 206
 207 static char* recovery_time[] ={
 208         "12 PCICLK", "1 PCICLK",
 209         "2 PCICLK", "3 PCICLK",
 210         "4 PCICLK", "5 PCICLCK",
 211         "6 PCICLK", "7 PCICLCK",
 212         "8 PCICLK", "9 PCICLCK",
 213         "10 PCICLK", "11 PCICLK",
 214         "13 PCICLK", "14 PCICLK",
 215         "15 PCICLK", "15 PCICLK"
 216 };
 217
 218 static char* active_time[] = {
 219         "8 PCICLK", "1 PCICLCK",
 220         "2 PCICLK", "3 PCICLK",
 221         "4 PCICLK", "5 PCICLK",
 222         "6 PCICLK", "12 PCICLK"
 223 };
 224
 225 static char* cycle_time[] = {
 226         "Reserved", "2 CLK",
 227         "3 CLK", "4 CLK",
 228         "5 CLK", "6 CLK",
 229         "7 CLK", "8 CLK",
 230         "9 CLK", "10 CLK",
 231         "11 CLK", "12 CLK",
 232         "13 CLK", "14 CLK",
 233         "15 CLK", "16 CLK"
 234 };
 235
 236 /* Generic add master or slave info function */
 237 static char* get_drives_info (char *buffer, u8 pos)
 238 {
 239         u8 reg00, reg01, reg10, reg11; /* timing registers */
 240         u32 regdw0, regdw1;
 241         char* p = buffer;
 242
 243 /* Postwrite/Prefetch */
 244         if (chipset_family < ATA_133) {
 245                 pci_read_config_byte(bmide_dev, 0x4b, &reg00);
 246                 p += sprintf(p, "Drive %d:        Postwrite %s \t \t Postwrite %s\n",
 247                              pos, (reg00 & (0x10 << pos)) ? "Enabled" : "Disabled",
 248                              (reg00 & (0x40 << pos)) ? "Enabled" : "Disabled");
 249                 p += sprintf(p, "                Prefetch  %s \t \t Prefetch  %s\n",
 250                              (reg00 & (0x01 << pos)) ? "Enabled" : "Disabled",
 251                              (reg00 & (0x04 << pos)) ? "Enabled" : "Disabled");
 252                 pci_read_config_byte(bmide_dev, 0x40+2*pos, &reg00);
 253                 pci_read_config_byte(bmide_dev, 0x41+2*pos, &reg01);
 254                 pci_read_config_byte(bmide_dev, 0x44+2*pos, &reg10);
 255                 pci_read_config_byte(bmide_dev, 0x45+2*pos, &reg11);
 256         } else {
 257                 u32 reg54h;
 258                 u8 drive_pci = 0x40;
 259                 pci_read_config_dword(bmide_dev, 0x54, &reg54h);
 260                 if (reg54h & 0x40000000) {
 261                         // Configuration space remapped to 0x70
 262                         drive_pci = 0x70;
 263                 }
 264                 pci_read_config_dword(bmide_dev, (unsigned long)drive_pci+4*pos, &regdw0);
 265                 pci_read_config_dword(bmide_dev, (unsigned long)drive_pci+4*pos+8, &regdw1);
 266
 267                 p += sprintf(p, "Drive %d:\n", pos);
 268         }
 269
 270
 271 /* UDMA */
 272         if (chipset_family >= ATA_133) {
 273                 p += sprintf(p, "                UDMA %s \t \t \t UDMA %s\n",
 274                              (regdw0 & 0x04) ? "Enabled" : "Disabled",
 275                              (regdw1 & 0x04) ? "Enabled" : "Disabled");
 276                 p += sprintf(p, "                UDMA Cycle Time    %s \t UDMA Cycle Time    %s\n",
 277                              cycle_time[(regdw0 & 0xF0) >> 4],
 278                              cycle_time[(regdw1 & 0xF0) >> 4]);
 279         } else if (chipset_family >= ATA_33) {
 280                 p += sprintf(p, "                UDMA %s \t \t \t UDMA %s\n",
 281                              (reg01 & 0x80) ? "Enabled" : "Disabled",
 282                              (reg11 & 0x80) ? "Enabled" : "Disabled");
 283
 284                 p += sprintf(p, "                UDMA Cycle Time    ");
 285                 switch(chipset_family) {
 286                         case ATA_33:    p += sprintf(p, cycle_time[(reg01 & 0x60) >> 5]); break;
 287                         case ATA_66:
 288                         case ATA_100a:  p += sprintf(p, cycle_time[(reg01 & 0x70) >> 4]); break;
 289                         case ATA_100:
 290                         case ATA_133a:  p += sprintf(p, cycle_time[reg01 & 0x0F]); break;
 291                         default:        p += sprintf(p, "?"); break;
 292                 }
 293                 p += sprintf(p, " \t UDMA Cycle Time    ");
 294                 switch(chipset_family) {
 295                         case ATA_33:    p += sprintf(p, cycle_time[(reg11 & 0x60) >> 5]); break;
 296                         case ATA_66:
 297                         case ATA_100a:  p += sprintf(p, cycle_time[(reg11 & 0x70) >> 4]); break;
 298                         case ATA_100:
 299                         case ATA_133a:  p += sprintf(p, cycle_time[reg11 & 0x0F]); break;
 300                         default:        p += sprintf(p, "?"); break;
 301                 }
 302                 p += sprintf(p, "\n");
 303         }
 304
 305
 306         if (chipset_family < ATA_133) { /* else case TODO */
 307
 308 /* Data Active */
 309                 p += sprintf(p, "                Data Active Time   ");
 310                 switch(chipset_family) {
 311                         case ATA_16: /* confirmed */
 312                         case ATA_33:
 313                         case ATA_66:
 314                         case ATA_100a: p += sprintf(p, active_time[reg01 & 0x07]); break;
 315                         case ATA_100:
 316                         case ATA_133a: p += sprintf(p, active_time[(reg00 & 0x70) >> 4]); break;
 317                         default: p += sprintf(p, "?"); break;
 318                 }
 319                 p += sprintf(p, " \t Data Active Time   ");
 320                 switch(chipset_family) {
 321                         case ATA_16:
 322                         case ATA_33:
 323                         case ATA_66:
 324                         case ATA_100a: p += sprintf(p, active_time[reg11 & 0x07]); break;
 325                         case ATA_100:
 326                         case ATA_133a: p += sprintf(p, active_time[(reg10 & 0x70) >> 4]); break;
 327                         default: p += sprintf(p, "?"); break;
 328                 }
 329                 p += sprintf(p, "\n");
 330
 331 /* Data Recovery */
 332         /* warning: may need (reg&0x07) for pre ATA66 chips */
 333                 p += sprintf(p, "                Data Recovery Time %s \t Data Recovery Time %s\n",
 334                              recovery_time[reg00 & 0x0f], recovery_time[reg10 & 0x0f]);
 335         }
 336
 337         return p;
 338 }
 339
 340 static char* get_masters_info(char* buffer)
 341 {
 342         return get_drives_info(buffer, 0);
 343 }
 344
 345 static char* get_slaves_info(char* buffer)
 346 {
 347         return get_drives_info(buffer, 1);
 348 }
 349
 350 /* Main get_info, called on /proc/ide/sis reads */
 351 static int sis_get_info (char *buffer, char **addr, off_t offset, int count)
 352 {
 353         char *p = buffer;
 354         int len;
 355         u8 reg;
 356         u16 reg2, reg3;
 357
 358         p += sprintf(p, "\nSiS 5513 ");
 359         switch(chipset_family) {
 360                 case ATA_16: p += sprintf(p, "DMA 16"); break;
 361                 case ATA_33: p += sprintf(p, "Ultra 33"); break;
 362                 case ATA_66: p += sprintf(p, "Ultra 66"); break;
 363                 case ATA_100a:
 364                 case ATA_100: p += sprintf(p, "Ultra 100"); break;
 365                 case ATA_133a:
 366                 case ATA_133: p += sprintf(p, "Ultra 133"); break;
 367                 default: p+= sprintf(p, "Unknown???"); break;
 368         }
 369         p += sprintf(p, " chipset\n");
 370         p += sprintf(p, "--------------- Primary Channel "
 371                      "---------------- Secondary Channel "
 372                      "-------------\n");
 373
 374 /* Status */
 375         pci_read_config_byte(bmide_dev, 0x4a, &reg);
 376         if (chipset_family == ATA_133) {
 377                 pci_read_config_word(bmide_dev, 0x50, &reg2);
 378                 pci_read_config_word(bmide_dev, 0x52, &reg3);
 379         }
 380         p += sprintf(p, "Channel Status: ");
 381         if (chipset_family < ATA_66) {
 382                 p += sprintf(p, "%s \t \t \t \t %s\n",
 383                              (reg & 0x04) ? "On" : "Off",
 384                              (reg & 0x02) ? "On" : "Off");
 385         } else if (chipset_family < ATA_133) {
 386                 p += sprintf(p, "%s \t \t \t \t %s \n",
 387                              (reg & 0x02) ? "On" : "Off",
 388                              (reg & 0x04) ? "On" : "Off");
 389         } else { /* ATA_133 */
 390                 p += sprintf(p, "%s \t \t \t \t %s \n",
 391                              (reg2 & 0x02) ? "On" : "Off",
 392                              (reg3 & 0x02) ? "On" : "Off");
 393         }
 394
 395 /* Operation Mode */
 396         pci_read_config_byte(bmide_dev, 0x09, &reg);
 397         p += sprintf(p, "Operation Mode: %s \t \t \t %s \n",
 398                      (reg & 0x01) ? "Native" : "Compatible",
 399                      (reg & 0x04) ? "Native" : "Compatible");
 400
 401 /* 80-pin cable ? */
 402         if (chipset_family >= ATA_133) {
 403                 p += sprintf(p, "Cable Type:     %s \t \t \t %s\n",
 404                              (reg2 & 0x01) ? cable_type[1] : cable_type[0],
 405                              (reg3 & 0x01) ? cable_type[1] : cable_type[0]);
 406         } else if (chipset_family > ATA_33) {
 407                 pci_read_config_byte(bmide_dev, 0x48, &reg);
 408                 p += sprintf(p, "Cable Type:     %s \t \t \t %s\n",
 409                              (reg & 0x10) ? cable_type[1] : cable_type[0],
 410                              (reg & 0x20) ? cable_type[1] : cable_type[0]);
 411         }
 412
 413 /* Prefetch Count */
 414         if (chipset_family < ATA_133) {
 415                 pci_read_config_word(bmide_dev, 0x4c, &reg2);
 416                 pci_read_config_word(bmide_dev, 0x4e, &reg3);
 417                 p += sprintf(p, "Prefetch Count: %d \t \t \t \t %d\n",
 418                              reg2, reg3);
 419         }
 420
 421         p = get_masters_info(p);
 422         p = get_slaves_info(p);
 423
 424         len = (p - buffer) - offset;
 425         *addr = buffer + offset;
 426
 427         return len > count ? count : len;
 428 }
 429 #endif /* defined(DISPLAY_SIS_TIMINGS) && defined(CONFIG_IDE_PROC_FS) */
 430
 431 /*
 432  * Configuration functions
 433  */
 434 /* Enables per-drive prefetch and postwrite */
 435 static void config_drive_art_rwp (ide_drive_t *drive)
 436 {
 437         ide_hwif_t *hwif        = HWIF(drive);
 438         struct pci_dev *dev     = hwif->pci_dev;
 439
 440         u8 reg4bh               = 0;
 441         u8 rw_prefetch          = (0x11 << drive->dn);
 442
 443         if (drive->media != ide_disk)
 444                 return;
 445         pci_read_config_byte(dev, 0x4b, &reg4bh);
 446
 447         if ((reg4bh & rw_prefetch) != rw_prefetch)
 448                 pci_write_config_byte(dev, 0x4b, reg4bh|rw_prefetch);
 449 }
 450
 451
 452 /* Set per-drive active and recovery time */
 453 static void config_art_rwp_pio (ide_drive_t *drive, u8 pio)
 454 {
 455         ide_hwif_t *hwif        = HWIF(drive);
 456         struct pci_dev *dev     = hwif->pci_dev;
 457
 458         u8                      timing, drive_pci, test1, test2;
 459
 460         u16 eide_pio_timing[6] = {600, 390, 240, 180, 120, 90};
 461         u16 xfer_pio = drive->id->eide_pio_modes;
 462
 463         config_drive_art_rwp(drive);
 464         pio = ide_get_best_pio_mode(drive, 255, pio, NULL);
 465
 466         if (xfer_pio> 4)
 467                 xfer_pio = 0;
 468
 469         if (drive->id->eide_pio_iordy > 0) {
 470                 for (xfer_pio = 5;
 471                         (xfer_pio > 0) &&
 472                         (drive->id->eide_pio_iordy > eide_pio_timing[xfer_pio]);
 473                         xfer_pio--);
 474         } else {
 475                 xfer_pio = (drive->id->eide_pio_modes & 4) ? 0x05 :
 476                            (drive->id->eide_pio_modes & 2) ? 0x04 :
 477                            (drive->id->eide_pio_modes & 1) ? 0x03 : xfer_pio;
 478         }
 479
 480         timing = (xfer_pio >= pio) ? xfer_pio : pio;
 481
 482         /* In pre ATA_133 case, drives sit at 0x40 + 4*drive->dn */
 483         drive_pci = 0x40;
 484         /* In SiS962 case drives sit at (0x40 or 0x70) + 8*drive->dn) */
 485         if (chipset_family >= ATA_133) {
 486                 u32 reg54h;
 487                 pci_read_config_dword(dev, 0x54, &reg54h);
 488                 if (reg54h & 0x40000000) drive_pci = 0x70;
 489                 drive_pci += ((drive->dn)*0x4);
 490         } else {
 491                 drive_pci += ((drive->dn)*0x2);
 492         }
 493
 494         /* register layout changed with newer ATA100 chips */
 495         if (chipset_family < ATA_100) {
 496                 pci_read_config_byte(dev, drive_pci, &test1);
 497                 pci_read_config_byte(dev, drive_pci+1, &test2);
 498
 499                 /* Clear active and recovery timings */
 500                 test1 &= ~0x0F;
 501                 test2 &= ~0x07;
 502
 503                 switch(timing) {
 504                         case 4:         test1 |= 0x01; test2 |= 0x03; break;
 505                         case 3:         test1 |= 0x03; test2 |= 0x03; break;
 506                         case 2:         test1 |= 0x04; test2 |= 0x04; break;
 507                         case 1:         test1 |= 0x07; test2 |= 0x06; break;
 508                         default:        break;
 509                 }
 510                 pci_write_config_byte(dev, drive_pci, test1);
 511                 pci_write_config_byte(dev, drive_pci+1, test2);
 512         } else if (chipset_family < ATA_133) {
 513                 switch(timing) { /*             active  recovery
 514                                                   v     v */
 515                         case 4:         test1 = 0x30|0x01; break;
 516                         case 3:         test1 = 0x30|0x03; break;
 517                         case 2:         test1 = 0x40|0x04; break;
 518                         case 1:         test1 = 0x60|0x07; break;
 519                         case 0:         test1 = 0x00; break;
 520                         default:        break;
 521                 }
 522                 pci_write_config_byte(dev, drive_pci, test1);
 523         } else { /* ATA_133 */
 524                 u32 test3;
 525                 pci_read_config_dword(dev, drive_pci, &test3);
 526                 test3 &= 0xc0c00fff;
 527                 if (test3 & 0x08) {
 528                         test3 |= (unsigned long)ini_time_value[ATA_133][timing] << 12;
 529                         test3 |= (unsigned long)act_time_value[ATA_133][timing] << 16;
 530                         test3 |= (unsigned long)rco_time_value[ATA_133][timing] << 24;
 531                 } else {
 532                         test3 |= (unsigned long)ini_time_value[ATA_100][timing] << 12;
 533                         test3 |= (unsigned long)act_time_value[ATA_100][timing] << 16;
 534                         test3 |= (unsigned long)rco_time_value[ATA_100][timing] << 24;
 535                 }
 536                 pci_write_config_dword(dev, drive_pci, test3);
 537         }
 538 }
 539
 540 static int config_chipset_for_pio (ide_drive_t *drive, u8 pio)
 541 {
 542         if (pio == 255)
 543                 pio = ide_find_best_mode(drive, XFER_PIO | XFER_EPIO) - XFER_PIO_0;
 544         config_art_rwp_pio(drive, pio);
 545         return ide_config_drive_speed(drive, XFER_PIO_0 + min_t(u8, pio, 4));
 546 }
 547
 548 static int sis5513_tune_chipset (ide_drive_t *drive, u8 xferspeed)
 549 {
 550         ide_hwif_t *hwif        = HWIF(drive);
 551         struct pci_dev *dev     = hwif->pci_dev;
 552
 553         u8 drive_pci, reg, speed;
 554         u32 regdw;
 555
 556         speed = ide_rate_filter(drive, xferspeed);
 557
 558         /* See config_art_rwp_pio for drive pci config registers */
 559         drive_pci = 0x40;
 560         if (chipset_family >= ATA_133) {
 561                 u32 reg54h;
 562                 pci_read_config_dword(dev, 0x54, &reg54h);
 563                 if (reg54h & 0x40000000) drive_pci = 0x70;
 564                 drive_pci += ((drive->dn)*0x4);
 565                 pci_read_config_dword(dev, (unsigned long)drive_pci, &regdw);
 566                 /* Disable UDMA bit for non UDMA modes on UDMA chips */
 567                 if (speed < XFER_UDMA_0) {
 568                         regdw &= 0xfffffffb;
 569                         pci_write_config_dword(dev, (unsigned long)drive_pci, regdw);
 570                 }
 571
 572         } else {
 573                 drive_pci += ((drive->dn)*0x2);
 574                 pci_read_config_byte(dev, drive_pci+1, &reg);
 575                 /* Disable UDMA bit for non UDMA modes on UDMA chips */
 576                 if ((speed < XFER_UDMA_0) && (chipset_family > ATA_16)) {
 577                         reg &= 0x7F;
 578                         pci_write_config_byte(dev, drive_pci+1, reg);
 579                 }
 580         }
 581
 582         /* Config chip for mode */
 583         switch(speed) {
 584                 case XFER_UDMA_6:
 585                 case XFER_UDMA_5:
 586                 case XFER_UDMA_4:
 587                 case XFER_UDMA_3:
 588                 case XFER_UDMA_2:
 589                 case XFER_UDMA_1:
 590                 case XFER_UDMA_0:
 591                         if (chipset_family >= ATA_133) {
 592                                 regdw |= 0x04;
 593                                 regdw &= 0xfffff00f;
 594                                 /* check if ATA133 enable */
 595                                 if (regdw & 0x08) {
 596                                         regdw |= (unsigned long)cycle_time_value[ATA_133][speed-XFER_UDMA_0] << 4;
 597                                         regdw |= (unsigned long)cvs_time_value[ATA_133][speed-XFER_UDMA_0] << 8;
 598                                 } else {
 599                                 /* if ATA133 disable, we should not set speed above UDMA5 */
 600                                         if (speed > XFER_UDMA_5)
 601                                                 speed = XFER_UDMA_5;
 602                                         regdw |= (unsigned long)cycle_time_value[ATA_100][speed-XFER_UDMA_0] << 4;
 603                                         regdw |= (unsigned long)cvs_time_value[ATA_100][speed-XFER_UDMA_0] << 8;
 604                                 }
 605                                 pci_write_config_dword(dev, (unsigned long)drive_pci, regdw);
 606                         } else {
 607                                 /* Force the UDMA bit on if we want to use UDMA */
 608                                 reg |= 0x80;
 609                                 /* clean reg cycle time bits */
 610                                 reg &= ~((0xFF >> (8 - cycle_time_range[chipset_family]))
 611                                          << cycle_time_offset[chipset_family]);
 612                                 /* set reg cycle time bits */
 613                                 reg |= cycle_time_value[chipset_family][speed-XFER_UDMA_0]
 614                                         << cycle_time_offset[chipset_family];
 615                                 pci_write_config_byte(dev, drive_pci+1, reg);
 616                         }
 617                         break;
 618                 case XFER_MW_DMA_2:
 619                 case XFER_MW_DMA_1:
 620                 case XFER_MW_DMA_0:
 621                 case XFER_SW_DMA_2:
 622                 case XFER_SW_DMA_1:
 623                 case XFER_SW_DMA_0:
 624                         break;
 625                 case XFER_PIO_4: return((int) config_chipset_for_pio(drive, 4));
 626                 case XFER_PIO_3: return((int) config_chipset_for_pio(drive, 3));
 627                 case XFER_PIO_2: return((int) config_chipset_for_pio(drive, 2));
 628                 case XFER_PIO_1: return((int) config_chipset_for_pio(drive, 1));
 629                 case XFER_PIO_0:
 630                 default:         return((int) config_chipset_for_pio(drive, 0));
 631         }
 632
 633         return ((int) ide_config_drive_speed(drive, speed));
 634 }
 635
 636 static void sis5513_tune_drive (ide_drive_t *drive, u8 pio)
 637 {
 638         (void) config_chipset_for_pio(drive, pio);
 639 }
 640
 641 static int sis5513_config_xfer_rate(ide_drive_t *drive)
 642 {
 643         config_art_rwp_pio(drive, 5);
 644
 645         drive->init_speed = 0;
 646
 647         if (ide_tune_dma(drive))
 648                 return 0;
 649
 650         if (ide_use_fast_pio(drive))
 651                 sis5513_tune_drive(drive, 5);
 652
 653         return -1;
 654 }
 655
 656 /* Chip detection and general config */
 657 static unsigned int __devinit init_chipset_sis5513 (struct pci_dev *dev, const char *name)
 658 {
 659         struct pci_dev *host;
 660         int i = 0;
 661
 662         chipset_family = 0;
 663
 664         for (i = 0; i < ARRAY_SIZE(SiSHostChipInfo) && !chipset_family; i++) {
 665
 666                 host = pci_get_device(PCI_VENDOR_ID_SI, SiSHostChipInfo[i].host_id, NULL);
 667
 668                 if (!host)
 669                         continue;
 670
 671                 chipset_family = SiSHostChipInfo[i].chipset_family;
 672
 673                 /* Special case for SiS630 : 630S/ET is ATA_100a */
 674                 if (SiSHostChipInfo[i].host_id == PCI_DEVICE_ID_SI_630) {
 675                         u8 hostrev;
 676                         pci_read_config_byte(host, PCI_REVISION_ID, &hostrev);
 677                         if (hostrev >= 0x30)
 678                                 chipset_family = ATA_100a;
 679                 }
 680                 pci_dev_put(host);
 681
 682                 printk(KERN_INFO "SIS5513: %s %s controller\n",
 683                          SiSHostChipInfo[i].name, chipset_capability[chipset_family]);
 684         }
 685
 686         if (!chipset_family) { /* Belongs to pci-quirks */
 687
 688                         u32 idemisc;
 689                         u16 trueid;
 690
 691                         /* Disable ID masking and register remapping */
 692                         pci_read_config_dword(dev, 0x54, &idemisc);
 693                         pci_write_config_dword(dev, 0x54, (idemisc & 0x7fffffff));
 694                         pci_read_config_word(dev, PCI_DEVICE_ID, &trueid);
 695                         pci_write_config_dword(dev, 0x54, idemisc);
 696
 697                         if (trueid == 0x5518) {
 698                                 printk(KERN_INFO "SIS5513: SiS 962/963 MuTIOL IDE UDMA133 controller\n");
 699                                 chipset_family = ATA_133;
 700
 701                                 /* Check for 5513 compability mapping
 702                                  * We must use this, else the port enabled code will fail,
 703                                  * as it expects the enablebits at 0x4a.
 704                                  */
 705                                 if ((idemisc & 0x40000000) == 0) {
 706                                         pci_write_config_dword(dev, 0x54, idemisc | 0x40000000);
 707                                         printk(KERN_INFO "SIS5513: Switching to 5513 register mapping\n");
 708                                 }
 709                         }
 710         }
 711
 712         if (!chipset_family) { /* Belongs to pci-quirks */
 713
 714                         struct pci_dev *lpc_bridge;
 715                         u16 trueid;
 716                         u8 prefctl;
 717                         u8 idecfg;
 718                         u8 sbrev;
 719
 720                         pci_read_config_byte(dev, 0x4a, &idecfg);
 721                         pci_write_config_byte(dev, 0x4a, idecfg | 0x10);
 722                         pci_read_config_word(dev, PCI_DEVICE_ID, &trueid);
 723                         pci_write_config_byte(dev, 0x4a, idecfg);
 724
 725                         if (trueid == 0x5517) { /* SiS 961/961B */
 726
 727                                 lpc_bridge = pci_get_slot(dev->bus, 0x10); /* Bus 0, Dev 2, Fn 0 */
 728                                 pci_read_config_byte(lpc_bridge, PCI_REVISION_ID, &sbrev);
 729                                 pci_read_config_byte(dev, 0x49, &prefctl);
 730                                 pci_dev_put(lpc_bridge);
 731
 732                                 if (sbrev == 0x10 && (prefctl & 0x80)) {
 733                                         printk(KERN_INFO "SIS5513: SiS 961B MuTIOL IDE UDMA133 controller\n");
 734                                         chipset_family = ATA_133a;
 735                                 } else {
 736                                         printk(KERN_INFO "SIS5513: SiS 961 MuTIOL IDE UDMA100 controller\n");
 737                                         chipset_family = ATA_100;
 738                                 }
 739                         }
 740         }
 741
 742         if (!chipset_family)
 743                 return -1;
 744
 745         /* Make general config ops here
 746            1/ tell IDE channels to operate in Compatibility mode only
 747            2/ tell old chips to allow per drive IDE timings */
 748
 749         {
 750                 u8 reg;
 751                 u16 regw;
 752
 753                 switch(chipset_family) {
 754                         case ATA_133:
 755                                 /* SiS962 operation mode */
 756                                 pci_read_config_word(dev, 0x50, &regw);
 757                                 if (regw & 0x08)
 758                                         pci_write_config_word(dev, 0x50, regw&0xfff7);
 759                                 pci_read_config_word(dev, 0x52, &regw);
 760                                 if (regw & 0x08)
 761                                         pci_write_config_word(dev, 0x52, regw&0xfff7);
 762                                 break;
 763                         case ATA_133a:
 764                         case ATA_100:
 765                                 /* Fixup latency */
 766                                 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x80);
 767                                 /* Set compatibility bit */
 768                                 pci_read_config_byte(dev, 0x49, &reg);
 769                                 if (!(reg & 0x01)) {
 770                                         pci_write_config_byte(dev, 0x49, reg|0x01);
 771                                 }
 772                                 break;
 773                         case ATA_100a:
 774                         case ATA_66:
 775                                 /* Fixup latency */
 776                                 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x10);
 777
 778                                 /* On ATA_66 chips the bit was elsewhere */
 779                                 pci_read_config_byte(dev, 0x52, &reg);
 780                                 if (!(reg & 0x04)) {
 781                                         pci_write_config_byte(dev, 0x52, reg|0x04);
 782                                 }
 783                                 break;
 784                         case ATA_33:
 785                                 /* On ATA_33 we didn't have a single bit to set */
 786                                 pci_read_config_byte(dev, 0x09, &reg);
 787                                 if ((reg & 0x0f) != 0x00) {
 788                                         pci_write_config_byte(dev, 0x09, reg&0xf0);
 789                                 }
 790                         case ATA_16:
 791                                 /* force per drive recovery and active timings
 792                                    needed on ATA_33 and below chips */
 793                                 pci_read_config_byte(dev, 0x52, &reg);
 794                                 if (!(reg & 0x08)) {
 795                                         pci_write_config_byte(dev, 0x52, reg|0x08);
 796                                 }
 797                                 break;
 798                 }
 799
 800 #if defined(DISPLAY_SIS_TIMINGS) && defined(CONFIG_IDE_PROC_FS)
 801                 if (!sis_proc) {
 802                         sis_proc = 1;
 803                         bmide_dev = dev;
 804                         ide_pci_create_host_proc("sis", sis_get_info);
 805                 }
 806 #endif
 807         }
 808
 809         return 0;
 810 }
 811
 812 static unsigned int __devinit ata66_sis5513 (ide_hwif_t *hwif)
 813 {
 814         u8 ata66 = 0;
 815
 816         if (chipset_family >= ATA_133) {
 817                 u16 regw = 0;
 818                 u16 reg_addr = hwif->channel ? 0x52: 0x50;
 819                 pci_read_config_word(hwif->pci_dev, reg_addr, &regw);
 820                 ata66 = (regw & 0x8000) ? 0 : 1;
 821         } else if (chipset_family >= ATA_66) {
 822                 u8 reg48h = 0;
 823                 u8 mask = hwif->channel ? 0x20 : 0x10;
 824                 pci_read_config_byte(hwif->pci_dev, 0x48, &reg48h);
 825                 ata66 = (reg48h & mask) ? 0 : 1;
 826         }
 827         return ata66;
 828 }
 829
 830 static void __devinit init_hwif_sis5513 (ide_hwif_t *hwif)
 831 {
 832         u8 udma_rates[] = { 0x00, 0x00, 0x07, 0x1f, 0x3f, 0x3f, 0x7f, 0x7f };
 833
 834         hwif->autodma = 0;
 835
 836         if (!hwif->irq)
 837                 hwif->irq = hwif->channel ? 15 : 14;
 838
 839         hwif->tuneproc = &sis5513_tune_drive;
 840         hwif->speedproc = &sis5513_tune_chipset;
 841
 842         if (!(hwif->dma_base)) {
 843                 hwif->drives[0].autotune = 1;
 844                 hwif->drives[1].autotune = 1;
 845                 return;
 846         }
 847
 848         hwif->atapi_dma = 1;
 849
 850         hwif->ultra_mask = udma_rates[chipset_family];
 851         hwif->mwdma_mask = 0x07;
 852         hwif->swdma_mask = 0x07;
 853
 854         if (!chipset_family)
 855                 return;
 856
 857         if (!(hwif->udma_four))
 858                 hwif->udma_four = ata66_sis5513(hwif);
 859
 860         if (chipset_family > ATA_16) {
 861                 hwif->ide_dma_check = &sis5513_config_xfer_rate;
 862                 if (!noautodma)
 863                         hwif->autodma = 1;
 864         }
 865         hwif->drives[0].autodma = hwif->autodma;
 866         hwif->drives[1].autodma = hwif->autodma;
 867         return;
 868 }
 869
 870 static ide_pci_device_t sis5513_chipset __devinitdata = {
 871         .name           = "SIS5513",
 872         .init_chipset   = init_chipset_sis5513,
 873         .init_hwif      = init_hwif_sis5513,
 874         .channels       = 2,
 875         .autodma        = NOAUTODMA,
 876         .enablebits     = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
 877         .bootable       = ON_BOARD,
 878 };
 879
 880 static int __devinit sis5513_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 881 {
 882         return ide_setup_pci_device(dev, &sis5513_chipset);
 883 }
 884
 885 static struct pci_device_id sis5513_pci_tbl[] = {
 886         { PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5513, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
 887         { PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5518, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
 888         { 0, },
 889 };
 890 MODULE_DEVICE_TABLE(pci, sis5513_pci_tbl);
 891
 892 static struct pci_driver driver = {
 893         .name           = "SIS_IDE",
 894         .id_table       = sis5513_pci_tbl,
 895         .probe          = sis5513_init_one,
 896 };
 897
 898 static int __init sis5513_ide_init(void)
 899 {
 900         return ide_pci_register_driver(&driver);
 901 }
 902
 903 module_init(sis5513_ide_init);
 904
 905 MODULE_AUTHOR("Lionel Bouton, L C Chang, Andre Hedrick, Vojtech Pavlik");
 906 MODULE_DESCRIPTION("PCI driver module for SIS IDE");
 907 MODULE_LICENSE("GPL");
 908
 909 /*
 910  * TODO:
 911  *      - CLEANUP
 912  *      - Use drivers/ide/ide-timing.h !
 913  *      - More checks in the config registers (force values instead of
 914  *        relying on the BIOS setting them correctly).
 915  *      - Further optimisations ?
 916  *        . for example ATA66+ regs 0x48 & 0x4A
 917  */