2 * File: arch/blackfin/mach-common/ints-priority-sc.c
7 * Description: Set up the interrupt priorities
11 * 1999 D. Jeff Dionne <jeff@uclinux.org>
12 * 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
13 * 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
14 * 2003 Metrowerks/Motorola
15 * 2003 Bas Vermeulen <bas@buyways.nl>
16 * Copyright 2004-2007 Analog Devices Inc.
18 * Bugs: Enter bugs at http://blackfin.uclinux.org/
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2 of the License, or
23 * (at your option) any later version.
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, see the file COPYING, or write
32 * to the Free Software Foundation, Inc.,
33 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
36 #include <linux/module.h>
37 #include <linux/kernel_stat.h>
38 #include <linux/seq_file.h>
39 #include <linux/irq.h>
41 #include <linux/kgdb.h>
43 #include <asm/traps.h>
44 #include <asm/blackfin.h>
46 #include <asm/irq_handler.h>
49 # define BF537_GENERIC_ERROR_INT_DEMUX
51 # undef BF537_GENERIC_ERROR_INT_DEMUX
56 * - we have separated the physical Hardware interrupt from the
57 * levels that the LINUX kernel sees (see the description in irq.h)
61 /* Initialize this to an actual value to force it into the .data
62 * section so that we know it is properly initialized at entry into
63 * the kernel but before bss is initialized to zero (which is where
64 * it would live otherwise). The 0x1f magic represents the IRQs we
65 * cannot actually mask out in hardware.
67 unsigned long irq_flags = 0x1f;
69 /* The number of spurious interrupts */
70 atomic_t num_spurious;
73 /* irq number for request_irq, available in mach-bf533/irq.h */
75 /* corresponding bit in the SIC_ISR register */
77 } ivg_table[NR_PERI_INTS];
80 /* position of first irq in ivg_table for given ivg */
83 } ivg7_13[IVG13 - IVG7 + 1];
85 static void search_IAR(void);
88 * Search SIC_IAR and fill tables with the irqvalues
89 * and their positions in the SIC_ISR register.
91 static void __init search_IAR(void)
93 unsigned ivg, irq_pos = 0;
94 for (ivg = 0; ivg <= IVG13 - IVG7; ivg++) {
97 ivg7_13[ivg].istop = ivg7_13[ivg].ifirst = &ivg_table[irq_pos];
99 for (irqn = 0; irqn < NR_PERI_INTS; irqn++) {
100 int iar_shift = (irqn & 7) * 4;
104 bfin_read32((unsigned long *)SIC_IAR0 +
105 (irqn >> 3)) >> iar_shift)) {
107 bfin_read32((unsigned long *)SIC_IAR0 +
108 ((irqn%32) >> 3) + ((irqn / 32) * 16)) >> iar_shift)) {
110 ivg_table[irq_pos].irqno = IVG7 + irqn;
111 ivg_table[irq_pos].isrflag = 1 << (irqn % 32);
112 ivg7_13[ivg].istop++;
120 * This is for BF533 internal IRQs
123 static void ack_noop(unsigned int irq)
125 /* Dummy function. */
128 static void bfin_core_mask_irq(unsigned int irq)
130 irq_flags &= ~(1 << irq);
131 if (!irqs_disabled())
135 static void bfin_core_unmask_irq(unsigned int irq)
137 irq_flags |= 1 << irq;
139 * If interrupts are enabled, IMASK must contain the same value
140 * as irq_flags. Make sure that invariant holds. If interrupts
141 * are currently disabled we need not do anything; one of the
142 * callers will take care of setting IMASK to the proper value
143 * when reenabling interrupts.
144 * local_irq_enable just does "STI irq_flags", so it's exactly
147 if (!irqs_disabled())
152 static void bfin_internal_mask_irq(unsigned int irq)
155 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
156 ~(1 << (irq - (IRQ_CORETMR + 1))));
158 unsigned mask_bank, mask_bit;
159 mask_bank = (irq - (IRQ_CORETMR + 1)) / 32;
160 mask_bit = (irq - (IRQ_CORETMR + 1)) % 32;
161 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) &
167 static void bfin_internal_unmask_irq(unsigned int irq)
170 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
171 (1 << (irq - (IRQ_CORETMR + 1))));
173 unsigned mask_bank, mask_bit;
174 mask_bank = (irq - (IRQ_CORETMR + 1)) / 32;
175 mask_bit = (irq - (IRQ_CORETMR + 1)) % 32;
176 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) |
182 static struct irq_chip bfin_core_irqchip = {
184 .mask = bfin_core_mask_irq,
185 .unmask = bfin_core_unmask_irq,
188 static struct irq_chip bfin_internal_irqchip = {
190 .mask = bfin_internal_mask_irq,
191 .unmask = bfin_internal_unmask_irq,
194 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
195 static int error_int_mask;
197 static void bfin_generic_error_ack_irq(unsigned int irq)
202 static void bfin_generic_error_mask_irq(unsigned int irq)
204 error_int_mask &= ~(1L << (irq - IRQ_PPI_ERROR));
206 if (!error_int_mask) {
208 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
211 (IRQ_CORETMR + 1))));
217 static void bfin_generic_error_unmask_irq(unsigned int irq)
220 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() | 1 <<
221 (IRQ_GENERIC_ERROR - (IRQ_CORETMR + 1)));
225 error_int_mask |= 1L << (irq - IRQ_PPI_ERROR);
228 static struct irq_chip bfin_generic_error_irqchip = {
229 .ack = bfin_generic_error_ack_irq,
230 .mask = bfin_generic_error_mask_irq,
231 .unmask = bfin_generic_error_unmask_irq,
234 static void bfin_demux_error_irq(unsigned int int_err_irq,
235 struct irq_desc *intb_desc)
241 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
242 if (bfin_read_EMAC_SYSTAT() & EMAC_ERR_MASK)
246 if (bfin_read_SPORT0_STAT() & SPORT_ERR_MASK)
247 irq = IRQ_SPORT0_ERROR;
248 else if (bfin_read_SPORT1_STAT() & SPORT_ERR_MASK)
249 irq = IRQ_SPORT1_ERROR;
250 else if (bfin_read_PPI_STATUS() & PPI_ERR_MASK)
252 else if (bfin_read_CAN_GIF() & CAN_ERR_MASK)
254 else if (bfin_read_SPI_STAT() & SPI_ERR_MASK)
256 else if ((bfin_read_UART0_IIR() & UART_ERR_MASK_STAT1) &&
257 (bfin_read_UART0_IIR() & UART_ERR_MASK_STAT0))
258 irq = IRQ_UART0_ERROR;
259 else if ((bfin_read_UART1_IIR() & UART_ERR_MASK_STAT1) &&
260 (bfin_read_UART1_IIR() & UART_ERR_MASK_STAT0))
261 irq = IRQ_UART1_ERROR;
264 if (error_int_mask & (1L << (irq - IRQ_PPI_ERROR))) {
265 struct irq_desc *desc = irq_desc + irq;
266 desc->handle_irq(irq, desc);
271 bfin_write_PPI_STATUS(PPI_ERR_MASK);
273 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
275 bfin_write_EMAC_SYSTAT(EMAC_ERR_MASK);
278 case IRQ_SPORT0_ERROR:
279 bfin_write_SPORT0_STAT(SPORT_ERR_MASK);
282 case IRQ_SPORT1_ERROR:
283 bfin_write_SPORT1_STAT(SPORT_ERR_MASK);
287 bfin_write_CAN_GIS(CAN_ERR_MASK);
291 bfin_write_SPI_STAT(SPI_ERR_MASK);
299 " MASKED PERIPHERAL ERROR INTERRUPT ASSERTED\n",
304 "%s : %s : LINE %d :\nIRQ ?: PERIPHERAL ERROR"
305 " INTERRUPT ASSERTED BUT NO SOURCE FOUND\n",
306 __FUNCTION__, __FILE__, __LINE__);
309 #endif /* BF537_GENERIC_ERROR_INT_DEMUX */
311 #if !defined(CONFIG_BF54x)
313 static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)];
314 static unsigned short gpio_edge_triggered[gpio_bank(MAX_BLACKFIN_GPIOS)];
316 static void bfin_gpio_ack_irq(unsigned int irq)
318 u16 gpionr = irq - IRQ_PF0;
320 if (gpio_edge_triggered[gpio_bank(gpionr)] & gpio_bit(gpionr)) {
321 set_gpio_data(gpionr, 0);
326 static void bfin_gpio_mask_ack_irq(unsigned int irq)
328 u16 gpionr = irq - IRQ_PF0;
330 if (gpio_edge_triggered[gpio_bank(gpionr)] & gpio_bit(gpionr)) {
331 set_gpio_data(gpionr, 0);
335 set_gpio_maska(gpionr, 0);
339 static void bfin_gpio_mask_irq(unsigned int irq)
341 set_gpio_maska(irq - IRQ_PF0, 0);
345 static void bfin_gpio_unmask_irq(unsigned int irq)
347 set_gpio_maska(irq - IRQ_PF0, 1);
351 static unsigned int bfin_gpio_irq_startup(unsigned int irq)
354 u16 gpionr = irq - IRQ_PF0;
356 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
357 ret = gpio_request(gpionr, "IRQ");
362 gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
363 bfin_gpio_unmask_irq(irq);
368 static void bfin_gpio_irq_shutdown(unsigned int irq)
370 bfin_gpio_mask_irq(irq);
371 gpio_free(irq - IRQ_PF0);
372 gpio_enabled[gpio_bank(irq - IRQ_PF0)] &= ~gpio_bit(irq - IRQ_PF0);
375 static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
379 u16 gpionr = irq - IRQ_PF0;
381 if (type == IRQ_TYPE_PROBE) {
382 /* only probe unenabled GPIO interrupt lines */
383 if (gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))
385 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
388 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
389 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
390 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
391 ret = gpio_request(gpionr, "IRQ");
396 gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
398 gpio_enabled[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
402 set_gpio_dir(gpionr, 0);
403 set_gpio_inen(gpionr, 1);
405 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
406 gpio_edge_triggered[gpio_bank(gpionr)] |= gpio_bit(gpionr);
407 set_gpio_edge(gpionr, 1);
409 set_gpio_edge(gpionr, 0);
410 gpio_edge_triggered[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
413 if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
414 == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
415 set_gpio_both(gpionr, 1);
417 set_gpio_both(gpionr, 0);
419 if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
420 set_gpio_polar(gpionr, 1); /* low or falling edge denoted by one */
422 set_gpio_polar(gpionr, 0); /* high or rising edge denoted by zero */
426 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
427 set_irq_handler(irq, handle_edge_irq);
429 set_irq_handler(irq, handle_level_irq);
434 static struct irq_chip bfin_gpio_irqchip = {
435 .ack = bfin_gpio_ack_irq,
436 .mask = bfin_gpio_mask_irq,
437 .mask_ack = bfin_gpio_mask_ack_irq,
438 .unmask = bfin_gpio_unmask_irq,
439 .set_type = bfin_gpio_irq_type,
440 .startup = bfin_gpio_irq_startup,
441 .shutdown = bfin_gpio_irq_shutdown
444 static void bfin_demux_gpio_irq(unsigned int intb_irq,
445 struct irq_desc *intb_desc)
448 struct irq_desc *desc;
450 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += 16) {
451 int irq = IRQ_PF0 + i;
452 int flag_d = get_gpiop_data(i);
454 flag_d & (gpio_enabled[gpio_bank(i)] & get_gpiop_maska(i));
458 desc = irq_desc + irq;
459 desc->handle_irq(irq, desc);
467 #else /* CONFIG_BF54x */
469 #define NR_PINT_SYS_IRQS 4
470 #define NR_PINT_BITS 32
472 #define IRQ_NOT_AVAIL 0xFF
474 #define PINT_2_BANK(x) ((x) >> 5)
475 #define PINT_2_BIT(x) ((x) & 0x1F)
476 #define PINT_BIT(x) (1 << (PINT_2_BIT(x)))
478 static unsigned char irq2pint_lut[NR_PINTS];
479 static unsigned char pint2irq_lut[NR_PINT_SYS_IRQS * NR_PINT_BITS];
482 unsigned int mask_set;
483 unsigned int mask_clear;
484 unsigned int request;
486 unsigned int edge_set;
487 unsigned int edge_clear;
488 unsigned int invert_set;
489 unsigned int invert_clear;
490 unsigned int pinstate;
494 static struct pin_int_t *pint[NR_PINT_SYS_IRQS] = {
495 (struct pin_int_t *)PINT0_MASK_SET,
496 (struct pin_int_t *)PINT1_MASK_SET,
497 (struct pin_int_t *)PINT2_MASK_SET,
498 (struct pin_int_t *)PINT3_MASK_SET,
501 unsigned short get_irq_base(u8 bank, u8 bmap)
506 if (bank < 2) { /*PA-PB */
507 irq_base = IRQ_PA0 + bmap * 16;
509 irq_base = IRQ_PC0 + bmap * 16;
516 /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
517 void init_pint_lut(void)
519 u16 bank, bit, irq_base, bit_pos;
523 memset(irq2pint_lut, IRQ_NOT_AVAIL, sizeof(irq2pint_lut));
525 for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) {
527 pint_assign = pint[bank]->assign;
529 for (bit = 0; bit < NR_PINT_BITS; bit++) {
531 bmap = (pint_assign >> ((bit / 8) * 8)) & 0xFF;
533 irq_base = get_irq_base(bank, bmap);
535 irq_base += (bit % 8) + ((bit / 8) & 1 ? 8 : 0);
536 bit_pos = bit + bank * NR_PINT_BITS;
538 pint2irq_lut[bit_pos] = irq_base - SYS_IRQS;
539 irq2pint_lut[irq_base - SYS_IRQS] = bit_pos;
547 static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)];
549 static void bfin_gpio_ack_irq(unsigned int irq)
551 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
553 pint[PINT_2_BANK(pint_val)]->request = PINT_BIT(pint_val);
557 static void bfin_gpio_mask_ack_irq(unsigned int irq)
559 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
560 u32 pintbit = PINT_BIT(pint_val);
561 u8 bank = PINT_2_BANK(pint_val);
563 pint[bank]->request = pintbit;
564 pint[bank]->mask_clear = pintbit;
568 static void bfin_gpio_mask_irq(unsigned int irq)
570 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
572 pint[PINT_2_BANK(pint_val)]->mask_clear = PINT_BIT(pint_val);
576 static void bfin_gpio_unmask_irq(unsigned int irq)
578 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
579 u32 pintbit = PINT_BIT(pint_val);
580 u8 bank = PINT_2_BANK(pint_val);
582 pint[bank]->request = pintbit;
583 pint[bank]->mask_set = pintbit;
587 static unsigned int bfin_gpio_irq_startup(unsigned int irq)
590 u16 gpionr = irq - IRQ_PA0;
591 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
593 if (pint_val == IRQ_NOT_AVAIL) {
595 "GPIO IRQ %d :Not in PINT Assign table "
596 "Reconfigure Interrupt to Port Assignemt\n", irq);
600 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
601 ret = gpio_request(gpionr, "IRQ");
606 gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
607 bfin_gpio_unmask_irq(irq);
612 static void bfin_gpio_irq_shutdown(unsigned int irq)
614 bfin_gpio_mask_irq(irq);
615 gpio_free(irq - IRQ_PA0);
616 gpio_enabled[gpio_bank(irq - IRQ_PA0)] &= ~gpio_bit(irq - IRQ_PA0);
619 static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
623 u16 gpionr = irq - IRQ_PA0;
624 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
625 u32 pintbit = PINT_BIT(pint_val);
626 u8 bank = PINT_2_BANK(pint_val);
628 if (pint_val == IRQ_NOT_AVAIL)
631 if (type == IRQ_TYPE_PROBE) {
632 /* only probe unenabled GPIO interrupt lines */
633 if (gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))
635 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
638 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
639 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
640 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
641 ret = gpio_request(gpionr, "IRQ");
646 gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
648 gpio_enabled[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
652 gpio_direction_input(gpionr);
654 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
655 pint[bank]->edge_set = pintbit;
657 pint[bank]->edge_clear = pintbit;
660 if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
661 pint[bank]->invert_set = pintbit; /* low or falling edge denoted by one */
663 pint[bank]->invert_set = pintbit; /* high or rising edge denoted by zero */
665 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
666 pint[bank]->invert_set = pintbit;
668 pint[bank]->invert_set = pintbit;
672 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
673 set_irq_handler(irq, handle_edge_irq);
675 set_irq_handler(irq, handle_level_irq);
680 static struct irq_chip bfin_gpio_irqchip = {
681 .ack = bfin_gpio_ack_irq,
682 .mask = bfin_gpio_mask_irq,
683 .mask_ack = bfin_gpio_mask_ack_irq,
684 .unmask = bfin_gpio_unmask_irq,
685 .set_type = bfin_gpio_irq_type,
686 .startup = bfin_gpio_irq_startup,
687 .shutdown = bfin_gpio_irq_shutdown
690 static void bfin_demux_gpio_irq(unsigned int intb_irq,
691 struct irq_desc *intb_desc)
695 struct irq_desc *desc;
714 pint_val = bank * NR_PINT_BITS;
716 request = pint[bank]->request;
720 irq = pint2irq_lut[pint_val] + SYS_IRQS;
721 desc = irq_desc + irq;
722 desc->handle_irq(irq, desc);
731 void __init init_exception_vectors(void)
735 /* cannot program in software:
736 * evt0 - emulation (jtag)
739 bfin_write_EVT2(evt_nmi);
740 bfin_write_EVT3(trap);
741 bfin_write_EVT5(evt_ivhw);
742 bfin_write_EVT6(evt_timer);
743 bfin_write_EVT7(evt_evt7);
744 bfin_write_EVT8(evt_evt8);
745 bfin_write_EVT9(evt_evt9);
746 bfin_write_EVT10(evt_evt10);
747 bfin_write_EVT11(evt_evt11);
748 bfin_write_EVT12(evt_evt12);
749 bfin_write_EVT13(evt_evt13);
750 bfin_write_EVT14(evt14_softirq);
751 bfin_write_EVT15(evt_system_call);
756 * This function should be called during kernel startup to initialize
757 * the BFin IRQ handling routines.
759 int __init init_arch_irq(void)
762 unsigned long ilat = 0;
763 /* Disable all the peripheral intrs - page 4-29 HW Ref manual */
764 #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x)
765 bfin_write_SIC_IMASK0(SIC_UNMASK_ALL);
766 bfin_write_SIC_IMASK1(SIC_UNMASK_ALL);
767 bfin_write_SIC_IWR0(IWR_ENABLE_ALL);
768 bfin_write_SIC_IWR1(IWR_ENABLE_ALL);
770 bfin_write_SIC_IMASK2(SIC_UNMASK_ALL);
771 bfin_write_SIC_IWR2(IWR_ENABLE_ALL);
774 bfin_write_SIC_IMASK(SIC_UNMASK_ALL);
775 bfin_write_SIC_IWR(IWR_ENABLE_ALL);
782 # ifdef CONFIG_PINTx_REASSIGN
783 pint[0]->assign = CONFIG_PINT0_ASSIGN;
784 pint[1]->assign = CONFIG_PINT1_ASSIGN;
785 pint[2]->assign = CONFIG_PINT2_ASSIGN;
786 pint[3]->assign = CONFIG_PINT3_ASSIGN;
788 /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
792 for (irq = 0; irq <= SYS_IRQS; irq++) {
793 if (irq <= IRQ_CORETMR)
794 set_irq_chip(irq, &bfin_core_irqchip);
796 set_irq_chip(irq, &bfin_internal_irqchip);
797 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
798 if (irq != IRQ_GENERIC_ERROR) {
802 #if defined(CONFIG_BF53x)
804 set_irq_chained_handler(irq,
805 bfin_demux_gpio_irq);
807 # if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
809 set_irq_chained_handler(irq,
810 bfin_demux_gpio_irq);
813 #elif defined(CONFIG_BF54x)
815 set_irq_chained_handler(irq,
816 bfin_demux_gpio_irq);
819 set_irq_chained_handler(irq,
820 bfin_demux_gpio_irq);
823 set_irq_chained_handler(irq,
824 bfin_demux_gpio_irq);
827 set_irq_chained_handler(irq,
828 bfin_demux_gpio_irq);
830 #elif defined(CONFIG_BF52x)
832 set_irq_chained_handler(irq,
833 bfin_demux_gpio_irq);
836 set_irq_chained_handler(irq,
837 bfin_demux_gpio_irq);
840 set_irq_chained_handler(irq,
841 bfin_demux_gpio_irq);
845 set_irq_handler(irq, handle_simple_irq);
849 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
851 set_irq_handler(irq, bfin_demux_error_irq);
855 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
856 for (irq = IRQ_PPI_ERROR; irq <= IRQ_UART1_ERROR; irq++) {
857 set_irq_chip(irq, &bfin_generic_error_irqchip);
858 set_irq_handler(irq, handle_level_irq);
863 for (irq = IRQ_PF0; irq < NR_IRQS; irq++) {
865 for (irq = IRQ_PA0; irq < NR_IRQS; irq++) {
867 set_irq_chip(irq, &bfin_gpio_irqchip);
868 /* if configured as edge, then will be changed to do_edge_IRQ */
869 set_irq_handler(irq, handle_level_irq);
874 ilat = bfin_read_ILAT();
876 bfin_write_ILAT(ilat);
879 printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n");
880 /* IMASK=xxx is equivalent to STI xx or irq_flags=xx,
884 /* Therefore it's better to setup IARs before interrupts enabled */
887 /* Enable interrupts IVG7-15 */
888 irq_flags = irq_flags | IMASK_IVG15 |
889 IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
890 IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
895 #ifdef CONFIG_DO_IRQ_L1
896 __attribute__((l1_text))
898 void do_irq(int vec, struct pt_regs *fp)
900 if (vec == EVT_IVTMR_P) {
903 struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
904 struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
905 #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x)
906 unsigned long sic_status[3];
909 sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
910 sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
912 sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
915 if (ivg >= ivg_stop) {
916 atomic_inc(&num_spurious);
919 if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
923 unsigned long sic_status;
925 sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
928 if (ivg >= ivg_stop) {
929 atomic_inc(&num_spurious);
931 } else if (sic_status & ivg->isrflag)
940 kgdb_process_breakpoint();