4 * Derived from cx25840-core.h
6 * Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl>
7 * Copyright (C) 2008 Andy Walls <awalls@radix.net>
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version 2
12 * of the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
25 #ifndef _CX18_AV_CORE_H_
26 #define _CX18_AV_CORE_H_
30 enum cx18_av_video_input {
31 /* Composite video inputs In1-In8 */
32 CX18_AV_COMPOSITE1 = 1,
41 /* S-Video inputs consist of one luma input (In1-In8) ORed with one
42 chroma input (In5-In8) */
43 CX18_AV_SVIDEO_LUMA1 = 0x10,
44 CX18_AV_SVIDEO_LUMA2 = 0x20,
45 CX18_AV_SVIDEO_LUMA3 = 0x30,
46 CX18_AV_SVIDEO_LUMA4 = 0x40,
47 CX18_AV_SVIDEO_LUMA5 = 0x50,
48 CX18_AV_SVIDEO_LUMA6 = 0x60,
49 CX18_AV_SVIDEO_LUMA7 = 0x70,
50 CX18_AV_SVIDEO_LUMA8 = 0x80,
51 CX18_AV_SVIDEO_CHROMA4 = 0x400,
52 CX18_AV_SVIDEO_CHROMA5 = 0x500,
53 CX18_AV_SVIDEO_CHROMA6 = 0x600,
54 CX18_AV_SVIDEO_CHROMA7 = 0x700,
55 CX18_AV_SVIDEO_CHROMA8 = 0x800,
57 /* S-Video aliases for common luma/chroma combinations */
58 CX18_AV_SVIDEO1 = 0x510,
59 CX18_AV_SVIDEO2 = 0x620,
60 CX18_AV_SVIDEO3 = 0x730,
61 CX18_AV_SVIDEO4 = 0x840,
64 enum cx18_av_audio_input {
65 /* Audio inputs: serial or In4-In8 */
66 CX18_AV_AUDIO_SERIAL1,
67 CX18_AV_AUDIO_SERIAL2,
75 struct cx18_av_state {
78 enum cx18_av_video_input vid_input;
79 enum cx18_av_audio_input aud_input;
88 * The VBI slicer starts operating and counting lines, begining at
89 * slicer line count of 1, at D lines after the deassertion of VRESET
90 * This staring field line, S, is 6 or 10 for 625 or 525 line systems.
91 * Sliced ancillary data captured on VBI slicer line M is sent at the
92 * beginning of the next VBI slicer line, VBI slicer line count N = M+1.
93 * Thus when the VBI slicer reports a VBI slicer line number with
94 * ancillary data, the IDID0 byte indicates VBI slicer line N.
95 * The actual field line that the captured data comes from is
96 * L = M+(S+D-1) = N-1+(S+D-1) = N + (S+D-2).
98 * D is the slicer_line_delay value programmed into register 0x47f.
99 * (S+D-2) is the slicer_line_offset used to convert slicer reported
100 * line counts to actual field lines.
102 int slicer_line_delay;
103 int slicer_line_offset;
108 #define CXADEC_CHIP_TYPE_TIGER 0x837
109 #define CXADEC_CHIP_TYPE_MAKO 0x843
111 #define CXADEC_HOST_REG1 0x000
112 #define CXADEC_HOST_REG2 0x001
114 #define CXADEC_CHIP_CTRL 0x100
115 #define CXADEC_AFE_CTRL 0x104
116 #define CXADEC_PLL_CTRL1 0x108
117 #define CXADEC_VID_PLL_FRAC 0x10C
118 #define CXADEC_AUX_PLL_FRAC 0x110
119 #define CXADEC_PIN_CTRL1 0x114
120 #define CXADEC_PIN_CTRL2 0x118
121 #define CXADEC_PIN_CFG1 0x11C
122 #define CXADEC_PIN_CFG2 0x120
124 #define CXADEC_PIN_CFG3 0x124
125 #define CXADEC_I2S_MCLK 0x127
127 #define CXADEC_AUD_LOCK1 0x128
128 #define CXADEC_AUD_LOCK2 0x12C
129 #define CXADEC_POWER_CTRL 0x130
130 #define CXADEC_AFE_DIAG_CTRL1 0x134
131 #define CXADEC_AFE_DIAG_CTRL2 0x138
132 #define CXADEC_AFE_DIAG_CTRL3 0x13C
133 #define CXADEC_PLL_DIAG_CTRL 0x140
134 #define CXADEC_TEST_CTRL1 0x144
135 #define CXADEC_TEST_CTRL2 0x148
136 #define CXADEC_BIST_STAT 0x14C
137 #define CXADEC_DLL1_DIAG_CTRL 0x158
138 #define CXADEC_DLL2_DIAG_CTRL 0x15C
141 #define CXADEC_IR_CTRL_REG 0x200
142 #define CXADEC_IR_TXCLK_REG 0x204
143 #define CXADEC_IR_RXCLK_REG 0x208
144 #define CXADEC_IR_CDUTY_REG 0x20C
145 #define CXADEC_IR_STAT_REG 0x210
146 #define CXADEC_IR_IRQEN_REG 0x214
147 #define CXADEC_IR_FILTER_REG 0x218
148 #define CXADEC_IR_FIFO_REG 0x21C
150 /* Video Registers */
151 #define CXADEC_MODE_CTRL 0x400
152 #define CXADEC_OUT_CTRL1 0x404
153 #define CXADEC_OUT_CTRL2 0x408
154 #define CXADEC_GEN_STAT 0x40C
155 #define CXADEC_INT_STAT_MASK 0x410
156 #define CXADEC_LUMA_CTRL 0x414
158 #define CXADEC_BRIGHTNESS_CTRL_BYTE 0x414
159 #define CXADEC_CONTRAST_CTRL_BYTE 0x415
160 #define CXADEC_LUMA_CTRL_BYTE_3 0x416
162 #define CXADEC_HSCALE_CTRL 0x418
163 #define CXADEC_VSCALE_CTRL 0x41C
165 #define CXADEC_CHROMA_CTRL 0x420
167 #define CXADEC_USAT_CTRL_BYTE 0x420
168 #define CXADEC_VSAT_CTRL_BYTE 0x421
169 #define CXADEC_HUE_CTRL_BYTE 0x422
171 #define CXADEC_VBI_LINE_CTRL1 0x424
172 #define CXADEC_VBI_LINE_CTRL2 0x428
173 #define CXADEC_VBI_LINE_CTRL3 0x42C
174 #define CXADEC_VBI_LINE_CTRL4 0x430
175 #define CXADEC_VBI_LINE_CTRL5 0x434
176 #define CXADEC_VBI_FC_CFG 0x438
177 #define CXADEC_VBI_MISC_CFG1 0x43C
178 #define CXADEC_VBI_MISC_CFG2 0x440
179 #define CXADEC_VBI_PAY1 0x444
180 #define CXADEC_VBI_PAY2 0x448
181 #define CXADEC_VBI_CUST1_CFG1 0x44C
182 #define CXADEC_VBI_CUST1_CFG2 0x450
183 #define CXADEC_VBI_CUST1_CFG3 0x454
184 #define CXADEC_VBI_CUST2_CFG1 0x458
185 #define CXADEC_VBI_CUST2_CFG2 0x45C
186 #define CXADEC_VBI_CUST2_CFG3 0x460
187 #define CXADEC_VBI_CUST3_CFG1 0x464
188 #define CXADEC_VBI_CUST3_CFG2 0x468
189 #define CXADEC_VBI_CUST3_CFG3 0x46C
190 #define CXADEC_HORIZ_TIM_CTRL 0x470
191 #define CXADEC_VERT_TIM_CTRL 0x474
192 #define CXADEC_SRC_COMB_CFG 0x478
193 #define CXADEC_CHROMA_VBIOFF_CFG 0x47C
194 #define CXADEC_FIELD_COUNT 0x480
195 #define CXADEC_MISC_TIM_CTRL 0x484
196 #define CXADEC_DFE_CTRL1 0x488
197 #define CXADEC_DFE_CTRL2 0x48C
198 #define CXADEC_DFE_CTRL3 0x490
199 #define CXADEC_PLL_CTRL2 0x494
200 #define CXADEC_HTL_CTRL 0x498
201 #define CXADEC_COMB_CTRL 0x49C
202 #define CXADEC_CRUSH_CTRL 0x4A0
203 #define CXADEC_SOFT_RST_CTRL 0x4A4
204 #define CXADEC_MV_DT_CTRL2 0x4A8
205 #define CXADEC_MV_DT_CTRL3 0x4AC
206 #define CXADEC_MISC_DIAG_CTRL 0x4B8
208 #define CXADEC_DL_CTL 0x800
209 #define CXADEC_DL_CTL_ADDRESS_LOW 0x800 /* Byte 1 in DL_CTL */
210 #define CXADEC_DL_CTL_ADDRESS_HIGH 0x801 /* Byte 2 in DL_CTL */
211 #define CXADEC_DL_CTL_DATA 0x802 /* Byte 3 in DL_CTL */
212 #define CXADEC_DL_CTL_CONTROL 0x803 /* Byte 4 in DL_CTL */
214 #define CXADEC_STD_DET_STATUS 0x804
216 #define CXADEC_STD_DET_CTL 0x808
217 #define CXADEC_STD_DET_CTL_AUD_CTL 0x808 /* Byte 1 in STD_DET_CTL */
218 #define CXADEC_STD_DET_CTL_PREF_MODE 0x809 /* Byte 2 in STD_DET_CTL */
220 #define CXADEC_DW8051_INT 0x80C
221 #define CXADEC_GENERAL_CTL 0x810
222 #define CXADEC_AAGC_CTL 0x814
223 #define CXADEC_IF_SRC_CTL 0x818
224 #define CXADEC_ANLOG_DEMOD_CTL 0x81C
225 #define CXADEC_ROT_FREQ_CTL 0x820
226 #define CXADEC_FM1_CTL 0x824
227 #define CXADEC_PDF_CTL 0x828
228 #define CXADEC_DFT1_CTL1 0x82C
229 #define CXADEC_DFT1_CTL2 0x830
230 #define CXADEC_DFT_STATUS 0x834
231 #define CXADEC_DFT2_CTL1 0x838
232 #define CXADEC_DFT2_CTL2 0x83C
233 #define CXADEC_DFT2_STATUS 0x840
234 #define CXADEC_DFT3_CTL1 0x844
235 #define CXADEC_DFT3_CTL2 0x848
236 #define CXADEC_DFT3_STATUS 0x84C
237 #define CXADEC_DFT4_CTL1 0x850
238 #define CXADEC_DFT4_CTL2 0x854
239 #define CXADEC_DFT4_STATUS 0x858
240 #define CXADEC_AM_MTS_DET 0x85C
241 #define CXADEC_ANALOG_MUX_CTL 0x860
242 #define CXADEC_DIG_PLL_CTL1 0x864
243 #define CXADEC_DIG_PLL_CTL2 0x868
244 #define CXADEC_DIG_PLL_CTL3 0x86C
245 #define CXADEC_DIG_PLL_CTL4 0x870
246 #define CXADEC_DIG_PLL_CTL5 0x874
247 #define CXADEC_DEEMPH_GAIN_CTL 0x878
248 #define CXADEC_DEEMPH_COEF1 0x87C
249 #define CXADEC_DEEMPH_COEF2 0x880
250 #define CXADEC_DBX1_CTL1 0x884
251 #define CXADEC_DBX1_CTL2 0x888
252 #define CXADEC_DBX1_STATUS 0x88C
253 #define CXADEC_DBX2_CTL1 0x890
254 #define CXADEC_DBX2_CTL2 0x894
255 #define CXADEC_DBX2_STATUS 0x898
256 #define CXADEC_AM_FM_DIFF 0x89C
258 /* NICAM registers go here */
259 #define CXADEC_NICAM_STATUS 0x8C8
260 #define CXADEC_DEMATRIX_CTL 0x8CC
262 #define CXADEC_PATH1_CTL1 0x8D0
263 #define CXADEC_PATH1_VOL_CTL 0x8D4
264 #define CXADEC_PATH1_EQ_CTL 0x8D8
265 #define CXADEC_PATH1_SC_CTL 0x8DC
267 #define CXADEC_PATH2_CTL1 0x8E0
268 #define CXADEC_PATH2_VOL_CTL 0x8E4
269 #define CXADEC_PATH2_EQ_CTL 0x8E8
270 #define CXADEC_PATH2_SC_CTL 0x8EC
272 #define CXADEC_SRC_CTL 0x8F0
273 #define CXADEC_SRC_LF_COEF 0x8F4
274 #define CXADEC_SRC1_CTL 0x8F8
275 #define CXADEC_SRC2_CTL 0x8FC
276 #define CXADEC_SRC3_CTL 0x900
277 #define CXADEC_SRC4_CTL 0x904
278 #define CXADEC_SRC5_CTL 0x908
279 #define CXADEC_SRC6_CTL 0x90C
281 #define CXADEC_BASEBAND_OUT_SEL 0x910
282 #define CXADEC_I2S_IN_CTL 0x914
283 #define CXADEC_I2S_OUT_CTL 0x918
284 #define CXADEC_AC97_CTL 0x91C
285 #define CXADEC_QAM_PDF 0x920
286 #define CXADEC_QAM_CONST_DEC 0x924
287 #define CXADEC_QAM_ROTATOR_FREQ 0x948
289 /* Bit defintions / settings used in Mako Audio */
290 #define CXADEC_PREF_MODE_MONO_LANGA 0
291 #define CXADEC_PREF_MODE_MONO_LANGB 1
292 #define CXADEC_PREF_MODE_MONO_LANGC 2
293 #define CXADEC_PREF_MODE_FALLBACK 3
294 #define CXADEC_PREF_MODE_STEREO 4
295 #define CXADEC_PREF_MODE_DUAL_LANG_AC 5
296 #define CXADEC_PREF_MODE_DUAL_LANG_BC 6
297 #define CXADEC_PREF_MODE_DUAL_LANG_AB 7
300 #define CXADEC_DETECT_STEREO 1
301 #define CXADEC_DETECT_DUAL 2
302 #define CXADEC_DETECT_TRI 4
303 #define CXADEC_DETECT_SAP 0x10
304 #define CXADEC_DETECT_NO_SIGNAL 0xFF
306 #define CXADEC_SELECT_AUDIO_STANDARD_BG 0xF0 /* NICAM BG and A2 BG */
307 #define CXADEC_SELECT_AUDIO_STANDARD_DK1 0xF1 /* NICAM DK and A2 DK */
308 #define CXADEC_SELECT_AUDIO_STANDARD_DK2 0xF2
309 #define CXADEC_SELECT_AUDIO_STANDARD_DK3 0xF3
310 #define CXADEC_SELECT_AUDIO_STANDARD_I 0xF4 /* NICAM I and A1 */
311 #define CXADEC_SELECT_AUDIO_STANDARD_L 0xF5 /* NICAM L and System L AM */
312 #define CXADEC_SELECT_AUDIO_STANDARD_BTSC 0xF6
313 #define CXADEC_SELECT_AUDIO_STANDARD_EIAJ 0xF7
314 #define CXADEC_SELECT_AUDIO_STANDARD_A2_M 0xF8 /* A2 M */
315 #define CXADEC_SELECT_AUDIO_STANDARD_FM 0xF9 /* FM radio */
316 #define CXADEC_SELECT_AUDIO_STANDARD_AUTO 0xFF /* Auto detect */
318 /* ----------------------------------------------------------------------- */
320 int cx18_av_write(struct cx18 *cx, u16 addr, u8 value);
321 int cx18_av_write4(struct cx18 *cx, u16 addr, u32 value);
322 int cx18_av_write4_noretry(struct cx18 *cx, u16 addr, u32 value);
323 int cx18_av_write_expect(struct cx18 *cx, u16 addr, u8 value, u8 eval, u8 mask);
324 int cx18_av_write4_expect(struct cx18 *cx, u16 addr, u32 value, u32 eval,
326 u8 cx18_av_read(struct cx18 *cx, u16 addr);
327 u32 cx18_av_read4(struct cx18 *cx, u16 addr);
328 int cx18_av_and_or(struct cx18 *cx, u16 addr, unsigned mask, u8 value);
329 int cx18_av_and_or4(struct cx18 *cx, u16 addr, u32 mask, u32 value);
330 int cx18_av_cmd(struct cx18 *cx, unsigned int cmd, void *arg);
331 void cx18_av_std_setup(struct cx18 *cx);
333 /* ----------------------------------------------------------------------- */
334 /* cx18_av-firmware.c */
335 int cx18_av_loadfw(struct cx18 *cx);
337 /* ----------------------------------------------------------------------- */
338 /* cx18_av-audio.c */
339 int cx18_av_audio(struct cx18 *cx, unsigned int cmd, void *arg);
340 void cx18_av_audio_set_path(struct cx18 *cx);
342 /* ----------------------------------------------------------------------- */
344 int cx18_av_vbi(struct cx18 *cx, unsigned int cmd, void *arg);