git.oblomov.eu Git - linux-2.6/blob - arch/powerpc/platforms/cell/spufs/switch.c

   1 /*
   2  * spu_switch.c
   3  *
   4  * (C) Copyright IBM Corp. 2005
   5  *
   6  * Author: Mark Nutter <mnutter@us.ibm.com>
   7  *
   8  * Host-side part of SPU context switch sequence outlined in
   9  * Synergistic Processor Element, Book IV.
  10  *
  11  * A fully premptive switch of an SPE is very expensive in terms
  12  * of time and system resources.  SPE Book IV indicates that SPE
  13  * allocation should follow a "serially reusable device" model,
  14  * in which the SPE is assigned a task until it completes.  When
  15  * this is not possible, this sequence may be used to premptively
  16  * save, and then later (optionally) restore the context of a
  17  * program executing on an SPE.
  18  *
  19  *
  20  * This program is free software; you can redistribute it and/or modify
  21  * it under the terms of the GNU General Public License as published by
  22  * the Free Software Foundation; either version 2, or (at your option)
  23  * any later version.
  24  *
  25  * This program is distributed in the hope that it will be useful,
  26  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  27  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  28  * GNU General Public License for more details.
  29  *
  30  * You should have received a copy of the GNU General Public License
  31  * along with this program; if not, write to the Free Software
  32  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  33  */
  34
  35 #include <linux/module.h>
  36 #include <linux/errno.h>
  37 #include <linux/sched.h>
  38 #include <linux/kernel.h>
  39 #include <linux/mm.h>
  40 #include <linux/vmalloc.h>
  41 #include <linux/smp.h>
  42 #include <linux/stddef.h>
  43 #include <linux/unistd.h>
  44
  45 #include <asm/io.h>
  46 #include <asm/spu.h>
  47 #include <asm/spu_priv1.h>
  48 #include <asm/spu_csa.h>
  49 #include <asm/mmu_context.h>
  50
  51 #include "spu_save_dump.h"
  52 #include "spu_restore_dump.h"
  53
  54 #if 0
  55 #define POLL_WHILE_TRUE(_c) {                           \
  56     do {                                                \
  57     } while (_c);                                       \
  58   }
  59 #else
  60 #define RELAX_SPIN_COUNT                                1000
  61 #define POLL_WHILE_TRUE(_c) {                           \
  62     do {                                                \
  63         int _i;                                         \
  64         for (_i=0; _i<RELAX_SPIN_COUNT && (_c); _i++) { \
  65             cpu_relax();                                \
  66         }                                               \
  67         if (unlikely(_c)) yield();                      \
  68         else break;                                     \
  69     } while (_c);                                       \
  70   }
  71 #endif                          /* debug */
  72
  73 #define POLL_WHILE_FALSE(_c)    POLL_WHILE_TRUE(!(_c))
  74
  75 static inline void acquire_spu_lock(struct spu *spu)
  76 {
  77         /* Save, Step 1:
  78          * Restore, Step 1:
  79          *    Acquire SPU-specific mutual exclusion lock.
  80          *    TBD.
  81          */
  82 }
  83
  84 static inline void release_spu_lock(struct spu *spu)
  85 {
  86         /* Restore, Step 76:
  87          *    Release SPU-specific mutual exclusion lock.
  88          *    TBD.
  89          */
  90 }
  91
  92 static inline int check_spu_isolate(struct spu_state *csa, struct spu *spu)
  93 {
  94         struct spu_problem __iomem *prob = spu->problem;
  95         u32 isolate_state;
  96
  97         /* Save, Step 2:
  98          * Save, Step 6:
  99          *     If SPU_Status[E,L,IS] any field is '1', this
 100          *     SPU is in isolate state and cannot be context
 101          *     saved at this time.
 102          */
 103         isolate_state = SPU_STATUS_ISOLATED_STATE |
 104             SPU_STATUS_ISOLATED_LOAD_STATUS | SPU_STATUS_ISOLATED_EXIT_STATUS;
 105         return (in_be32(&prob->spu_status_R) & isolate_state) ? 1 : 0;
 106 }
 107
 108 static inline void disable_interrupts(struct spu_state *csa, struct spu *spu)
 109 {
 110         /* Save, Step 3:
 111          * Restore, Step 2:
 112          *     Save INT_Mask_class0 in CSA.
 113          *     Write INT_MASK_class0 with value of 0.
 114          *     Save INT_Mask_class1 in CSA.
 115          *     Write INT_MASK_class1 with value of 0.
 116          *     Save INT_Mask_class2 in CSA.
 117          *     Write INT_MASK_class2 with value of 0.
 118          */
 119         spin_lock_irq(&spu->register_lock);
 120         if (csa) {
 121                 csa->priv1.int_mask_class0_RW = spu_int_mask_get(spu, 0);
 122                 csa->priv1.int_mask_class1_RW = spu_int_mask_get(spu, 1);
 123                 csa->priv1.int_mask_class2_RW = spu_int_mask_get(spu, 2);
 124         }
 125         spu_int_mask_set(spu, 0, 0ul);
 126         spu_int_mask_set(spu, 1, 0ul);
 127         spu_int_mask_set(spu, 2, 0ul);
 128         eieio();
 129         spin_unlock_irq(&spu->register_lock);
 130 }
 131
 132 static inline void set_watchdog_timer(struct spu_state *csa, struct spu *spu)
 133 {
 134         /* Save, Step 4:
 135          * Restore, Step 25.
 136          *    Set a software watchdog timer, which specifies the
 137          *    maximum allowable time for a context save sequence.
 138          *
 139          *    For present, this implementation will not set a global
 140          *    watchdog timer, as virtualization & variable system load
 141          *    may cause unpredictable execution times.
 142          */
 143 }
 144
 145 static inline void inhibit_user_access(struct spu_state *csa, struct spu *spu)
 146 {
 147         /* Save, Step 5:
 148          * Restore, Step 3:
 149          *     Inhibit user-space access (if provided) to this
 150          *     SPU by unmapping the virtual pages assigned to
 151          *     the SPU memory-mapped I/O (MMIO) for problem
 152          *     state. TBD.
 153          */
 154 }
 155
 156 static inline void set_switch_pending(struct spu_state *csa, struct spu *spu)
 157 {
 158         /* Save, Step 7:
 159          * Restore, Step 5:
 160          *     Set a software context switch pending flag.
 161          */
 162         set_bit(SPU_CONTEXT_SWITCH_PENDING, &spu->flags);
 163         mb();
 164 }
 165
 166 static inline void save_mfc_cntl(struct spu_state *csa, struct spu *spu)
 167 {
 168         struct spu_priv2 __iomem *priv2 = spu->priv2;
 169
 170         /* Save, Step 8:
 171          *     Suspend DMA and save MFC_CNTL.
 172          */
 173         switch (in_be64(&priv2->mfc_control_RW) &
 174                MFC_CNTL_SUSPEND_DMA_STATUS_MASK) {
 175         case MFC_CNTL_SUSPEND_IN_PROGRESS:
 176                 POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) &
 177                                   MFC_CNTL_SUSPEND_DMA_STATUS_MASK) ==
 178                                  MFC_CNTL_SUSPEND_COMPLETE);
 179                 /* fall through */
 180         case MFC_CNTL_SUSPEND_COMPLETE:
 181                 if (csa) {
 182                         csa->priv2.mfc_control_RW =
 183                                 MFC_CNTL_SUSPEND_MASK |
 184                                 MFC_CNTL_SUSPEND_DMA_QUEUE;
 185                 }
 186                 break;
 187         case MFC_CNTL_NORMAL_DMA_QUEUE_OPERATION:
 188                 out_be64(&priv2->mfc_control_RW, MFC_CNTL_SUSPEND_DMA_QUEUE);
 189                 POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) &
 190                                   MFC_CNTL_SUSPEND_DMA_STATUS_MASK) ==
 191                                  MFC_CNTL_SUSPEND_COMPLETE);
 192                 if (csa) {
 193                         csa->priv2.mfc_control_RW = 0;
 194                 }
 195                 break;
 196         }
 197 }
 198
 199 static inline void save_spu_runcntl(struct spu_state *csa, struct spu *spu)
 200 {
 201         struct spu_problem __iomem *prob = spu->problem;
 202
 203         /* Save, Step 9:
 204          *     Save SPU_Runcntl in the CSA.  This value contains
 205          *     the "Application Desired State".
 206          */
 207         csa->prob.spu_runcntl_RW = in_be32(&prob->spu_runcntl_RW);
 208 }
 209
 210 static inline void save_mfc_sr1(struct spu_state *csa, struct spu *spu)
 211 {
 212         /* Save, Step 10:
 213          *     Save MFC_SR1 in the CSA.
 214          */
 215         csa->priv1.mfc_sr1_RW = spu_mfc_sr1_get(spu);
 216 }
 217
 218 static inline void save_spu_status(struct spu_state *csa, struct spu *spu)
 219 {
 220         struct spu_problem __iomem *prob = spu->problem;
 221
 222         /* Save, Step 11:
 223          *     Read SPU_Status[R], and save to CSA.
 224          */
 225         if ((in_be32(&prob->spu_status_R) & SPU_STATUS_RUNNING) == 0) {
 226                 csa->prob.spu_status_R = in_be32(&prob->spu_status_R);
 227         } else {
 228                 u32 stopped;
 229
 230                 out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_STOP);
 231                 eieio();
 232                 POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
 233                                 SPU_STATUS_RUNNING);
 234                 stopped =
 235                     SPU_STATUS_INVALID_INSTR | SPU_STATUS_SINGLE_STEP |
 236                     SPU_STATUS_STOPPED_BY_HALT | SPU_STATUS_STOPPED_BY_STOP;
 237                 if ((in_be32(&prob->spu_status_R) & stopped) == 0)
 238                         csa->prob.spu_status_R = SPU_STATUS_RUNNING;
 239                 else
 240                         csa->prob.spu_status_R = in_be32(&prob->spu_status_R);
 241         }
 242 }
 243
 244 static inline void save_mfc_decr(struct spu_state *csa, struct spu *spu)
 245 {
 246         struct spu_priv2 __iomem *priv2 = spu->priv2;
 247
 248         /* Save, Step 12:
 249          *     Read MFC_CNTL[Ds].  Update saved copy of
 250          *     CSA.MFC_CNTL[Ds].
 251          */
 252         csa->priv2.mfc_control_RW |=
 253                 in_be64(&priv2->mfc_control_RW) & MFC_CNTL_DECREMENTER_RUNNING;
 254 }
 255
 256 static inline void halt_mfc_decr(struct spu_state *csa, struct spu *spu)
 257 {
 258         struct spu_priv2 __iomem *priv2 = spu->priv2;
 259
 260         /* Save, Step 13:
 261          *     Write MFC_CNTL[Dh] set to a '1' to halt
 262          *     the decrementer.
 263          */
 264         out_be64(&priv2->mfc_control_RW,
 265                  MFC_CNTL_DECREMENTER_HALTED | MFC_CNTL_SUSPEND_MASK);
 266         eieio();
 267 }
 268
 269 static inline void save_timebase(struct spu_state *csa, struct spu *spu)
 270 {
 271         /* Save, Step 14:
 272          *    Read PPE Timebase High and Timebase low registers
 273          *    and save in CSA.  TBD.
 274          */
 275         csa->suspend_time = get_cycles();
 276 }
 277
 278 static inline void remove_other_spu_access(struct spu_state *csa,
 279                                            struct spu *spu)
 280 {
 281         /* Save, Step 15:
 282          *     Remove other SPU access to this SPU by unmapping
 283          *     this SPU's pages from their address space.  TBD.
 284          */
 285 }
 286
 287 static inline void do_mfc_mssync(struct spu_state *csa, struct spu *spu)
 288 {
 289         struct spu_problem __iomem *prob = spu->problem;
 290
 291         /* Save, Step 16:
 292          * Restore, Step 11.
 293          *     Write SPU_MSSync register. Poll SPU_MSSync[P]
 294          *     for a value of 0.
 295          */
 296         out_be64(&prob->spc_mssync_RW, 1UL);
 297         POLL_WHILE_TRUE(in_be64(&prob->spc_mssync_RW) & MS_SYNC_PENDING);
 298 }
 299
 300 static inline void issue_mfc_tlbie(struct spu_state *csa, struct spu *spu)
 301 {
 302         /* Save, Step 17:
 303          * Restore, Step 12.
 304          * Restore, Step 48.
 305          *     Write TLB_Invalidate_Entry[IS,VPN,L,Lp]=0 register.
 306          *     Then issue a PPE sync instruction.
 307          */
 308         spu_tlb_invalidate(spu);
 309         mb();
 310 }
 311
 312 static inline void handle_pending_interrupts(struct spu_state *csa,
 313                                              struct spu *spu)
 314 {
 315         /* Save, Step 18:
 316          *     Handle any pending interrupts from this SPU
 317          *     here.  This is OS or hypervisor specific.  One
 318          *     option is to re-enable interrupts to handle any
 319          *     pending interrupts, with the interrupt handlers
 320          *     recognizing the software Context Switch Pending
 321          *     flag, to ensure the SPU execution or MFC command
 322          *     queue is not restarted.  TBD.
 323          */
 324 }
 325
 326 static inline void save_mfc_queues(struct spu_state *csa, struct spu *spu)
 327 {
 328         struct spu_priv2 __iomem *priv2 = spu->priv2;
 329         int i;
 330
 331         /* Save, Step 19:
 332          *     If MFC_Cntl[Se]=0 then save
 333          *     MFC command queues.
 334          */
 335         if ((in_be64(&priv2->mfc_control_RW) & MFC_CNTL_DMA_QUEUES_EMPTY) == 0) {
 336                 for (i = 0; i < 8; i++) {
 337                         csa->priv2.puq[i].mfc_cq_data0_RW =
 338                             in_be64(&priv2->puq[i].mfc_cq_data0_RW);
 339                         csa->priv2.puq[i].mfc_cq_data1_RW =
 340                             in_be64(&priv2->puq[i].mfc_cq_data1_RW);
 341                         csa->priv2.puq[i].mfc_cq_data2_RW =
 342                             in_be64(&priv2->puq[i].mfc_cq_data2_RW);
 343                         csa->priv2.puq[i].mfc_cq_data3_RW =
 344                             in_be64(&priv2->puq[i].mfc_cq_data3_RW);
 345                 }
 346                 for (i = 0; i < 16; i++) {
 347                         csa->priv2.spuq[i].mfc_cq_data0_RW =
 348                             in_be64(&priv2->spuq[i].mfc_cq_data0_RW);
 349                         csa->priv2.spuq[i].mfc_cq_data1_RW =
 350                             in_be64(&priv2->spuq[i].mfc_cq_data1_RW);
 351                         csa->priv2.spuq[i].mfc_cq_data2_RW =
 352                             in_be64(&priv2->spuq[i].mfc_cq_data2_RW);
 353                         csa->priv2.spuq[i].mfc_cq_data3_RW =
 354                             in_be64(&priv2->spuq[i].mfc_cq_data3_RW);
 355                 }
 356         }
 357 }
 358
 359 static inline void save_ppu_querymask(struct spu_state *csa, struct spu *spu)
 360 {
 361         struct spu_problem __iomem *prob = spu->problem;
 362
 363         /* Save, Step 20:
 364          *     Save the PPU_QueryMask register
 365          *     in the CSA.
 366          */
 367         csa->prob.dma_querymask_RW = in_be32(&prob->dma_querymask_RW);
 368 }
 369
 370 static inline void save_ppu_querytype(struct spu_state *csa, struct spu *spu)
 371 {
 372         struct spu_problem __iomem *prob = spu->problem;
 373
 374         /* Save, Step 21:
 375          *     Save the PPU_QueryType register
 376          *     in the CSA.
 377          */
 378         csa->prob.dma_querytype_RW = in_be32(&prob->dma_querytype_RW);
 379 }
 380
 381 static inline void save_ppu_tagstatus(struct spu_state *csa, struct spu *spu)
 382 {
 383         struct spu_problem __iomem *prob = spu->problem;
 384
 385         /* Save the Prxy_TagStatus register in the CSA.
 386          *
 387          * It is unnecessary to restore dma_tagstatus_R, however,
 388          * dma_tagstatus_R in the CSA is accessed via backing_ops, so
 389          * we must save it.
 390          */
 391         csa->prob.dma_tagstatus_R = in_be32(&prob->dma_tagstatus_R);
 392 }
 393
 394 static inline void save_mfc_csr_tsq(struct spu_state *csa, struct spu *spu)
 395 {
 396         struct spu_priv2 __iomem *priv2 = spu->priv2;
 397
 398         /* Save, Step 22:
 399          *     Save the MFC_CSR_TSQ register
 400          *     in the LSCSA.
 401          */
 402         csa->priv2.spu_tag_status_query_RW =
 403             in_be64(&priv2->spu_tag_status_query_RW);
 404 }
 405
 406 static inline void save_mfc_csr_cmd(struct spu_state *csa, struct spu *spu)
 407 {
 408         struct spu_priv2 __iomem *priv2 = spu->priv2;
 409
 410         /* Save, Step 23:
 411          *     Save the MFC_CSR_CMD1 and MFC_CSR_CMD2
 412          *     registers in the CSA.
 413          */
 414         csa->priv2.spu_cmd_buf1_RW = in_be64(&priv2->spu_cmd_buf1_RW);
 415         csa->priv2.spu_cmd_buf2_RW = in_be64(&priv2->spu_cmd_buf2_RW);
 416 }
 417
 418 static inline void save_mfc_csr_ato(struct spu_state *csa, struct spu *spu)
 419 {
 420         struct spu_priv2 __iomem *priv2 = spu->priv2;
 421
 422         /* Save, Step 24:
 423          *     Save the MFC_CSR_ATO register in
 424          *     the CSA.
 425          */
 426         csa->priv2.spu_atomic_status_RW = in_be64(&priv2->spu_atomic_status_RW);
 427 }
 428
 429 static inline void save_mfc_tclass_id(struct spu_state *csa, struct spu *spu)
 430 {
 431         /* Save, Step 25:
 432          *     Save the MFC_TCLASS_ID register in
 433          *     the CSA.
 434          */
 435         csa->priv1.mfc_tclass_id_RW = spu_mfc_tclass_id_get(spu);
 436 }
 437
 438 static inline void set_mfc_tclass_id(struct spu_state *csa, struct spu *spu)
 439 {
 440         /* Save, Step 26:
 441          * Restore, Step 23.
 442          *     Write the MFC_TCLASS_ID register with
 443          *     the value 0x10000000.
 444          */
 445         spu_mfc_tclass_id_set(spu, 0x10000000);
 446         eieio();
 447 }
 448
 449 static inline void purge_mfc_queue(struct spu_state *csa, struct spu *spu)
 450 {
 451         struct spu_priv2 __iomem *priv2 = spu->priv2;
 452
 453         /* Save, Step 27:
 454          * Restore, Step 14.
 455          *     Write MFC_CNTL[Pc]=1 (purge queue).
 456          */
 457         out_be64(&priv2->mfc_control_RW, MFC_CNTL_PURGE_DMA_REQUEST);
 458         eieio();
 459 }
 460
 461 static inline void wait_purge_complete(struct spu_state *csa, struct spu *spu)
 462 {
 463         struct spu_priv2 __iomem *priv2 = spu->priv2;
 464
 465         /* Save, Step 28:
 466          *     Poll MFC_CNTL[Ps] until value '11' is read
 467          *     (purge complete).
 468          */
 469         POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) &
 470                          MFC_CNTL_PURGE_DMA_STATUS_MASK) ==
 471                          MFC_CNTL_PURGE_DMA_COMPLETE);
 472 }
 473
 474 static inline void setup_mfc_sr1(struct spu_state *csa, struct spu *spu)
 475 {
 476         /* Save, Step 30:
 477          * Restore, Step 18:
 478          *     Write MFC_SR1 with MFC_SR1[D=0,S=1] and
 479          *     MFC_SR1[TL,R,Pr,T] set correctly for the
 480          *     OS specific environment.
 481          *
 482          *     Implementation note: The SPU-side code
 483          *     for save/restore is privileged, so the
 484          *     MFC_SR1[Pr] bit is not set.
 485          *
 486          */
 487         spu_mfc_sr1_set(spu, (MFC_STATE1_MASTER_RUN_CONTROL_MASK |
 488                               MFC_STATE1_RELOCATE_MASK |
 489                               MFC_STATE1_BUS_TLBIE_MASK));
 490 }
 491
 492 static inline void save_spu_npc(struct spu_state *csa, struct spu *spu)
 493 {
 494         struct spu_problem __iomem *prob = spu->problem;
 495
 496         /* Save, Step 31:
 497          *     Save SPU_NPC in the CSA.
 498          */
 499         csa->prob.spu_npc_RW = in_be32(&prob->spu_npc_RW);
 500 }
 501
 502 static inline void save_spu_privcntl(struct spu_state *csa, struct spu *spu)
 503 {
 504         struct spu_priv2 __iomem *priv2 = spu->priv2;
 505
 506         /* Save, Step 32:
 507          *     Save SPU_PrivCntl in the CSA.
 508          */
 509         csa->priv2.spu_privcntl_RW = in_be64(&priv2->spu_privcntl_RW);
 510 }
 511
 512 static inline void reset_spu_privcntl(struct spu_state *csa, struct spu *spu)
 513 {
 514         struct spu_priv2 __iomem *priv2 = spu->priv2;
 515
 516         /* Save, Step 33:
 517          * Restore, Step 16:
 518          *     Write SPU_PrivCntl[S,Le,A] fields reset to 0.
 519          */
 520         out_be64(&priv2->spu_privcntl_RW, 0UL);
 521         eieio();
 522 }
 523
 524 static inline void save_spu_lslr(struct spu_state *csa, struct spu *spu)
 525 {
 526         struct spu_priv2 __iomem *priv2 = spu->priv2;
 527
 528         /* Save, Step 34:
 529          *     Save SPU_LSLR in the CSA.
 530          */
 531         csa->priv2.spu_lslr_RW = in_be64(&priv2->spu_lslr_RW);
 532 }
 533
 534 static inline void reset_spu_lslr(struct spu_state *csa, struct spu *spu)
 535 {
 536         struct spu_priv2 __iomem *priv2 = spu->priv2;
 537
 538         /* Save, Step 35:
 539          * Restore, Step 17.
 540          *     Reset SPU_LSLR.
 541          */
 542         out_be64(&priv2->spu_lslr_RW, LS_ADDR_MASK);
 543         eieio();
 544 }
 545
 546 static inline void save_spu_cfg(struct spu_state *csa, struct spu *spu)
 547 {
 548         struct spu_priv2 __iomem *priv2 = spu->priv2;
 549
 550         /* Save, Step 36:
 551          *     Save SPU_Cfg in the CSA.
 552          */
 553         csa->priv2.spu_cfg_RW = in_be64(&priv2->spu_cfg_RW);
 554 }
 555
 556 static inline void save_pm_trace(struct spu_state *csa, struct spu *spu)
 557 {
 558         /* Save, Step 37:
 559          *     Save PM_Trace_Tag_Wait_Mask in the CSA.
 560          *     Not performed by this implementation.
 561          */
 562 }
 563
 564 static inline void save_mfc_rag(struct spu_state *csa, struct spu *spu)
 565 {
 566         /* Save, Step 38:
 567          *     Save RA_GROUP_ID register and the
 568          *     RA_ENABLE reigster in the CSA.
 569          */
 570         csa->priv1.resource_allocation_groupID_RW =
 571                 spu_resource_allocation_groupID_get(spu);
 572         csa->priv1.resource_allocation_enable_RW =
 573                 spu_resource_allocation_enable_get(spu);
 574 }
 575
 576 static inline void save_ppu_mb_stat(struct spu_state *csa, struct spu *spu)
 577 {
 578         struct spu_problem __iomem *prob = spu->problem;
 579
 580         /* Save, Step 39:
 581          *     Save MB_Stat register in the CSA.
 582          */
 583         csa->prob.mb_stat_R = in_be32(&prob->mb_stat_R);
 584 }
 585
 586 static inline void save_ppu_mb(struct spu_state *csa, struct spu *spu)
 587 {
 588         struct spu_problem __iomem *prob = spu->problem;
 589
 590         /* Save, Step 40:
 591          *     Save the PPU_MB register in the CSA.
 592          */
 593         csa->prob.pu_mb_R = in_be32(&prob->pu_mb_R);
 594 }
 595
 596 static inline void save_ppuint_mb(struct spu_state *csa, struct spu *spu)
 597 {
 598         struct spu_priv2 __iomem *priv2 = spu->priv2;
 599
 600         /* Save, Step 41:
 601          *     Save the PPUINT_MB register in the CSA.
 602          */
 603         csa->priv2.puint_mb_R = in_be64(&priv2->puint_mb_R);
 604 }
 605
 606 static inline void save_ch_part1(struct spu_state *csa, struct spu *spu)
 607 {
 608         struct spu_priv2 __iomem *priv2 = spu->priv2;
 609         u64 idx, ch_indices[] = { 0UL, 3UL, 4UL, 24UL, 25UL, 27UL };
 610         int i;
 611
 612         /* Save, Step 42:
 613          */
 614
 615         /* Save CH 1, without channel count */
 616         out_be64(&priv2->spu_chnlcntptr_RW, 1);
 617         csa->spu_chnldata_RW[1] = in_be64(&priv2->spu_chnldata_RW);
 618
 619         /* Save the following CH: [0,3,4,24,25,27] */
 620         for (i = 0; i < ARRAY_SIZE(ch_indices); i++) {
 621                 idx = ch_indices[i];
 622                 out_be64(&priv2->spu_chnlcntptr_RW, idx);
 623                 eieio();
 624                 csa->spu_chnldata_RW[idx] = in_be64(&priv2->spu_chnldata_RW);
 625                 csa->spu_chnlcnt_RW[idx] = in_be64(&priv2->spu_chnlcnt_RW);
 626                 out_be64(&priv2->spu_chnldata_RW, 0UL);
 627                 out_be64(&priv2->spu_chnlcnt_RW, 0UL);
 628                 eieio();
 629         }
 630 }
 631
 632 static inline void save_spu_mb(struct spu_state *csa, struct spu *spu)
 633 {
 634         struct spu_priv2 __iomem *priv2 = spu->priv2;
 635         int i;
 636
 637         /* Save, Step 43:
 638          *     Save SPU Read Mailbox Channel.
 639          */
 640         out_be64(&priv2->spu_chnlcntptr_RW, 29UL);
 641         eieio();
 642         csa->spu_chnlcnt_RW[29] = in_be64(&priv2->spu_chnlcnt_RW);
 643         for (i = 0; i < 4; i++) {
 644                 csa->spu_mailbox_data[i] = in_be64(&priv2->spu_chnldata_RW);
 645         }
 646         out_be64(&priv2->spu_chnlcnt_RW, 0UL);
 647         eieio();
 648 }
 649
 650 static inline void save_mfc_cmd(struct spu_state *csa, struct spu *spu)
 651 {
 652         struct spu_priv2 __iomem *priv2 = spu->priv2;
 653
 654         /* Save, Step 44:
 655          *     Save MFC_CMD Channel.
 656          */
 657         out_be64(&priv2->spu_chnlcntptr_RW, 21UL);
 658         eieio();
 659         csa->spu_chnlcnt_RW[21] = in_be64(&priv2->spu_chnlcnt_RW);
 660         eieio();
 661 }
 662
 663 static inline void reset_ch(struct spu_state *csa, struct spu *spu)
 664 {
 665         struct spu_priv2 __iomem *priv2 = spu->priv2;
 666         u64 ch_indices[4] = { 21UL, 23UL, 28UL, 30UL };
 667         u64 ch_counts[4] = { 16UL, 1UL, 1UL, 1UL };
 668         u64 idx;
 669         int i;
 670
 671         /* Save, Step 45:
 672          *     Reset the following CH: [21, 23, 28, 30]
 673          */
 674         for (i = 0; i < 4; i++) {
 675                 idx = ch_indices[i];
 676                 out_be64(&priv2->spu_chnlcntptr_RW, idx);
 677                 eieio();
 678                 out_be64(&priv2->spu_chnlcnt_RW, ch_counts[i]);
 679                 eieio();
 680         }
 681 }
 682
 683 static inline void resume_mfc_queue(struct spu_state *csa, struct spu *spu)
 684 {
 685         struct spu_priv2 __iomem *priv2 = spu->priv2;
 686
 687         /* Save, Step 46:
 688          * Restore, Step 25.
 689          *     Write MFC_CNTL[Sc]=0 (resume queue processing).
 690          */
 691         out_be64(&priv2->mfc_control_RW, MFC_CNTL_RESUME_DMA_QUEUE);
 692 }
 693
 694 static inline void setup_mfc_slbs(struct spu_state *csa, struct spu *spu)
 695 {
 696         /* Save, Step 47:
 697          * Restore, Step 30.
 698          *     If MFC_SR1[R]=1, write 0 to SLB_Invalidate_All
 699          *     register, then initialize SLB_VSID and SLB_ESID
 700          *     to provide access to SPU context save code and
 701          *     LSCSA.
 702          *
 703          *     This implementation places both the context
 704          *     switch code and LSCSA in kernel address space.
 705          *
 706          *     Further this implementation assumes that the
 707          *     MFC_SR1[R]=1 (in other words, assume that
 708          *     translation is desired by OS environment).
 709          */
 710         spu_invalidate_slbs(spu);
 711         spu_setup_kernel_slbs(spu, csa->lscsa, &spu_save_code);
 712 }
 713
 714 static inline void set_switch_active(struct spu_state *csa, struct spu *spu)
 715 {
 716         /* Save, Step 48:
 717          * Restore, Step 23.
 718          *     Change the software context switch pending flag
 719          *     to context switch active.
 720          */
 721         set_bit(SPU_CONTEXT_SWITCH_ACTIVE, &spu->flags);
 722         clear_bit(SPU_CONTEXT_SWITCH_PENDING, &spu->flags);
 723         mb();
 724 }
 725
 726 static inline void enable_interrupts(struct spu_state *csa, struct spu *spu)
 727 {
 728         unsigned long class1_mask = CLASS1_ENABLE_SEGMENT_FAULT_INTR |
 729             CLASS1_ENABLE_STORAGE_FAULT_INTR;
 730
 731         /* Save, Step 49:
 732          * Restore, Step 22:
 733          *     Reset and then enable interrupts, as
 734          *     needed by OS.
 735          *
 736          *     This implementation enables only class1
 737          *     (translation) interrupts.
 738          */
 739         spin_lock_irq(&spu->register_lock);
 740         spu_int_stat_clear(spu, 0, ~0ul);
 741         spu_int_stat_clear(spu, 1, ~0ul);
 742         spu_int_stat_clear(spu, 2, ~0ul);
 743         spu_int_mask_set(spu, 0, 0ul);
 744         spu_int_mask_set(spu, 1, class1_mask);
 745         spu_int_mask_set(spu, 2, 0ul);
 746         spin_unlock_irq(&spu->register_lock);
 747 }
 748
 749 static inline int send_mfc_dma(struct spu *spu, unsigned long ea,
 750                                unsigned int ls_offset, unsigned int size,
 751                                unsigned int tag, unsigned int rclass,
 752                                unsigned int cmd)
 753 {
 754         struct spu_problem __iomem *prob = spu->problem;
 755         union mfc_tag_size_class_cmd command;
 756         unsigned int transfer_size;
 757         volatile unsigned int status = 0x0;
 758
 759         while (size > 0) {
 760                 transfer_size =
 761                     (size > MFC_MAX_DMA_SIZE) ? MFC_MAX_DMA_SIZE : size;
 762                 command.u.mfc_size = transfer_size;
 763                 command.u.mfc_tag = tag;
 764                 command.u.mfc_rclassid = rclass;
 765                 command.u.mfc_cmd = cmd;
 766                 do {
 767                         out_be32(&prob->mfc_lsa_W, ls_offset);
 768                         out_be64(&prob->mfc_ea_W, ea);
 769                         out_be64(&prob->mfc_union_W.all64, command.all64);
 770                         status =
 771                             in_be32(&prob->mfc_union_W.by32.mfc_class_cmd32);
 772                         if (unlikely(status & 0x2)) {
 773                                 cpu_relax();
 774                         }
 775                 } while (status & 0x3);
 776                 size -= transfer_size;
 777                 ea += transfer_size;
 778                 ls_offset += transfer_size;
 779         }
 780         return 0;
 781 }
 782
 783 static inline void save_ls_16kb(struct spu_state *csa, struct spu *spu)
 784 {
 785         unsigned long addr = (unsigned long)&csa->lscsa->ls[0];
 786         unsigned int ls_offset = 0x0;
 787         unsigned int size = 16384;
 788         unsigned int tag = 0;
 789         unsigned int rclass = 0;
 790         unsigned int cmd = MFC_PUT_CMD;
 791
 792         /* Save, Step 50:
 793          *     Issue a DMA command to copy the first 16K bytes
 794          *     of local storage to the CSA.
 795          */
 796         send_mfc_dma(spu, addr, ls_offset, size, tag, rclass, cmd);
 797 }
 798
 799 static inline void set_spu_npc(struct spu_state *csa, struct spu *spu)
 800 {
 801         struct spu_problem __iomem *prob = spu->problem;
 802
 803         /* Save, Step 51:
 804          * Restore, Step 31.
 805          *     Write SPU_NPC[IE]=0 and SPU_NPC[LSA] to entry
 806          *     point address of context save code in local
 807          *     storage.
 808          *
 809          *     This implementation uses SPU-side save/restore
 810          *     programs with entry points at LSA of 0.
 811          */
 812         out_be32(&prob->spu_npc_RW, 0);
 813         eieio();
 814 }
 815
 816 static inline void set_signot1(struct spu_state *csa, struct spu *spu)
 817 {
 818         struct spu_problem __iomem *prob = spu->problem;
 819         union {
 820                 u64 ull;
 821                 u32 ui[2];
 822         } addr64;
 823
 824         /* Save, Step 52:
 825          * Restore, Step 32:
 826          *    Write SPU_Sig_Notify_1 register with upper 32-bits
 827          *    of the CSA.LSCSA effective address.
 828          */
 829         addr64.ull = (u64) csa->lscsa;
 830         out_be32(&prob->signal_notify1, addr64.ui[0]);
 831         eieio();
 832 }
 833
 834 static inline void set_signot2(struct spu_state *csa, struct spu *spu)
 835 {
 836         struct spu_problem __iomem *prob = spu->problem;
 837         union {
 838                 u64 ull;
 839                 u32 ui[2];
 840         } addr64;
 841
 842         /* Save, Step 53:
 843          * Restore, Step 33:
 844          *    Write SPU_Sig_Notify_2 register with lower 32-bits
 845          *    of the CSA.LSCSA effective address.
 846          */
 847         addr64.ull = (u64) csa->lscsa;
 848         out_be32(&prob->signal_notify2, addr64.ui[1]);
 849         eieio();
 850 }
 851
 852 static inline void send_save_code(struct spu_state *csa, struct spu *spu)
 853 {
 854         unsigned long addr = (unsigned long)&spu_save_code[0];
 855         unsigned int ls_offset = 0x0;
 856         unsigned int size = sizeof(spu_save_code);
 857         unsigned int tag = 0;
 858         unsigned int rclass = 0;
 859         unsigned int cmd = MFC_GETFS_CMD;
 860
 861         /* Save, Step 54:
 862          *     Issue a DMA command to copy context save code
 863          *     to local storage and start SPU.
 864          */
 865         send_mfc_dma(spu, addr, ls_offset, size, tag, rclass, cmd);
 866 }
 867
 868 static inline void set_ppu_querymask(struct spu_state *csa, struct spu *spu)
 869 {
 870         struct spu_problem __iomem *prob = spu->problem;
 871
 872         /* Save, Step 55:
 873          * Restore, Step 38.
 874          *     Write PPU_QueryMask=1 (enable Tag Group 0)
 875          *     and issue eieio instruction.
 876          */
 877         out_be32(&prob->dma_querymask_RW, MFC_TAGID_TO_TAGMASK(0));
 878         eieio();
 879 }
 880
 881 static inline void wait_tag_complete(struct spu_state *csa, struct spu *spu)
 882 {
 883         struct spu_problem __iomem *prob = spu->problem;
 884         u32 mask = MFC_TAGID_TO_TAGMASK(0);
 885         unsigned long flags;
 886
 887         /* Save, Step 56:
 888          * Restore, Step 39.
 889          * Restore, Step 39.
 890          * Restore, Step 46.
 891          *     Poll PPU_TagStatus[gn] until 01 (Tag group 0 complete)
 892          *     or write PPU_QueryType[TS]=01 and wait for Tag Group
 893          *     Complete Interrupt.  Write INT_Stat_Class0 or
 894          *     INT_Stat_Class2 with value of 'handled'.
 895          */
 896         POLL_WHILE_FALSE(in_be32(&prob->dma_tagstatus_R) & mask);
 897
 898         local_irq_save(flags);
 899         spu_int_stat_clear(spu, 0, ~(0ul));
 900         spu_int_stat_clear(spu, 2, ~(0ul));
 901         local_irq_restore(flags);
 902 }
 903
 904 static inline void wait_spu_stopped(struct spu_state *csa, struct spu *spu)
 905 {
 906         struct spu_problem __iomem *prob = spu->problem;
 907         unsigned long flags;
 908
 909         /* Save, Step 57:
 910          * Restore, Step 40.
 911          *     Poll until SPU_Status[R]=0 or wait for SPU Class 0
 912          *     or SPU Class 2 interrupt.  Write INT_Stat_class0
 913          *     or INT_Stat_class2 with value of handled.
 914          */
 915         POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) & SPU_STATUS_RUNNING);
 916
 917         local_irq_save(flags);
 918         spu_int_stat_clear(spu, 0, ~(0ul));
 919         spu_int_stat_clear(spu, 2, ~(0ul));
 920         local_irq_restore(flags);
 921 }
 922
 923 static inline int check_save_status(struct spu_state *csa, struct spu *spu)
 924 {
 925         struct spu_problem __iomem *prob = spu->problem;
 926         u32 complete;
 927
 928         /* Save, Step 54:
 929          *     If SPU_Status[P]=1 and SPU_Status[SC] = "success",
 930          *     context save succeeded, otherwise context save
 931          *     failed.
 932          */
 933         complete = ((SPU_SAVE_COMPLETE << SPU_STOP_STATUS_SHIFT) |
 934                     SPU_STATUS_STOPPED_BY_STOP);
 935         return (in_be32(&prob->spu_status_R) != complete) ? 1 : 0;
 936 }
 937
 938 static inline void terminate_spu_app(struct spu_state *csa, struct spu *spu)
 939 {
 940         /* Restore, Step 4:
 941          *    If required, notify the "using application" that
 942          *    the SPU task has been terminated.  TBD.
 943          */
 944 }
 945
 946 static inline void suspend_mfc_and_halt_decr(struct spu_state *csa,
 947                 struct spu *spu)
 948 {
 949         struct spu_priv2 __iomem *priv2 = spu->priv2;
 950
 951         /* Restore, Step 7:
 952          *     Write MFC_Cntl[Dh,Sc,Sm]='1','1','0' to suspend
 953          *     the queue and halt the decrementer.
 954          */
 955         out_be64(&priv2->mfc_control_RW, MFC_CNTL_SUSPEND_DMA_QUEUE |
 956                  MFC_CNTL_DECREMENTER_HALTED);
 957         eieio();
 958 }
 959
 960 static inline void wait_suspend_mfc_complete(struct spu_state *csa,
 961                                              struct spu *spu)
 962 {
 963         struct spu_priv2 __iomem *priv2 = spu->priv2;
 964
 965         /* Restore, Step 8:
 966          * Restore, Step 47.
 967          *     Poll MFC_CNTL[Ss] until 11 is returned.
 968          */
 969         POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) &
 970                          MFC_CNTL_SUSPEND_DMA_STATUS_MASK) ==
 971                          MFC_CNTL_SUSPEND_COMPLETE);
 972 }
 973
 974 static inline int suspend_spe(struct spu_state *csa, struct spu *spu)
 975 {
 976         struct spu_problem __iomem *prob = spu->problem;
 977
 978         /* Restore, Step 9:
 979          *    If SPU_Status[R]=1, stop SPU execution
 980          *    and wait for stop to complete.
 981          *
 982          *    Returns       1 if SPU_Status[R]=1 on entry.
 983          *                  0 otherwise
 984          */
 985         if (in_be32(&prob->spu_status_R) & SPU_STATUS_RUNNING) {
 986                 if (in_be32(&prob->spu_status_R) &
 987                     SPU_STATUS_ISOLATED_EXIT_STATUS) {
 988                         POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
 989                                         SPU_STATUS_RUNNING);
 990                 }
 991                 if ((in_be32(&prob->spu_status_R) &
 992                      SPU_STATUS_ISOLATED_LOAD_STATUS)
 993                     || (in_be32(&prob->spu_status_R) &
 994                         SPU_STATUS_ISOLATED_STATE)) {
 995                         out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_STOP);
 996                         eieio();
 997                         POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
 998                                         SPU_STATUS_RUNNING);
 999                         out_be32(&prob->spu_runcntl_RW, 0x2);
1000                         eieio();
1001                         POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
1002                                         SPU_STATUS_RUNNING);
1003                 }
1004                 if (in_be32(&prob->spu_status_R) &
1005                     SPU_STATUS_WAITING_FOR_CHANNEL) {
1006                         out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_STOP);
1007                         eieio();
1008                         POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
1009                                         SPU_STATUS_RUNNING);
1010                 }
1011                 return 1;
1012         }
1013         return 0;
1014 }
1015
1016 static inline void clear_spu_status(struct spu_state *csa, struct spu *spu)
1017 {
1018         struct spu_problem __iomem *prob = spu->problem;
1019
1020         /* Restore, Step 10:
1021          *    If SPU_Status[R]=0 and SPU_Status[E,L,IS]=1,
1022          *    release SPU from isolate state.
1023          */
1024         if (!(in_be32(&prob->spu_status_R) & SPU_STATUS_RUNNING)) {
1025                 if (in_be32(&prob->spu_status_R) &
1026                     SPU_STATUS_ISOLATED_EXIT_STATUS) {
1027                         spu_mfc_sr1_set(spu,
1028                                         MFC_STATE1_MASTER_RUN_CONTROL_MASK);
1029                         eieio();
1030                         out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_RUNNABLE);
1031                         eieio();
1032                         POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
1033                                         SPU_STATUS_RUNNING);
1034                 }
1035                 if ((in_be32(&prob->spu_status_R) &
1036                      SPU_STATUS_ISOLATED_LOAD_STATUS)
1037                     || (in_be32(&prob->spu_status_R) &
1038                         SPU_STATUS_ISOLATED_STATE)) {
1039                         spu_mfc_sr1_set(spu,
1040                                         MFC_STATE1_MASTER_RUN_CONTROL_MASK);
1041                         eieio();
1042                         out_be32(&prob->spu_runcntl_RW, 0x2);
1043                         eieio();
1044                         POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
1045                                         SPU_STATUS_RUNNING);
1046                 }
1047         }
1048 }
1049
1050 static inline void reset_ch_part1(struct spu_state *csa, struct spu *spu)
1051 {
1052         struct spu_priv2 __iomem *priv2 = spu->priv2;
1053         u64 ch_indices[] = { 0UL, 3UL, 4UL, 24UL, 25UL, 27UL };
1054         u64 idx;
1055         int i;
1056
1057         /* Restore, Step 20:
1058          */
1059
1060         /* Reset CH 1 */
1061         out_be64(&priv2->spu_chnlcntptr_RW, 1);
1062         out_be64(&priv2->spu_chnldata_RW, 0UL);
1063
1064         /* Reset the following CH: [0,3,4,24,25,27] */
1065         for (i = 0; i < ARRAY_SIZE(ch_indices); i++) {
1066                 idx = ch_indices[i];
1067                 out_be64(&priv2->spu_chnlcntptr_RW, idx);
1068                 eieio();
1069                 out_be64(&priv2->spu_chnldata_RW, 0UL);
1070                 out_be64(&priv2->spu_chnlcnt_RW, 0UL);
1071                 eieio();
1072         }
1073 }
1074
1075 static inline void reset_ch_part2(struct spu_state *csa, struct spu *spu)
1076 {
1077         struct spu_priv2 __iomem *priv2 = spu->priv2;
1078         u64 ch_indices[5] = { 21UL, 23UL, 28UL, 29UL, 30UL };
1079         u64 ch_counts[5] = { 16UL, 1UL, 1UL, 0UL, 1UL };
1080         u64 idx;
1081         int i;
1082
1083         /* Restore, Step 21:
1084          *     Reset the following CH: [21, 23, 28, 29, 30]
1085          */
1086         for (i = 0; i < 5; i++) {
1087                 idx = ch_indices[i];
1088                 out_be64(&priv2->spu_chnlcntptr_RW, idx);
1089                 eieio();
1090                 out_be64(&priv2->spu_chnlcnt_RW, ch_counts[i]);
1091                 eieio();
1092         }
1093 }
1094
1095 static inline void setup_spu_status_part1(struct spu_state *csa,
1096                                           struct spu *spu)
1097 {
1098         u32 status_P = SPU_STATUS_STOPPED_BY_STOP;
1099         u32 status_I = SPU_STATUS_INVALID_INSTR;
1100         u32 status_H = SPU_STATUS_STOPPED_BY_HALT;
1101         u32 status_S = SPU_STATUS_SINGLE_STEP;
1102         u32 status_S_I = SPU_STATUS_SINGLE_STEP | SPU_STATUS_INVALID_INSTR;
1103         u32 status_S_P = SPU_STATUS_SINGLE_STEP | SPU_STATUS_STOPPED_BY_STOP;
1104         u32 status_P_H = SPU_STATUS_STOPPED_BY_HALT |SPU_STATUS_STOPPED_BY_STOP;
1105         u32 status_P_I = SPU_STATUS_STOPPED_BY_STOP |SPU_STATUS_INVALID_INSTR;
1106         u32 status_code;
1107
1108         /* Restore, Step 27:
1109          *     If the CSA.SPU_Status[I,S,H,P]=1 then add the correct
1110          *     instruction sequence to the end of the SPU based restore
1111          *     code (after the "context restored" stop and signal) to
1112          *     restore the correct SPU status.
1113          *
1114          *     NOTE: Rather than modifying the SPU executable, we
1115          *     instead add a new 'stopped_status' field to the
1116          *     LSCSA.  The SPU-side restore reads this field and
1117          *     takes the appropriate action when exiting.
1118          */
1119
1120         status_code =
1121             (csa->prob.spu_status_R >> SPU_STOP_STATUS_SHIFT) & 0xFFFF;
1122         if ((csa->prob.spu_status_R & status_P_I) == status_P_I) {
1123
1124                 /* SPU_Status[P,I]=1 - Illegal Instruction followed
1125                  * by Stop and Signal instruction, followed by 'br -4'.
1126                  *
1127                  */
1128                 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_P_I;
1129                 csa->lscsa->stopped_status.slot[1] = status_code;
1130
1131         } else if ((csa->prob.spu_status_R & status_P_H) == status_P_H) {
1132
1133                 /* SPU_Status[P,H]=1 - Halt Conditional, followed
1134                  * by Stop and Signal instruction, followed by
1135                  * 'br -4'.
1136                  */
1137                 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_P_H;
1138                 csa->lscsa->stopped_status.slot[1] = status_code;
1139
1140         } else if ((csa->prob.spu_status_R & status_S_P) == status_S_P) {
1141
1142                 /* SPU_Status[S,P]=1 - Stop and Signal instruction
1143                  * followed by 'br -4'.
1144                  */
1145                 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_S_P;
1146                 csa->lscsa->stopped_status.slot[1] = status_code;
1147
1148         } else if ((csa->prob.spu_status_R & status_S_I) == status_S_I) {
1149
1150                 /* SPU_Status[S,I]=1 - Illegal instruction followed
1151                  * by 'br -4'.
1152                  */
1153                 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_S_I;
1154                 csa->lscsa->stopped_status.slot[1] = status_code;
1155
1156         } else if ((csa->prob.spu_status_R & status_P) == status_P) {
1157
1158                 /* SPU_Status[P]=1 - Stop and Signal instruction
1159                  * followed by 'br -4'.
1160                  */
1161                 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_P;
1162                 csa->lscsa->stopped_status.slot[1] = status_code;
1163
1164         } else if ((csa->prob.spu_status_R & status_H) == status_H) {
1165
1166                 /* SPU_Status[H]=1 - Halt Conditional, followed
1167                  * by 'br -4'.
1168                  */
1169                 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_H;
1170
1171         } else if ((csa->prob.spu_status_R & status_S) == status_S) {
1172
1173                 /* SPU_Status[S]=1 - Two nop instructions.
1174                  */
1175                 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_S;
1176
1177         } else if ((csa->prob.spu_status_R & status_I) == status_I) {
1178
1179                 /* SPU_Status[I]=1 - Illegal instruction followed
1180                  * by 'br -4'.
1181                  */
1182                 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_I;
1183
1184         }
1185 }
1186
1187 static inline void setup_spu_status_part2(struct spu_state *csa,
1188                                           struct spu *spu)
1189 {
1190         u32 mask;
1191
1192         /* Restore, Step 28:
1193          *     If the CSA.SPU_Status[I,S,H,P,R]=0 then
1194          *     add a 'br *' instruction to the end of
1195          *     the SPU based restore code.
1196          *
1197          *     NOTE: Rather than modifying the SPU executable, we
1198          *     instead add a new 'stopped_status' field to the
1199          *     LSCSA.  The SPU-side restore reads this field and
1200          *     takes the appropriate action when exiting.
1201          */
1202         mask = SPU_STATUS_INVALID_INSTR |
1203             SPU_STATUS_SINGLE_STEP |
1204             SPU_STATUS_STOPPED_BY_HALT |
1205             SPU_STATUS_STOPPED_BY_STOP | SPU_STATUS_RUNNING;
1206         if (!(csa->prob.spu_status_R & mask)) {
1207                 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_R;
1208         }
1209 }
1210
1211 static inline void restore_mfc_rag(struct spu_state *csa, struct spu *spu)
1212 {
1213         /* Restore, Step 29:
1214          *     Restore RA_GROUP_ID register and the
1215          *     RA_ENABLE reigster from the CSA.
1216          */
1217         spu_resource_allocation_groupID_set(spu,
1218                         csa->priv1.resource_allocation_groupID_RW);
1219         spu_resource_allocation_enable_set(spu,
1220                         csa->priv1.resource_allocation_enable_RW);
1221 }
1222
1223 static inline void send_restore_code(struct spu_state *csa, struct spu *spu)
1224 {
1225         unsigned long addr = (unsigned long)&spu_restore_code[0];
1226         unsigned int ls_offset = 0x0;
1227         unsigned int size = sizeof(spu_restore_code);
1228         unsigned int tag = 0;
1229         unsigned int rclass = 0;
1230         unsigned int cmd = MFC_GETFS_CMD;
1231
1232         /* Restore, Step 37:
1233          *     Issue MFC DMA command to copy context
1234          *     restore code to local storage.
1235          */
1236         send_mfc_dma(spu, addr, ls_offset, size, tag, rclass, cmd);
1237 }
1238
1239 static inline void setup_decr(struct spu_state *csa, struct spu *spu)
1240 {
1241         /* Restore, Step 34:
1242          *     If CSA.MFC_CNTL[Ds]=1 (decrementer was
1243          *     running) then adjust decrementer, set
1244          *     decrementer running status in LSCSA,
1245          *     and set decrementer "wrapped" status
1246          *     in LSCSA.
1247          */
1248         if (csa->priv2.mfc_control_RW & MFC_CNTL_DECREMENTER_RUNNING) {
1249                 cycles_t resume_time = get_cycles();
1250                 cycles_t delta_time = resume_time - csa->suspend_time;
1251
1252                 csa->lscsa->decr_status.slot[0] = SPU_DECR_STATUS_RUNNING;
1253                 if (csa->lscsa->decr.slot[0] < delta_time) {
1254                         csa->lscsa->decr_status.slot[0] |=
1255                                  SPU_DECR_STATUS_WRAPPED;
1256                 }
1257
1258                 csa->lscsa->decr.slot[0] -= delta_time;
1259         } else {
1260                 csa->lscsa->decr_status.slot[0] = 0;
1261         }
1262 }
1263
1264 static inline void setup_ppu_mb(struct spu_state *csa, struct spu *spu)
1265 {
1266         /* Restore, Step 35:
1267          *     Copy the CSA.PU_MB data into the LSCSA.
1268          */
1269         csa->lscsa->ppu_mb.slot[0] = csa->prob.pu_mb_R;
1270 }
1271
1272 static inline void setup_ppuint_mb(struct spu_state *csa, struct spu *spu)
1273 {
1274         /* Restore, Step 36:
1275          *     Copy the CSA.PUINT_MB data into the LSCSA.
1276          */
1277         csa->lscsa->ppuint_mb.slot[0] = csa->priv2.puint_mb_R;
1278 }
1279
1280 static inline int check_restore_status(struct spu_state *csa, struct spu *spu)
1281 {
1282         struct spu_problem __iomem *prob = spu->problem;
1283         u32 complete;
1284
1285         /* Restore, Step 40:
1286          *     If SPU_Status[P]=1 and SPU_Status[SC] = "success",
1287          *     context restore succeeded, otherwise context restore
1288          *     failed.
1289          */
1290         complete = ((SPU_RESTORE_COMPLETE << SPU_STOP_STATUS_SHIFT) |
1291                     SPU_STATUS_STOPPED_BY_STOP);
1292         return (in_be32(&prob->spu_status_R) != complete) ? 1 : 0;
1293 }
1294
1295 static inline void restore_spu_privcntl(struct spu_state *csa, struct spu *spu)
1296 {
1297         struct spu_priv2 __iomem *priv2 = spu->priv2;
1298
1299         /* Restore, Step 41:
1300          *     Restore SPU_PrivCntl from the CSA.
1301          */
1302         out_be64(&priv2->spu_privcntl_RW, csa->priv2.spu_privcntl_RW);
1303         eieio();
1304 }
1305
1306 static inline void restore_status_part1(struct spu_state *csa, struct spu *spu)
1307 {
1308         struct spu_problem __iomem *prob = spu->problem;
1309         u32 mask;
1310
1311         /* Restore, Step 42:
1312          *     If any CSA.SPU_Status[I,S,H,P]=1, then
1313          *     restore the error or single step state.
1314          */
1315         mask = SPU_STATUS_INVALID_INSTR |
1316             SPU_STATUS_SINGLE_STEP |
1317             SPU_STATUS_STOPPED_BY_HALT | SPU_STATUS_STOPPED_BY_STOP;
1318         if (csa->prob.spu_status_R & mask) {
1319                 out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_RUNNABLE);
1320                 eieio();
1321                 POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
1322                                 SPU_STATUS_RUNNING);
1323         }
1324 }
1325
1326 static inline void restore_status_part2(struct spu_state *csa, struct spu *spu)
1327 {
1328         struct spu_problem __iomem *prob = spu->problem;
1329         u32 mask;
1330
1331         /* Restore, Step 43:
1332          *     If all CSA.SPU_Status[I,S,H,P,R]=0 then write
1333          *     SPU_RunCntl[R0R1]='01', wait for SPU_Status[R]=1,
1334          *     then write '00' to SPU_RunCntl[R0R1] and wait
1335          *     for SPU_Status[R]=0.
1336          */
1337         mask = SPU_STATUS_INVALID_INSTR |
1338             SPU_STATUS_SINGLE_STEP |
1339             SPU_STATUS_STOPPED_BY_HALT |
1340             SPU_STATUS_STOPPED_BY_STOP | SPU_STATUS_RUNNING;
1341         if (!(csa->prob.spu_status_R & mask)) {
1342                 out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_RUNNABLE);
1343                 eieio();
1344                 POLL_WHILE_FALSE(in_be32(&prob->spu_status_R) &
1345                                  SPU_STATUS_RUNNING);
1346                 out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_STOP);
1347                 eieio();
1348                 POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
1349                                 SPU_STATUS_RUNNING);
1350         }
1351 }
1352
1353 static inline void restore_ls_16kb(struct spu_state *csa, struct spu *spu)
1354 {
1355         unsigned long addr = (unsigned long)&csa->lscsa->ls[0];
1356         unsigned int ls_offset = 0x0;
1357         unsigned int size = 16384;
1358         unsigned int tag = 0;
1359         unsigned int rclass = 0;
1360         unsigned int cmd = MFC_GET_CMD;
1361
1362         /* Restore, Step 44:
1363          *     Issue a DMA command to restore the first
1364          *     16kb of local storage from CSA.
1365          */
1366         send_mfc_dma(spu, addr, ls_offset, size, tag, rclass, cmd);
1367 }
1368
1369 static inline void suspend_mfc(struct spu_state *csa, struct spu *spu)
1370 {
1371         struct spu_priv2 __iomem *priv2 = spu->priv2;
1372
1373         /* Restore, Step 47.
1374          *     Write MFC_Cntl[Sc,Sm]='1','0' to suspend
1375          *     the queue.
1376          */
1377         out_be64(&priv2->mfc_control_RW, MFC_CNTL_SUSPEND_DMA_QUEUE);
1378         eieio();
1379 }
1380
1381 static inline void clear_interrupts(struct spu_state *csa, struct spu *spu)
1382 {
1383         /* Restore, Step 49:
1384          *     Write INT_MASK_class0 with value of 0.
1385          *     Write INT_MASK_class1 with value of 0.
1386          *     Write INT_MASK_class2 with value of 0.
1387          *     Write INT_STAT_class0 with value of -1.
1388          *     Write INT_STAT_class1 with value of -1.
1389          *     Write INT_STAT_class2 with value of -1.
1390          */
1391         spin_lock_irq(&spu->register_lock);
1392         spu_int_mask_set(spu, 0, 0ul);
1393         spu_int_mask_set(spu, 1, 0ul);
1394         spu_int_mask_set(spu, 2, 0ul);
1395         spu_int_stat_clear(spu, 0, ~0ul);
1396         spu_int_stat_clear(spu, 1, ~0ul);
1397         spu_int_stat_clear(spu, 2, ~0ul);
1398         spin_unlock_irq(&spu->register_lock);
1399 }
1400
1401 static inline void restore_mfc_queues(struct spu_state *csa, struct spu *spu)
1402 {
1403         struct spu_priv2 __iomem *priv2 = spu->priv2;
1404         int i;
1405
1406         /* Restore, Step 50:
1407          *     If MFC_Cntl[Se]!=0 then restore
1408          *     MFC command queues.
1409          */
1410         if ((csa->priv2.mfc_control_RW & MFC_CNTL_DMA_QUEUES_EMPTY_MASK) == 0) {
1411                 for (i = 0; i < 8; i++) {
1412                         out_be64(&priv2->puq[i].mfc_cq_data0_RW,
1413                                  csa->priv2.puq[i].mfc_cq_data0_RW);
1414                         out_be64(&priv2->puq[i].mfc_cq_data1_RW,
1415                                  csa->priv2.puq[i].mfc_cq_data1_RW);
1416                         out_be64(&priv2->puq[i].mfc_cq_data2_RW,
1417                                  csa->priv2.puq[i].mfc_cq_data2_RW);
1418                         out_be64(&priv2->puq[i].mfc_cq_data3_RW,
1419                                  csa->priv2.puq[i].mfc_cq_data3_RW);
1420                 }
1421                 for (i = 0; i < 16; i++) {
1422                         out_be64(&priv2->spuq[i].mfc_cq_data0_RW,
1423                                  csa->priv2.spuq[i].mfc_cq_data0_RW);
1424                         out_be64(&priv2->spuq[i].mfc_cq_data1_RW,
1425                                  csa->priv2.spuq[i].mfc_cq_data1_RW);
1426                         out_be64(&priv2->spuq[i].mfc_cq_data2_RW,
1427                                  csa->priv2.spuq[i].mfc_cq_data2_RW);
1428                         out_be64(&priv2->spuq[i].mfc_cq_data3_RW,
1429                                  csa->priv2.spuq[i].mfc_cq_data3_RW);
1430                 }
1431         }
1432         eieio();
1433 }
1434
1435 static inline void restore_ppu_querymask(struct spu_state *csa, struct spu *spu)
1436 {
1437         struct spu_problem __iomem *prob = spu->problem;
1438
1439         /* Restore, Step 51:
1440          *     Restore the PPU_QueryMask register from CSA.
1441          */
1442         out_be32(&prob->dma_querymask_RW, csa->prob.dma_querymask_RW);
1443         eieio();
1444 }
1445
1446 static inline void restore_ppu_querytype(struct spu_state *csa, struct spu *spu)
1447 {
1448         struct spu_problem __iomem *prob = spu->problem;
1449
1450         /* Restore, Step 52:
1451          *     Restore the PPU_QueryType register from CSA.
1452          */
1453         out_be32(&prob->dma_querytype_RW, csa->prob.dma_querytype_RW);
1454         eieio();
1455 }
1456
1457 static inline void restore_mfc_csr_tsq(struct spu_state *csa, struct spu *spu)
1458 {
1459         struct spu_priv2 __iomem *priv2 = spu->priv2;
1460
1461         /* Restore, Step 53:
1462          *     Restore the MFC_CSR_TSQ register from CSA.
1463          */
1464         out_be64(&priv2->spu_tag_status_query_RW,
1465                  csa->priv2.spu_tag_status_query_RW);
1466         eieio();
1467 }
1468
1469 static inline void restore_mfc_csr_cmd(struct spu_state *csa, struct spu *spu)
1470 {
1471         struct spu_priv2 __iomem *priv2 = spu->priv2;
1472
1473         /* Restore, Step 54:
1474          *     Restore the MFC_CSR_CMD1 and MFC_CSR_CMD2
1475          *     registers from CSA.
1476          */
1477         out_be64(&priv2->spu_cmd_buf1_RW, csa->priv2.spu_cmd_buf1_RW);
1478         out_be64(&priv2->spu_cmd_buf2_RW, csa->priv2.spu_cmd_buf2_RW);
1479         eieio();
1480 }
1481
1482 static inline void restore_mfc_csr_ato(struct spu_state *csa, struct spu *spu)
1483 {
1484         struct spu_priv2 __iomem *priv2 = spu->priv2;
1485
1486         /* Restore, Step 55:
1487          *     Restore the MFC_CSR_ATO register from CSA.
1488          */
1489         out_be64(&priv2->spu_atomic_status_RW, csa->priv2.spu_atomic_status_RW);
1490 }
1491
1492 static inline void restore_mfc_tclass_id(struct spu_state *csa, struct spu *spu)
1493 {
1494         /* Restore, Step 56:
1495          *     Restore the MFC_TCLASS_ID register from CSA.
1496          */
1497         spu_mfc_tclass_id_set(spu, csa->priv1.mfc_tclass_id_RW);
1498         eieio();
1499 }
1500
1501 static inline void set_llr_event(struct spu_state *csa, struct spu *spu)
1502 {
1503         u64 ch0_cnt, ch0_data;
1504         u64 ch1_data;
1505
1506         /* Restore, Step 57:
1507          *    Set the Lock Line Reservation Lost Event by:
1508          *      1. OR CSA.SPU_Event_Status with bit 21 (Lr) set to 1.
1509          *      2. If CSA.SPU_Channel_0_Count=0 and
1510          *         CSA.SPU_Wr_Event_Mask[Lr]=1 and
1511          *         CSA.SPU_Event_Status[Lr]=0 then set
1512          *         CSA.SPU_Event_Status_Count=1.
1513          */
1514         ch0_cnt = csa->spu_chnlcnt_RW[0];
1515         ch0_data = csa->spu_chnldata_RW[0];
1516         ch1_data = csa->spu_chnldata_RW[1];
1517         csa->spu_chnldata_RW[0] |= MFC_LLR_LOST_EVENT;
1518         if ((ch0_cnt == 0) && !(ch0_data & MFC_LLR_LOST_EVENT) &&
1519             (ch1_data & MFC_LLR_LOST_EVENT)) {
1520                 csa->spu_chnlcnt_RW[0] = 1;
1521         }
1522 }
1523
1524 static inline void restore_decr_wrapped(struct spu_state *csa, struct spu *spu)
1525 {
1526         /* Restore, Step 58:
1527          *     If the status of the CSA software decrementer
1528          *     "wrapped" flag is set, OR in a '1' to
1529          *     CSA.SPU_Event_Status[Tm].
1530          */
1531         if (!(csa->lscsa->decr_status.slot[0] & SPU_DECR_STATUS_WRAPPED))
1532                 return;
1533
1534         if ((csa->spu_chnlcnt_RW[0] == 0) &&
1535             (csa->spu_chnldata_RW[1] & 0x20) &&
1536             !(csa->spu_chnldata_RW[0] & 0x20))
1537                 csa->spu_chnlcnt_RW[0] = 1;
1538
1539         csa->spu_chnldata_RW[0] |= 0x20;
1540 }
1541
1542 static inline void restore_ch_part1(struct spu_state *csa, struct spu *spu)
1543 {
1544         struct spu_priv2 __iomem *priv2 = spu->priv2;
1545         u64 idx, ch_indices[] = { 0UL, 3UL, 4UL, 24UL, 25UL, 27UL };
1546         int i;
1547
1548         /* Restore, Step 59:
1549          *      Restore the following CH: [0,3,4,24,25,27]
1550          */
1551         for (i = 0; i < ARRAY_SIZE(ch_indices); i++) {
1552                 idx = ch_indices[i];
1553                 out_be64(&priv2->spu_chnlcntptr_RW, idx);
1554                 eieio();
1555                 out_be64(&priv2->spu_chnldata_RW, csa->spu_chnldata_RW[idx]);
1556                 out_be64(&priv2->spu_chnlcnt_RW, csa->spu_chnlcnt_RW[idx]);
1557                 eieio();
1558         }
1559 }
1560
1561 static inline void restore_ch_part2(struct spu_state *csa, struct spu *spu)
1562 {
1563         struct spu_priv2 __iomem *priv2 = spu->priv2;
1564         u64 ch_indices[3] = { 9UL, 21UL, 23UL };
1565         u64 ch_counts[3] = { 1UL, 16UL, 1UL };
1566         u64 idx;
1567         int i;
1568
1569         /* Restore, Step 60:
1570          *     Restore the following CH: [9,21,23].
1571          */
1572         ch_counts[0] = 1UL;
1573         ch_counts[1] = csa->spu_chnlcnt_RW[21];
1574         ch_counts[2] = 1UL;
1575         for (i = 0; i < 3; i++) {
1576                 idx = ch_indices[i];
1577                 out_be64(&priv2->spu_chnlcntptr_RW, idx);
1578                 eieio();
1579                 out_be64(&priv2->spu_chnlcnt_RW, ch_counts[i]);
1580                 eieio();
1581         }
1582 }
1583
1584 static inline void restore_spu_lslr(struct spu_state *csa, struct spu *spu)
1585 {
1586         struct spu_priv2 __iomem *priv2 = spu->priv2;
1587
1588         /* Restore, Step 61:
1589          *     Restore the SPU_LSLR register from CSA.
1590          */
1591         out_be64(&priv2->spu_lslr_RW, csa->priv2.spu_lslr_RW);
1592         eieio();
1593 }
1594
1595 static inline void restore_spu_cfg(struct spu_state *csa, struct spu *spu)
1596 {
1597         struct spu_priv2 __iomem *priv2 = spu->priv2;
1598
1599         /* Restore, Step 62:
1600          *     Restore the SPU_Cfg register from CSA.
1601          */
1602         out_be64(&priv2->spu_cfg_RW, csa->priv2.spu_cfg_RW);
1603         eieio();
1604 }
1605
1606 static inline void restore_pm_trace(struct spu_state *csa, struct spu *spu)
1607 {
1608         /* Restore, Step 63:
1609          *     Restore PM_Trace_Tag_Wait_Mask from CSA.
1610          *     Not performed by this implementation.
1611          */
1612 }
1613
1614 static inline void restore_spu_npc(struct spu_state *csa, struct spu *spu)
1615 {
1616         struct spu_problem __iomem *prob = spu->problem;
1617
1618         /* Restore, Step 64:
1619          *     Restore SPU_NPC from CSA.
1620          */
1621         out_be32(&prob->spu_npc_RW, csa->prob.spu_npc_RW);
1622         eieio();
1623 }
1624
1625 static inline void restore_spu_mb(struct spu_state *csa, struct spu *spu)
1626 {
1627         struct spu_priv2 __iomem *priv2 = spu->priv2;
1628         int i;
1629
1630         /* Restore, Step 65:
1631          *     Restore MFC_RdSPU_MB from CSA.
1632          */
1633         out_be64(&priv2->spu_chnlcntptr_RW, 29UL);
1634         eieio();
1635         out_be64(&priv2->spu_chnlcnt_RW, csa->spu_chnlcnt_RW[29]);
1636         for (i = 0; i < 4; i++) {
1637                 out_be64(&priv2->spu_chnldata_RW, csa->spu_mailbox_data[i]);
1638         }
1639         eieio();
1640 }
1641
1642 static inline void check_ppu_mb_stat(struct spu_state *csa, struct spu *spu)
1643 {
1644         struct spu_problem __iomem *prob = spu->problem;
1645         u32 dummy = 0;
1646
1647         /* Restore, Step 66:
1648          *     If CSA.MB_Stat[P]=0 (mailbox empty) then
1649          *     read from the PPU_MB register.
1650          */
1651         if ((csa->prob.mb_stat_R & 0xFF) == 0) {
1652                 dummy = in_be32(&prob->pu_mb_R);
1653                 eieio();
1654         }
1655 }
1656
1657 static inline void check_ppuint_mb_stat(struct spu_state *csa, struct spu *spu)
1658 {
1659         struct spu_priv2 __iomem *priv2 = spu->priv2;
1660         u64 dummy = 0UL;
1661
1662         /* Restore, Step 66:
1663          *     If CSA.MB_Stat[I]=0 (mailbox empty) then
1664          *     read from the PPUINT_MB register.
1665          */
1666         if ((csa->prob.mb_stat_R & 0xFF0000) == 0) {
1667                 dummy = in_be64(&priv2->puint_mb_R);
1668                 eieio();
1669                 spu_int_stat_clear(spu, 2, CLASS2_ENABLE_MAILBOX_INTR);
1670                 eieio();
1671         }
1672 }
1673
1674 static inline void restore_mfc_sr1(struct spu_state *csa, struct spu *spu)
1675 {
1676         /* Restore, Step 69:
1677          *     Restore the MFC_SR1 register from CSA.
1678          */
1679         spu_mfc_sr1_set(spu, csa->priv1.mfc_sr1_RW);
1680         eieio();
1681 }
1682
1683 static inline void restore_other_spu_access(struct spu_state *csa,
1684                                             struct spu *spu)
1685 {
1686         /* Restore, Step 70:
1687          *     Restore other SPU mappings to this SPU. TBD.
1688          */
1689 }
1690
1691 static inline void restore_spu_runcntl(struct spu_state *csa, struct spu *spu)
1692 {
1693         struct spu_problem __iomem *prob = spu->problem;
1694
1695         /* Restore, Step 71:
1696          *     If CSA.SPU_Status[R]=1 then write
1697          *     SPU_RunCntl[R0R1]='01'.
1698          */
1699         if (csa->prob.spu_status_R & SPU_STATUS_RUNNING) {
1700                 out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_RUNNABLE);
1701                 eieio();
1702         }
1703 }
1704
1705 static inline void restore_mfc_cntl(struct spu_state *csa, struct spu *spu)
1706 {
1707         struct spu_priv2 __iomem *priv2 = spu->priv2;
1708
1709         /* Restore, Step 72:
1710          *    Restore the MFC_CNTL register for the CSA.
1711          */
1712         out_be64(&priv2->mfc_control_RW, csa->priv2.mfc_control_RW);
1713         eieio();
1714         /*
1715          * FIXME: this is to restart a DMA that we were processing
1716          *        before the save. better remember the fault information
1717          *        in the csa instead.
1718          */
1719         if ((csa->priv2.mfc_control_RW & MFC_CNTL_SUSPEND_DMA_QUEUE_MASK)) {
1720                 out_be64(&priv2->mfc_control_RW, MFC_CNTL_RESTART_DMA_COMMAND);
1721                 eieio();
1722         }
1723 }
1724
1725 static inline void enable_user_access(struct spu_state *csa, struct spu *spu)
1726 {
1727         /* Restore, Step 73:
1728          *     Enable user-space access (if provided) to this
1729          *     SPU by mapping the virtual pages assigned to
1730          *     the SPU memory-mapped I/O (MMIO) for problem
1731          *     state. TBD.
1732          */
1733 }
1734
1735 static inline void reset_switch_active(struct spu_state *csa, struct spu *spu)
1736 {
1737         /* Restore, Step 74:
1738          *     Reset the "context switch active" flag.
1739          */
1740         clear_bit(SPU_CONTEXT_SWITCH_ACTIVE, &spu->flags);
1741         mb();
1742 }
1743
1744 static inline void reenable_interrupts(struct spu_state *csa, struct spu *spu)
1745 {
1746         /* Restore, Step 75:
1747          *     Re-enable SPU interrupts.
1748          */
1749         spin_lock_irq(&spu->register_lock);
1750         spu_int_mask_set(spu, 0, csa->priv1.int_mask_class0_RW);
1751         spu_int_mask_set(spu, 1, csa->priv1.int_mask_class1_RW);
1752         spu_int_mask_set(spu, 2, csa->priv1.int_mask_class2_RW);
1753         spin_unlock_irq(&spu->register_lock);
1754 }
1755
1756 static int quiece_spu(struct spu_state *prev, struct spu *spu)
1757 {
1758         /*
1759          * Combined steps 2-18 of SPU context save sequence, which
1760          * quiesce the SPU state (disable SPU execution, MFC command
1761          * queues, decrementer, SPU interrupts, etc.).
1762          *
1763          * Returns      0 on success.
1764          *              2 if failed step 2.
1765          *              6 if failed step 6.
1766          */
1767
1768         if (check_spu_isolate(prev, spu)) {     /* Step 2. */
1769                 return 2;
1770         }
1771         disable_interrupts(prev, spu);          /* Step 3. */
1772         set_watchdog_timer(prev, spu);          /* Step 4. */
1773         inhibit_user_access(prev, spu);         /* Step 5. */
1774         if (check_spu_isolate(prev, spu)) {     /* Step 6. */
1775                 return 6;
1776         }
1777         set_switch_pending(prev, spu);          /* Step 7. */
1778         save_mfc_cntl(prev, spu);               /* Step 8. */
1779         save_spu_runcntl(prev, spu);            /* Step 9. */
1780         save_mfc_sr1(prev, spu);                /* Step 10. */
1781         save_spu_status(prev, spu);             /* Step 11. */
1782         save_mfc_decr(prev, spu);               /* Step 12. */
1783         halt_mfc_decr(prev, spu);               /* Step 13. */
1784         save_timebase(prev, spu);               /* Step 14. */
1785         remove_other_spu_access(prev, spu);     /* Step 15. */
1786         do_mfc_mssync(prev, spu);               /* Step 16. */
1787         issue_mfc_tlbie(prev, spu);             /* Step 17. */
1788         handle_pending_interrupts(prev, spu);   /* Step 18. */
1789
1790         return 0;
1791 }
1792
1793 static void save_csa(struct spu_state *prev, struct spu *spu)
1794 {
1795         /*
1796          * Combine steps 19-44 of SPU context save sequence, which
1797          * save regions of the privileged & problem state areas.
1798          */
1799
1800         save_mfc_queues(prev, spu);     /* Step 19. */
1801         save_ppu_querymask(prev, spu);  /* Step 20. */
1802         save_ppu_querytype(prev, spu);  /* Step 21. */
1803         save_ppu_tagstatus(prev, spu);  /* NEW.     */
1804         save_mfc_csr_tsq(prev, spu);    /* Step 22. */
1805         save_mfc_csr_cmd(prev, spu);    /* Step 23. */
1806         save_mfc_csr_ato(prev, spu);    /* Step 24. */
1807         save_mfc_tclass_id(prev, spu);  /* Step 25. */
1808         set_mfc_tclass_id(prev, spu);   /* Step 26. */
1809         purge_mfc_queue(prev, spu);     /* Step 27. */
1810         wait_purge_complete(prev, spu); /* Step 28. */
1811         setup_mfc_sr1(prev, spu);       /* Step 30. */
1812         save_spu_npc(prev, spu);        /* Step 31. */
1813         save_spu_privcntl(prev, spu);   /* Step 32. */
1814         reset_spu_privcntl(prev, spu);  /* Step 33. */
1815         save_spu_lslr(prev, spu);       /* Step 34. */
1816         reset_spu_lslr(prev, spu);      /* Step 35. */
1817         save_spu_cfg(prev, spu);        /* Step 36. */
1818         save_pm_trace(prev, spu);       /* Step 37. */
1819         save_mfc_rag(prev, spu);        /* Step 38. */
1820         save_ppu_mb_stat(prev, spu);    /* Step 39. */
1821         save_ppu_mb(prev, spu);         /* Step 40. */
1822         save_ppuint_mb(prev, spu);      /* Step 41. */
1823         save_ch_part1(prev, spu);       /* Step 42. */
1824         save_spu_mb(prev, spu);         /* Step 43. */
1825         save_mfc_cmd(prev, spu);        /* Step 44. */
1826         reset_ch(prev, spu);            /* Step 45. */
1827 }
1828
1829 static void save_lscsa(struct spu_state *prev, struct spu *spu)
1830 {
1831         /*
1832          * Perform steps 46-57 of SPU context save sequence,
1833          * which save regions of the local store and register
1834          * file.
1835          */
1836
1837         resume_mfc_queue(prev, spu);    /* Step 46. */
1838         setup_mfc_slbs(prev, spu);      /* Step 47. */
1839         set_switch_active(prev, spu);   /* Step 48. */
1840         enable_interrupts(prev, spu);   /* Step 49. */
1841         save_ls_16kb(prev, spu);        /* Step 50. */
1842         set_spu_npc(prev, spu);         /* Step 51. */
1843         set_signot1(prev, spu);         /* Step 52. */
1844         set_signot2(prev, spu);         /* Step 53. */
1845         send_save_code(prev, spu);      /* Step 54. */
1846         set_ppu_querymask(prev, spu);   /* Step 55. */
1847         wait_tag_complete(prev, spu);   /* Step 56. */
1848         wait_spu_stopped(prev, spu);    /* Step 57. */
1849 }
1850
1851 static void force_spu_isolate_exit(struct spu *spu)
1852 {
1853         struct spu_problem __iomem *prob = spu->problem;
1854         struct spu_priv2 __iomem *priv2 = spu->priv2;
1855
1856         /* Stop SPE execution and wait for completion. */
1857         out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_STOP);
1858         iobarrier_rw();
1859         POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) & SPU_STATUS_RUNNING);
1860
1861         /* Restart SPE master runcntl. */
1862         spu_mfc_sr1_set(spu, MFC_STATE1_MASTER_RUN_CONTROL_MASK);
1863         iobarrier_w();
1864
1865         /* Initiate isolate exit request and wait for completion. */
1866         out_be64(&priv2->spu_privcntl_RW, 4LL);
1867         iobarrier_w();
1868         out_be32(&prob->spu_runcntl_RW, 2);
1869         iobarrier_rw();
1870         POLL_WHILE_FALSE((in_be32(&prob->spu_status_R)
1871                                 & SPU_STATUS_STOPPED_BY_STOP));
1872
1873         /* Reset load request to normal. */
1874         out_be64(&priv2->spu_privcntl_RW, SPU_PRIVCNT_LOAD_REQUEST_NORMAL);
1875         iobarrier_w();
1876 }
1877
1878 /**
1879  * stop_spu_isolate
1880  *      Check SPU run-control state and force isolated
1881  *      exit function as necessary.
1882  */
1883 static void stop_spu_isolate(struct spu *spu)
1884 {
1885         struct spu_problem __iomem *prob = spu->problem;
1886
1887         if (in_be32(&prob->spu_status_R) & SPU_STATUS_ISOLATED_STATE) {
1888                 /* The SPU is in isolated state; the only way
1889                  * to get it out is to perform an isolated
1890                  * exit (clean) operation.
1891                  */
1892                 force_spu_isolate_exit(spu);
1893         }
1894 }
1895
1896 static void harvest(struct spu_state *prev, struct spu *spu)
1897 {
1898         /*
1899          * Perform steps 2-25 of SPU context restore sequence,
1900          * which resets an SPU either after a failed save, or
1901          * when using SPU for first time.
1902          */
1903
1904         disable_interrupts(prev, spu);          /* Step 2.  */
1905         inhibit_user_access(prev, spu);         /* Step 3.  */
1906         terminate_spu_app(prev, spu);           /* Step 4.  */
1907         set_switch_pending(prev, spu);          /* Step 5.  */
1908         stop_spu_isolate(spu);                  /* NEW.     */
1909         remove_other_spu_access(prev, spu);     /* Step 6.  */
1910         suspend_mfc_and_halt_decr(prev, spu);   /* Step 7.  */
1911         wait_suspend_mfc_complete(prev, spu);   /* Step 8.  */
1912         if (!suspend_spe(prev, spu))            /* Step 9.  */
1913                 clear_spu_status(prev, spu);    /* Step 10. */
1914         do_mfc_mssync(prev, spu);               /* Step 11. */
1915         issue_mfc_tlbie(prev, spu);             /* Step 12. */
1916         handle_pending_interrupts(prev, spu);   /* Step 13. */
1917         purge_mfc_queue(prev, spu);             /* Step 14. */
1918         wait_purge_complete(prev, spu);         /* Step 15. */
1919         reset_spu_privcntl(prev, spu);          /* Step 16. */
1920         reset_spu_lslr(prev, spu);              /* Step 17. */
1921         setup_mfc_sr1(prev, spu);               /* Step 18. */
1922         spu_invalidate_slbs(spu);               /* Step 19. */
1923         reset_ch_part1(prev, spu);              /* Step 20. */
1924         reset_ch_part2(prev, spu);              /* Step 21. */
1925         enable_interrupts(prev, spu);           /* Step 22. */
1926         set_switch_active(prev, spu);           /* Step 23. */
1927         set_mfc_tclass_id(prev, spu);           /* Step 24. */
1928         resume_mfc_queue(prev, spu);            /* Step 25. */
1929 }
1930
1931 static void restore_lscsa(struct spu_state *next, struct spu *spu)
1932 {
1933         /*
1934          * Perform steps 26-40 of SPU context restore sequence,
1935          * which restores regions of the local store and register
1936          * file.
1937          */
1938
1939         set_watchdog_timer(next, spu);          /* Step 26. */
1940         setup_spu_status_part1(next, spu);      /* Step 27. */
1941         setup_spu_status_part2(next, spu);      /* Step 28. */
1942         restore_mfc_rag(next, spu);             /* Step 29. */
1943         setup_mfc_slbs(next, spu);              /* Step 30. */
1944         set_spu_npc(next, spu);                 /* Step 31. */
1945         set_signot1(next, spu);                 /* Step 32. */
1946         set_signot2(next, spu);                 /* Step 33. */
1947         setup_decr(next, spu);                  /* Step 34. */
1948         setup_ppu_mb(next, spu);                /* Step 35. */
1949         setup_ppuint_mb(next, spu);             /* Step 36. */
1950         send_restore_code(next, spu);           /* Step 37. */
1951         set_ppu_querymask(next, spu);           /* Step 38. */
1952         wait_tag_complete(next, spu);           /* Step 39. */
1953         wait_spu_stopped(next, spu);            /* Step 40. */
1954 }
1955
1956 static void restore_csa(struct spu_state *next, struct spu *spu)
1957 {
1958         /*
1959          * Combine steps 41-76 of SPU context restore sequence, which
1960          * restore regions of the privileged & problem state areas.
1961          */
1962
1963         restore_spu_privcntl(next, spu);        /* Step 41. */
1964         restore_status_part1(next, spu);        /* Step 42. */
1965         restore_status_part2(next, spu);        /* Step 43. */
1966         restore_ls_16kb(next, spu);             /* Step 44. */
1967         wait_tag_complete(next, spu);           /* Step 45. */
1968         suspend_mfc(next, spu);                 /* Step 46. */
1969         wait_suspend_mfc_complete(next, spu);   /* Step 47. */
1970         issue_mfc_tlbie(next, spu);             /* Step 48. */
1971         clear_interrupts(next, spu);            /* Step 49. */
1972         restore_mfc_queues(next, spu);          /* Step 50. */
1973         restore_ppu_querymask(next, spu);       /* Step 51. */
1974         restore_ppu_querytype(next, spu);       /* Step 52. */
1975         restore_mfc_csr_tsq(next, spu);         /* Step 53. */
1976         restore_mfc_csr_cmd(next, spu);         /* Step 54. */
1977         restore_mfc_csr_ato(next, spu);         /* Step 55. */
1978         restore_mfc_tclass_id(next, spu);       /* Step 56. */
1979         set_llr_event(next, spu);               /* Step 57. */
1980         restore_decr_wrapped(next, spu);        /* Step 58. */
1981         restore_ch_part1(next, spu);            /* Step 59. */
1982         restore_ch_part2(next, spu);            /* Step 60. */
1983         restore_spu_lslr(next, spu);            /* Step 61. */
1984         restore_spu_cfg(next, spu);             /* Step 62. */
1985         restore_pm_trace(next, spu);            /* Step 63. */
1986         restore_spu_npc(next, spu);             /* Step 64. */
1987         restore_spu_mb(next, spu);              /* Step 65. */
1988         check_ppu_mb_stat(next, spu);           /* Step 66. */
1989         check_ppuint_mb_stat(next, spu);        /* Step 67. */
1990         spu_invalidate_slbs(spu);               /* Modified Step 68. */
1991         restore_mfc_sr1(next, spu);             /* Step 69. */
1992         restore_other_spu_access(next, spu);    /* Step 70. */
1993         restore_spu_runcntl(next, spu);         /* Step 71. */
1994         restore_mfc_cntl(next, spu);            /* Step 72. */
1995         enable_user_access(next, spu);          /* Step 73. */
1996         reset_switch_active(next, spu);         /* Step 74. */
1997         reenable_interrupts(next, spu);         /* Step 75. */
1998 }
1999
2000 static int __do_spu_save(struct spu_state *prev, struct spu *spu)
2001 {
2002         int rc;
2003
2004         /*
2005          * SPU context save can be broken into three phases:
2006          *
2007          *     (a) quiesce [steps 2-16].
2008          *     (b) save of CSA, performed by PPE [steps 17-42]
2009          *     (c) save of LSCSA, mostly performed by SPU [steps 43-52].
2010          *
2011          * Returns      0 on success.
2012          *              2,6 if failed to quiece SPU
2013          *              53 if SPU-side of save failed.
2014          */
2015
2016         rc = quiece_spu(prev, spu);             /* Steps 2-16. */
2017         switch (rc) {
2018         default:
2019         case 2:
2020         case 6:
2021                 harvest(prev, spu);
2022                 return rc;
2023                 break;
2024         case 0:
2025                 break;
2026         }
2027         save_csa(prev, spu);                    /* Steps 17-43. */
2028         save_lscsa(prev, spu);                  /* Steps 44-53. */
2029         return check_save_status(prev, spu);    /* Step 54.     */
2030 }
2031
2032 static int __do_spu_restore(struct spu_state *next, struct spu *spu)
2033 {
2034         int rc;
2035
2036         /*
2037          * SPU context restore can be broken into three phases:
2038          *
2039          *    (a) harvest (or reset) SPU [steps 2-24].
2040          *    (b) restore LSCSA [steps 25-40], mostly performed by SPU.
2041          *    (c) restore CSA [steps 41-76], performed by PPE.
2042          *
2043          * The 'harvest' step is not performed here, but rather
2044          * as needed below.
2045          */
2046
2047         restore_lscsa(next, spu);               /* Steps 24-39. */
2048         rc = check_restore_status(next, spu);   /* Step 40.     */
2049         switch (rc) {
2050         default:
2051                 /* Failed. Return now. */
2052                 return rc;
2053                 break;
2054         case 0:
2055                 /* Fall through to next step. */
2056                 break;
2057         }
2058         restore_csa(next, spu);
2059
2060         return 0;
2061 }
2062
2063 /**
2064  * spu_save - SPU context save, with locking.
2065  * @prev: pointer to SPU context save area, to be saved.
2066  * @spu: pointer to SPU iomem structure.
2067  *
2068  * Acquire locks, perform the save operation then return.
2069  */
2070 int spu_save(struct spu_state *prev, struct spu *spu)
2071 {
2072         int rc;
2073
2074         acquire_spu_lock(spu);          /* Step 1.     */
2075         prev->dar = spu->dar;
2076         prev->dsisr = spu->dsisr;
2077         spu->dar = 0;
2078         spu->dsisr = 0;
2079         rc = __do_spu_save(prev, spu);  /* Steps 2-53. */
2080         release_spu_lock(spu);
2081         if (rc != 0 && rc != 2 && rc != 6) {
2082                 panic("%s failed on SPU[%d], rc=%d.\n",
2083                       __func__, spu->number, rc);
2084         }
2085         return 0;
2086 }
2087 EXPORT_SYMBOL_GPL(spu_save);
2088
2089 /**
2090  * spu_restore - SPU context restore, with harvest and locking.
2091  * @new: pointer to SPU context save area, to be restored.
2092  * @spu: pointer to SPU iomem structure.
2093  *
2094  * Perform harvest + restore, as we may not be coming
2095  * from a previous successful save operation, and the
2096  * hardware state is unknown.
2097  */
2098 int spu_restore(struct spu_state *new, struct spu *spu)
2099 {
2100         int rc;
2101
2102         acquire_spu_lock(spu);
2103         harvest(NULL, spu);
2104         spu->slb_replace = 0;
2105         new->dar = 0;
2106         new->dsisr = 0;
2107         spu->class_0_pending = 0;
2108         rc = __do_spu_restore(new, spu);
2109         release_spu_lock(spu);
2110         if (rc) {
2111                 panic("%s failed on SPU[%d] rc=%d.\n",
2112                        __func__, spu->number, rc);
2113         }
2114         return rc;
2115 }
2116 EXPORT_SYMBOL_GPL(spu_restore);
2117
2118 static void init_prob(struct spu_state *csa)
2119 {
2120         csa->spu_chnlcnt_RW[9] = 1;
2121         csa->spu_chnlcnt_RW[21] = 16;
2122         csa->spu_chnlcnt_RW[23] = 1;
2123         csa->spu_chnlcnt_RW[28] = 1;
2124         csa->spu_chnlcnt_RW[30] = 1;
2125         csa->prob.spu_runcntl_RW = SPU_RUNCNTL_STOP;
2126         csa->prob.mb_stat_R = 0x000400;
2127 }
2128
2129 static void init_priv1(struct spu_state *csa)
2130 {
2131         /* Enable decode, relocate, tlbie response, master runcntl. */
2132         csa->priv1.mfc_sr1_RW = MFC_STATE1_LOCAL_STORAGE_DECODE_MASK |
2133             MFC_STATE1_MASTER_RUN_CONTROL_MASK |
2134             MFC_STATE1_PROBLEM_STATE_MASK |
2135             MFC_STATE1_RELOCATE_MASK | MFC_STATE1_BUS_TLBIE_MASK;
2136
2137         /* Enable OS-specific set of interrupts. */
2138         csa->priv1.int_mask_class0_RW = CLASS0_ENABLE_DMA_ALIGNMENT_INTR |
2139             CLASS0_ENABLE_INVALID_DMA_COMMAND_INTR |
2140             CLASS0_ENABLE_SPU_ERROR_INTR;
2141         csa->priv1.int_mask_class1_RW = CLASS1_ENABLE_SEGMENT_FAULT_INTR |
2142             CLASS1_ENABLE_STORAGE_FAULT_INTR;
2143         csa->priv1.int_mask_class2_RW = CLASS2_ENABLE_SPU_STOP_INTR |
2144             CLASS2_ENABLE_SPU_HALT_INTR |
2145             CLASS2_ENABLE_SPU_DMA_TAG_GROUP_COMPLETE_INTR;
2146 }
2147
2148 static void init_priv2(struct spu_state *csa)
2149 {
2150         csa->priv2.spu_lslr_RW = LS_ADDR_MASK;
2151         csa->priv2.mfc_control_RW = MFC_CNTL_RESUME_DMA_QUEUE |
2152             MFC_CNTL_NORMAL_DMA_QUEUE_OPERATION |
2153             MFC_CNTL_DMA_QUEUES_EMPTY_MASK;
2154 }
2155
2156 /**
2157  * spu_alloc_csa - allocate and initialize an SPU context save area.
2158  *
2159  * Allocate and initialize the contents of an SPU context save area.
2160  * This includes enabling address translation, interrupt masks, etc.,
2161  * as appropriate for the given OS environment.
2162  *
2163  * Note that storage for the 'lscsa' is allocated separately,
2164  * as it is by far the largest of the context save regions,
2165  * and may need to be pinned or otherwise specially aligned.
2166  */
2167 int spu_init_csa(struct spu_state *csa)
2168 {
2169         int rc;
2170
2171         if (!csa)
2172                 return -EINVAL;
2173         memset(csa, 0, sizeof(struct spu_state));
2174
2175         rc = spu_alloc_lscsa(csa);
2176         if (rc)
2177                 return rc;
2178
2179         spin_lock_init(&csa->register_lock);
2180
2181         init_prob(csa);
2182         init_priv1(csa);
2183         init_priv2(csa);
2184
2185         return 0;
2186 }
2187 EXPORT_SYMBOL_GPL(spu_init_csa);
2188
2189 void spu_fini_csa(struct spu_state *csa)
2190 {
2191         spu_free_lscsa(csa);
2192 }
2193 EXPORT_SYMBOL_GPL(spu_fini_csa);