Merge git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/v4l-dvb
[linux-2.6] / drivers / i2c / busses / i2c-bfin-twi.c
1 /*
2  * Blackfin On-Chip Two Wire Interface Driver
3  *
4  * Copyright 2005-2007 Analog Devices Inc.
5  *
6  * Enter bugs at http://blackfin.uclinux.org/
7  *
8  * Licensed under the GPL-2 or later.
9  */
10
11 #include <linux/module.h>
12 #include <linux/kernel.h>
13 #include <linux/init.h>
14 #include <linux/i2c.h>
15 #include <linux/mm.h>
16 #include <linux/timer.h>
17 #include <linux/spinlock.h>
18 #include <linux/completion.h>
19 #include <linux/interrupt.h>
20 #include <linux/platform_device.h>
21
22 #include <asm/blackfin.h>
23 #include <asm/portmux.h>
24 #include <asm/irq.h>
25
26 #define POLL_TIMEOUT       (2 * HZ)
27
28 /* SMBus mode*/
29 #define TWI_I2C_MODE_STANDARD           1
30 #define TWI_I2C_MODE_STANDARDSUB        2
31 #define TWI_I2C_MODE_COMBINED           3
32 #define TWI_I2C_MODE_REPEAT             4
33
34 struct bfin_twi_iface {
35         int                     irq;
36         spinlock_t              lock;
37         char                    read_write;
38         u8                      command;
39         u8                      *transPtr;
40         int                     readNum;
41         int                     writeNum;
42         int                     cur_mode;
43         int                     manual_stop;
44         int                     result;
45         int                     timeout_count;
46         struct timer_list       timeout_timer;
47         struct i2c_adapter      adap;
48         struct completion       complete;
49         struct i2c_msg          *pmsg;
50         int                     msg_num;
51         int                     cur_msg;
52         u16                     saved_clkdiv;
53         u16                     saved_control;
54         void __iomem            *regs_base;
55 };
56
57
58 #define DEFINE_TWI_REG(reg, off) \
59 static inline u16 read_##reg(struct bfin_twi_iface *iface) \
60         { return bfin_read16(iface->regs_base + (off)); } \
61 static inline void write_##reg(struct bfin_twi_iface *iface, u16 v) \
62         { bfin_write16(iface->regs_base + (off), v); }
63
64 DEFINE_TWI_REG(CLKDIV, 0x00)
65 DEFINE_TWI_REG(CONTROL, 0x04)
66 DEFINE_TWI_REG(SLAVE_CTL, 0x08)
67 DEFINE_TWI_REG(SLAVE_STAT, 0x0C)
68 DEFINE_TWI_REG(SLAVE_ADDR, 0x10)
69 DEFINE_TWI_REG(MASTER_CTL, 0x14)
70 DEFINE_TWI_REG(MASTER_STAT, 0x18)
71 DEFINE_TWI_REG(MASTER_ADDR, 0x1C)
72 DEFINE_TWI_REG(INT_STAT, 0x20)
73 DEFINE_TWI_REG(INT_MASK, 0x24)
74 DEFINE_TWI_REG(FIFO_CTL, 0x28)
75 DEFINE_TWI_REG(FIFO_STAT, 0x2C)
76 DEFINE_TWI_REG(XMT_DATA8, 0x80)
77 DEFINE_TWI_REG(XMT_DATA16, 0x84)
78 DEFINE_TWI_REG(RCV_DATA8, 0x88)
79 DEFINE_TWI_REG(RCV_DATA16, 0x8C)
80
81 static const u16 pin_req[2][3] = {
82         {P_TWI0_SCL, P_TWI0_SDA, 0},
83         {P_TWI1_SCL, P_TWI1_SDA, 0},
84 };
85
86 static void bfin_twi_handle_interrupt(struct bfin_twi_iface *iface)
87 {
88         unsigned short twi_int_status = read_INT_STAT(iface);
89         unsigned short mast_stat = read_MASTER_STAT(iface);
90
91         if (twi_int_status & XMTSERV) {
92                 /* Transmit next data */
93                 if (iface->writeNum > 0) {
94                         write_XMT_DATA8(iface, *(iface->transPtr++));
95                         iface->writeNum--;
96                 }
97                 /* start receive immediately after complete sending in
98                  * combine mode.
99                  */
100                 else if (iface->cur_mode == TWI_I2C_MODE_COMBINED)
101                         write_MASTER_CTL(iface,
102                                 read_MASTER_CTL(iface) | MDIR | RSTART);
103                 else if (iface->manual_stop)
104                         write_MASTER_CTL(iface,
105                                 read_MASTER_CTL(iface) | STOP);
106                 else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
107                                 iface->cur_msg+1 < iface->msg_num)
108                         write_MASTER_CTL(iface,
109                                 read_MASTER_CTL(iface) | RSTART);
110                 SSYNC();
111                 /* Clear status */
112                 write_INT_STAT(iface, XMTSERV);
113                 SSYNC();
114         }
115         if (twi_int_status & RCVSERV) {
116                 if (iface->readNum > 0) {
117                         /* Receive next data */
118                         *(iface->transPtr) = read_RCV_DATA8(iface);
119                         if (iface->cur_mode == TWI_I2C_MODE_COMBINED) {
120                                 /* Change combine mode into sub mode after
121                                  * read first data.
122                                  */
123                                 iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
124                                 /* Get read number from first byte in block
125                                  * combine mode.
126                                  */
127                                 if (iface->readNum == 1 && iface->manual_stop)
128                                         iface->readNum = *iface->transPtr + 1;
129                         }
130                         iface->transPtr++;
131                         iface->readNum--;
132                 } else if (iface->manual_stop) {
133                         write_MASTER_CTL(iface,
134                                 read_MASTER_CTL(iface) | STOP);
135                         SSYNC();
136                 } else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
137                                 iface->cur_msg+1 < iface->msg_num) {
138                         write_MASTER_CTL(iface,
139                                 read_MASTER_CTL(iface) | RSTART);
140                         SSYNC();
141                 }
142                 /* Clear interrupt source */
143                 write_INT_STAT(iface, RCVSERV);
144                 SSYNC();
145         }
146         if (twi_int_status & MERR) {
147                 write_INT_STAT(iface, MERR);
148                 write_INT_MASK(iface, 0);
149                 write_MASTER_STAT(iface, 0x3e);
150                 write_MASTER_CTL(iface, 0);
151                 SSYNC();
152                 iface->result = -EIO;
153                 /* if both err and complete int stats are set, return proper
154                  * results.
155                  */
156                 if (twi_int_status & MCOMP) {
157                         write_INT_STAT(iface, MCOMP);
158                         write_INT_MASK(iface, 0);
159                         write_MASTER_CTL(iface, 0);
160                         SSYNC();
161                         /* If it is a quick transfer, only address bug no data,
162                          * not an err, return 1.
163                          */
164                         if (iface->writeNum == 0 && (mast_stat & BUFRDERR))
165                                 iface->result = 1;
166                         /* If address not acknowledged return -1,
167                          * else return 0.
168                          */
169                         else if (!(mast_stat & ANAK))
170                                 iface->result = 0;
171                 }
172                 complete(&iface->complete);
173                 return;
174         }
175         if (twi_int_status & MCOMP) {
176                 write_INT_STAT(iface, MCOMP);
177                 SSYNC();
178                 if (iface->cur_mode == TWI_I2C_MODE_COMBINED) {
179                         if (iface->readNum == 0) {
180                                 /* set the read number to 1 and ask for manual
181                                  * stop in block combine mode
182                                  */
183                                 iface->readNum = 1;
184                                 iface->manual_stop = 1;
185                                 write_MASTER_CTL(iface,
186                                         read_MASTER_CTL(iface) | (0xff << 6));
187                         } else {
188                                 /* set the readd number in other
189                                  * combine mode.
190                                  */
191                                 write_MASTER_CTL(iface,
192                                         (read_MASTER_CTL(iface) &
193                                         (~(0xff << 6))) |
194                                         (iface->readNum << 6));
195                         }
196                         /* remove restart bit and enable master receive */
197                         write_MASTER_CTL(iface,
198                                 read_MASTER_CTL(iface) & ~RSTART);
199                         write_MASTER_CTL(iface,
200                                 read_MASTER_CTL(iface) | MEN | MDIR);
201                         SSYNC();
202                 } else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
203                                 iface->cur_msg+1 < iface->msg_num) {
204                         iface->cur_msg++;
205                         iface->transPtr = iface->pmsg[iface->cur_msg].buf;
206                         iface->writeNum = iface->readNum =
207                                 iface->pmsg[iface->cur_msg].len;
208                         /* Set Transmit device address */
209                         write_MASTER_ADDR(iface,
210                                 iface->pmsg[iface->cur_msg].addr);
211                         if (iface->pmsg[iface->cur_msg].flags & I2C_M_RD)
212                                 iface->read_write = I2C_SMBUS_READ;
213                         else {
214                                 iface->read_write = I2C_SMBUS_WRITE;
215                                 /* Transmit first data */
216                                 if (iface->writeNum > 0) {
217                                         write_XMT_DATA8(iface,
218                                                 *(iface->transPtr++));
219                                         iface->writeNum--;
220                                         SSYNC();
221                                 }
222                         }
223
224                         if (iface->pmsg[iface->cur_msg].len <= 255)
225                                 write_MASTER_CTL(iface,
226                                 iface->pmsg[iface->cur_msg].len << 6);
227                         else {
228                                 write_MASTER_CTL(iface, 0xff << 6);
229                                 iface->manual_stop = 1;
230                         }
231                         /* remove restart bit and enable master receive */
232                         write_MASTER_CTL(iface,
233                                 read_MASTER_CTL(iface) & ~RSTART);
234                         write_MASTER_CTL(iface, read_MASTER_CTL(iface) |
235                                 MEN | ((iface->read_write == I2C_SMBUS_READ) ?
236                                 MDIR : 0));
237                         SSYNC();
238                 } else {
239                         iface->result = 1;
240                         write_INT_MASK(iface, 0);
241                         write_MASTER_CTL(iface, 0);
242                         SSYNC();
243                         complete(&iface->complete);
244                 }
245         }
246 }
247
248 /* Interrupt handler */
249 static irqreturn_t bfin_twi_interrupt_entry(int irq, void *dev_id)
250 {
251         struct bfin_twi_iface *iface = dev_id;
252         unsigned long flags;
253
254         spin_lock_irqsave(&iface->lock, flags);
255         del_timer(&iface->timeout_timer);
256         bfin_twi_handle_interrupt(iface);
257         spin_unlock_irqrestore(&iface->lock, flags);
258         return IRQ_HANDLED;
259 }
260
261 static void bfin_twi_timeout(unsigned long data)
262 {
263         struct bfin_twi_iface *iface = (struct bfin_twi_iface *)data;
264         unsigned long flags;
265
266         spin_lock_irqsave(&iface->lock, flags);
267         bfin_twi_handle_interrupt(iface);
268         if (iface->result == 0) {
269                 iface->timeout_count--;
270                 if (iface->timeout_count > 0) {
271                         iface->timeout_timer.expires = jiffies + POLL_TIMEOUT;
272                         add_timer(&iface->timeout_timer);
273                 } else {
274                         iface->result = -1;
275                         complete(&iface->complete);
276                 }
277         }
278         spin_unlock_irqrestore(&iface->lock, flags);
279 }
280
281 /*
282  * Generic i2c master transfer entrypoint
283  */
284 static int bfin_twi_master_xfer(struct i2c_adapter *adap,
285                                 struct i2c_msg *msgs, int num)
286 {
287         struct bfin_twi_iface *iface = adap->algo_data;
288         struct i2c_msg *pmsg;
289         int rc = 0;
290
291         if (!(read_CONTROL(iface) & TWI_ENA))
292                 return -ENXIO;
293
294         while (read_MASTER_STAT(iface) & BUSBUSY)
295                 yield();
296
297         iface->pmsg = msgs;
298         iface->msg_num = num;
299         iface->cur_msg = 0;
300
301         pmsg = &msgs[0];
302         if (pmsg->flags & I2C_M_TEN) {
303                 dev_err(&adap->dev, "10 bits addr not supported!\n");
304                 return -EINVAL;
305         }
306
307         iface->cur_mode = TWI_I2C_MODE_REPEAT;
308         iface->manual_stop = 0;
309         iface->transPtr = pmsg->buf;
310         iface->writeNum = iface->readNum = pmsg->len;
311         iface->result = 0;
312         iface->timeout_count = 10;
313         init_completion(&(iface->complete));
314         /* Set Transmit device address */
315         write_MASTER_ADDR(iface, pmsg->addr);
316
317         /* FIFO Initiation. Data in FIFO should be
318          *  discarded before start a new operation.
319          */
320         write_FIFO_CTL(iface, 0x3);
321         SSYNC();
322         write_FIFO_CTL(iface, 0);
323         SSYNC();
324
325         if (pmsg->flags & I2C_M_RD)
326                 iface->read_write = I2C_SMBUS_READ;
327         else {
328                 iface->read_write = I2C_SMBUS_WRITE;
329                 /* Transmit first data */
330                 if (iface->writeNum > 0) {
331                         write_XMT_DATA8(iface, *(iface->transPtr++));
332                         iface->writeNum--;
333                         SSYNC();
334                 }
335         }
336
337         /* clear int stat */
338         write_INT_STAT(iface, MERR | MCOMP | XMTSERV | RCVSERV);
339
340         /* Interrupt mask . Enable XMT, RCV interrupt */
341         write_INT_MASK(iface, MCOMP | MERR | RCVSERV | XMTSERV);
342         SSYNC();
343
344         if (pmsg->len <= 255)
345                 write_MASTER_CTL(iface, pmsg->len << 6);
346         else {
347                 write_MASTER_CTL(iface, 0xff << 6);
348                 iface->manual_stop = 1;
349         }
350
351         iface->timeout_timer.expires = jiffies + POLL_TIMEOUT;
352         add_timer(&iface->timeout_timer);
353
354         /* Master enable */
355         write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
356                 ((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) |
357                 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ > 100) ? FAST : 0));
358         SSYNC();
359
360         wait_for_completion(&iface->complete);
361
362         rc = iface->result;
363
364         if (rc == 1)
365                 return num;
366         else
367                 return rc;
368 }
369
370 /*
371  * SMBus type transfer entrypoint
372  */
373
374 int bfin_twi_smbus_xfer(struct i2c_adapter *adap, u16 addr,
375                         unsigned short flags, char read_write,
376                         u8 command, int size, union i2c_smbus_data *data)
377 {
378         struct bfin_twi_iface *iface = adap->algo_data;
379         int rc = 0;
380
381         if (!(read_CONTROL(iface) & TWI_ENA))
382                 return -ENXIO;
383
384         while (read_MASTER_STAT(iface) & BUSBUSY)
385                 yield();
386
387         iface->writeNum = 0;
388         iface->readNum = 0;
389
390         /* Prepare datas & select mode */
391         switch (size) {
392         case I2C_SMBUS_QUICK:
393                 iface->transPtr = NULL;
394                 iface->cur_mode = TWI_I2C_MODE_STANDARD;
395                 break;
396         case I2C_SMBUS_BYTE:
397                 if (data == NULL)
398                         iface->transPtr = NULL;
399                 else {
400                         if (read_write == I2C_SMBUS_READ)
401                                 iface->readNum = 1;
402                         else
403                                 iface->writeNum = 1;
404                         iface->transPtr = &data->byte;
405                 }
406                 iface->cur_mode = TWI_I2C_MODE_STANDARD;
407                 break;
408         case I2C_SMBUS_BYTE_DATA:
409                 if (read_write == I2C_SMBUS_READ) {
410                         iface->readNum = 1;
411                         iface->cur_mode = TWI_I2C_MODE_COMBINED;
412                 } else {
413                         iface->writeNum = 1;
414                         iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
415                 }
416                 iface->transPtr = &data->byte;
417                 break;
418         case I2C_SMBUS_WORD_DATA:
419                 if (read_write == I2C_SMBUS_READ) {
420                         iface->readNum = 2;
421                         iface->cur_mode = TWI_I2C_MODE_COMBINED;
422                 } else {
423                         iface->writeNum = 2;
424                         iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
425                 }
426                 iface->transPtr = (u8 *)&data->word;
427                 break;
428         case I2C_SMBUS_PROC_CALL:
429                 iface->writeNum = 2;
430                 iface->readNum = 2;
431                 iface->cur_mode = TWI_I2C_MODE_COMBINED;
432                 iface->transPtr = (u8 *)&data->word;
433                 break;
434         case I2C_SMBUS_BLOCK_DATA:
435                 if (read_write == I2C_SMBUS_READ) {
436                         iface->readNum = 0;
437                         iface->cur_mode = TWI_I2C_MODE_COMBINED;
438                 } else {
439                         iface->writeNum = data->block[0] + 1;
440                         iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
441                 }
442                 iface->transPtr = data->block;
443                 break;
444         default:
445                 return -1;
446         }
447
448         iface->result = 0;
449         iface->manual_stop = 0;
450         iface->read_write = read_write;
451         iface->command = command;
452         iface->timeout_count = 10;
453         init_completion(&(iface->complete));
454
455         /* FIFO Initiation. Data in FIFO should be discarded before
456          * start a new operation.
457          */
458         write_FIFO_CTL(iface, 0x3);
459         SSYNC();
460         write_FIFO_CTL(iface, 0);
461
462         /* clear int stat */
463         write_INT_STAT(iface, MERR | MCOMP | XMTSERV | RCVSERV);
464
465         /* Set Transmit device address */
466         write_MASTER_ADDR(iface, addr);
467         SSYNC();
468
469         iface->timeout_timer.expires = jiffies + POLL_TIMEOUT;
470         add_timer(&iface->timeout_timer);
471
472         switch (iface->cur_mode) {
473         case TWI_I2C_MODE_STANDARDSUB:
474                 write_XMT_DATA8(iface, iface->command);
475                 write_INT_MASK(iface, MCOMP | MERR |
476                         ((iface->read_write == I2C_SMBUS_READ) ?
477                         RCVSERV : XMTSERV));
478                 SSYNC();
479
480                 if (iface->writeNum + 1 <= 255)
481                         write_MASTER_CTL(iface, (iface->writeNum + 1) << 6);
482                 else {
483                         write_MASTER_CTL(iface, 0xff << 6);
484                         iface->manual_stop = 1;
485                 }
486                 /* Master enable */
487                 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
488                         ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ>100) ? FAST : 0));
489                 break;
490         case TWI_I2C_MODE_COMBINED:
491                 write_XMT_DATA8(iface, iface->command);
492                 write_INT_MASK(iface, MCOMP | MERR | RCVSERV | XMTSERV);
493                 SSYNC();
494
495                 if (iface->writeNum > 0)
496                         write_MASTER_CTL(iface, (iface->writeNum + 1) << 6);
497                 else
498                         write_MASTER_CTL(iface, 0x1 << 6);
499                 /* Master enable */
500                 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
501                         ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ>100) ? FAST : 0));
502                 break;
503         default:
504                 write_MASTER_CTL(iface, 0);
505                 if (size != I2C_SMBUS_QUICK) {
506                         /* Don't access xmit data register when this is a
507                          * read operation.
508                          */
509                         if (iface->read_write != I2C_SMBUS_READ) {
510                                 if (iface->writeNum > 0) {
511                                         write_XMT_DATA8(iface,
512                                                 *(iface->transPtr++));
513                                         if (iface->writeNum <= 255)
514                                                 write_MASTER_CTL(iface,
515                                                         iface->writeNum << 6);
516                                         else {
517                                                 write_MASTER_CTL(iface,
518                                                         0xff << 6);
519                                                 iface->manual_stop = 1;
520                                         }
521                                         iface->writeNum--;
522                                 } else {
523                                         write_XMT_DATA8(iface, iface->command);
524                                         write_MASTER_CTL(iface, 1 << 6);
525                                 }
526                         } else {
527                                 if (iface->readNum > 0 && iface->readNum <= 255)
528                                         write_MASTER_CTL(iface,
529                                                 iface->readNum << 6);
530                                 else if (iface->readNum > 255) {
531                                         write_MASTER_CTL(iface, 0xff << 6);
532                                         iface->manual_stop = 1;
533                                 } else {
534                                         del_timer(&iface->timeout_timer);
535                                         break;
536                                 }
537                         }
538                 }
539                 write_INT_MASK(iface, MCOMP | MERR |
540                         ((iface->read_write == I2C_SMBUS_READ) ?
541                         RCVSERV : XMTSERV));
542                 SSYNC();
543
544                 /* Master enable */
545                 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
546                         ((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) |
547                         ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ > 100) ? FAST : 0));
548                 break;
549         }
550         SSYNC();
551
552         wait_for_completion(&iface->complete);
553
554         rc = (iface->result >= 0) ? 0 : -1;
555
556         return rc;
557 }
558
559 /*
560  * Return what the adapter supports
561  */
562 static u32 bfin_twi_functionality(struct i2c_adapter *adap)
563 {
564         return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
565                I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
566                I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_PROC_CALL |
567                I2C_FUNC_I2C;
568 }
569
570 static struct i2c_algorithm bfin_twi_algorithm = {
571         .master_xfer   = bfin_twi_master_xfer,
572         .smbus_xfer    = bfin_twi_smbus_xfer,
573         .functionality = bfin_twi_functionality,
574 };
575
576 static int i2c_bfin_twi_suspend(struct platform_device *pdev, pm_message_t state)
577 {
578         struct bfin_twi_iface *iface = platform_get_drvdata(pdev);
579
580         iface->saved_clkdiv = read_CLKDIV(iface);
581         iface->saved_control = read_CONTROL(iface);
582
583         free_irq(iface->irq, iface);
584
585         /* Disable TWI */
586         write_CONTROL(iface, iface->saved_control & ~TWI_ENA);
587
588         return 0;
589 }
590
591 static int i2c_bfin_twi_resume(struct platform_device *pdev)
592 {
593         struct bfin_twi_iface *iface = platform_get_drvdata(pdev);
594
595         int rc = request_irq(iface->irq, bfin_twi_interrupt_entry,
596                 IRQF_DISABLED, pdev->name, iface);
597         if (rc) {
598                 dev_err(&pdev->dev, "Can't get IRQ %d !\n", iface->irq);
599                 return -ENODEV;
600         }
601
602         /* Resume TWI interface clock as specified */
603         write_CLKDIV(iface, iface->saved_clkdiv);
604
605         /* Resume TWI */
606         write_CONTROL(iface, iface->saved_control);
607
608         return 0;
609 }
610
611 static int i2c_bfin_twi_probe(struct platform_device *pdev)
612 {
613         struct bfin_twi_iface *iface;
614         struct i2c_adapter *p_adap;
615         struct resource *res;
616         int rc;
617
618         iface = kzalloc(sizeof(struct bfin_twi_iface), GFP_KERNEL);
619         if (!iface) {
620                 dev_err(&pdev->dev, "Cannot allocate memory\n");
621                 rc = -ENOMEM;
622                 goto out_error_nomem;
623         }
624
625         spin_lock_init(&(iface->lock));
626
627         /* Find and map our resources */
628         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
629         if (res == NULL) {
630                 dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
631                 rc = -ENOENT;
632                 goto out_error_get_res;
633         }
634
635         iface->regs_base = ioremap(res->start, res->end - res->start + 1);
636         if (iface->regs_base == NULL) {
637                 dev_err(&pdev->dev, "Cannot map IO\n");
638                 rc = -ENXIO;
639                 goto out_error_ioremap;
640         }
641
642         iface->irq = platform_get_irq(pdev, 0);
643         if (iface->irq < 0) {
644                 dev_err(&pdev->dev, "No IRQ specified\n");
645                 rc = -ENOENT;
646                 goto out_error_no_irq;
647         }
648
649         init_timer(&(iface->timeout_timer));
650         iface->timeout_timer.function = bfin_twi_timeout;
651         iface->timeout_timer.data = (unsigned long)iface;
652
653         p_adap = &iface->adap;
654         p_adap->id = I2C_HW_BLACKFIN;
655         p_adap->nr = pdev->id;
656         strlcpy(p_adap->name, pdev->name, sizeof(p_adap->name));
657         p_adap->algo = &bfin_twi_algorithm;
658         p_adap->algo_data = iface;
659         p_adap->class = I2C_CLASS_ALL;
660         p_adap->dev.parent = &pdev->dev;
661
662         rc = peripheral_request_list(pin_req[pdev->id], "i2c-bfin-twi");
663         if (rc) {
664                 dev_err(&pdev->dev, "Can't setup pin mux!\n");
665                 goto out_error_pin_mux;
666         }
667
668         rc = request_irq(iface->irq, bfin_twi_interrupt_entry,
669                 IRQF_DISABLED, pdev->name, iface);
670         if (rc) {
671                 dev_err(&pdev->dev, "Can't get IRQ %d !\n", iface->irq);
672                 rc = -ENODEV;
673                 goto out_error_req_irq;
674         }
675
676         /* Set TWI internal clock as 10MHz */
677         write_CONTROL(iface, ((get_sclk() / 1024 / 1024 + 5) / 10) & 0x7F);
678
679         /* Set Twi interface clock as specified */
680         write_CLKDIV(iface, ((5*1024 / CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ)
681                         << 8) | ((5*1024 / CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ)
682                         & 0xFF));
683
684         /* Enable TWI */
685         write_CONTROL(iface, read_CONTROL(iface) | TWI_ENA);
686         SSYNC();
687
688         rc = i2c_add_numbered_adapter(p_adap);
689         if (rc < 0) {
690                 dev_err(&pdev->dev, "Can't add i2c adapter!\n");
691                 goto out_error_add_adapter;
692         }
693
694         platform_set_drvdata(pdev, iface);
695
696         dev_info(&pdev->dev, "Blackfin BF5xx on-chip I2C TWI Contoller, "
697                 "regs_base@%p\n", iface->regs_base);
698
699         return 0;
700
701 out_error_add_adapter:
702         free_irq(iface->irq, iface);
703 out_error_req_irq:
704 out_error_no_irq:
705         peripheral_free_list(pin_req[pdev->id]);
706 out_error_pin_mux:
707         iounmap(iface->regs_base);
708 out_error_ioremap:
709 out_error_get_res:
710         kfree(iface);
711 out_error_nomem:
712         return rc;
713 }
714
715 static int i2c_bfin_twi_remove(struct platform_device *pdev)
716 {
717         struct bfin_twi_iface *iface = platform_get_drvdata(pdev);
718
719         platform_set_drvdata(pdev, NULL);
720
721         i2c_del_adapter(&(iface->adap));
722         free_irq(iface->irq, iface);
723         peripheral_free_list(pin_req[pdev->id]);
724         iounmap(iface->regs_base);
725         kfree(iface);
726
727         return 0;
728 }
729
730 static struct platform_driver i2c_bfin_twi_driver = {
731         .probe          = i2c_bfin_twi_probe,
732         .remove         = i2c_bfin_twi_remove,
733         .suspend        = i2c_bfin_twi_suspend,
734         .resume         = i2c_bfin_twi_resume,
735         .driver         = {
736                 .name   = "i2c-bfin-twi",
737                 .owner  = THIS_MODULE,
738         },
739 };
740
741 static int __init i2c_bfin_twi_init(void)
742 {
743         return platform_driver_register(&i2c_bfin_twi_driver);
744 }
745
746 static void __exit i2c_bfin_twi_exit(void)
747 {
748         platform_driver_unregister(&i2c_bfin_twi_driver);
749 }
750
751 module_init(i2c_bfin_twi_init);
752 module_exit(i2c_bfin_twi_exit);
753
754 MODULE_AUTHOR("Bryan Wu, Sonic Zhang");
755 MODULE_DESCRIPTION("Blackfin BF5xx on-chip I2C TWI Contoller Driver");
756 MODULE_LICENSE("GPL");
757 MODULE_ALIAS("platform:i2c-bfin-twi");