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   1 /*
   2  *  linux/drivers/video/kyro/STG4000InitDevice.c
   3  *
   4  *  Copyright (C) 2000 Imagination Technologies Ltd
   5  *  Copyright (C) 2002 STMicroelectronics
   6  *
   7  * This file is subject to the terms and conditions of the GNU General Public
   8  * License.  See the file COPYING in the main directory of this archive
   9  * for more details.
  10  */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/errno.h>
  14 #include <linux/types.h>
  15 #include <linux/pci.h>
  16
  17 #include "STG4000Reg.h"
  18
  19 /* SDRAM fixed settings */
  20 #define SDRAM_CFG_0   0x49A1
  21 #define SDRAM_CFG_1   0xA732
  22 #define SDRAM_CFG_2   0x31
  23 #define SDRAM_ARB_CFG 0xA0
  24 #define SDRAM_REFRESH 0x20
  25
  26 /* Reset values */
  27 #define PMX2_SOFTRESET_DAC_RST          0x0001
  28 #define PMX2_SOFTRESET_C1_RST           0x0004
  29 #define PMX2_SOFTRESET_C2_RST           0x0008
  30 #define PMX2_SOFTRESET_3D_RST           0x0010
  31 #define PMX2_SOFTRESET_VIDIN_RST        0x0020
  32 #define PMX2_SOFTRESET_TLB_RST          0x0040
  33 #define PMX2_SOFTRESET_SD_RST           0x0080
  34 #define PMX2_SOFTRESET_VGA_RST          0x0100
  35 #define PMX2_SOFTRESET_ROM_RST          0x0200  /* reserved bit, do not reset */
  36 #define PMX2_SOFTRESET_TA_RST           0x0400
  37 #define PMX2_SOFTRESET_REG_RST          0x4000
  38 #define PMX2_SOFTRESET_ALL              0x7fff
  39
  40 /* Core clock freq */
  41 #define CORE_PLL_FREQ 1000000
  42
  43 /* Reference Clock freq */
  44 #define REF_FREQ 14318
  45
  46 /* PCI Registers */
  47 static u16 CorePllControl = 0x70;
  48
  49 #define PCI_CONFIG_SUBSYS_ID    0x2e
  50
  51 /* Misc */
  52 #define CORE_PLL_MODE_REG_0_7      3
  53 #define CORE_PLL_MODE_REG_8_15     2
  54 #define CORE_PLL_MODE_CONFIG_REG   1
  55 #define DAC_PLL_CONFIG_REG         0
  56
  57 #define STG_MAX_VCO 500000
  58 #define STG_MIN_VCO 100000
  59
  60 /* PLL Clock */
  61 #define    STG4K3_PLL_SCALER      8     /* scale numbers by 2^8 for fixed point calc */
  62 #define    STG4K3_PLL_MIN_R       2     /* Minimum multiplier */
  63 #define    STG4K3_PLL_MAX_R       33    /* Max */
  64 #define    STG4K3_PLL_MIN_F       2     /* Minimum divisor */
  65 #define    STG4K3_PLL_MAX_F       513   /* Max */
  66 #define    STG4K3_PLL_MIN_OD      0     /* Min output divider (shift) */
  67 #define    STG4K3_PLL_MAX_OD      2     /* Max */
  68 #define    STG4K3_PLL_MIN_VCO_SC  (100000000 >> STG4K3_PLL_SCALER)      /* Min VCO rate */
  69 #define    STG4K3_PLL_MAX_VCO_SC  (500000000 >> STG4K3_PLL_SCALER)      /* Max VCO rate */
  70 #define    STG4K3_PLL_MINR_VCO_SC (100000000 >> STG4K3_PLL_SCALER)      /* Min VCO rate (restricted) */
  71 #define    STG4K3_PLL_MAXR_VCO_SC (500000000 >> STG4K3_PLL_SCALER)      /* Max VCO rate (restricted) */
  72 #define    STG4K3_PLL_MINR_VCO    100000000     /* Min VCO rate (restricted) */
  73 #define    STG4K3_PLL_MAX_VCO     500000000     /* Max VCO rate */
  74 #define    STG4K3_PLL_MAXR_VCO    500000000     /* Max VCO rate (restricted) */
  75
  76 #define OS_DELAY(X) \
  77 { \
  78 volatile u32 i,count=0; \
  79     for(i=0;i<X;i++) count++; \
  80 }
  81
  82 static u32 InitSDRAMRegisters(volatile STG4000REG __iomem *pSTGReg,
  83                               u32 dwSubSysID, u32 dwRevID)
  84 {
  85         u32 adwSDRAMArgCfg0[] = { 0xa0, 0x80, 0xa0, 0xa0, 0xa0 };
  86         u32 adwSDRAMCfg1[] = { 0x8732, 0x8732, 0xa732, 0xa732, 0x8732 };
  87         u32 adwSDRAMCfg2[] = { 0x87d2, 0x87d2, 0xa7d2, 0x87d2, 0xa7d2 };
  88         u32 adwSDRAMRsh[] = { 36, 39, 40 };
  89         u32 adwChipSpeed[] = { 110, 120, 125 };
  90         u32 dwMemTypeIdx;
  91         u32 dwChipSpeedIdx;
  92
  93         /* Get memory tpye and chip speed indexs from the SubSysDevID */
  94         dwMemTypeIdx = (dwSubSysID & 0x70) >> 4;
  95         dwChipSpeedIdx = (dwSubSysID & 0x180) >> 7;
  96
  97         if (dwMemTypeIdx > 4 || dwChipSpeedIdx > 2)
  98                 return 0;
  99
 100         /* Program SD-RAM interface */
 101         STG_WRITE_REG(SDRAMArbiterConf, adwSDRAMArgCfg0[dwMemTypeIdx]);
 102         if (dwRevID < 5) {
 103                 STG_WRITE_REG(SDRAMConf0, 0x49A1);
 104                 STG_WRITE_REG(SDRAMConf1, adwSDRAMCfg1[dwMemTypeIdx]);
 105         } else {
 106                 STG_WRITE_REG(SDRAMConf0, 0x4DF1);
 107                 STG_WRITE_REG(SDRAMConf1, adwSDRAMCfg2[dwMemTypeIdx]);
 108         }
 109
 110         STG_WRITE_REG(SDRAMConf2, 0x31);
 111         STG_WRITE_REG(SDRAMRefresh, adwSDRAMRsh[dwChipSpeedIdx]);
 112
 113         return adwChipSpeed[dwChipSpeedIdx] * 10000;
 114 }
 115
 116 u32 ProgramClock(u32 refClock,
 117                    u32 coreClock,
 118                    u32 * FOut, u32 * ROut, u32 * POut)
 119 {
 120         u32 R = 0, F = 0, OD = 0, ODIndex = 0;
 121         u32 ulBestR = 0, ulBestF = 0, ulBestOD = 0;
 122         u32 ulBestVCO = 0, ulBestClk = 0, ulBestScore = 0;
 123         u32 ulScore, ulPhaseScore, ulVcoScore;
 124         u32 ulTmp = 0, ulVCO;
 125         u32 ulScaleClockReq, ulMinClock, ulMaxClock;
 126         u32 ODValues[] = { 1, 2, 0 };
 127
 128         /* Translate clock in Hz */
 129         coreClock *= 100;       /* in Hz */
 130         refClock *= 1000;       /* in Hz */
 131
 132         /* Work out acceptable clock
 133          * The method calculates ~ +- 0.4% (1/256)
 134          */
 135         ulMinClock = coreClock - (coreClock >> 8);
 136         ulMaxClock = coreClock + (coreClock >> 8);
 137
 138         /* Scale clock required for use in calculations */
 139         ulScaleClockReq = coreClock >> STG4K3_PLL_SCALER;
 140
 141         /* Iterate through post divider values */
 142         for (ODIndex = 0; ODIndex < 3; ODIndex++) {
 143                 OD = ODValues[ODIndex];
 144                 R = STG4K3_PLL_MIN_R;
 145
 146                 /* loop for pre-divider from min to max  */
 147                 while (R <= STG4K3_PLL_MAX_R) {
 148                         /* estimate required feedback multiplier */
 149                         ulTmp = R * (ulScaleClockReq << OD);
 150
 151                         /* F = ClkRequired * R * (2^OD) / Fref */
 152                         F = (u32)(ulTmp / (refClock >> STG4K3_PLL_SCALER));
 153
 154                         /* compensate for accuracy */
 155                         if (F > STG4K3_PLL_MIN_F)
 156                                 F--;
 157
 158
 159                         /*
 160                          * We should be close to our target frequency (if it's
 161                          * achievable with current OD & R) let's iterate
 162                          * through F for best fit
 163                          */
 164                         while ((F >= STG4K3_PLL_MIN_F) &&
 165                                (F <= STG4K3_PLL_MAX_F)) {
 166                                 /* Calc VCO at full accuracy */
 167                                 ulVCO = refClock / R;
 168                                 ulVCO = F * ulVCO;
 169
 170                                 /*
 171                                  * Check it's within restricted VCO range
 172                                  * unless of course the desired frequency is
 173                                  * above the restricted range, then test
 174                                  * against VCO limit
 175                                  */
 176                                 if ((ulVCO >= STG4K3_PLL_MINR_VCO) &&
 177                                     ((ulVCO <= STG4K3_PLL_MAXR_VCO) ||
 178                                      ((coreClock > STG4K3_PLL_MAXR_VCO)
 179                                       && (ulVCO <= STG4K3_PLL_MAX_VCO)))) {
 180                                         ulTmp = (ulVCO >> OD);  /* Clock = VCO / (2^OD) */
 181
 182                                         /* Is this clock good enough? */
 183                                         if ((ulTmp >= ulMinClock)
 184                                             && (ulTmp <= ulMaxClock)) {
 185                                                 ulPhaseScore = (((refClock / R) - (refClock / STG4K3_PLL_MAX_R))) / ((refClock - (refClock / STG4K3_PLL_MAX_R)) >> 10);
 186
 187                                                 ulVcoScore = ((ulVCO - STG4K3_PLL_MINR_VCO)) / ((STG4K3_PLL_MAXR_VCO - STG4K3_PLL_MINR_VCO) >> 10);
 188                                                 ulScore = ulPhaseScore + ulVcoScore;
 189
 190                                                 if (!ulBestScore) {
 191                                                         ulBestVCO = ulVCO;
 192                                                         ulBestOD = OD;
 193                                                         ulBestF = F;
 194                                                         ulBestR = R;
 195                                                         ulBestClk = ulTmp;
 196                                                         ulBestScore =
 197                                                             ulScore;
 198                                                 }
 199                                                 /* is this better, ( aim for highest Score) */
 200                         /*--------------------------------------------------------------------------
 201                              Here we want to use a scoring system which will take account of both the
 202                             value at the phase comparater and the VCO output
 203                              to do this we will use a cumulative score between the two
 204                           The way this ends up is that we choose the first value in the loop anyway
 205                           but we shall keep this code in case new restrictions come into play
 206                           --------------------------------------------------------------------------*/
 207                                                 if ((ulScore >= ulBestScore) && (OD > 0)) {
 208                                                         ulBestVCO = ulVCO;
 209                                                         ulBestOD = OD;
 210                                                         ulBestF = F;
 211                                                         ulBestR = R;
 212                                                         ulBestClk = ulTmp;
 213                                                         ulBestScore =
 214                                                             ulScore;
 215                                                 }
 216                                         }
 217                                 }
 218                                 F++;
 219                         }
 220                         R++;
 221                 }
 222         }
 223
 224         /*
 225            did we find anything?
 226            Then return RFOD
 227          */
 228         if (ulBestScore) {
 229                 *ROut = ulBestR;
 230                 *FOut = ulBestF;
 231
 232                 if ((ulBestOD == 2) || (ulBestOD == 3)) {
 233                         *POut = 3;
 234                 } else
 235                         *POut = ulBestOD;
 236
 237         }
 238
 239         return (ulBestClk);
 240 }
 241
 242 int SetCoreClockPLL(volatile STG4000REG __iomem *pSTGReg, struct pci_dev *pDev)
 243 {
 244         u32 F, R, P;
 245         u16 core_pll = 0, sub;
 246         u32 ulCoreClock;
 247         u32 tmp;
 248         u32 ulChipSpeed;
 249         u8 rev;
 250
 251         STG_WRITE_REG(IntMask, 0xFFFF);
 252
 253         /* Disable Primary Core Thread0 */
 254         tmp = STG_READ_REG(Thread0Enable);
 255         CLEAR_BIT(0);
 256         STG_WRITE_REG(Thread0Enable, tmp);
 257
 258         /* Disable Primary Core Thread1 */
 259         tmp = STG_READ_REG(Thread1Enable);
 260         CLEAR_BIT(0);
 261         STG_WRITE_REG(Thread1Enable, tmp);
 262
 263         STG_WRITE_REG(SoftwareReset,
 264                       PMX2_SOFTRESET_REG_RST | PMX2_SOFTRESET_ROM_RST);
 265         STG_WRITE_REG(SoftwareReset,
 266                       PMX2_SOFTRESET_REG_RST | PMX2_SOFTRESET_TA_RST |
 267                       PMX2_SOFTRESET_ROM_RST);
 268
 269         /* Need to play around to reset TA */
 270         STG_WRITE_REG(TAConfiguration, 0);
 271         STG_WRITE_REG(SoftwareReset,
 272                       PMX2_SOFTRESET_REG_RST | PMX2_SOFTRESET_ROM_RST);
 273         STG_WRITE_REG(SoftwareReset,
 274                       PMX2_SOFTRESET_REG_RST | PMX2_SOFTRESET_TA_RST |
 275                       PMX2_SOFTRESET_ROM_RST);
 276
 277         pci_read_config_word(pDev, PCI_CONFIG_SUBSYS_ID, &sub);
 278         pci_read_config_byte(pDev, PCI_REVISION_ID, &rev);
 279
 280         ulChipSpeed = InitSDRAMRegisters(pSTGReg, (u32)sub, (u32)rev);
 281
 282         if (ulChipSpeed == 0)
 283                 return -EINVAL;
 284
 285         ulCoreClock = ProgramClock(REF_FREQ, CORE_PLL_FREQ, &F, &R, &P);
 286
 287         core_pll |= ((P) | ((F - 2) << 2) | ((R - 2) << 11));
 288
 289         /* Set Core PLL Control to Core PLL Mode  */
 290
 291         /* Send bits 0:7 of the Core PLL Mode register */
 292         tmp = ((CORE_PLL_MODE_REG_0_7 << 8) | (core_pll & 0x00FF));
 293         pci_write_config_word(pDev, CorePllControl, tmp);
 294         /* Without some delay between the PCI config writes the clock does
 295            not reliably set when the code is compiled -O3
 296          */
 297         OS_DELAY(1000000);
 298
 299         tmp |= SET_BIT(14);
 300         pci_write_config_word(pDev, CorePllControl, tmp);
 301         OS_DELAY(1000000);
 302
 303         /* Send bits 8:15 of the Core PLL Mode register */
 304         tmp =
 305             ((CORE_PLL_MODE_REG_8_15 << 8) | ((core_pll & 0xFF00) >> 8));
 306         pci_write_config_word(pDev, CorePllControl, tmp);
 307         OS_DELAY(1000000);
 308
 309         tmp |= SET_BIT(14);
 310         pci_write_config_word(pDev, CorePllControl, tmp);
 311         OS_DELAY(1000000);
 312
 313         STG_WRITE_REG(SoftwareReset, PMX2_SOFTRESET_ALL);
 314
 315 #if 0
 316         /* Enable Primary Core Thread0 */
 317         tmp = ((STG_READ_REG(Thread0Enable)) | SET_BIT(0));
 318         STG_WRITE_REG(Thread0Enable, tmp);
 319
 320         /* Enable Primary Core Thread1 */
 321         tmp = ((STG_READ_REG(Thread1Enable)) | SET_BIT(0));
 322         STG_WRITE_REG(Thread1Enable, tmp);
 323 #endif
 324
 325         return 0;
 326 }