2 * xtensa/config/core.h -- HAL definitions that are dependent on CORE configuration
4 * This header file is sometimes referred to as the "compile-time HAL" or CHAL.
5 * It was generated for a specific Xtensa processor configuration.
7 * Source for configuration-independent binaries (which link in a
8 * configuration-specific HAL library) must NEVER include this file.
9 * It is perfectly normal, however, for the HAL source itself to include this file.
13 * Copyright (c) 2003 Tensilica, Inc. All Rights Reserved.
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of version 2.1 of the GNU Lesser General Public
17 * License as published by the Free Software Foundation.
19 * This program is distributed in the hope that it would be useful, but
20 * WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
23 * Further, this software is distributed without any warranty that it is
24 * free of the rightful claim of any third person regarding infringement
25 * or the like. Any license provided herein, whether implied or
26 * otherwise, applies only to this software file. Patent licenses, if
27 * any, provided herein do not apply to combinations of this program with
28 * other software, or any other product whatsoever.
30 * You should have received a copy of the GNU Lesser General Public
31 * License along with this program; if not, write the Free Software
32 * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307,
37 #ifndef XTENSA_CONFIG_CORE_H
38 #define XTENSA_CONFIG_CORE_H
40 #include <xtensa/hal.h>
43 /*----------------------------------------------------------------------
45 ----------------------------------------------------------------------*/
48 * Separators for macros that expand into arrays.
49 * These can be predefined by files that #include this one,
50 * when different separators are required.
52 /* Element separator for macros that expand into 1-dimensional arrays: */
56 /* Array separator for macros that expand into 2-dimensional arrays: */
58 #define XCHAL_SEP2 },{
62 /*----------------------------------------------------------------------
64 ----------------------------------------------------------------------*/
66 #define XCHAL_HAVE_BE 1
67 #define XCHAL_HAVE_LE 0
68 #define XCHAL_MEMORY_ORDER XTHAL_BIGENDIAN
71 /*----------------------------------------------------------------------
73 ----------------------------------------------------------------------*/
75 #define XCHAL_HAVE_WINDOWED 1 /* 1 if windowed registers option configured, 0 otherwise */
76 #define XCHAL_NUM_AREGS 64 /* number of physical address regs */
77 #define XCHAL_NUM_AREGS_LOG2 6 /* log2(XCHAL_NUM_AREGS) */
80 /*----------------------------------------------------------------------
82 ----------------------------------------------------------------------*/
84 /* These apply to a selected set of core load and store instructions only (see ISA): */
85 #define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* 1 if unaligned loads cause an exception, 0 otherwise */
86 #define XCHAL_UNALIGNED_STORE_EXCEPTION 1 /* 1 if unaligned stores cause an exception, 0 otherwise */
89 /*----------------------------------------------------------------------
91 ----------------------------------------------------------------------*/
93 #define XCHAL_HAVE_INTERRUPTS 1 /* 1 if interrupt option configured, 0 otherwise */
94 #define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* 1 if high-priority interrupt option configured, 0 otherwise */
95 #define XCHAL_HAVE_HIGHLEVEL_INTERRUPTS XCHAL_HAVE_HIGHPRI_INTERRUPTS
96 #define XCHAL_HAVE_NMI 0 /* 1 if NMI option configured, 0 otherwise */
97 #define XCHAL_NUM_INTERRUPTS 17 /* number of interrupts */
98 #define XCHAL_NUM_INTERRUPTS_LOG2 5 /* number of bits to hold an interrupt number: roundup(log2(number of interrupts)) */
99 #define XCHAL_NUM_EXTINTERRUPTS 10 /* number of external interrupts */
100 #define XCHAL_NUM_INTLEVELS 4 /* number of interrupt levels (not including level zero!) */
101 #define XCHAL_NUM_LOWPRI_LEVELS 1 /* number of low-priority interrupt levels (always 1) */
102 #define XCHAL_FIRST_HIGHPRI_LEVEL (XCHAL_NUM_LOWPRI_LEVELS+1) /* level of first high-priority interrupt (always 2) */
103 #define XCHAL_EXCM_LEVEL 1 /* level of interrupts masked by PS.EXCM (XEA2 only; always 1 in T10xx);
104 for XEA1, where there is no PS.EXCM, this is always 1;
105 interrupts at levels FIRST_HIGHPRI <= n <= EXCM_LEVEL, if any,
106 are termed "medium priority" interrupts (post T10xx only) */
107 /* Note: 1 <= LOWPRI_LEVELS <= EXCM_LEVEL < DEBUGLEVEL <= NUM_INTLEVELS < NMILEVEL <= 15 */
109 /* Masks of interrupts at each interrupt level: */
110 #define XCHAL_INTLEVEL0_MASK 0x00000000
111 #define XCHAL_INTLEVEL1_MASK 0x000064F9
112 #define XCHAL_INTLEVEL2_MASK 0x00008902
113 #define XCHAL_INTLEVEL3_MASK 0x00011204
114 #define XCHAL_INTLEVEL4_MASK 0x00000000
115 #define XCHAL_INTLEVEL5_MASK 0x00000000
116 #define XCHAL_INTLEVEL6_MASK 0x00000000
117 #define XCHAL_INTLEVEL7_MASK 0x00000000
118 #define XCHAL_INTLEVEL8_MASK 0x00000000
119 #define XCHAL_INTLEVEL9_MASK 0x00000000
120 #define XCHAL_INTLEVEL10_MASK 0x00000000
121 #define XCHAL_INTLEVEL11_MASK 0x00000000
122 #define XCHAL_INTLEVEL12_MASK 0x00000000
123 #define XCHAL_INTLEVEL13_MASK 0x00000000
124 #define XCHAL_INTLEVEL14_MASK 0x00000000
125 #define XCHAL_INTLEVEL15_MASK 0x00000000
126 /* As an array of entries (eg. for C constant arrays): */
127 #define XCHAL_INTLEVEL_MASKS 0x00000000 XCHAL_SEP \
128 0x000064F9 XCHAL_SEP \
129 0x00008902 XCHAL_SEP \
130 0x00011204 XCHAL_SEP \
131 0x00000000 XCHAL_SEP \
132 0x00000000 XCHAL_SEP \
133 0x00000000 XCHAL_SEP \
134 0x00000000 XCHAL_SEP \
135 0x00000000 XCHAL_SEP \
136 0x00000000 XCHAL_SEP \
137 0x00000000 XCHAL_SEP \
138 0x00000000 XCHAL_SEP \
139 0x00000000 XCHAL_SEP \
140 0x00000000 XCHAL_SEP \
141 0x00000000 XCHAL_SEP \
144 /* Masks of interrupts at each range 1..n of interrupt levels: */
145 #define XCHAL_INTLEVEL0_ANDBELOW_MASK 0x00000000
146 #define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x000064F9
147 #define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x0000EDFB
148 #define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x0001FFFF
149 #define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x0001FFFF
150 #define XCHAL_INTLEVEL5_ANDBELOW_MASK 0x0001FFFF
151 #define XCHAL_INTLEVEL6_ANDBELOW_MASK 0x0001FFFF
152 #define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x0001FFFF
153 #define XCHAL_INTLEVEL8_ANDBELOW_MASK 0x0001FFFF
154 #define XCHAL_INTLEVEL9_ANDBELOW_MASK 0x0001FFFF
155 #define XCHAL_INTLEVEL10_ANDBELOW_MASK 0x0001FFFF
156 #define XCHAL_INTLEVEL11_ANDBELOW_MASK 0x0001FFFF
157 #define XCHAL_INTLEVEL12_ANDBELOW_MASK 0x0001FFFF
158 #define XCHAL_INTLEVEL13_ANDBELOW_MASK 0x0001FFFF
159 #define XCHAL_INTLEVEL14_ANDBELOW_MASK 0x0001FFFF
160 #define XCHAL_INTLEVEL15_ANDBELOW_MASK 0x0001FFFF
161 #define XCHAL_LOWPRI_MASK XCHAL_INTLEVEL1_ANDBELOW_MASK /* mask of all low-priority interrupts */
162 #define XCHAL_EXCM_MASK XCHAL_INTLEVEL1_ANDBELOW_MASK /* mask of all interrupts masked by PS.EXCM (or CEXCM) */
163 /* As an array of entries (eg. for C constant arrays): */
164 #define XCHAL_INTLEVEL_ANDBELOW_MASKS 0x00000000 XCHAL_SEP \
165 0x000064F9 XCHAL_SEP \
166 0x0000EDFB XCHAL_SEP \
167 0x0001FFFF XCHAL_SEP \
168 0x0001FFFF XCHAL_SEP \
169 0x0001FFFF XCHAL_SEP \
170 0x0001FFFF XCHAL_SEP \
171 0x0001FFFF XCHAL_SEP \
172 0x0001FFFF XCHAL_SEP \
173 0x0001FFFF XCHAL_SEP \
174 0x0001FFFF XCHAL_SEP \
175 0x0001FFFF XCHAL_SEP \
176 0x0001FFFF XCHAL_SEP \
177 0x0001FFFF XCHAL_SEP \
178 0x0001FFFF XCHAL_SEP \
181 /* Interrupt numbers for each interrupt level at which only one interrupt was configured: */
182 /*#define XCHAL_INTLEVEL1_NUM ...more than one interrupt at this level...*/
183 /*#define XCHAL_INTLEVEL2_NUM ...more than one interrupt at this level...*/
184 /*#define XCHAL_INTLEVEL3_NUM ...more than one interrupt at this level...*/
186 /* Level of each interrupt: */
187 #define XCHAL_INT0_LEVEL 1
188 #define XCHAL_INT1_LEVEL 2
189 #define XCHAL_INT2_LEVEL 3
190 #define XCHAL_INT3_LEVEL 1
191 #define XCHAL_INT4_LEVEL 1
192 #define XCHAL_INT5_LEVEL 1
193 #define XCHAL_INT6_LEVEL 1
194 #define XCHAL_INT7_LEVEL 1
195 #define XCHAL_INT8_LEVEL 2
196 #define XCHAL_INT9_LEVEL 3
197 #define XCHAL_INT10_LEVEL 1
198 #define XCHAL_INT11_LEVEL 2
199 #define XCHAL_INT12_LEVEL 3
200 #define XCHAL_INT13_LEVEL 1
201 #define XCHAL_INT14_LEVEL 1
202 #define XCHAL_INT15_LEVEL 2
203 #define XCHAL_INT16_LEVEL 3
204 #define XCHAL_INT17_LEVEL 0
205 #define XCHAL_INT18_LEVEL 0
206 #define XCHAL_INT19_LEVEL 0
207 #define XCHAL_INT20_LEVEL 0
208 #define XCHAL_INT21_LEVEL 0
209 #define XCHAL_INT22_LEVEL 0
210 #define XCHAL_INT23_LEVEL 0
211 #define XCHAL_INT24_LEVEL 0
212 #define XCHAL_INT25_LEVEL 0
213 #define XCHAL_INT26_LEVEL 0
214 #define XCHAL_INT27_LEVEL 0
215 #define XCHAL_INT28_LEVEL 0
216 #define XCHAL_INT29_LEVEL 0
217 #define XCHAL_INT30_LEVEL 0
218 #define XCHAL_INT31_LEVEL 0
219 /* As an array of entries (eg. for C constant arrays): */
220 #define XCHAL_INT_LEVELS 1 XCHAL_SEP \
253 /* Type of each interrupt: */
254 #define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
255 #define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
256 #define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
257 #define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
258 #define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
259 #define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
260 #define XCHAL_INT6_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
261 #define XCHAL_INT7_TYPE XTHAL_INTTYPE_EXTERN_EDGE
262 #define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_EDGE
263 #define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_EDGE
264 #define XCHAL_INT10_TYPE XTHAL_INTTYPE_TIMER
265 #define XCHAL_INT11_TYPE XTHAL_INTTYPE_TIMER
266 #define XCHAL_INT12_TYPE XTHAL_INTTYPE_TIMER
267 #define XCHAL_INT13_TYPE XTHAL_INTTYPE_SOFTWARE
268 #define XCHAL_INT14_TYPE XTHAL_INTTYPE_SOFTWARE
269 #define XCHAL_INT15_TYPE XTHAL_INTTYPE_SOFTWARE
270 #define XCHAL_INT16_TYPE XTHAL_INTTYPE_SOFTWARE
271 #define XCHAL_INT17_TYPE XTHAL_INTTYPE_UNCONFIGURED
272 #define XCHAL_INT18_TYPE XTHAL_INTTYPE_UNCONFIGURED
273 #define XCHAL_INT19_TYPE XTHAL_INTTYPE_UNCONFIGURED
274 #define XCHAL_INT20_TYPE XTHAL_INTTYPE_UNCONFIGURED
275 #define XCHAL_INT21_TYPE XTHAL_INTTYPE_UNCONFIGURED
276 #define XCHAL_INT22_TYPE XTHAL_INTTYPE_UNCONFIGURED
277 #define XCHAL_INT23_TYPE XTHAL_INTTYPE_UNCONFIGURED
278 #define XCHAL_INT24_TYPE XTHAL_INTTYPE_UNCONFIGURED
279 #define XCHAL_INT25_TYPE XTHAL_INTTYPE_UNCONFIGURED
280 #define XCHAL_INT26_TYPE XTHAL_INTTYPE_UNCONFIGURED
281 #define XCHAL_INT27_TYPE XTHAL_INTTYPE_UNCONFIGURED
282 #define XCHAL_INT28_TYPE XTHAL_INTTYPE_UNCONFIGURED
283 #define XCHAL_INT29_TYPE XTHAL_INTTYPE_UNCONFIGURED
284 #define XCHAL_INT30_TYPE XTHAL_INTTYPE_UNCONFIGURED
285 #define XCHAL_INT31_TYPE XTHAL_INTTYPE_UNCONFIGURED
286 /* As an array of entries (eg. for C constant arrays): */
287 #define XCHAL_INT_TYPES XTHAL_INTTYPE_EXTERN_LEVEL XCHAL_SEP \
288 XTHAL_INTTYPE_EXTERN_LEVEL XCHAL_SEP \
289 XTHAL_INTTYPE_EXTERN_LEVEL XCHAL_SEP \
290 XTHAL_INTTYPE_EXTERN_LEVEL XCHAL_SEP \
291 XTHAL_INTTYPE_EXTERN_LEVEL XCHAL_SEP \
292 XTHAL_INTTYPE_EXTERN_LEVEL XCHAL_SEP \
293 XTHAL_INTTYPE_EXTERN_LEVEL XCHAL_SEP \
294 XTHAL_INTTYPE_EXTERN_EDGE XCHAL_SEP \
295 XTHAL_INTTYPE_EXTERN_EDGE XCHAL_SEP \
296 XTHAL_INTTYPE_EXTERN_EDGE XCHAL_SEP \
297 XTHAL_INTTYPE_TIMER XCHAL_SEP \
298 XTHAL_INTTYPE_TIMER XCHAL_SEP \
299 XTHAL_INTTYPE_TIMER XCHAL_SEP \
300 XTHAL_INTTYPE_SOFTWARE XCHAL_SEP \
301 XTHAL_INTTYPE_SOFTWARE XCHAL_SEP \
302 XTHAL_INTTYPE_SOFTWARE XCHAL_SEP \
303 XTHAL_INTTYPE_SOFTWARE XCHAL_SEP \
304 XTHAL_INTTYPE_UNCONFIGURED XCHAL_SEP \
305 XTHAL_INTTYPE_UNCONFIGURED XCHAL_SEP \
306 XTHAL_INTTYPE_UNCONFIGURED XCHAL_SEP \
307 XTHAL_INTTYPE_UNCONFIGURED XCHAL_SEP \
308 XTHAL_INTTYPE_UNCONFIGURED XCHAL_SEP \
309 XTHAL_INTTYPE_UNCONFIGURED XCHAL_SEP \
310 XTHAL_INTTYPE_UNCONFIGURED XCHAL_SEP \
311 XTHAL_INTTYPE_UNCONFIGURED XCHAL_SEP \
312 XTHAL_INTTYPE_UNCONFIGURED XCHAL_SEP \
313 XTHAL_INTTYPE_UNCONFIGURED XCHAL_SEP \
314 XTHAL_INTTYPE_UNCONFIGURED XCHAL_SEP \
315 XTHAL_INTTYPE_UNCONFIGURED XCHAL_SEP \
316 XTHAL_INTTYPE_UNCONFIGURED XCHAL_SEP \
317 XTHAL_INTTYPE_UNCONFIGURED XCHAL_SEP \
318 XTHAL_INTTYPE_UNCONFIGURED
320 /* Masks of interrupts for each type of interrupt: */
321 #define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFFFE0000
322 #define XCHAL_INTTYPE_MASK_SOFTWARE 0x0001E000
323 #define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x00000380
324 #define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x0000007F
325 #define XCHAL_INTTYPE_MASK_TIMER 0x00001C00
326 #define XCHAL_INTTYPE_MASK_NMI 0x00000000
327 /* As an array of entries (eg. for C constant arrays): */
328 #define XCHAL_INTTYPE_MASKS 0xFFFE0000 XCHAL_SEP \
329 0x0001E000 XCHAL_SEP \
330 0x00000380 XCHAL_SEP \
331 0x0000007F XCHAL_SEP \
332 0x00001C00 XCHAL_SEP \
335 /* Interrupts assigned to each timer (CCOMPARE0 to CCOMPARE3), -1 if unassigned */
336 #define XCHAL_TIMER0_INTERRUPT 10
337 #define XCHAL_TIMER1_INTERRUPT 11
338 #define XCHAL_TIMER2_INTERRUPT 12
339 #define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED
340 /* As an array of entries (eg. for C constant arrays): */
341 #define XCHAL_TIMER_INTERRUPTS 10 XCHAL_SEP \
344 XTHAL_TIMER_UNCONFIGURED
346 /* Indexing macros: */
347 #define _XCHAL_INTLEVEL_MASK(n) XCHAL_INTLEVEL ## n ## _MASK
348 #define XCHAL_INTLEVEL_MASK(n) _XCHAL_INTLEVEL_MASK(n) /* n = 0 .. 15 */
349 #define _XCHAL_INTLEVEL_ANDBELOWMASK(n) XCHAL_INTLEVEL ## n ## _ANDBELOW_MASK
350 #define XCHAL_INTLEVEL_ANDBELOW_MASK(n) _XCHAL_INTLEVEL_ANDBELOWMASK(n) /* n = 0 .. 15 */
351 #define _XCHAL_INT_LEVEL(n) XCHAL_INT ## n ## _LEVEL
352 #define XCHAL_INT_LEVEL(n) _XCHAL_INT_LEVEL(n) /* n = 0 .. 31 */
353 #define _XCHAL_INT_TYPE(n) XCHAL_INT ## n ## _TYPE
354 #define XCHAL_INT_TYPE(n) _XCHAL_INT_TYPE(n) /* n = 0 .. 31 */
355 #define _XCHAL_TIMER_INTERRUPT(n) XCHAL_TIMER ## n ## _INTERRUPT
356 #define XCHAL_TIMER_INTERRUPT(n) _XCHAL_TIMER_INTERRUPT(n) /* n = 0 .. 3 */
361 * External interrupt vectors/levels.
362 * These macros describe how Xtensa processor interrupt numbers
363 * (as numbered internally, eg. in INTERRUPT and INTENABLE registers)
364 * map to external BInterrupt<n> pins, for those interrupts
365 * configured as external (level-triggered, edge-triggered, or NMI).
366 * See the Xtensa processor databook for more details.
369 /* Core interrupt numbers mapped to each EXTERNAL interrupt number: */
370 #define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */
371 #define XCHAL_EXTINT1_NUM 1 /* (intlevel 2) */
372 #define XCHAL_EXTINT2_NUM 2 /* (intlevel 3) */
373 #define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */
374 #define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */
375 #define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */
376 #define XCHAL_EXTINT6_NUM 6 /* (intlevel 1) */
377 #define XCHAL_EXTINT7_NUM 7 /* (intlevel 1) */
378 #define XCHAL_EXTINT8_NUM 8 /* (intlevel 2) */
379 #define XCHAL_EXTINT9_NUM 9 /* (intlevel 3) */
381 /* Corresponding interrupt masks: */
382 #define XCHAL_EXTINT0_MASK 0x00000001
383 #define XCHAL_EXTINT1_MASK 0x00000002
384 #define XCHAL_EXTINT2_MASK 0x00000004
385 #define XCHAL_EXTINT3_MASK 0x00000008
386 #define XCHAL_EXTINT4_MASK 0x00000010
387 #define XCHAL_EXTINT5_MASK 0x00000020
388 #define XCHAL_EXTINT6_MASK 0x00000040
389 #define XCHAL_EXTINT7_MASK 0x00000080
390 #define XCHAL_EXTINT8_MASK 0x00000100
391 #define XCHAL_EXTINT9_MASK 0x00000200
393 /* Core config interrupt levels mapped to each external interrupt: */
394 #define XCHAL_EXTINT0_LEVEL 1 /* (int number 0) */
395 #define XCHAL_EXTINT1_LEVEL 2 /* (int number 1) */
396 #define XCHAL_EXTINT2_LEVEL 3 /* (int number 2) */
397 #define XCHAL_EXTINT3_LEVEL 1 /* (int number 3) */
398 #define XCHAL_EXTINT4_LEVEL 1 /* (int number 4) */
399 #define XCHAL_EXTINT5_LEVEL 1 /* (int number 5) */
400 #define XCHAL_EXTINT6_LEVEL 1 /* (int number 6) */
401 #define XCHAL_EXTINT7_LEVEL 1 /* (int number 7) */
402 #define XCHAL_EXTINT8_LEVEL 2 /* (int number 8) */
403 #define XCHAL_EXTINT9_LEVEL 3 /* (int number 9) */
406 /*----------------------------------------------------------------------
407 EXCEPTIONS and VECTORS
408 ----------------------------------------------------------------------*/
410 #define XCHAL_HAVE_EXCEPTIONS 1 /* 1 if exception option configured, 0 otherwise */
412 #define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture number: 1 for XEA1 (old), 2 for XEA2 (new) */
413 #define XCHAL_HAVE_XEA1 0 /* 1 if XEA1, 0 otherwise */
414 #define XCHAL_HAVE_XEA2 1 /* 1 if XEA2, 0 otherwise */
415 /* For backward compatibility ONLY -- DO NOT USE (will be removed in future release): */
416 #define XCHAL_HAVE_OLD_EXC_ARCH XCHAL_HAVE_XEA1 /* (DEPRECATED) 1 if old exception architecture (XEA1), 0 otherwise (eg. XEA2) */
417 #define XCHAL_HAVE_EXCM XCHAL_HAVE_XEA2 /* (DEPRECATED) 1 if PS.EXCM bit exists (currently equals XCHAL_HAVE_TLBS) */
419 #define XCHAL_RESET_VECTOR_VADDR 0xFE000020
420 #define XCHAL_RESET_VECTOR_PADDR 0xFE000020
421 #define XCHAL_USER_VECTOR_VADDR 0xD0000220
422 #define XCHAL_PROGRAMEXC_VECTOR_VADDR XCHAL_USER_VECTOR_VADDR /* for backward compatibility */
423 #define XCHAL_USEREXC_VECTOR_VADDR XCHAL_USER_VECTOR_VADDR /* for backward compatibility */
424 #define XCHAL_USER_VECTOR_PADDR 0x00000220
425 #define XCHAL_PROGRAMEXC_VECTOR_PADDR XCHAL_USER_VECTOR_PADDR /* for backward compatibility */
426 #define XCHAL_USEREXC_VECTOR_PADDR XCHAL_USER_VECTOR_PADDR /* for backward compatibility */
427 #define XCHAL_KERNEL_VECTOR_VADDR 0xD0000200
428 #define XCHAL_STACKEDEXC_VECTOR_VADDR XCHAL_KERNEL_VECTOR_VADDR /* for backward compatibility */
429 #define XCHAL_KERNELEXC_VECTOR_VADDR XCHAL_KERNEL_VECTOR_VADDR /* for backward compatibility */
430 #define XCHAL_KERNEL_VECTOR_PADDR 0x00000200
431 #define XCHAL_STACKEDEXC_VECTOR_PADDR XCHAL_KERNEL_VECTOR_PADDR /* for backward compatibility */
432 #define XCHAL_KERNELEXC_VECTOR_PADDR XCHAL_KERNEL_VECTOR_PADDR /* for backward compatibility */
433 #define XCHAL_DOUBLEEXC_VECTOR_VADDR 0xD0000290
434 #define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x00000290
435 #define XCHAL_WINDOW_VECTORS_VADDR 0xD0000000
436 #define XCHAL_WINDOW_VECTORS_PADDR 0x00000000
437 #define XCHAL_INTLEVEL2_VECTOR_VADDR 0xD0000240
438 #define XCHAL_INTLEVEL2_VECTOR_PADDR 0x00000240
439 #define XCHAL_INTLEVEL3_VECTOR_VADDR 0xD0000250
440 #define XCHAL_INTLEVEL3_VECTOR_PADDR 0x00000250
441 #define XCHAL_INTLEVEL4_VECTOR_VADDR 0xFE000520
442 #define XCHAL_INTLEVEL4_VECTOR_PADDR 0xFE000520
443 #define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL4_VECTOR_VADDR
444 #define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL4_VECTOR_PADDR
446 /* Indexing macros: */
447 #define _XCHAL_INTLEVEL_VECTOR_VADDR(n) XCHAL_INTLEVEL ## n ## _VECTOR_VADDR
448 #define XCHAL_INTLEVEL_VECTOR_VADDR(n) _XCHAL_INTLEVEL_VECTOR_VADDR(n) /* n = 0 .. 15 */
451 * General Exception Causes
452 * (values of EXCCAUSE special register set by general exceptions,
453 * which vector to the user, kernel, or double-exception vectors):
455 #define XCHAL_EXCCAUSE_ILLEGAL_INSTRUCTION 0 /* Illegal Instruction (IllegalInstruction) */
456 #define XCHAL_EXCCAUSE_SYSTEM_CALL 1 /* System Call (SystemCall) */
457 #define XCHAL_EXCCAUSE_INSTRUCTION_FETCH_ERROR 2 /* Instruction Fetch Error (InstructionFetchError) */
458 #define XCHAL_EXCCAUSE_LOAD_STORE_ERROR 3 /* Load Store Error (LoadStoreError) */
459 #define XCHAL_EXCCAUSE_LEVEL1_INTERRUPT 4 /* Level 1 Interrupt (Level1Interrupt) */
460 #define XCHAL_EXCCAUSE_ALLOCA 5 /* Stack Extension Assist (Alloca) */
461 #define XCHAL_EXCCAUSE_INTEGER_DIVIDE_BY_ZERO 6 /* Integer Divide by Zero (IntegerDivideByZero) */
462 #define XCHAL_EXCCAUSE_SPECULATION 7 /* Speculation (Speculation) */
463 #define XCHAL_EXCCAUSE_PRIVILEGED 8 /* Privileged Instruction (Privileged) */
464 #define XCHAL_EXCCAUSE_UNALIGNED 9 /* Unaligned Load Store (Unaligned) */
465 #define XCHAL_EXCCAUSE_ITLB_MISS 16 /* ITlb Miss Exception (ITlbMiss) */
466 #define XCHAL_EXCCAUSE_ITLB_MULTIHIT 17 /* ITlb Mutltihit Exception (ITlbMultihit) */
467 #define XCHAL_EXCCAUSE_ITLB_PRIVILEGE 18 /* ITlb Privilege Exception (ITlbPrivilege) */
468 #define XCHAL_EXCCAUSE_ITLB_SIZE_RESTRICTION 19 /* ITlb Size Restriction Exception (ITlbSizeRestriction) */
469 #define XCHAL_EXCCAUSE_FETCH_CACHE_ATTRIBUTE 20 /* Fetch Cache Attribute Exception (FetchCacheAttribute) */
470 #define XCHAL_EXCCAUSE_DTLB_MISS 24 /* DTlb Miss Exception (DTlbMiss) */
471 #define XCHAL_EXCCAUSE_DTLB_MULTIHIT 25 /* DTlb Multihit Exception (DTlbMultihit) */
472 #define XCHAL_EXCCAUSE_DTLB_PRIVILEGE 26 /* DTlb Privilege Exception (DTlbPrivilege) */
473 #define XCHAL_EXCCAUSE_DTLB_SIZE_RESTRICTION 27 /* DTlb Size Restriction Exception (DTlbSizeRestriction) */
474 #define XCHAL_EXCCAUSE_LOAD_CACHE_ATTRIBUTE 28 /* Load Cache Attribute Exception (LoadCacheAttribute) */
475 #define XCHAL_EXCCAUSE_STORE_CACHE_ATTRIBUTE 29 /* Store Cache Attribute Exception (StoreCacheAttribute) */
476 #define XCHAL_EXCCAUSE_FLOATING_POINT 40 /* Floating Point Exception (FloatingPoint) */
480 /*----------------------------------------------------------------------
482 ----------------------------------------------------------------------*/
484 #define XCHAL_HAVE_CCOUNT 1 /* 1 if have CCOUNT, 0 otherwise */
485 /*#define XCHAL_HAVE_TIMERS XCHAL_HAVE_CCOUNT*/
486 #define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */
490 /*----------------------------------------------------------------------
492 ----------------------------------------------------------------------*/
494 #define XCHAL_HAVE_DEBUG 1 /* 1 if debug option configured, 0 otherwise */
495 #define XCHAL_HAVE_OCD 1 /* 1 if OnChipDebug option configured, 0 otherwise */
496 #define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */
497 #define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */
498 #define XCHAL_DEBUGLEVEL 4 /* debug interrupt level */
499 /*DebugExternalInterrupt 0 0|1*/
500 /*DebugUseDIRArray 0 0|1*/
505 /*----------------------------------------------------------------------
506 COPROCESSORS and EXTRA STATE
507 ----------------------------------------------------------------------*/
509 #define XCHAL_HAVE_CP 0 /* 1 if coprocessor option configured (CPENABLE present) */
510 #define XCHAL_CP_MAXCFG 0 /* max allowed cp id plus one (per cfg) */
512 #include <xtensa/config/tie.h>
517 /*----------------------------------------------------------------------
518 INTERNAL I/D RAM/ROMs and XLMI
519 ----------------------------------------------------------------------*/
521 #define XCHAL_NUM_INSTROM 0 /* number of core instruction ROMs configured */
522 #define XCHAL_NUM_INSTRAM 0 /* number of core instruction RAMs configured */
523 #define XCHAL_NUM_DATAROM 0 /* number of core data ROMs configured */
524 #define XCHAL_NUM_DATARAM 0 /* number of core data RAMs configured */
525 #define XCHAL_NUM_XLMI 0 /* number of core XLMI ports configured */
526 #define XCHAL_NUM_IROM XCHAL_NUM_INSTROM /* (DEPRECATED) */
527 #define XCHAL_NUM_IRAM XCHAL_NUM_INSTRAM /* (DEPRECATED) */
528 #define XCHAL_NUM_DROM XCHAL_NUM_DATAROM /* (DEPRECATED) */
529 #define XCHAL_NUM_DRAM XCHAL_NUM_DATARAM /* (DEPRECATED) */
533 /*----------------------------------------------------------------------
535 ----------------------------------------------------------------------*/
537 /* Size of the cache lines in log2(bytes): */
538 #define XCHAL_ICACHE_LINEWIDTH 4
539 #define XCHAL_DCACHE_LINEWIDTH 4
540 /* Size of the cache lines in bytes: */
541 #define XCHAL_ICACHE_LINESIZE 16
542 #define XCHAL_DCACHE_LINESIZE 16
543 /* Max for both I-cache and D-cache (used for general alignment): */
544 #define XCHAL_CACHE_LINEWIDTH_MAX 4
545 #define XCHAL_CACHE_LINESIZE_MAX 16
547 /* Number of cache sets in log2(lines per way): */
548 #define XCHAL_ICACHE_SETWIDTH 8
549 #define XCHAL_DCACHE_SETWIDTH 8
550 /* Max for both I-cache and D-cache (used for general cache-coherency page alignment): */
551 #define XCHAL_CACHE_SETWIDTH_MAX 8
552 #define XCHAL_CACHE_SETSIZE_MAX 256
554 /* Cache set associativity (number of ways): */
555 #define XCHAL_ICACHE_WAYS 2
556 #define XCHAL_DCACHE_WAYS 2
558 /* Size of the caches in bytes (ways * 2^(linewidth + setwidth)): */
559 #define XCHAL_ICACHE_SIZE 8192
560 #define XCHAL_DCACHE_SIZE 8192
562 /* Cache features: */
563 #define XCHAL_DCACHE_IS_WRITEBACK 0
564 /* Whether cache locking feature is available: */
565 #define XCHAL_ICACHE_LINE_LOCKABLE 0
566 #define XCHAL_DCACHE_LINE_LOCKABLE 0
568 /* Number of (encoded) cache attribute bits: */
569 #define XCHAL_CA_BITS 4 /* number of bits needed to hold cache attribute encoding */
570 /* (The number of access mode bits (decoded cache attribute bits) is defined by the architecture; see xtensa/hal.h?) */
573 /* Cache Attribute encodings -- lists of access modes for each cache attribute: */
574 #define XCHAL_FCA_LIST XTHAL_FAM_EXCEPTION XCHAL_SEP \
575 XTHAL_FAM_BYPASS XCHAL_SEP \
576 XTHAL_FAM_EXCEPTION XCHAL_SEP \
577 XTHAL_FAM_BYPASS XCHAL_SEP \
578 XTHAL_FAM_EXCEPTION XCHAL_SEP \
579 XTHAL_FAM_CACHED XCHAL_SEP \
580 XTHAL_FAM_EXCEPTION XCHAL_SEP \
581 XTHAL_FAM_CACHED XCHAL_SEP \
582 XTHAL_FAM_EXCEPTION XCHAL_SEP \
583 XTHAL_FAM_CACHED XCHAL_SEP \
584 XTHAL_FAM_EXCEPTION XCHAL_SEP \
585 XTHAL_FAM_CACHED XCHAL_SEP \
586 XTHAL_FAM_EXCEPTION XCHAL_SEP \
587 XTHAL_FAM_EXCEPTION XCHAL_SEP \
588 XTHAL_FAM_EXCEPTION XCHAL_SEP \
590 #define XCHAL_LCA_LIST XTHAL_LAM_EXCEPTION XCHAL_SEP \
591 XTHAL_LAM_BYPASSG XCHAL_SEP \
592 XTHAL_LAM_EXCEPTION XCHAL_SEP \
593 XTHAL_LAM_BYPASSG XCHAL_SEP \
594 XTHAL_LAM_EXCEPTION XCHAL_SEP \
595 XTHAL_LAM_CACHED XCHAL_SEP \
596 XTHAL_LAM_EXCEPTION XCHAL_SEP \
597 XTHAL_LAM_CACHED XCHAL_SEP \
598 XTHAL_LAM_EXCEPTION XCHAL_SEP \
599 XTHAL_LAM_NACACHED XCHAL_SEP \
600 XTHAL_LAM_EXCEPTION XCHAL_SEP \
601 XTHAL_LAM_NACACHED XCHAL_SEP \
602 XTHAL_LAM_EXCEPTION XCHAL_SEP \
603 XTHAL_LAM_ISOLATE XCHAL_SEP \
604 XTHAL_LAM_EXCEPTION XCHAL_SEP \
606 #define XCHAL_SCA_LIST XTHAL_SAM_EXCEPTION XCHAL_SEP \
607 XTHAL_SAM_EXCEPTION XCHAL_SEP \
608 XTHAL_SAM_EXCEPTION XCHAL_SEP \
609 XTHAL_SAM_BYPASS XCHAL_SEP \
610 XTHAL_SAM_EXCEPTION XCHAL_SEP \
611 XTHAL_SAM_EXCEPTION XCHAL_SEP \
612 XTHAL_SAM_EXCEPTION XCHAL_SEP \
613 XTHAL_SAM_WRITETHRU XCHAL_SEP \
614 XTHAL_SAM_EXCEPTION XCHAL_SEP \
615 XTHAL_SAM_EXCEPTION XCHAL_SEP \
616 XTHAL_SAM_EXCEPTION XCHAL_SEP \
617 XTHAL_SAM_WRITETHRU XCHAL_SEP \
618 XTHAL_SAM_EXCEPTION XCHAL_SEP \
619 XTHAL_SAM_ISOLATE XCHAL_SEP \
620 XTHAL_SAM_EXCEPTION XCHAL_SEP \
624 read/only: 0 + 1 + 2 + 4 + 5 + 6 + 8 + 9 + 10 + 12 + 14
625 read/only: 0 + 1 + 2 + 4 + 5 + 6 + 8 + 9 + 10 + 12 + 14
626 all: 0 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8 + 9 + 10 + 11 + 12 + 13 + 14 + 15
627 fault: 0 + 2 + 4 + 6 + 8 + 10 + 12 + 14
632 load guard bit set: 1 + 3
633 load guard bit clr: 0 + 2 + 4 + 5 + 6 + 7 + 8 + 9 + 10 + 11 + 12 + 13 + 14 + 15
634 hit-cache r/w/x: 7 + 11
637 fams: 0 / 6 / 18 / 1 / 2
638 fams: Bypass / Isolate / Cached / Exception / NACached
644 /*----------------------------------------------------------------------
646 ----------------------------------------------------------------------*/
649 * General notes on MMU parameters.
652 * ASID = address-space ID (acts as an "extension" of virtual addresses)
653 * VPN = virtual page number
654 * PPN = physical page number
655 * CA = encoded cache attribute (access modes)
656 * TLB = translation look-aside buffer (term is stretched somewhat here)
657 * I = instruction (fetch accesses)
658 * D = data (load and store accesses)
659 * way = each TLB (ITLB and DTLB) consists of a number of "ways"
660 * that simultaneously match the virtual address of an access;
661 * a TLB successfully translates a virtual address if exactly
662 * one way matches the vaddr; if none match, it is a miss;
663 * if multiple match, one gets a "multihit" exception;
664 * each way can be independently configured in terms of number of
665 * entries, page sizes, which fields are writable or constant, etc.
666 * set = group of contiguous ways with exactly identical parameters
667 * ARF = auto-refill; hardware services a 1st-level miss by loading a PTE
668 * from the page table and storing it in one of the auto-refill ways;
669 * if this PTE load also misses, a miss exception is posted for s/w.
670 * min-wired = a "min-wired" way can be used to map a single (minimum-sized)
671 * page arbitrarily under program control; it has a single entry,
672 * is non-auto-refill (some other way(s) must be auto-refill),
673 * all its fields (VPN, PPN, ASID, CA) are all writable, and it
674 * supports the XCHAL_MMU_MIN_PTE_PAGE_SIZE page size (a current
675 * restriction is that this be the only page size it supports).
677 * TLB way entries are virtually indexed.
678 * TLB ways that support multiple page sizes:
679 * - must have all writable VPN and PPN fields;
680 * - can only use one page size at any given time (eg. setup at startup),
681 * selected by the respective ITLBCFG or DTLBCFG special register,
682 * whose bits n*4+3 .. n*4 index the list of page sizes for way n
683 * (XCHAL_xTLB_SETm_PAGESZ_LOG2_LIST for set m corresponding to way n);
684 * this list may be sparse for auto-refill ways because auto-refill
685 * ways have independent lists of supported page sizes sharing a
686 * common encoding with PTE entries; the encoding is the index into
687 * this list; unsupported sizes for a given way are zero in the list;
688 * selecting unsupported sizes results in undefined hardware behaviour;
689 * - is only possible for ways 0 thru 7 (due to ITLBCFG/DTLBCFG definition).
692 #define XCHAL_HAVE_CACHEATTR 0 /* 1 if CACHEATTR register present, 0 if TLBs present instead */
693 #define XCHAL_HAVE_TLBS 1 /* 1 if TLBs present, 0 if CACHEATTR present instead */
694 #define XCHAL_HAVE_MMU XCHAL_HAVE_TLBS /* (DEPRECATED; use XCHAL_HAVE_TLBS instead; will be removed in future release) */
695 #define XCHAL_HAVE_SPANNING_WAY 0 /* 1 if single way maps entire virtual address space in I+D */
696 #define XCHAL_HAVE_IDENTITY_MAP 0 /* 1 if virtual addr == physical addr always, 0 otherwise */
697 #define XCHAL_HAVE_MIMIC_CACHEATTR 0 /* 1 if have MMU that mimics a CACHEATTR config (CaMMU) */
698 #define XCHAL_HAVE_XLT_CACHEATTR 0 /* 1 if have MMU that mimics a CACHEATTR config, but with translation (CaXltMMU) */
700 #define XCHAL_MMU_ASID_BITS 8 /* number of bits in ASIDs (address space IDs) */
701 #define XCHAL_MMU_ASID_INVALID 0 /* ASID value indicating invalid address space */
702 #define XCHAL_MMU_ASID_KERNEL 1 /* ASID value indicating kernel (ring 0) address space */
703 #define XCHAL_MMU_RINGS 4 /* number of rings supported (1..4) */
704 #define XCHAL_MMU_RING_BITS 2 /* number of bits needed to hold ring number */
705 #define XCHAL_MMU_SR_BITS 0 /* number of size-restriction bits supported */
706 #define XCHAL_MMU_CA_BITS 4 /* number of bits needed to hold cache attribute encoding */
707 #define XCHAL_MMU_MAX_PTE_PAGE_SIZE 12 /* max page size in a PTE structure (log2) */
708 #define XCHAL_MMU_MIN_PTE_PAGE_SIZE 12 /* min page size in a PTE structure (log2) */
711 /*** Instruction TLB: ***/
713 #define XCHAL_ITLB_WAY_BITS 3 /* number of bits holding the ways */
714 #define XCHAL_ITLB_WAYS 7 /* number of ways (n-way set-associative TLB) */
715 #define XCHAL_ITLB_ARF_WAYS 4 /* number of auto-refill ways */
716 #define XCHAL_ITLB_SETS 4 /* number of sets (groups of ways with identical settings) */
718 /* Way set to which each way belongs: */
719 #define XCHAL_ITLB_WAY0_SET 0
720 #define XCHAL_ITLB_WAY1_SET 0
721 #define XCHAL_ITLB_WAY2_SET 0
722 #define XCHAL_ITLB_WAY3_SET 0
723 #define XCHAL_ITLB_WAY4_SET 1
724 #define XCHAL_ITLB_WAY5_SET 2
725 #define XCHAL_ITLB_WAY6_SET 3
727 /* Ways sets that are used by hardware auto-refill (ARF): */
728 #define XCHAL_ITLB_ARF_SETS 1 /* number of auto-refill sets */
729 #define XCHAL_ITLB_ARF_SET0 0 /* index of n'th auto-refill set */
731 /* Way sets that are "min-wired" (see terminology comment above): */
732 #define XCHAL_ITLB_MINWIRED_SETS 0 /* number of "min-wired" sets */
735 /* ITLB way set 0 (group of ways 0 thru 3): */
736 #define XCHAL_ITLB_SET0_WAY 0 /* index of first way in this way set */
737 #define XCHAL_ITLB_SET0_WAYS 4 /* number of (contiguous) ways in this way set */
738 #define XCHAL_ITLB_SET0_ENTRIES_LOG2 2 /* log2(number of entries in this way) */
739 #define XCHAL_ITLB_SET0_ENTRIES 4 /* number of entries in this way (always a power of 2) */
740 #define XCHAL_ITLB_SET0_ARF 1 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
741 #define XCHAL_ITLB_SET0_PAGESIZES 1 /* number of supported page sizes in this way */
742 #define XCHAL_ITLB_SET0_PAGESZ_BITS 0 /* number of bits to encode the page size */
743 #define XCHAL_ITLB_SET0_PAGESZ_LOG2_MIN 12 /* log2(minimum supported page size) */
744 #define XCHAL_ITLB_SET0_PAGESZ_LOG2_MAX 12 /* log2(maximum supported page size) */
745 #define XCHAL_ITLB_SET0_PAGESZ_LOG2_LIST 12 /* list of log2(page size)s, separated by XCHAL_SEP;
746 2^PAGESZ_BITS entries in list, unsupported entries are zero */
747 #define XCHAL_ITLB_SET0_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
748 #define XCHAL_ITLB_SET0_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */
749 #define XCHAL_ITLB_SET0_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */
750 #define XCHAL_ITLB_SET0_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
751 #define XCHAL_ITLB_SET0_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
752 #define XCHAL_ITLB_SET0_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
753 #define XCHAL_ITLB_SET0_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
754 #define XCHAL_ITLB_SET0_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */
756 /* ITLB way set 1 (group of ways 4 thru 4): */
757 #define XCHAL_ITLB_SET1_WAY 4 /* index of first way in this way set */
758 #define XCHAL_ITLB_SET1_WAYS 1 /* number of (contiguous) ways in this way set */
759 #define XCHAL_ITLB_SET1_ENTRIES_LOG2 2 /* log2(number of entries in this way) */
760 #define XCHAL_ITLB_SET1_ENTRIES 4 /* number of entries in this way (always a power of 2) */
761 #define XCHAL_ITLB_SET1_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
762 #define XCHAL_ITLB_SET1_PAGESIZES 4 /* number of supported page sizes in this way */
763 #define XCHAL_ITLB_SET1_PAGESZ_BITS 2 /* number of bits to encode the page size */
764 #define XCHAL_ITLB_SET1_PAGESZ_LOG2_MIN 20 /* log2(minimum supported page size) */
765 #define XCHAL_ITLB_SET1_PAGESZ_LOG2_MAX 26 /* log2(maximum supported page size) */
766 #define XCHAL_ITLB_SET1_PAGESZ_LOG2_LIST 20 XCHAL_SEP 22 XCHAL_SEP 24 XCHAL_SEP 26 /* list of log2(page size)s, separated by XCHAL_SEP;
767 2^PAGESZ_BITS entries in list, unsupported entries are zero */
768 #define XCHAL_ITLB_SET1_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
769 #define XCHAL_ITLB_SET1_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */
770 #define XCHAL_ITLB_SET1_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */
771 #define XCHAL_ITLB_SET1_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
772 #define XCHAL_ITLB_SET1_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
773 #define XCHAL_ITLB_SET1_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
774 #define XCHAL_ITLB_SET1_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
775 #define XCHAL_ITLB_SET1_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */
777 /* ITLB way set 2 (group of ways 5 thru 5): */
778 #define XCHAL_ITLB_SET2_WAY 5 /* index of first way in this way set */
779 #define XCHAL_ITLB_SET2_WAYS 1 /* number of (contiguous) ways in this way set */
780 #define XCHAL_ITLB_SET2_ENTRIES_LOG2 1 /* log2(number of entries in this way) */
781 #define XCHAL_ITLB_SET2_ENTRIES 2 /* number of entries in this way (always a power of 2) */
782 #define XCHAL_ITLB_SET2_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
783 #define XCHAL_ITLB_SET2_PAGESIZES 1 /* number of supported page sizes in this way */
784 #define XCHAL_ITLB_SET2_PAGESZ_BITS 0 /* number of bits to encode the page size */
785 #define XCHAL_ITLB_SET2_PAGESZ_LOG2_MIN 27 /* log2(minimum supported page size) */
786 #define XCHAL_ITLB_SET2_PAGESZ_LOG2_MAX 27 /* log2(maximum supported page size) */
787 #define XCHAL_ITLB_SET2_PAGESZ_LOG2_LIST 27 /* list of log2(page size)s, separated by XCHAL_SEP;
788 2^PAGESZ_BITS entries in list, unsupported entries are zero */
789 #define XCHAL_ITLB_SET2_ASID_CONSTMASK 0xFF /* constant ASID bits; 0 if all writable */
790 #define XCHAL_ITLB_SET2_VPN_CONSTMASK 0xF0000000 /* constant VPN bits, not including entry index bits; 0 if all writable */
791 #define XCHAL_ITLB_SET2_PPN_CONSTMASK 0xF8000000 /* constant PPN bits, including entry index bits; 0 if all writable */
792 #define XCHAL_ITLB_SET2_CA_CONSTMASK 0x0000000F /* constant CA bits; 0 if all writable */
793 #define XCHAL_ITLB_SET2_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
794 #define XCHAL_ITLB_SET2_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
795 #define XCHAL_ITLB_SET2_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
796 #define XCHAL_ITLB_SET2_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */
797 /* Constant ASID values for each entry of ITLB way set 2 (because ASID_CONSTMASK is non-zero): */
798 #define XCHAL_ITLB_SET2_E0_ASID_CONST 0x01
799 #define XCHAL_ITLB_SET2_E1_ASID_CONST 0x01
800 /* Constant VPN values for each entry of ITLB way set 2 (because VPN_CONSTMASK is non-zero): */
801 #define XCHAL_ITLB_SET2_E0_VPN_CONST 0xD0000000
802 #define XCHAL_ITLB_SET2_E1_VPN_CONST 0xD8000000
803 /* Constant PPN values for each entry of ITLB way set 2 (because PPN_CONSTMASK is non-zero): */
804 #define XCHAL_ITLB_SET2_E0_PPN_CONST 0x00000000
805 #define XCHAL_ITLB_SET2_E1_PPN_CONST 0x00000000
806 /* Constant CA values for each entry of ITLB way set 2 (because CA_CONSTMASK is non-zero): */
807 #define XCHAL_ITLB_SET2_E0_CA_CONST 0x07
808 #define XCHAL_ITLB_SET2_E1_CA_CONST 0x03
810 /* ITLB way set 3 (group of ways 6 thru 6): */
811 #define XCHAL_ITLB_SET3_WAY 6 /* index of first way in this way set */
812 #define XCHAL_ITLB_SET3_WAYS 1 /* number of (contiguous) ways in this way set */
813 #define XCHAL_ITLB_SET3_ENTRIES_LOG2 1 /* log2(number of entries in this way) */
814 #define XCHAL_ITLB_SET3_ENTRIES 2 /* number of entries in this way (always a power of 2) */
815 #define XCHAL_ITLB_SET3_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
816 #define XCHAL_ITLB_SET3_PAGESIZES 1 /* number of supported page sizes in this way */
817 #define XCHAL_ITLB_SET3_PAGESZ_BITS 0 /* number of bits to encode the page size */
818 #define XCHAL_ITLB_SET3_PAGESZ_LOG2_MIN 28 /* log2(minimum supported page size) */
819 #define XCHAL_ITLB_SET3_PAGESZ_LOG2_MAX 28 /* log2(maximum supported page size) */
820 #define XCHAL_ITLB_SET3_PAGESZ_LOG2_LIST 28 /* list of log2(page size)s, separated by XCHAL_SEP;
821 2^PAGESZ_BITS entries in list, unsupported entries are zero */
822 #define XCHAL_ITLB_SET3_ASID_CONSTMASK 0xFF /* constant ASID bits; 0 if all writable */
823 #define XCHAL_ITLB_SET3_VPN_CONSTMASK 0xE0000000 /* constant VPN bits, not including entry index bits; 0 if all writable */
824 #define XCHAL_ITLB_SET3_PPN_CONSTMASK 0xF0000000 /* constant PPN bits, including entry index bits; 0 if all writable */
825 #define XCHAL_ITLB_SET3_CA_CONSTMASK 0x0000000F /* constant CA bits; 0 if all writable */
826 #define XCHAL_ITLB_SET3_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
827 #define XCHAL_ITLB_SET3_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
828 #define XCHAL_ITLB_SET3_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
829 #define XCHAL_ITLB_SET3_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */
830 /* Constant ASID values for each entry of ITLB way set 3 (because ASID_CONSTMASK is non-zero): */
831 #define XCHAL_ITLB_SET3_E0_ASID_CONST 0x01
832 #define XCHAL_ITLB_SET3_E1_ASID_CONST 0x01
833 /* Constant VPN values for each entry of ITLB way set 3 (because VPN_CONSTMASK is non-zero): */
834 #define XCHAL_ITLB_SET3_E0_VPN_CONST 0xE0000000
835 #define XCHAL_ITLB_SET3_E1_VPN_CONST 0xF0000000
836 /* Constant PPN values for each entry of ITLB way set 3 (because PPN_CONSTMASK is non-zero): */
837 #define XCHAL_ITLB_SET3_E0_PPN_CONST 0xF0000000
838 #define XCHAL_ITLB_SET3_E1_PPN_CONST 0xF0000000
839 /* Constant CA values for each entry of ITLB way set 3 (because CA_CONSTMASK is non-zero): */
840 #define XCHAL_ITLB_SET3_E0_CA_CONST 0x07
841 #define XCHAL_ITLB_SET3_E1_CA_CONST 0x03
843 /* Indexing macros: */
844 #define _XCHAL_ITLB_SET(n,_what) XCHAL_ITLB_SET ## n ## _what
845 #define XCHAL_ITLB_SET(n,what) _XCHAL_ITLB_SET(n, _ ## what )
846 #define _XCHAL_ITLB_SET_E(n,i,_what) XCHAL_ITLB_SET ## n ## _E ## i ## _what
847 #define XCHAL_ITLB_SET_E(n,i,what) _XCHAL_ITLB_SET_E(n,i, _ ## what )
849 * Example use: XCHAL_ITLB_SET(XCHAL_ITLB_ARF_SET0,ENTRIES)
850 * to get the value of XCHAL_ITLB_SET<n>_ENTRIES where <n> is the first auto-refill set.
856 #define XCHAL_DTLB_WAY_BITS 4 /* number of bits holding the ways */
857 #define XCHAL_DTLB_WAYS 10 /* number of ways (n-way set-associative TLB) */
858 #define XCHAL_DTLB_ARF_WAYS 4 /* number of auto-refill ways */
859 #define XCHAL_DTLB_SETS 5 /* number of sets (groups of ways with identical settings) */
861 /* Way set to which each way belongs: */
862 #define XCHAL_DTLB_WAY0_SET 0
863 #define XCHAL_DTLB_WAY1_SET 0
864 #define XCHAL_DTLB_WAY2_SET 0
865 #define XCHAL_DTLB_WAY3_SET 0
866 #define XCHAL_DTLB_WAY4_SET 1
867 #define XCHAL_DTLB_WAY5_SET 2
868 #define XCHAL_DTLB_WAY6_SET 3
869 #define XCHAL_DTLB_WAY7_SET 4
870 #define XCHAL_DTLB_WAY8_SET 4
871 #define XCHAL_DTLB_WAY9_SET 4
873 /* Ways sets that are used by hardware auto-refill (ARF): */
874 #define XCHAL_DTLB_ARF_SETS 1 /* number of auto-refill sets */
875 #define XCHAL_DTLB_ARF_SET0 0 /* index of n'th auto-refill set */
877 /* Way sets that are "min-wired" (see terminology comment above): */
878 #define XCHAL_DTLB_MINWIRED_SETS 1 /* number of "min-wired" sets */
879 #define XCHAL_DTLB_MINWIRED_SET0 4 /* index of n'th "min-wired" set */
882 /* DTLB way set 0 (group of ways 0 thru 3): */
883 #define XCHAL_DTLB_SET0_WAY 0 /* index of first way in this way set */
884 #define XCHAL_DTLB_SET0_WAYS 4 /* number of (contiguous) ways in this way set */
885 #define XCHAL_DTLB_SET0_ENTRIES_LOG2 2 /* log2(number of entries in this way) */
886 #define XCHAL_DTLB_SET0_ENTRIES 4 /* number of entries in this way (always a power of 2) */
887 #define XCHAL_DTLB_SET0_ARF 1 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
888 #define XCHAL_DTLB_SET0_PAGESIZES 1 /* number of supported page sizes in this way */
889 #define XCHAL_DTLB_SET0_PAGESZ_BITS 0 /* number of bits to encode the page size */
890 #define XCHAL_DTLB_SET0_PAGESZ_LOG2_MIN 12 /* log2(minimum supported page size) */
891 #define XCHAL_DTLB_SET0_PAGESZ_LOG2_MAX 12 /* log2(maximum supported page size) */
892 #define XCHAL_DTLB_SET0_PAGESZ_LOG2_LIST 12 /* list of log2(page size)s, separated by XCHAL_SEP;
893 2^PAGESZ_BITS entries in list, unsupported entries are zero */
894 #define XCHAL_DTLB_SET0_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
895 #define XCHAL_DTLB_SET0_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */
896 #define XCHAL_DTLB_SET0_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */
897 #define XCHAL_DTLB_SET0_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
898 #define XCHAL_DTLB_SET0_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
899 #define XCHAL_DTLB_SET0_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
900 #define XCHAL_DTLB_SET0_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
901 #define XCHAL_DTLB_SET0_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */
903 /* DTLB way set 1 (group of ways 4 thru 4): */
904 #define XCHAL_DTLB_SET1_WAY 4 /* index of first way in this way set */
905 #define XCHAL_DTLB_SET1_WAYS 1 /* number of (contiguous) ways in this way set */
906 #define XCHAL_DTLB_SET1_ENTRIES_LOG2 2 /* log2(number of entries in this way) */
907 #define XCHAL_DTLB_SET1_ENTRIES 4 /* number of entries in this way (always a power of 2) */
908 #define XCHAL_DTLB_SET1_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
909 #define XCHAL_DTLB_SET1_PAGESIZES 4 /* number of supported page sizes in this way */
910 #define XCHAL_DTLB_SET1_PAGESZ_BITS 2 /* number of bits to encode the page size */
911 #define XCHAL_DTLB_SET1_PAGESZ_LOG2_MIN 20 /* log2(minimum supported page size) */
912 #define XCHAL_DTLB_SET1_PAGESZ_LOG2_MAX 26 /* log2(maximum supported page size) */
913 #define XCHAL_DTLB_SET1_PAGESZ_LOG2_LIST 20 XCHAL_SEP 22 XCHAL_SEP 24 XCHAL_SEP 26 /* list of log2(page size)s, separated by XCHAL_SEP;
914 2^PAGESZ_BITS entries in list, unsupported entries are zero */
915 #define XCHAL_DTLB_SET1_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
916 #define XCHAL_DTLB_SET1_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */
917 #define XCHAL_DTLB_SET1_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */
918 #define XCHAL_DTLB_SET1_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
919 #define XCHAL_DTLB_SET1_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
920 #define XCHAL_DTLB_SET1_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
921 #define XCHAL_DTLB_SET1_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
922 #define XCHAL_DTLB_SET1_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */
924 /* DTLB way set 2 (group of ways 5 thru 5): */
925 #define XCHAL_DTLB_SET2_WAY 5 /* index of first way in this way set */
926 #define XCHAL_DTLB_SET2_WAYS 1 /* number of (contiguous) ways in this way set */
927 #define XCHAL_DTLB_SET2_ENTRIES_LOG2 1 /* log2(number of entries in this way) */
928 #define XCHAL_DTLB_SET2_ENTRIES 2 /* number of entries in this way (always a power of 2) */
929 #define XCHAL_DTLB_SET2_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
930 #define XCHAL_DTLB_SET2_PAGESIZES 1 /* number of supported page sizes in this way */
931 #define XCHAL_DTLB_SET2_PAGESZ_BITS 0 /* number of bits to encode the page size */
932 #define XCHAL_DTLB_SET2_PAGESZ_LOG2_MIN 27 /* log2(minimum supported page size) */
933 #define XCHAL_DTLB_SET2_PAGESZ_LOG2_MAX 27 /* log2(maximum supported page size) */
934 #define XCHAL_DTLB_SET2_PAGESZ_LOG2_LIST 27 /* list of log2(page size)s, separated by XCHAL_SEP;
935 2^PAGESZ_BITS entries in list, unsupported entries are zero */
936 #define XCHAL_DTLB_SET2_ASID_CONSTMASK 0xFF /* constant ASID bits; 0 if all writable */
937 #define XCHAL_DTLB_SET2_VPN_CONSTMASK 0xF0000000 /* constant VPN bits, not including entry index bits; 0 if all writable */
938 #define XCHAL_DTLB_SET2_PPN_CONSTMASK 0xF8000000 /* constant PPN bits, including entry index bits; 0 if all writable */
939 #define XCHAL_DTLB_SET2_CA_CONSTMASK 0x0000000F /* constant CA bits; 0 if all writable */
940 #define XCHAL_DTLB_SET2_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
941 #define XCHAL_DTLB_SET2_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
942 #define XCHAL_DTLB_SET2_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
943 #define XCHAL_DTLB_SET2_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */
944 /* Constant ASID values for each entry of DTLB way set 2 (because ASID_CONSTMASK is non-zero): */
945 #define XCHAL_DTLB_SET2_E0_ASID_CONST 0x01
946 #define XCHAL_DTLB_SET2_E1_ASID_CONST 0x01
947 /* Constant VPN values for each entry of DTLB way set 2 (because VPN_CONSTMASK is non-zero): */
948 #define XCHAL_DTLB_SET2_E0_VPN_CONST 0xD0000000
949 #define XCHAL_DTLB_SET2_E1_VPN_CONST 0xD8000000
950 /* Constant PPN values for each entry of DTLB way set 2 (because PPN_CONSTMASK is non-zero): */
951 #define XCHAL_DTLB_SET2_E0_PPN_CONST 0x00000000
952 #define XCHAL_DTLB_SET2_E1_PPN_CONST 0x00000000
953 /* Constant CA values for each entry of DTLB way set 2 (because CA_CONSTMASK is non-zero): */
954 #define XCHAL_DTLB_SET2_E0_CA_CONST 0x07
955 #define XCHAL_DTLB_SET2_E1_CA_CONST 0x03
957 /* DTLB way set 3 (group of ways 6 thru 6): */
958 #define XCHAL_DTLB_SET3_WAY 6 /* index of first way in this way set */
959 #define XCHAL_DTLB_SET3_WAYS 1 /* number of (contiguous) ways in this way set */
960 #define XCHAL_DTLB_SET3_ENTRIES_LOG2 1 /* log2(number of entries in this way) */
961 #define XCHAL_DTLB_SET3_ENTRIES 2 /* number of entries in this way (always a power of 2) */
962 #define XCHAL_DTLB_SET3_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
963 #define XCHAL_DTLB_SET3_PAGESIZES 1 /* number of supported page sizes in this way */
964 #define XCHAL_DTLB_SET3_PAGESZ_BITS 0 /* number of bits to encode the page size */
965 #define XCHAL_DTLB_SET3_PAGESZ_LOG2_MIN 28 /* log2(minimum supported page size) */
966 #define XCHAL_DTLB_SET3_PAGESZ_LOG2_MAX 28 /* log2(maximum supported page size) */
967 #define XCHAL_DTLB_SET3_PAGESZ_LOG2_LIST 28 /* list of log2(page size)s, separated by XCHAL_SEP;
968 2^PAGESZ_BITS entries in list, unsupported entries are zero */
969 #define XCHAL_DTLB_SET3_ASID_CONSTMASK 0xFF /* constant ASID bits; 0 if all writable */
970 #define XCHAL_DTLB_SET3_VPN_CONSTMASK 0xE0000000 /* constant VPN bits, not including entry index bits; 0 if all writable */
971 #define XCHAL_DTLB_SET3_PPN_CONSTMASK 0xF0000000 /* constant PPN bits, including entry index bits; 0 if all writable */
972 #define XCHAL_DTLB_SET3_CA_CONSTMASK 0x0000000F /* constant CA bits; 0 if all writable */
973 #define XCHAL_DTLB_SET3_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
974 #define XCHAL_DTLB_SET3_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
975 #define XCHAL_DTLB_SET3_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
976 #define XCHAL_DTLB_SET3_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */
977 /* Constant ASID values for each entry of DTLB way set 3 (because ASID_CONSTMASK is non-zero): */
978 #define XCHAL_DTLB_SET3_E0_ASID_CONST 0x01
979 #define XCHAL_DTLB_SET3_E1_ASID_CONST 0x01
980 /* Constant VPN values for each entry of DTLB way set 3 (because VPN_CONSTMASK is non-zero): */
981 #define XCHAL_DTLB_SET3_E0_VPN_CONST 0xE0000000
982 #define XCHAL_DTLB_SET3_E1_VPN_CONST 0xF0000000
983 /* Constant PPN values for each entry of DTLB way set 3 (because PPN_CONSTMASK is non-zero): */
984 #define XCHAL_DTLB_SET3_E0_PPN_CONST 0xF0000000
985 #define XCHAL_DTLB_SET3_E1_PPN_CONST 0xF0000000
986 /* Constant CA values for each entry of DTLB way set 3 (because CA_CONSTMASK is non-zero): */
987 #define XCHAL_DTLB_SET3_E0_CA_CONST 0x07
988 #define XCHAL_DTLB_SET3_E1_CA_CONST 0x03
990 /* DTLB way set 4 (group of ways 7 thru 9): */
991 #define XCHAL_DTLB_SET4_WAY 7 /* index of first way in this way set */
992 #define XCHAL_DTLB_SET4_WAYS 3 /* number of (contiguous) ways in this way set */
993 #define XCHAL_DTLB_SET4_ENTRIES_LOG2 0 /* log2(number of entries in this way) */
994 #define XCHAL_DTLB_SET4_ENTRIES 1 /* number of entries in this way (always a power of 2) */
995 #define XCHAL_DTLB_SET4_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
996 #define XCHAL_DTLB_SET4_PAGESIZES 1 /* number of supported page sizes in this way */
997 #define XCHAL_DTLB_SET4_PAGESZ_BITS 0 /* number of bits to encode the page size */
998 #define XCHAL_DTLB_SET4_PAGESZ_LOG2_MIN 12 /* log2(minimum supported page size) */
999 #define XCHAL_DTLB_SET4_PAGESZ_LOG2_MAX 12 /* log2(maximum supported page size) */
1000 #define XCHAL_DTLB_SET4_PAGESZ_LOG2_LIST 12 /* list of log2(page size)s, separated by XCHAL_SEP;
1001 2^PAGESZ_BITS entries in list, unsupported entries are zero */
1002 #define XCHAL_DTLB_SET4_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
1003 #define XCHAL_DTLB_SET4_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */
1004 #define XCHAL_DTLB_SET4_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */
1005 #define XCHAL_DTLB_SET4_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
1006 #define XCHAL_DTLB_SET4_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
1007 #define XCHAL_DTLB_SET4_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
1008 #define XCHAL_DTLB_SET4_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
1009 #define XCHAL_DTLB_SET4_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */
1011 /* Indexing macros: */
1012 #define _XCHAL_DTLB_SET(n,_what) XCHAL_DTLB_SET ## n ## _what
1013 #define XCHAL_DTLB_SET(n,what) _XCHAL_DTLB_SET(n, _ ## what )
1014 #define _XCHAL_DTLB_SET_E(n,i,_what) XCHAL_DTLB_SET ## n ## _E ## i ## _what
1015 #define XCHAL_DTLB_SET_E(n,i,what) _XCHAL_DTLB_SET_E(n,i, _ ## what )
1017 * Example use: XCHAL_DTLB_SET(XCHAL_DTLB_ARF_SET0,ENTRIES)
1018 * to get the value of XCHAL_DTLB_SET<n>_ENTRIES where <n> is the first auto-refill set.
1023 * Determine whether we have a full MMU (with Page Table and Protection)
1024 * usable for an MMU-based OS:
1026 #if XCHAL_HAVE_TLBS && !XCHAL_HAVE_SPANNING_WAY && XCHAL_ITLB_ARF_WAYS > 0 && XCHAL_DTLB_ARF_WAYS > 0 && XCHAL_MMU_RINGS >= 2
1027 # define XCHAL_HAVE_PTP_MMU 1 /* have full MMU (with page table [autorefill] and protection) */
1029 # define XCHAL_HAVE_PTP_MMU 0 /* don't have full MMU */
1033 * For full MMUs, report kernel RAM segment and kernel I/O segment static page mappings:
1035 #if XCHAL_HAVE_PTP_MMU
1036 #define XCHAL_KSEG_CACHED_VADDR 0xD0000000 /* virt.addr of kernel RAM cached static map */
1037 #define XCHAL_KSEG_CACHED_PADDR 0x00000000 /* phys.addr of kseg_cached */
1038 #define XCHAL_KSEG_CACHED_SIZE 0x08000000 /* size in bytes of kseg_cached (assumed power of 2!!!) */
1039 #define XCHAL_KSEG_BYPASS_VADDR 0xD8000000 /* virt.addr of kernel RAM bypass (uncached) static map */
1040 #define XCHAL_KSEG_BYPASS_PADDR 0x00000000 /* phys.addr of kseg_bypass */
1041 #define XCHAL_KSEG_BYPASS_SIZE 0x08000000 /* size in bytes of kseg_bypass (assumed power of 2!!!) */
1043 #define XCHAL_KIO_CACHED_VADDR 0xE0000000 /* virt.addr of kernel I/O cached static map */
1044 #define XCHAL_KIO_CACHED_PADDR 0xF0000000 /* phys.addr of kio_cached */
1045 #define XCHAL_KIO_CACHED_SIZE 0x10000000 /* size in bytes of kio_cached (assumed power of 2!!!) */
1046 #define XCHAL_KIO_BYPASS_VADDR 0xF0000000 /* virt.addr of kernel I/O bypass (uncached) static map */
1047 #define XCHAL_KIO_BYPASS_PADDR 0xF0000000 /* phys.addr of kio_bypass */
1048 #define XCHAL_KIO_BYPASS_SIZE 0x10000000 /* size in bytes of kio_bypass (assumed power of 2!!!) */
1050 #define XCHAL_SEG_MAPPABLE_VADDR 0x00000000 /* start of largest non-static-mapped virtual addr area */
1051 #define XCHAL_SEG_MAPPABLE_SIZE 0xD0000000 /* size in bytes of " */
1052 /* define XCHAL_SEG_MAPPABLE2_xxx if more areas present, sorted in order of descending size. */
1056 /*----------------------------------------------------------------------
1058 ----------------------------------------------------------------------*/
1060 #define XCHAL_NUM_WRITEBUFFER_ENTRIES 4 /* number of write buffer entries */
1062 #define XCHAL_CORE_ID "linux_be" /* configuration's alphanumeric core identifier
1063 (CoreID) set in the Xtensa Processor Generator */
1065 #define XCHAL_BUILD_UNIQUE_ID 0x00003256 /* software build-unique ID (22-bit) */
1067 /* These definitions describe the hardware targeted by this software: */
1068 #define XCHAL_HW_CONFIGID0 0xC103D1FF /* config ID reg 0 value (upper 32 of 64 bits) */
1069 #define XCHAL_HW_CONFIGID1 0x00803256 /* config ID reg 1 value (lower 32 of 64 bits) */
1070 #define XCHAL_CONFIGID0 XCHAL_HW_CONFIGID0 /* for backward compatibility only -- don't use! */
1071 #define XCHAL_CONFIGID1 XCHAL_HW_CONFIGID1 /* for backward compatibility only -- don't use! */
1072 #define XCHAL_HW_RELEASE_MAJOR 1050 /* major release of targeted hardware */
1073 #define XCHAL_HW_RELEASE_MINOR 1 /* minor release of targeted hardware */
1074 #define XCHAL_HW_RELEASE_NAME "T1050.1" /* full release name of targeted hardware */
1075 #define XTHAL_HW_REL_T1050 1
1076 #define XTHAL_HW_REL_T1050_1 1
1077 #define XCHAL_HW_CONFIGID_RELIABLE 1
1081 * Miscellaneous special register fields:
1085 /* DBREAKC (special register number 160): */
1086 #define XCHAL_DBREAKC_VALIDMASK 0xC000003F /* bits of DBREAKC that are defined */
1088 #define XCHAL_DBREAKC_MASK_BITS 6 /* number of bits in MASK field */
1089 #define XCHAL_DBREAKC_MASK_NUM 64 /* max number of possible causes (2^bits) */
1090 #define XCHAL_DBREAKC_MASK_SHIFT 0 /* position of MASK bits in DBREAKC, starting from lsbit */
1091 #define XCHAL_DBREAKC_MASK_MASK 0x0000003F /* mask of bits in MASK field of DBREAKC */
1092 /* LOADBREAK field: */
1093 #define XCHAL_DBREAKC_LOADBREAK_BITS 1 /* number of bits in LOADBREAK field */
1094 #define XCHAL_DBREAKC_LOADBREAK_NUM 2 /* max number of possible causes (2^bits) */
1095 #define XCHAL_DBREAKC_LOADBREAK_SHIFT 30 /* position of LOADBREAK bits in DBREAKC, starting from lsbit */
1096 #define XCHAL_DBREAKC_LOADBREAK_MASK 0x40000000 /* mask of bits in LOADBREAK field of DBREAKC */
1097 /* STOREBREAK field: */
1098 #define XCHAL_DBREAKC_STOREBREAK_BITS 1 /* number of bits in STOREBREAK field */
1099 #define XCHAL_DBREAKC_STOREBREAK_NUM 2 /* max number of possible causes (2^bits) */
1100 #define XCHAL_DBREAKC_STOREBREAK_SHIFT 31 /* position of STOREBREAK bits in DBREAKC, starting from lsbit */
1101 #define XCHAL_DBREAKC_STOREBREAK_MASK 0x80000000 /* mask of bits in STOREBREAK field of DBREAKC */
1103 /* PS (special register number 230): */
1104 #define XCHAL_PS_VALIDMASK 0x00070FFF /* bits of PS that are defined */
1105 /* INTLEVEL field: */
1106 #define XCHAL_PS_INTLEVEL_BITS 4 /* number of bits in INTLEVEL field */
1107 #define XCHAL_PS_INTLEVEL_NUM 16 /* max number of possible causes (2^bits) */
1108 #define XCHAL_PS_INTLEVEL_SHIFT 0 /* position of INTLEVEL bits in PS, starting from lsbit */
1109 #define XCHAL_PS_INTLEVEL_MASK 0x0000000F /* mask of bits in INTLEVEL field of PS */
1111 #define XCHAL_PS_EXCM_BITS 1 /* number of bits in EXCM field */
1112 #define XCHAL_PS_EXCM_NUM 2 /* max number of possible causes (2^bits) */
1113 #define XCHAL_PS_EXCM_SHIFT 4 /* position of EXCM bits in PS, starting from lsbit */
1114 #define XCHAL_PS_EXCM_MASK 0x00000010 /* mask of bits in EXCM field of PS */
1115 /* PROGSTACK field: */
1116 #define XCHAL_PS_PROGSTACK_BITS 1 /* number of bits in PROGSTACK field */
1117 #define XCHAL_PS_PROGSTACK_NUM 2 /* max number of possible causes (2^bits) */
1118 #define XCHAL_PS_PROGSTACK_SHIFT 5 /* position of PROGSTACK bits in PS, starting from lsbit */
1119 #define XCHAL_PS_PROGSTACK_MASK 0x00000020 /* mask of bits in PROGSTACK field of PS */
1121 #define XCHAL_PS_RING_BITS 2 /* number of bits in RING field */
1122 #define XCHAL_PS_RING_NUM 4 /* max number of possible causes (2^bits) */
1123 #define XCHAL_PS_RING_SHIFT 6 /* position of RING bits in PS, starting from lsbit */
1124 #define XCHAL_PS_RING_MASK 0x000000C0 /* mask of bits in RING field of PS */
1126 #define XCHAL_PS_OWB_BITS 4 /* number of bits in OWB field */
1127 #define XCHAL_PS_OWB_NUM 16 /* max number of possible causes (2^bits) */
1128 #define XCHAL_PS_OWB_SHIFT 8 /* position of OWB bits in PS, starting from lsbit */
1129 #define XCHAL_PS_OWB_MASK 0x00000F00 /* mask of bits in OWB field of PS */
1130 /* CALLINC field: */
1131 #define XCHAL_PS_CALLINC_BITS 2 /* number of bits in CALLINC field */
1132 #define XCHAL_PS_CALLINC_NUM 4 /* max number of possible causes (2^bits) */
1133 #define XCHAL_PS_CALLINC_SHIFT 16 /* position of CALLINC bits in PS, starting from lsbit */
1134 #define XCHAL_PS_CALLINC_MASK 0x00030000 /* mask of bits in CALLINC field of PS */
1136 #define XCHAL_PS_WOE_BITS 1 /* number of bits in WOE field */
1137 #define XCHAL_PS_WOE_NUM 2 /* max number of possible causes (2^bits) */
1138 #define XCHAL_PS_WOE_SHIFT 18 /* position of WOE bits in PS, starting from lsbit */
1139 #define XCHAL_PS_WOE_MASK 0x00040000 /* mask of bits in WOE field of PS */
1141 /* EXCCAUSE (special register number 232): */
1142 #define XCHAL_EXCCAUSE_VALIDMASK 0x0000003F /* bits of EXCCAUSE that are defined */
1143 /* EXCCAUSE field: */
1144 #define XCHAL_EXCCAUSE_BITS 6 /* number of bits in EXCCAUSE register */
1145 #define XCHAL_EXCCAUSE_NUM 64 /* max number of possible causes (2^bits) */
1146 #define XCHAL_EXCCAUSE_SHIFT 0 /* position of EXCCAUSE bits in register, starting from lsbit */
1147 #define XCHAL_EXCCAUSE_MASK 0x0000003F /* mask of bits in EXCCAUSE register */
1149 /* DEBUGCAUSE (special register number 233): */
1150 #define XCHAL_DEBUGCAUSE_VALIDMASK 0x0000003F /* bits of DEBUGCAUSE that are defined */
1152 #define XCHAL_DEBUGCAUSE_ICOUNT_BITS 1 /* number of bits in ICOUNT field */
1153 #define XCHAL_DEBUGCAUSE_ICOUNT_NUM 2 /* max number of possible causes (2^bits) */
1154 #define XCHAL_DEBUGCAUSE_ICOUNT_SHIFT 0 /* position of ICOUNT bits in DEBUGCAUSE, starting from lsbit */
1155 #define XCHAL_DEBUGCAUSE_ICOUNT_MASK 0x00000001 /* mask of bits in ICOUNT field of DEBUGCAUSE */
1157 #define XCHAL_DEBUGCAUSE_IBREAK_BITS 1 /* number of bits in IBREAK field */
1158 #define XCHAL_DEBUGCAUSE_IBREAK_NUM 2 /* max number of possible causes (2^bits) */
1159 #define XCHAL_DEBUGCAUSE_IBREAK_SHIFT 1 /* position of IBREAK bits in DEBUGCAUSE, starting from lsbit */
1160 #define XCHAL_DEBUGCAUSE_IBREAK_MASK 0x00000002 /* mask of bits in IBREAK field of DEBUGCAUSE */
1162 #define XCHAL_DEBUGCAUSE_DBREAK_BITS 1 /* number of bits in DBREAK field */
1163 #define XCHAL_DEBUGCAUSE_DBREAK_NUM 2 /* max number of possible causes (2^bits) */
1164 #define XCHAL_DEBUGCAUSE_DBREAK_SHIFT 2 /* position of DBREAK bits in DEBUGCAUSE, starting from lsbit */
1165 #define XCHAL_DEBUGCAUSE_DBREAK_MASK 0x00000004 /* mask of bits in DBREAK field of DEBUGCAUSE */
1167 #define XCHAL_DEBUGCAUSE_BREAK_BITS 1 /* number of bits in BREAK field */
1168 #define XCHAL_DEBUGCAUSE_BREAK_NUM 2 /* max number of possible causes (2^bits) */
1169 #define XCHAL_DEBUGCAUSE_BREAK_SHIFT 3 /* position of BREAK bits in DEBUGCAUSE, starting from lsbit */
1170 #define XCHAL_DEBUGCAUSE_BREAK_MASK 0x00000008 /* mask of bits in BREAK field of DEBUGCAUSE */
1172 #define XCHAL_DEBUGCAUSE_BREAKN_BITS 1 /* number of bits in BREAKN field */
1173 #define XCHAL_DEBUGCAUSE_BREAKN_NUM 2 /* max number of possible causes (2^bits) */
1174 #define XCHAL_DEBUGCAUSE_BREAKN_SHIFT 4 /* position of BREAKN bits in DEBUGCAUSE, starting from lsbit */
1175 #define XCHAL_DEBUGCAUSE_BREAKN_MASK 0x00000010 /* mask of bits in BREAKN field of DEBUGCAUSE */
1176 /* DEBUGINT field: */
1177 #define XCHAL_DEBUGCAUSE_DEBUGINT_BITS 1 /* number of bits in DEBUGINT field */
1178 #define XCHAL_DEBUGCAUSE_DEBUGINT_NUM 2 /* max number of possible causes (2^bits) */
1179 #define XCHAL_DEBUGCAUSE_DEBUGINT_SHIFT 5 /* position of DEBUGINT bits in DEBUGCAUSE, starting from lsbit */
1180 #define XCHAL_DEBUGCAUSE_DEBUGINT_MASK 0x00000020 /* mask of bits in DEBUGINT field of DEBUGCAUSE */
1184 /*----------------------------------------------------------------------
1186 ----------------------------------------------------------------------*/
1188 #define XCHAL_HAVE_DENSITY 1 /* 1 if density option configured, 0 otherwise */
1189 #define XCHAL_HAVE_LOOPS 1 /* 1 if zero-overhead loops option configured, 0 otherwise */
1190 /* Misc instructions: */
1191 #define XCHAL_HAVE_NSA 0 /* 1 if NSA/NSAU instructions option configured, 0 otherwise */
1192 #define XCHAL_HAVE_MINMAX 0 /* 1 if MIN/MAX instructions option configured, 0 otherwise */
1193 #define XCHAL_HAVE_SEXT 0 /* 1 if sign-extend instruction option configured, 0 otherwise */
1194 #define XCHAL_HAVE_CLAMPS 0 /* 1 if CLAMPS instruction option configured, 0 otherwise */
1195 #define XCHAL_HAVE_MAC16 0 /* 1 if MAC16 option configured, 0 otherwise */
1196 #define XCHAL_HAVE_MUL16 0 /* 1 if 16-bit integer multiply option configured, 0 otherwise */
1197 /*#define XCHAL_HAVE_POPC 0*/ /* 1 if CRC instruction option configured, 0 otherwise */
1198 /*#define XCHAL_HAVE_CRC 0*/ /* 1 if POPC instruction option configured, 0 otherwise */
1200 #define XCHAL_HAVE_SPECULATION 0 /* 1 if speculation option configured, 0 otherwise */
1201 /*#define XCHAL_HAVE_MP_SYNC 0*/ /* 1 if multiprocessor sync. option configured, 0 otherwise */
1202 #define XCHAL_HAVE_PRID 0 /* 1 if processor ID register configured, 0 otherwise */
1204 #define XCHAL_NUM_MISC_REGS 2 /* number of miscellaneous registers (0..4) */
1206 /* These relate a bit more to TIE: */
1207 #define XCHAL_HAVE_BOOLEANS 0 /* 1 if booleans option configured, 0 otherwise */
1208 #define XCHAL_HAVE_MUL32 0 /* 1 if 32-bit integer multiply option configured, 0 otherwise */
1209 #define XCHAL_HAVE_MUL32_HIGH 0 /* 1 if MUL32 option includes MULUH and MULSH, 0 otherwise */
1210 #define XCHAL_HAVE_FP 0 /* 1 if floating point option configured, 0 otherwise */
1213 /*----------------------------------------------------------------------
1215 ----------------------------------------------------------------------*/
1218 #define XCHAL_INST_ILLN 0xD60F /* 2-byte illegal instruction, msb-first */
1219 #define XCHAL_INST_ILLN_BYTE0 0xD6 /* 2-byte illegal instruction, 1st byte */
1220 #define XCHAL_INST_ILLN_BYTE1 0x0F /* 2-byte illegal instruction, 2nd byte */
1222 #define XCHAL_INST_ILLN 0xF06D /* 2-byte illegal instruction, lsb-first */
1223 #define XCHAL_INST_ILLN_BYTE0 0x6D /* 2-byte illegal instruction, 1st byte */
1224 #define XCHAL_INST_ILLN_BYTE1 0xF0 /* 2-byte illegal instruction, 2nd byte */
1226 /* Belongs in xtensa/hal.h: */
1227 #define XTHAL_INST_ILL 0x000000 /* 3-byte illegal instruction */
1231 * Because information as to exactly which hardware release is targeted
1232 * by a given software build is not always available, compile-time HAL
1233 * Hardware-Release "_AT" macros are fuzzy (return 0, 1, or XCHAL_MAYBE):
1235 #ifndef XCHAL_HW_RELEASE_MAJOR
1236 # define XCHAL_HW_CONFIGID_RELIABLE 0
1238 #if XCHAL_HW_CONFIGID_RELIABLE
1239 # define XCHAL_HW_RELEASE_AT_OR_BELOW(major,minor) (XTHAL_REL_LE( XCHAL_HW_RELEASE_MAJOR,XCHAL_HW_RELEASE_MINOR, major,minor ) ? 1 : 0)
1240 # define XCHAL_HW_RELEASE_AT_OR_ABOVE(major,minor) (XTHAL_REL_GE( XCHAL_HW_RELEASE_MAJOR,XCHAL_HW_RELEASE_MINOR, major,minor ) ? 1 : 0)
1241 # define XCHAL_HW_RELEASE_AT(major,minor) (XTHAL_REL_EQ( XCHAL_HW_RELEASE_MAJOR,XCHAL_HW_RELEASE_MINOR, major,minor ) ? 1 : 0)
1242 # define XCHAL_HW_RELEASE_MAJOR_AT(major) ((XCHAL_HW_RELEASE_MAJOR == (major)) ? 1 : 0)
1244 # define XCHAL_HW_RELEASE_AT_OR_BELOW(major,minor) ( ((major) < 1040 && XCHAL_HAVE_XEA2) ? 0 \
1245 : ((major) > 1050 && XCHAL_HAVE_XEA1) ? 1 \
1247 # define XCHAL_HW_RELEASE_AT_OR_ABOVE(major,minor) ( ((major) >= 2000 && XCHAL_HAVE_XEA1) ? 0 \
1248 : (XTHAL_REL_LE(major,minor, 1040,0) && XCHAL_HAVE_XEA2) ? 1 \
1250 # define XCHAL_HW_RELEASE_AT(major,minor) ( (((major) < 1040 && XCHAL_HAVE_XEA2) || \
1251 ((major) >= 2000 && XCHAL_HAVE_XEA1)) ? 0 : XTHAL_MAYBE)
1252 # define XCHAL_HW_RELEASE_MAJOR_AT(major) XCHAL_HW_RELEASE_AT(major,0)
1260 * Erratum T1020.H13, T1030.H7, T1040.H10, T1050.H4 (fixed in T1040.3 and T1050.1;
1261 * relevant only in XEA1, kernel-vector mode, level-one interrupts and overflows enabled):
1263 #define XCHAL_MAYHAVE_ERRATUM_XEA1KWIN (XCHAL_HAVE_XEA1 && \
1264 (XCHAL_HW_RELEASE_AT_OR_BELOW(1040,2) != 0 \
1265 || XCHAL_HW_RELEASE_AT(1050,0)))
1269 #endif /*XTENSA_CONFIG_CORE_H*/
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