git.oblomov.eu Git - linux-2.6/blob - arch/x86/kvm/svm.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * AMD SVM support
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  *
   8  * Authors:
   9  *   Yaniv Kamay  <yaniv@qumranet.com>
  10  *   Avi Kivity   <avi@qumranet.com>
  11  *
  12  * This work is licensed under the terms of the GNU GPL, version 2.  See
  13  * the COPYING file in the top-level directory.
  14  *
  15  */
  16 #include <linux/kvm_host.h>
  17
  18 #include "kvm_svm.h"
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "kvm_cache_regs.h"
  22
  23 #include <linux/module.h>
  24 #include <linux/kernel.h>
  25 #include <linux/vmalloc.h>
  26 #include <linux/highmem.h>
  27 #include <linux/sched.h>
  28
  29 #include <asm/desc.h>
  30
  31 #include <asm/virtext.h>
  32
  33 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  34
  35 MODULE_AUTHOR("Qumranet");
  36 MODULE_LICENSE("GPL");
  37
  38 #define IOPM_ALLOC_ORDER 2
  39 #define MSRPM_ALLOC_ORDER 1
  40
  41 #define DR7_GD_MASK (1 << 13)
  42 #define DR6_BD_MASK (1 << 13)
  43
  44 #define SEG_TYPE_LDT 2
  45 #define SEG_TYPE_BUSY_TSS16 3
  46
  47 #define SVM_FEATURE_NPT  (1 << 0)
  48 #define SVM_FEATURE_LBRV (1 << 1)
  49 #define SVM_FEATURE_SVML (1 << 2)
  50
  51 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  52
  53 /* enable NPT for AMD64 and X86 with PAE */
  54 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
  55 static bool npt_enabled = true;
  56 #else
  57 static bool npt_enabled = false;
  58 #endif
  59 static int npt = 1;
  60
  61 module_param(npt, int, S_IRUGO);
  62
  63 static void kvm_reput_irq(struct vcpu_svm *svm);
  64 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
  65
  66 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
  67 {
  68         return container_of(vcpu, struct vcpu_svm, vcpu);
  69 }
  70
  71 static unsigned long iopm_base;
  72
  73 struct kvm_ldttss_desc {
  74         u16 limit0;
  75         u16 base0;
  76         unsigned base1 : 8, type : 5, dpl : 2, p : 1;
  77         unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
  78         u32 base3;
  79         u32 zero1;
  80 } __attribute__((packed));
  81
  82 struct svm_cpu_data {
  83         int cpu;
  84
  85         u64 asid_generation;
  86         u32 max_asid;
  87         u32 next_asid;
  88         struct kvm_ldttss_desc *tss_desc;
  89
  90         struct page *save_area;
  91 };
  92
  93 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
  94 static uint32_t svm_features;
  95
  96 struct svm_init_data {
  97         int cpu;
  98         int r;
  99 };
 100
 101 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 102
 103 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 104 #define MSRS_RANGE_SIZE 2048
 105 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 106
 107 #define MAX_INST_SIZE 15
 108
 109 static inline u32 svm_has(u32 feat)
 110 {
 111         return svm_features & feat;
 112 }
 113
 114 static inline u8 pop_irq(struct kvm_vcpu *vcpu)
 115 {
 116         int word_index = __ffs(vcpu->arch.irq_summary);
 117         int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
 118         int irq = word_index * BITS_PER_LONG + bit_index;
 119
 120         clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
 121         if (!vcpu->arch.irq_pending[word_index])
 122                 clear_bit(word_index, &vcpu->arch.irq_summary);
 123         return irq;
 124 }
 125
 126 static inline void push_irq(struct kvm_vcpu *vcpu, u8 irq)
 127 {
 128         set_bit(irq, vcpu->arch.irq_pending);
 129         set_bit(irq / BITS_PER_LONG, &vcpu->arch.irq_summary);
 130 }
 131
 132 static inline void clgi(void)
 133 {
 134         asm volatile (__ex(SVM_CLGI));
 135 }
 136
 137 static inline void stgi(void)
 138 {
 139         asm volatile (__ex(SVM_STGI));
 140 }
 141
 142 static inline void invlpga(unsigned long addr, u32 asid)
 143 {
 144         asm volatile (__ex(SVM_INVLPGA) :: "a"(addr), "c"(asid));
 145 }
 146
 147 static inline unsigned long kvm_read_cr2(void)
 148 {
 149         unsigned long cr2;
 150
 151         asm volatile ("mov %%cr2, %0" : "=r" (cr2));
 152         return cr2;
 153 }
 154
 155 static inline void kvm_write_cr2(unsigned long val)
 156 {
 157         asm volatile ("mov %0, %%cr2" :: "r" (val));
 158 }
 159
 160 static inline unsigned long read_dr6(void)
 161 {
 162         unsigned long dr6;
 163
 164         asm volatile ("mov %%dr6, %0" : "=r" (dr6));
 165         return dr6;
 166 }
 167
 168 static inline void write_dr6(unsigned long val)
 169 {
 170         asm volatile ("mov %0, %%dr6" :: "r" (val));
 171 }
 172
 173 static inline unsigned long read_dr7(void)
 174 {
 175         unsigned long dr7;
 176
 177         asm volatile ("mov %%dr7, %0" : "=r" (dr7));
 178         return dr7;
 179 }
 180
 181 static inline void write_dr7(unsigned long val)
 182 {
 183         asm volatile ("mov %0, %%dr7" :: "r" (val));
 184 }
 185
 186 static inline void force_new_asid(struct kvm_vcpu *vcpu)
 187 {
 188         to_svm(vcpu)->asid_generation--;
 189 }
 190
 191 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
 192 {
 193         force_new_asid(vcpu);
 194 }
 195
 196 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 197 {
 198         if (!npt_enabled && !(efer & EFER_LMA))
 199                 efer &= ~EFER_LME;
 200
 201         to_svm(vcpu)->vmcb->save.efer = efer | MSR_EFER_SVME_MASK;
 202         vcpu->arch.shadow_efer = efer;
 203 }
 204
 205 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 206                                 bool has_error_code, u32 error_code)
 207 {
 208         struct vcpu_svm *svm = to_svm(vcpu);
 209
 210         svm->vmcb->control.event_inj = nr
 211                 | SVM_EVTINJ_VALID
 212                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 213                 | SVM_EVTINJ_TYPE_EXEPT;
 214         svm->vmcb->control.event_inj_err = error_code;
 215 }
 216
 217 static bool svm_exception_injected(struct kvm_vcpu *vcpu)
 218 {
 219         struct vcpu_svm *svm = to_svm(vcpu);
 220
 221         return !(svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID);
 222 }
 223
 224 static int is_external_interrupt(u32 info)
 225 {
 226         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 227         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 228 }
 229
 230 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 231 {
 232         struct vcpu_svm *svm = to_svm(vcpu);
 233
 234         if (!svm->next_rip) {
 235                 printk(KERN_DEBUG "%s: NOP\n", __func__);
 236                 return;
 237         }
 238         if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
 239                 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
 240                        __func__, kvm_rip_read(vcpu), svm->next_rip);
 241
 242         kvm_rip_write(vcpu, svm->next_rip);
 243         svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 244
 245         vcpu->arch.interrupt_window_open = 1;
 246 }
 247
 248 static int has_svm(void)
 249 {
 250         const char *msg;
 251
 252         if (!cpu_has_svm(&msg)) {
 253                 printk(KERN_INFO "has_svn: %s\n", msg);
 254                 return 0;
 255         }
 256
 257         return 1;
 258 }
 259
 260 static void svm_hardware_disable(void *garbage)
 261 {
 262         cpu_svm_disable();
 263 }
 264
 265 static void svm_hardware_enable(void *garbage)
 266 {
 267
 268         struct svm_cpu_data *svm_data;
 269         uint64_t efer;
 270         struct desc_ptr gdt_descr;
 271         struct desc_struct *gdt;
 272         int me = raw_smp_processor_id();
 273
 274         if (!has_svm()) {
 275                 printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me);
 276                 return;
 277         }
 278         svm_data = per_cpu(svm_data, me);
 279
 280         if (!svm_data) {
 281                 printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n",
 282                        me);
 283                 return;
 284         }
 285
 286         svm_data->asid_generation = 1;
 287         svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 288         svm_data->next_asid = svm_data->max_asid + 1;
 289
 290         asm volatile ("sgdt %0" : "=m"(gdt_descr));
 291         gdt = (struct desc_struct *)gdt_descr.address;
 292         svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 293
 294         rdmsrl(MSR_EFER, efer);
 295         wrmsrl(MSR_EFER, efer | MSR_EFER_SVME_MASK);
 296
 297         wrmsrl(MSR_VM_HSAVE_PA,
 298                page_to_pfn(svm_data->save_area) << PAGE_SHIFT);
 299 }
 300
 301 static void svm_cpu_uninit(int cpu)
 302 {
 303         struct svm_cpu_data *svm_data
 304                 = per_cpu(svm_data, raw_smp_processor_id());
 305
 306         if (!svm_data)
 307                 return;
 308
 309         per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 310         __free_page(svm_data->save_area);
 311         kfree(svm_data);
 312 }
 313
 314 static int svm_cpu_init(int cpu)
 315 {
 316         struct svm_cpu_data *svm_data;
 317         int r;
 318
 319         svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 320         if (!svm_data)
 321                 return -ENOMEM;
 322         svm_data->cpu = cpu;
 323         svm_data->save_area = alloc_page(GFP_KERNEL);
 324         r = -ENOMEM;
 325         if (!svm_data->save_area)
 326                 goto err_1;
 327
 328         per_cpu(svm_data, cpu) = svm_data;
 329
 330         return 0;
 331
 332 err_1:
 333         kfree(svm_data);
 334         return r;
 335
 336 }
 337
 338 static void set_msr_interception(u32 *msrpm, unsigned msr,
 339                                  int read, int write)
 340 {
 341         int i;
 342
 343         for (i = 0; i < NUM_MSR_MAPS; i++) {
 344                 if (msr >= msrpm_ranges[i] &&
 345                     msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
 346                         u32 msr_offset = (i * MSRS_IN_RANGE + msr -
 347                                           msrpm_ranges[i]) * 2;
 348
 349                         u32 *base = msrpm + (msr_offset / 32);
 350                         u32 msr_shift = msr_offset % 32;
 351                         u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
 352                         *base = (*base & ~(0x3 << msr_shift)) |
 353                                 (mask << msr_shift);
 354                         return;
 355                 }
 356         }
 357         BUG();
 358 }
 359
 360 static void svm_vcpu_init_msrpm(u32 *msrpm)
 361 {
 362         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
 363
 364 #ifdef CONFIG_X86_64
 365         set_msr_interception(msrpm, MSR_GS_BASE, 1, 1);
 366         set_msr_interception(msrpm, MSR_FS_BASE, 1, 1);
 367         set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1);
 368         set_msr_interception(msrpm, MSR_LSTAR, 1, 1);
 369         set_msr_interception(msrpm, MSR_CSTAR, 1, 1);
 370         set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1);
 371 #endif
 372         set_msr_interception(msrpm, MSR_K6_STAR, 1, 1);
 373         set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1);
 374         set_msr_interception(msrpm, MSR_IA32_SYSENTER_ESP, 1, 1);
 375         set_msr_interception(msrpm, MSR_IA32_SYSENTER_EIP, 1, 1);
 376 }
 377
 378 static void svm_enable_lbrv(struct vcpu_svm *svm)
 379 {
 380         u32 *msrpm = svm->msrpm;
 381
 382         svm->vmcb->control.lbr_ctl = 1;
 383         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
 384         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
 385         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
 386         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
 387 }
 388
 389 static void svm_disable_lbrv(struct vcpu_svm *svm)
 390 {
 391         u32 *msrpm = svm->msrpm;
 392
 393         svm->vmcb->control.lbr_ctl = 0;
 394         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
 395         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
 396         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
 397         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
 398 }
 399
 400 static __init int svm_hardware_setup(void)
 401 {
 402         int cpu;
 403         struct page *iopm_pages;
 404         void *iopm_va;
 405         int r;
 406
 407         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
 408
 409         if (!iopm_pages)
 410                 return -ENOMEM;
 411
 412         iopm_va = page_address(iopm_pages);
 413         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
 414         clear_bit(0x80, iopm_va); /* allow direct access to PC debug port */
 415         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
 416
 417         if (boot_cpu_has(X86_FEATURE_NX))
 418                 kvm_enable_efer_bits(EFER_NX);
 419
 420         for_each_online_cpu(cpu) {
 421                 r = svm_cpu_init(cpu);
 422                 if (r)
 423                         goto err;
 424         }
 425
 426         svm_features = cpuid_edx(SVM_CPUID_FUNC);
 427
 428         if (!svm_has(SVM_FEATURE_NPT))
 429                 npt_enabled = false;
 430
 431         if (npt_enabled && !npt) {
 432                 printk(KERN_INFO "kvm: Nested Paging disabled\n");
 433                 npt_enabled = false;
 434         }
 435
 436         if (npt_enabled) {
 437                 printk(KERN_INFO "kvm: Nested Paging enabled\n");
 438                 kvm_enable_tdp();
 439         } else
 440                 kvm_disable_tdp();
 441
 442         return 0;
 443
 444 err:
 445         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
 446         iopm_base = 0;
 447         return r;
 448 }
 449
 450 static __exit void svm_hardware_unsetup(void)
 451 {
 452         int cpu;
 453
 454         for_each_online_cpu(cpu)
 455                 svm_cpu_uninit(cpu);
 456
 457         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
 458         iopm_base = 0;
 459 }
 460
 461 static void init_seg(struct vmcb_seg *seg)
 462 {
 463         seg->selector = 0;
 464         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
 465                 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
 466         seg->limit = 0xffff;
 467         seg->base = 0;
 468 }
 469
 470 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
 471 {
 472         seg->selector = 0;
 473         seg->attrib = SVM_SELECTOR_P_MASK | type;
 474         seg->limit = 0xffff;
 475         seg->base = 0;
 476 }
 477
 478 static void init_vmcb(struct vcpu_svm *svm)
 479 {
 480         struct vmcb_control_area *control = &svm->vmcb->control;
 481         struct vmcb_save_area *save = &svm->vmcb->save;
 482
 483         control->intercept_cr_read =    INTERCEPT_CR0_MASK |
 484                                         INTERCEPT_CR3_MASK |
 485                                         INTERCEPT_CR4_MASK;
 486
 487         control->intercept_cr_write =   INTERCEPT_CR0_MASK |
 488                                         INTERCEPT_CR3_MASK |
 489                                         INTERCEPT_CR4_MASK |
 490                                         INTERCEPT_CR8_MASK;
 491
 492         control->intercept_dr_read =    INTERCEPT_DR0_MASK |
 493                                         INTERCEPT_DR1_MASK |
 494                                         INTERCEPT_DR2_MASK |
 495                                         INTERCEPT_DR3_MASK;
 496
 497         control->intercept_dr_write =   INTERCEPT_DR0_MASK |
 498                                         INTERCEPT_DR1_MASK |
 499                                         INTERCEPT_DR2_MASK |
 500                                         INTERCEPT_DR3_MASK |
 501                                         INTERCEPT_DR5_MASK |
 502                                         INTERCEPT_DR7_MASK;
 503
 504         control->intercept_exceptions = (1 << PF_VECTOR) |
 505                                         (1 << UD_VECTOR) |
 506                                         (1 << MC_VECTOR);
 507
 508
 509         control->intercept =    (1ULL << INTERCEPT_INTR) |
 510                                 (1ULL << INTERCEPT_NMI) |
 511                                 (1ULL << INTERCEPT_SMI) |
 512                                 (1ULL << INTERCEPT_CPUID) |
 513                                 (1ULL << INTERCEPT_INVD) |
 514                                 (1ULL << INTERCEPT_HLT) |
 515                                 (1ULL << INTERCEPT_INVLPG) |
 516                                 (1ULL << INTERCEPT_INVLPGA) |
 517                                 (1ULL << INTERCEPT_IOIO_PROT) |
 518                                 (1ULL << INTERCEPT_MSR_PROT) |
 519                                 (1ULL << INTERCEPT_TASK_SWITCH) |
 520                                 (1ULL << INTERCEPT_SHUTDOWN) |
 521                                 (1ULL << INTERCEPT_VMRUN) |
 522                                 (1ULL << INTERCEPT_VMMCALL) |
 523                                 (1ULL << INTERCEPT_VMLOAD) |
 524                                 (1ULL << INTERCEPT_VMSAVE) |
 525                                 (1ULL << INTERCEPT_STGI) |
 526                                 (1ULL << INTERCEPT_CLGI) |
 527                                 (1ULL << INTERCEPT_SKINIT) |
 528                                 (1ULL << INTERCEPT_WBINVD) |
 529                                 (1ULL << INTERCEPT_MONITOR) |
 530                                 (1ULL << INTERCEPT_MWAIT);
 531
 532         control->iopm_base_pa = iopm_base;
 533         control->msrpm_base_pa = __pa(svm->msrpm);
 534         control->tsc_offset = 0;
 535         control->int_ctl = V_INTR_MASKING_MASK;
 536
 537         init_seg(&save->es);
 538         init_seg(&save->ss);
 539         init_seg(&save->ds);
 540         init_seg(&save->fs);
 541         init_seg(&save->gs);
 542
 543         save->cs.selector = 0xf000;
 544         /* Executable/Readable Code Segment */
 545         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
 546                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
 547         save->cs.limit = 0xffff;
 548         /*
 549          * cs.base should really be 0xffff0000, but vmx can't handle that, so
 550          * be consistent with it.
 551          *
 552          * Replace when we have real mode working for vmx.
 553          */
 554         save->cs.base = 0xf0000;
 555
 556         save->gdtr.limit = 0xffff;
 557         save->idtr.limit = 0xffff;
 558
 559         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
 560         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
 561
 562         save->efer = MSR_EFER_SVME_MASK;
 563         save->dr6 = 0xffff0ff0;
 564         save->dr7 = 0x400;
 565         save->rflags = 2;
 566         save->rip = 0x0000fff0;
 567         svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
 568
 569         /*
 570          * cr0 val on cpu init should be 0x60000010, we enable cpu
 571          * cache by default. the orderly way is to enable cache in bios.
 572          */
 573         save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP;
 574         save->cr4 = X86_CR4_PAE;
 575         /* rdx = ?? */
 576
 577         if (npt_enabled) {
 578                 /* Setup VMCB for Nested Paging */
 579                 control->nested_ctl = 1;
 580                 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
 581                                         (1ULL << INTERCEPT_INVLPG));
 582                 control->intercept_exceptions &= ~(1 << PF_VECTOR);
 583                 control->intercept_cr_read &= ~(INTERCEPT_CR0_MASK|
 584                                                 INTERCEPT_CR3_MASK);
 585                 control->intercept_cr_write &= ~(INTERCEPT_CR0_MASK|
 586                                                  INTERCEPT_CR3_MASK);
 587                 save->g_pat = 0x0007040600070406ULL;
 588                 /* enable caching because the QEMU Bios doesn't enable it */
 589                 save->cr0 = X86_CR0_ET;
 590                 save->cr3 = 0;
 591                 save->cr4 = 0;
 592         }
 593         force_new_asid(&svm->vcpu);
 594 }
 595
 596 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
 597 {
 598         struct vcpu_svm *svm = to_svm(vcpu);
 599
 600         init_vmcb(svm);
 601
 602         if (vcpu->vcpu_id != 0) {
 603                 kvm_rip_write(vcpu, 0);
 604                 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
 605                 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
 606         }
 607         vcpu->arch.regs_avail = ~0;
 608         vcpu->arch.regs_dirty = ~0;
 609
 610         return 0;
 611 }
 612
 613 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
 614 {
 615         struct vcpu_svm *svm;
 616         struct page *page;
 617         struct page *msrpm_pages;
 618         int err;
 619
 620         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
 621         if (!svm) {
 622                 err = -ENOMEM;
 623                 goto out;
 624         }
 625
 626         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
 627         if (err)
 628                 goto free_svm;
 629
 630         page = alloc_page(GFP_KERNEL);
 631         if (!page) {
 632                 err = -ENOMEM;
 633                 goto uninit;
 634         }
 635
 636         err = -ENOMEM;
 637         msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 638         if (!msrpm_pages)
 639                 goto uninit;
 640         svm->msrpm = page_address(msrpm_pages);
 641         svm_vcpu_init_msrpm(svm->msrpm);
 642
 643         svm->vmcb = page_address(page);
 644         clear_page(svm->vmcb);
 645         svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
 646         svm->asid_generation = 0;
 647         memset(svm->db_regs, 0, sizeof(svm->db_regs));
 648         init_vmcb(svm);
 649
 650         fx_init(&svm->vcpu);
 651         svm->vcpu.fpu_active = 1;
 652         svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
 653         if (svm->vcpu.vcpu_id == 0)
 654                 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
 655
 656         return &svm->vcpu;
 657
 658 uninit:
 659         kvm_vcpu_uninit(&svm->vcpu);
 660 free_svm:
 661         kmem_cache_free(kvm_vcpu_cache, svm);
 662 out:
 663         return ERR_PTR(err);
 664 }
 665
 666 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
 667 {
 668         struct vcpu_svm *svm = to_svm(vcpu);
 669
 670         __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
 671         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
 672         kvm_vcpu_uninit(vcpu);
 673         kmem_cache_free(kvm_vcpu_cache, svm);
 674 }
 675
 676 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 677 {
 678         struct vcpu_svm *svm = to_svm(vcpu);
 679         int i;
 680
 681         if (unlikely(cpu != vcpu->cpu)) {
 682                 u64 tsc_this, delta;
 683
 684                 /*
 685                  * Make sure that the guest sees a monotonically
 686                  * increasing TSC.
 687                  */
 688                 rdtscll(tsc_this);
 689                 delta = vcpu->arch.host_tsc - tsc_this;
 690                 svm->vmcb->control.tsc_offset += delta;
 691                 vcpu->cpu = cpu;
 692                 kvm_migrate_timers(vcpu);
 693         }
 694
 695         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 696                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 697 }
 698
 699 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
 700 {
 701         struct vcpu_svm *svm = to_svm(vcpu);
 702         int i;
 703
 704         ++vcpu->stat.host_state_reload;
 705         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 706                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 707
 708         rdtscll(vcpu->arch.host_tsc);
 709 }
 710
 711 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
 712 {
 713         return to_svm(vcpu)->vmcb->save.rflags;
 714 }
 715
 716 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 717 {
 718         to_svm(vcpu)->vmcb->save.rflags = rflags;
 719 }
 720
 721 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
 722 {
 723         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
 724
 725         switch (seg) {
 726         case VCPU_SREG_CS: return &save->cs;
 727         case VCPU_SREG_DS: return &save->ds;
 728         case VCPU_SREG_ES: return &save->es;
 729         case VCPU_SREG_FS: return &save->fs;
 730         case VCPU_SREG_GS: return &save->gs;
 731         case VCPU_SREG_SS: return &save->ss;
 732         case VCPU_SREG_TR: return &save->tr;
 733         case VCPU_SREG_LDTR: return &save->ldtr;
 734         }
 735         BUG();
 736         return NULL;
 737 }
 738
 739 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
 740 {
 741         struct vmcb_seg *s = svm_seg(vcpu, seg);
 742
 743         return s->base;
 744 }
 745
 746 static void svm_get_segment(struct kvm_vcpu *vcpu,
 747                             struct kvm_segment *var, int seg)
 748 {
 749         struct vmcb_seg *s = svm_seg(vcpu, seg);
 750
 751         var->base = s->base;
 752         var->limit = s->limit;
 753         var->selector = s->selector;
 754         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
 755         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
 756         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
 757         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
 758         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
 759         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
 760         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
 761         var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
 762
 763         /*
 764          * SVM always stores 0 for the 'G' bit in the CS selector in
 765          * the VMCB on a VMEXIT. This hurts cross-vendor migration:
 766          * Intel's VMENTRY has a check on the 'G' bit.
 767          */
 768         if (seg == VCPU_SREG_CS)
 769                 var->g = s->limit > 0xfffff;
 770
 771         /*
 772          * Work around a bug where the busy flag in the tr selector
 773          * isn't exposed
 774          */
 775         if (seg == VCPU_SREG_TR)
 776                 var->type |= 0x2;
 777
 778         var->unusable = !var->present;
 779 }
 780
 781 static int svm_get_cpl(struct kvm_vcpu *vcpu)
 782 {
 783         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
 784
 785         return save->cpl;
 786 }
 787
 788 static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 789 {
 790         struct vcpu_svm *svm = to_svm(vcpu);
 791
 792         dt->limit = svm->vmcb->save.idtr.limit;
 793         dt->base = svm->vmcb->save.idtr.base;
 794 }
 795
 796 static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 797 {
 798         struct vcpu_svm *svm = to_svm(vcpu);
 799
 800         svm->vmcb->save.idtr.limit = dt->limit;
 801         svm->vmcb->save.idtr.base = dt->base ;
 802 }
 803
 804 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 805 {
 806         struct vcpu_svm *svm = to_svm(vcpu);
 807
 808         dt->limit = svm->vmcb->save.gdtr.limit;
 809         dt->base = svm->vmcb->save.gdtr.base;
 810 }
 811
 812 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 813 {
 814         struct vcpu_svm *svm = to_svm(vcpu);
 815
 816         svm->vmcb->save.gdtr.limit = dt->limit;
 817         svm->vmcb->save.gdtr.base = dt->base ;
 818 }
 819
 820 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
 821 {
 822 }
 823
 824 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
 825 {
 826         struct vcpu_svm *svm = to_svm(vcpu);
 827
 828 #ifdef CONFIG_X86_64
 829         if (vcpu->arch.shadow_efer & EFER_LME) {
 830                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
 831                         vcpu->arch.shadow_efer |= EFER_LMA;
 832                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
 833                 }
 834
 835                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
 836                         vcpu->arch.shadow_efer &= ~EFER_LMA;
 837                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
 838                 }
 839         }
 840 #endif
 841         if (npt_enabled)
 842                 goto set;
 843
 844         if ((vcpu->arch.cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) {
 845                 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
 846                 vcpu->fpu_active = 1;
 847         }
 848
 849         vcpu->arch.cr0 = cr0;
 850         cr0 |= X86_CR0_PG | X86_CR0_WP;
 851         if (!vcpu->fpu_active) {
 852                 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
 853                 cr0 |= X86_CR0_TS;
 854         }
 855 set:
 856         /*
 857          * re-enable caching here because the QEMU bios
 858          * does not do it - this results in some delay at
 859          * reboot
 860          */
 861         cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
 862         svm->vmcb->save.cr0 = cr0;
 863 }
 864
 865 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
 866 {
 867         unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
 868         unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
 869
 870         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
 871                 force_new_asid(vcpu);
 872
 873         vcpu->arch.cr4 = cr4;
 874         if (!npt_enabled)
 875                 cr4 |= X86_CR4_PAE;
 876         cr4 |= host_cr4_mce;
 877         to_svm(vcpu)->vmcb->save.cr4 = cr4;
 878 }
 879
 880 static void svm_set_segment(struct kvm_vcpu *vcpu,
 881                             struct kvm_segment *var, int seg)
 882 {
 883         struct vcpu_svm *svm = to_svm(vcpu);
 884         struct vmcb_seg *s = svm_seg(vcpu, seg);
 885
 886         s->base = var->base;
 887         s->limit = var->limit;
 888         s->selector = var->selector;
 889         if (var->unusable)
 890                 s->attrib = 0;
 891         else {
 892                 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
 893                 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
 894                 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
 895                 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
 896                 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
 897                 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
 898                 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
 899                 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
 900         }
 901         if (seg == VCPU_SREG_CS)
 902                 svm->vmcb->save.cpl
 903                         = (svm->vmcb->save.cs.attrib
 904                            >> SVM_SELECTOR_DPL_SHIFT) & 3;
 905
 906 }
 907
 908 static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
 909 {
 910         return -EOPNOTSUPP;
 911 }
 912
 913 static int svm_get_irq(struct kvm_vcpu *vcpu)
 914 {
 915         struct vcpu_svm *svm = to_svm(vcpu);
 916         u32 exit_int_info = svm->vmcb->control.exit_int_info;
 917
 918         if (is_external_interrupt(exit_int_info))
 919                 return exit_int_info & SVM_EVTINJ_VEC_MASK;
 920         return -1;
 921 }
 922
 923 static void load_host_msrs(struct kvm_vcpu *vcpu)
 924 {
 925 #ifdef CONFIG_X86_64
 926         wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
 927 #endif
 928 }
 929
 930 static void save_host_msrs(struct kvm_vcpu *vcpu)
 931 {
 932 #ifdef CONFIG_X86_64
 933         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
 934 #endif
 935 }
 936
 937 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data)
 938 {
 939         if (svm_data->next_asid > svm_data->max_asid) {
 940                 ++svm_data->asid_generation;
 941                 svm_data->next_asid = 1;
 942                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
 943         }
 944
 945         svm->vcpu.cpu = svm_data->cpu;
 946         svm->asid_generation = svm_data->asid_generation;
 947         svm->vmcb->control.asid = svm_data->next_asid++;
 948 }
 949
 950 static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
 951 {
 952         unsigned long val = to_svm(vcpu)->db_regs[dr];
 953         KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler);
 954         return val;
 955 }
 956
 957 static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
 958                        int *exception)
 959 {
 960         struct vcpu_svm *svm = to_svm(vcpu);
 961
 962         *exception = 0;
 963
 964         if (svm->vmcb->save.dr7 & DR7_GD_MASK) {
 965                 svm->vmcb->save.dr7 &= ~DR7_GD_MASK;
 966                 svm->vmcb->save.dr6 |= DR6_BD_MASK;
 967                 *exception = DB_VECTOR;
 968                 return;
 969         }
 970
 971         switch (dr) {
 972         case 0 ... 3:
 973                 svm->db_regs[dr] = value;
 974                 return;
 975         case 4 ... 5:
 976                 if (vcpu->arch.cr4 & X86_CR4_DE) {
 977                         *exception = UD_VECTOR;
 978                         return;
 979                 }
 980         case 7: {
 981                 if (value & ~((1ULL << 32) - 1)) {
 982                         *exception = GP_VECTOR;
 983                         return;
 984                 }
 985                 svm->vmcb->save.dr7 = value;
 986                 return;
 987         }
 988         default:
 989                 printk(KERN_DEBUG "%s: unexpected dr %u\n",
 990                        __func__, dr);
 991                 *exception = UD_VECTOR;
 992                 return;
 993         }
 994 }
 995
 996 static int pf_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
 997 {
 998         u32 exit_int_info = svm->vmcb->control.exit_int_info;
 999         struct kvm *kvm = svm->vcpu.kvm;
1000         u64 fault_address;
1001         u32 error_code;
1002         bool event_injection = false;
1003
1004         if (!irqchip_in_kernel(kvm) &&
1005             is_external_interrupt(exit_int_info)) {
1006                 event_injection = true;
1007                 push_irq(&svm->vcpu, exit_int_info & SVM_EVTINJ_VEC_MASK);
1008         }
1009
1010         fault_address  = svm->vmcb->control.exit_info_2;
1011         error_code = svm->vmcb->control.exit_info_1;
1012
1013         if (!npt_enabled)
1014                 KVMTRACE_3D(PAGE_FAULT, &svm->vcpu, error_code,
1015                             (u32)fault_address, (u32)(fault_address >> 32),
1016                             handler);
1017         else
1018                 KVMTRACE_3D(TDP_FAULT, &svm->vcpu, error_code,
1019                             (u32)fault_address, (u32)(fault_address >> 32),
1020                             handler);
1021         /*
1022          * FIXME: Tis shouldn't be necessary here, but there is a flush
1023          * missing in the MMU code. Until we find this bug, flush the
1024          * complete TLB here on an NPF
1025          */
1026         if (npt_enabled)
1027                 svm_flush_tlb(&svm->vcpu);
1028
1029         if (!npt_enabled && event_injection)
1030                 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1031         return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1032 }
1033
1034 static int ud_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1035 {
1036         int er;
1037
1038         er = emulate_instruction(&svm->vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
1039         if (er != EMULATE_DONE)
1040                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1041         return 1;
1042 }
1043
1044 static int nm_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1045 {
1046         svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
1047         if (!(svm->vcpu.arch.cr0 & X86_CR0_TS))
1048                 svm->vmcb->save.cr0 &= ~X86_CR0_TS;
1049         svm->vcpu.fpu_active = 1;
1050
1051         return 1;
1052 }
1053
1054 static int mc_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1055 {
1056         /*
1057          * On an #MC intercept the MCE handler is not called automatically in
1058          * the host. So do it by hand here.
1059          */
1060         asm volatile (
1061                 "int $0x12\n");
1062         /* not sure if we ever come back to this point */
1063
1064         return 1;
1065 }
1066
1067 static int shutdown_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1068 {
1069         /*
1070          * VMCB is undefined after a SHUTDOWN intercept
1071          * so reinitialize it.
1072          */
1073         clear_page(svm->vmcb);
1074         init_vmcb(svm);
1075
1076         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1077         return 0;
1078 }
1079
1080 static int io_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1081 {
1082         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1083         int size, down, in, string, rep;
1084         unsigned port;
1085
1086         ++svm->vcpu.stat.io_exits;
1087
1088         svm->next_rip = svm->vmcb->control.exit_info_2;
1089
1090         string = (io_info & SVM_IOIO_STR_MASK) != 0;
1091
1092         if (string) {
1093                 if (emulate_instruction(&svm->vcpu,
1094                                         kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
1095                         return 0;
1096                 return 1;
1097         }
1098
1099         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1100         port = io_info >> 16;
1101         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1102         rep = (io_info & SVM_IOIO_REP_MASK) != 0;
1103         down = (svm->vmcb->save.rflags & X86_EFLAGS_DF) != 0;
1104
1105         skip_emulated_instruction(&svm->vcpu);
1106         return kvm_emulate_pio(&svm->vcpu, kvm_run, in, size, port);
1107 }
1108
1109 static int nmi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1110 {
1111         KVMTRACE_0D(NMI, &svm->vcpu, handler);
1112         return 1;
1113 }
1114
1115 static int intr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1116 {
1117         ++svm->vcpu.stat.irq_exits;
1118         KVMTRACE_0D(INTR, &svm->vcpu, handler);
1119         return 1;
1120 }
1121
1122 static int nop_on_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1123 {
1124         return 1;
1125 }
1126
1127 static int halt_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1128 {
1129         svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1130         skip_emulated_instruction(&svm->vcpu);
1131         return kvm_emulate_halt(&svm->vcpu);
1132 }
1133
1134 static int vmmcall_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1135 {
1136         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1137         skip_emulated_instruction(&svm->vcpu);
1138         kvm_emulate_hypercall(&svm->vcpu);
1139         return 1;
1140 }
1141
1142 static int invalid_op_interception(struct vcpu_svm *svm,
1143                                    struct kvm_run *kvm_run)
1144 {
1145         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1146         return 1;
1147 }
1148
1149 static int task_switch_interception(struct vcpu_svm *svm,
1150                                     struct kvm_run *kvm_run)
1151 {
1152         u16 tss_selector;
1153
1154         tss_selector = (u16)svm->vmcb->control.exit_info_1;
1155         if (svm->vmcb->control.exit_info_2 &
1156             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
1157                 return kvm_task_switch(&svm->vcpu, tss_selector,
1158                                        TASK_SWITCH_IRET);
1159         if (svm->vmcb->control.exit_info_2 &
1160             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
1161                 return kvm_task_switch(&svm->vcpu, tss_selector,
1162                                        TASK_SWITCH_JMP);
1163         return kvm_task_switch(&svm->vcpu, tss_selector, TASK_SWITCH_CALL);
1164 }
1165
1166 static int cpuid_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1167 {
1168         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
1169         kvm_emulate_cpuid(&svm->vcpu);
1170         return 1;
1171 }
1172
1173 static int invlpg_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1174 {
1175         if (emulate_instruction(&svm->vcpu, kvm_run, 0, 0, 0) != EMULATE_DONE)
1176                 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
1177         return 1;
1178 }
1179
1180 static int emulate_on_interception(struct vcpu_svm *svm,
1181                                    struct kvm_run *kvm_run)
1182 {
1183         if (emulate_instruction(&svm->vcpu, NULL, 0, 0, 0) != EMULATE_DONE)
1184                 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
1185         return 1;
1186 }
1187
1188 static int cr8_write_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1189 {
1190         emulate_instruction(&svm->vcpu, NULL, 0, 0, 0);
1191         if (irqchip_in_kernel(svm->vcpu.kvm))
1192                 return 1;
1193         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
1194         return 0;
1195 }
1196
1197 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
1198 {
1199         struct vcpu_svm *svm = to_svm(vcpu);
1200
1201         switch (ecx) {
1202         case MSR_IA32_TIME_STAMP_COUNTER: {
1203                 u64 tsc;
1204
1205                 rdtscll(tsc);
1206                 *data = svm->vmcb->control.tsc_offset + tsc;
1207                 break;
1208         }
1209         case MSR_K6_STAR:
1210                 *data = svm->vmcb->save.star;
1211                 break;
1212 #ifdef CONFIG_X86_64
1213         case MSR_LSTAR:
1214                 *data = svm->vmcb->save.lstar;
1215                 break;
1216         case MSR_CSTAR:
1217                 *data = svm->vmcb->save.cstar;
1218                 break;
1219         case MSR_KERNEL_GS_BASE:
1220                 *data = svm->vmcb->save.kernel_gs_base;
1221                 break;
1222         case MSR_SYSCALL_MASK:
1223                 *data = svm->vmcb->save.sfmask;
1224                 break;
1225 #endif
1226         case MSR_IA32_SYSENTER_CS:
1227                 *data = svm->vmcb->save.sysenter_cs;
1228                 break;
1229         case MSR_IA32_SYSENTER_EIP:
1230                 *data = svm->vmcb->save.sysenter_eip;
1231                 break;
1232         case MSR_IA32_SYSENTER_ESP:
1233                 *data = svm->vmcb->save.sysenter_esp;
1234                 break;
1235         /* Nobody will change the following 5 values in the VMCB so
1236            we can safely return them on rdmsr. They will always be 0
1237            until LBRV is implemented. */
1238         case MSR_IA32_DEBUGCTLMSR:
1239                 *data = svm->vmcb->save.dbgctl;
1240                 break;
1241         case MSR_IA32_LASTBRANCHFROMIP:
1242                 *data = svm->vmcb->save.br_from;
1243                 break;
1244         case MSR_IA32_LASTBRANCHTOIP:
1245                 *data = svm->vmcb->save.br_to;
1246                 break;
1247         case MSR_IA32_LASTINTFROMIP:
1248                 *data = svm->vmcb->save.last_excp_from;
1249                 break;
1250         case MSR_IA32_LASTINTTOIP:
1251                 *data = svm->vmcb->save.last_excp_to;
1252                 break;
1253         default:
1254                 return kvm_get_msr_common(vcpu, ecx, data);
1255         }
1256         return 0;
1257 }
1258
1259 static int rdmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1260 {
1261         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1262         u64 data;
1263
1264         if (svm_get_msr(&svm->vcpu, ecx, &data))
1265                 kvm_inject_gp(&svm->vcpu, 0);
1266         else {
1267                 KVMTRACE_3D(MSR_READ, &svm->vcpu, ecx, (u32)data,
1268                             (u32)(data >> 32), handler);
1269
1270                 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
1271                 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
1272                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
1273                 skip_emulated_instruction(&svm->vcpu);
1274         }
1275         return 1;
1276 }
1277
1278 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
1279 {
1280         struct vcpu_svm *svm = to_svm(vcpu);
1281
1282         switch (ecx) {
1283         case MSR_IA32_TIME_STAMP_COUNTER: {
1284                 u64 tsc;
1285
1286                 rdtscll(tsc);
1287                 svm->vmcb->control.tsc_offset = data - tsc;
1288                 break;
1289         }
1290         case MSR_K6_STAR:
1291                 svm->vmcb->save.star = data;
1292                 break;
1293 #ifdef CONFIG_X86_64
1294         case MSR_LSTAR:
1295                 svm->vmcb->save.lstar = data;
1296                 break;
1297         case MSR_CSTAR:
1298                 svm->vmcb->save.cstar = data;
1299                 break;
1300         case MSR_KERNEL_GS_BASE:
1301                 svm->vmcb->save.kernel_gs_base = data;
1302                 break;
1303         case MSR_SYSCALL_MASK:
1304                 svm->vmcb->save.sfmask = data;
1305                 break;
1306 #endif
1307         case MSR_IA32_SYSENTER_CS:
1308                 svm->vmcb->save.sysenter_cs = data;
1309                 break;
1310         case MSR_IA32_SYSENTER_EIP:
1311                 svm->vmcb->save.sysenter_eip = data;
1312                 break;
1313         case MSR_IA32_SYSENTER_ESP:
1314                 svm->vmcb->save.sysenter_esp = data;
1315                 break;
1316         case MSR_IA32_DEBUGCTLMSR:
1317                 if (!svm_has(SVM_FEATURE_LBRV)) {
1318                         pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
1319                                         __func__, data);
1320                         break;
1321                 }
1322                 if (data & DEBUGCTL_RESERVED_BITS)
1323                         return 1;
1324
1325                 svm->vmcb->save.dbgctl = data;
1326                 if (data & (1ULL<<0))
1327                         svm_enable_lbrv(svm);
1328                 else
1329                         svm_disable_lbrv(svm);
1330                 break;
1331         case MSR_K7_EVNTSEL0:
1332         case MSR_K7_EVNTSEL1:
1333         case MSR_K7_EVNTSEL2:
1334         case MSR_K7_EVNTSEL3:
1335         case MSR_K7_PERFCTR0:
1336         case MSR_K7_PERFCTR1:
1337         case MSR_K7_PERFCTR2:
1338         case MSR_K7_PERFCTR3:
1339                 /*
1340                  * Just discard all writes to the performance counters; this
1341                  * should keep both older linux and windows 64-bit guests
1342                  * happy
1343                  */
1344                 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: 0x%x data 0x%llx\n", ecx, data);
1345
1346                 break;
1347         default:
1348                 return kvm_set_msr_common(vcpu, ecx, data);
1349         }
1350         return 0;
1351 }
1352
1353 static int wrmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1354 {
1355         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1356         u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
1357                 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
1358
1359         KVMTRACE_3D(MSR_WRITE, &svm->vcpu, ecx, (u32)data, (u32)(data >> 32),
1360                     handler);
1361
1362         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
1363         if (svm_set_msr(&svm->vcpu, ecx, data))
1364                 kvm_inject_gp(&svm->vcpu, 0);
1365         else
1366                 skip_emulated_instruction(&svm->vcpu);
1367         return 1;
1368 }
1369
1370 static int msr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1371 {
1372         if (svm->vmcb->control.exit_info_1)
1373                 return wrmsr_interception(svm, kvm_run);
1374         else
1375                 return rdmsr_interception(svm, kvm_run);
1376 }
1377
1378 static int interrupt_window_interception(struct vcpu_svm *svm,
1379                                    struct kvm_run *kvm_run)
1380 {
1381         KVMTRACE_0D(PEND_INTR, &svm->vcpu, handler);
1382
1383         svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
1384         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1385         /*
1386          * If the user space waits to inject interrupts, exit as soon as
1387          * possible
1388          */
1389         if (kvm_run->request_interrupt_window &&
1390             !svm->vcpu.arch.irq_summary) {
1391                 ++svm->vcpu.stat.irq_window_exits;
1392                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
1393                 return 0;
1394         }
1395
1396         return 1;
1397 }
1398
1399 static int (*svm_exit_handlers[])(struct vcpu_svm *svm,
1400                                       struct kvm_run *kvm_run) = {
1401         [SVM_EXIT_READ_CR0]                     = emulate_on_interception,
1402         [SVM_EXIT_READ_CR3]                     = emulate_on_interception,
1403         [SVM_EXIT_READ_CR4]                     = emulate_on_interception,
1404         [SVM_EXIT_READ_CR8]                     = emulate_on_interception,
1405         /* for now: */
1406         [SVM_EXIT_WRITE_CR0]                    = emulate_on_interception,
1407         [SVM_EXIT_WRITE_CR3]                    = emulate_on_interception,
1408         [SVM_EXIT_WRITE_CR4]                    = emulate_on_interception,
1409         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
1410         [SVM_EXIT_READ_DR0]                     = emulate_on_interception,
1411         [SVM_EXIT_READ_DR1]                     = emulate_on_interception,
1412         [SVM_EXIT_READ_DR2]                     = emulate_on_interception,
1413         [SVM_EXIT_READ_DR3]                     = emulate_on_interception,
1414         [SVM_EXIT_WRITE_DR0]                    = emulate_on_interception,
1415         [SVM_EXIT_WRITE_DR1]                    = emulate_on_interception,
1416         [SVM_EXIT_WRITE_DR2]                    = emulate_on_interception,
1417         [SVM_EXIT_WRITE_DR3]                    = emulate_on_interception,
1418         [SVM_EXIT_WRITE_DR5]                    = emulate_on_interception,
1419         [SVM_EXIT_WRITE_DR7]                    = emulate_on_interception,
1420         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
1421         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
1422         [SVM_EXIT_EXCP_BASE + NM_VECTOR]        = nm_interception,
1423         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
1424         [SVM_EXIT_INTR]                         = intr_interception,
1425         [SVM_EXIT_NMI]                          = nmi_interception,
1426         [SVM_EXIT_SMI]                          = nop_on_interception,
1427         [SVM_EXIT_INIT]                         = nop_on_interception,
1428         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
1429         /* [SVM_EXIT_CR0_SEL_WRITE]             = emulate_on_interception, */
1430         [SVM_EXIT_CPUID]                        = cpuid_interception,
1431         [SVM_EXIT_INVD]                         = emulate_on_interception,
1432         [SVM_EXIT_HLT]                          = halt_interception,
1433         [SVM_EXIT_INVLPG]                       = invlpg_interception,
1434         [SVM_EXIT_INVLPGA]                      = invalid_op_interception,
1435         [SVM_EXIT_IOIO]                         = io_interception,
1436         [SVM_EXIT_MSR]                          = msr_interception,
1437         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
1438         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
1439         [SVM_EXIT_VMRUN]                        = invalid_op_interception,
1440         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
1441         [SVM_EXIT_VMLOAD]                       = invalid_op_interception,
1442         [SVM_EXIT_VMSAVE]                       = invalid_op_interception,
1443         [SVM_EXIT_STGI]                         = invalid_op_interception,
1444         [SVM_EXIT_CLGI]                         = invalid_op_interception,
1445         [SVM_EXIT_SKINIT]                       = invalid_op_interception,
1446         [SVM_EXIT_WBINVD]                       = emulate_on_interception,
1447         [SVM_EXIT_MONITOR]                      = invalid_op_interception,
1448         [SVM_EXIT_MWAIT]                        = invalid_op_interception,
1449         [SVM_EXIT_NPF]                          = pf_interception,
1450 };
1451
1452 static int handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
1453 {
1454         struct vcpu_svm *svm = to_svm(vcpu);
1455         u32 exit_code = svm->vmcb->control.exit_code;
1456
1457         KVMTRACE_3D(VMEXIT, vcpu, exit_code, (u32)svm->vmcb->save.rip,
1458                     (u32)((u64)svm->vmcb->save.rip >> 32), entryexit);
1459
1460         if (npt_enabled) {
1461                 int mmu_reload = 0;
1462                 if ((vcpu->arch.cr0 ^ svm->vmcb->save.cr0) & X86_CR0_PG) {
1463                         svm_set_cr0(vcpu, svm->vmcb->save.cr0);
1464                         mmu_reload = 1;
1465                 }
1466                 vcpu->arch.cr0 = svm->vmcb->save.cr0;
1467                 vcpu->arch.cr3 = svm->vmcb->save.cr3;
1468                 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1469                         if (!load_pdptrs(vcpu, vcpu->arch.cr3)) {
1470                                 kvm_inject_gp(vcpu, 0);
1471                                 return 1;
1472                         }
1473                 }
1474                 if (mmu_reload) {
1475                         kvm_mmu_reset_context(vcpu);
1476                         kvm_mmu_load(vcpu);
1477                 }
1478         }
1479
1480         kvm_reput_irq(svm);
1481
1482         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
1483                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
1484                 kvm_run->fail_entry.hardware_entry_failure_reason
1485                         = svm->vmcb->control.exit_code;
1486                 return 0;
1487         }
1488
1489         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
1490             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
1491             exit_code != SVM_EXIT_NPF)
1492                 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
1493                        "exit_code 0x%x\n",
1494                        __func__, svm->vmcb->control.exit_int_info,
1495                        exit_code);
1496
1497         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
1498             || !svm_exit_handlers[exit_code]) {
1499                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
1500                 kvm_run->hw.hardware_exit_reason = exit_code;
1501                 return 0;
1502         }
1503
1504         return svm_exit_handlers[exit_code](svm, kvm_run);
1505 }
1506
1507 static void reload_tss(struct kvm_vcpu *vcpu)
1508 {
1509         int cpu = raw_smp_processor_id();
1510
1511         struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
1512         svm_data->tss_desc->type = 9; /* available 32/64-bit TSS */
1513         load_TR_desc();
1514 }
1515
1516 static void pre_svm_run(struct vcpu_svm *svm)
1517 {
1518         int cpu = raw_smp_processor_id();
1519
1520         struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
1521
1522         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
1523         if (svm->vcpu.cpu != cpu ||
1524             svm->asid_generation != svm_data->asid_generation)
1525                 new_asid(svm, svm_data);
1526 }
1527
1528
1529 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
1530 {
1531         struct vmcb_control_area *control;
1532
1533         KVMTRACE_1D(INJ_VIRQ, &svm->vcpu, (u32)irq, handler);
1534
1535         ++svm->vcpu.stat.irq_injections;
1536         control = &svm->vmcb->control;
1537         control->int_vector = irq;
1538         control->int_ctl &= ~V_INTR_PRIO_MASK;
1539         control->int_ctl |= V_IRQ_MASK |
1540                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
1541 }
1542
1543 static void svm_set_irq(struct kvm_vcpu *vcpu, int irq)
1544 {
1545         struct vcpu_svm *svm = to_svm(vcpu);
1546
1547         svm_inject_irq(svm, irq);
1548 }
1549
1550 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
1551 {
1552         struct vcpu_svm *svm = to_svm(vcpu);
1553         struct vmcb *vmcb = svm->vmcb;
1554         int max_irr, tpr;
1555
1556         if (!irqchip_in_kernel(vcpu->kvm) || vcpu->arch.apic->vapic_addr)
1557                 return;
1558
1559         vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
1560
1561         max_irr = kvm_lapic_find_highest_irr(vcpu);
1562         if (max_irr == -1)
1563                 return;
1564
1565         tpr = kvm_lapic_get_cr8(vcpu) << 4;
1566
1567         if (tpr >= (max_irr & 0xf0))
1568                 vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
1569 }
1570
1571 static void svm_intr_assist(struct kvm_vcpu *vcpu)
1572 {
1573         struct vcpu_svm *svm = to_svm(vcpu);
1574         struct vmcb *vmcb = svm->vmcb;
1575         int intr_vector = -1;
1576
1577         if ((vmcb->control.exit_int_info & SVM_EVTINJ_VALID) &&
1578             ((vmcb->control.exit_int_info & SVM_EVTINJ_TYPE_MASK) == 0)) {
1579                 intr_vector = vmcb->control.exit_int_info &
1580                               SVM_EVTINJ_VEC_MASK;
1581                 vmcb->control.exit_int_info = 0;
1582                 svm_inject_irq(svm, intr_vector);
1583                 goto out;
1584         }
1585
1586         if (vmcb->control.int_ctl & V_IRQ_MASK)
1587                 goto out;
1588
1589         if (!kvm_cpu_has_interrupt(vcpu))
1590                 goto out;
1591
1592         if (!(vmcb->save.rflags & X86_EFLAGS_IF) ||
1593             (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) ||
1594             (vmcb->control.event_inj & SVM_EVTINJ_VALID)) {
1595                 /* unable to deliver irq, set pending irq */
1596                 vmcb->control.intercept |= (1ULL << INTERCEPT_VINTR);
1597                 svm_inject_irq(svm, 0x0);
1598                 goto out;
1599         }
1600         /* Okay, we can deliver the interrupt: grab it and update PIC state. */
1601         intr_vector = kvm_cpu_get_interrupt(vcpu);
1602         svm_inject_irq(svm, intr_vector);
1603 out:
1604         update_cr8_intercept(vcpu);
1605 }
1606
1607 static void kvm_reput_irq(struct vcpu_svm *svm)
1608 {
1609         struct vmcb_control_area *control = &svm->vmcb->control;
1610
1611         if ((control->int_ctl & V_IRQ_MASK)
1612             && !irqchip_in_kernel(svm->vcpu.kvm)) {
1613                 control->int_ctl &= ~V_IRQ_MASK;
1614                 push_irq(&svm->vcpu, control->int_vector);
1615         }
1616
1617         svm->vcpu.arch.interrupt_window_open =
1618                 !(control->int_state & SVM_INTERRUPT_SHADOW_MASK);
1619 }
1620
1621 static void svm_do_inject_vector(struct vcpu_svm *svm)
1622 {
1623         struct kvm_vcpu *vcpu = &svm->vcpu;
1624         int word_index = __ffs(vcpu->arch.irq_summary);
1625         int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
1626         int irq = word_index * BITS_PER_LONG + bit_index;
1627
1628         clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
1629         if (!vcpu->arch.irq_pending[word_index])
1630                 clear_bit(word_index, &vcpu->arch.irq_summary);
1631         svm_inject_irq(svm, irq);
1632 }
1633
1634 static void do_interrupt_requests(struct kvm_vcpu *vcpu,
1635                                        struct kvm_run *kvm_run)
1636 {
1637         struct vcpu_svm *svm = to_svm(vcpu);
1638         struct vmcb_control_area *control = &svm->vmcb->control;
1639
1640         svm->vcpu.arch.interrupt_window_open =
1641                 (!(control->int_state & SVM_INTERRUPT_SHADOW_MASK) &&
1642                  (svm->vmcb->save.rflags & X86_EFLAGS_IF));
1643
1644         if (svm->vcpu.arch.interrupt_window_open && svm->vcpu.arch.irq_summary)
1645                 /*
1646                  * If interrupts enabled, and not blocked by sti or mov ss. Good.
1647                  */
1648                 svm_do_inject_vector(svm);
1649
1650         /*
1651          * Interrupts blocked.  Wait for unblock.
1652          */
1653         if (!svm->vcpu.arch.interrupt_window_open &&
1654             (svm->vcpu.arch.irq_summary || kvm_run->request_interrupt_window))
1655                 control->intercept |= 1ULL << INTERCEPT_VINTR;
1656          else
1657                 control->intercept &= ~(1ULL << INTERCEPT_VINTR);
1658 }
1659
1660 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
1661 {
1662         return 0;
1663 }
1664
1665 static void save_db_regs(unsigned long *db_regs)
1666 {
1667         asm volatile ("mov %%dr0, %0" : "=r"(db_regs[0]));
1668         asm volatile ("mov %%dr1, %0" : "=r"(db_regs[1]));
1669         asm volatile ("mov %%dr2, %0" : "=r"(db_regs[2]));
1670         asm volatile ("mov %%dr3, %0" : "=r"(db_regs[3]));
1671 }
1672
1673 static void load_db_regs(unsigned long *db_regs)
1674 {
1675         asm volatile ("mov %0, %%dr0" : : "r"(db_regs[0]));
1676         asm volatile ("mov %0, %%dr1" : : "r"(db_regs[1]));
1677         asm volatile ("mov %0, %%dr2" : : "r"(db_regs[2]));
1678         asm volatile ("mov %0, %%dr3" : : "r"(db_regs[3]));
1679 }
1680
1681 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
1682 {
1683         force_new_asid(vcpu);
1684 }
1685
1686 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
1687 {
1688 }
1689
1690 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
1691 {
1692         struct vcpu_svm *svm = to_svm(vcpu);
1693
1694         if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
1695                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
1696                 kvm_lapic_set_tpr(vcpu, cr8);
1697         }
1698 }
1699
1700 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
1701 {
1702         struct vcpu_svm *svm = to_svm(vcpu);
1703         u64 cr8;
1704
1705         if (!irqchip_in_kernel(vcpu->kvm))
1706                 return;
1707
1708         cr8 = kvm_get_cr8(vcpu);
1709         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
1710         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
1711 }
1712
1713 #ifdef CONFIG_X86_64
1714 #define R "r"
1715 #else
1716 #define R "e"
1717 #endif
1718
1719 static void svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1720 {
1721         struct vcpu_svm *svm = to_svm(vcpu);
1722         u16 fs_selector;
1723         u16 gs_selector;
1724         u16 ldt_selector;
1725
1726         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
1727         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
1728         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
1729
1730         pre_svm_run(svm);
1731
1732         sync_lapic_to_cr8(vcpu);
1733
1734         save_host_msrs(vcpu);
1735         fs_selector = kvm_read_fs();
1736         gs_selector = kvm_read_gs();
1737         ldt_selector = kvm_read_ldt();
1738         svm->host_cr2 = kvm_read_cr2();
1739         svm->host_dr6 = read_dr6();
1740         svm->host_dr7 = read_dr7();
1741         svm->vmcb->save.cr2 = vcpu->arch.cr2;
1742         /* required for live migration with NPT */
1743         if (npt_enabled)
1744                 svm->vmcb->save.cr3 = vcpu->arch.cr3;
1745
1746         if (svm->vmcb->save.dr7 & 0xff) {
1747                 write_dr7(0);
1748                 save_db_regs(svm->host_db_regs);
1749                 load_db_regs(svm->db_regs);
1750         }
1751
1752         clgi();
1753
1754         local_irq_enable();
1755
1756         asm volatile (
1757                 "push %%"R"bp; \n\t"
1758                 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
1759                 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
1760                 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
1761                 "mov %c[rsi](%[svm]), %%"R"si \n\t"
1762                 "mov %c[rdi](%[svm]), %%"R"di \n\t"
1763                 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
1764 #ifdef CONFIG_X86_64
1765                 "mov %c[r8](%[svm]),  %%r8  \n\t"
1766                 "mov %c[r9](%[svm]),  %%r9  \n\t"
1767                 "mov %c[r10](%[svm]), %%r10 \n\t"
1768                 "mov %c[r11](%[svm]), %%r11 \n\t"
1769                 "mov %c[r12](%[svm]), %%r12 \n\t"
1770                 "mov %c[r13](%[svm]), %%r13 \n\t"
1771                 "mov %c[r14](%[svm]), %%r14 \n\t"
1772                 "mov %c[r15](%[svm]), %%r15 \n\t"
1773 #endif
1774
1775                 /* Enter guest mode */
1776                 "push %%"R"ax \n\t"
1777                 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
1778                 __ex(SVM_VMLOAD) "\n\t"
1779                 __ex(SVM_VMRUN) "\n\t"
1780                 __ex(SVM_VMSAVE) "\n\t"
1781                 "pop %%"R"ax \n\t"
1782
1783                 /* Save guest registers, load host registers */
1784                 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
1785                 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
1786                 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
1787                 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
1788                 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
1789                 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
1790 #ifdef CONFIG_X86_64
1791                 "mov %%r8,  %c[r8](%[svm]) \n\t"
1792                 "mov %%r9,  %c[r9](%[svm]) \n\t"
1793                 "mov %%r10, %c[r10](%[svm]) \n\t"
1794                 "mov %%r11, %c[r11](%[svm]) \n\t"
1795                 "mov %%r12, %c[r12](%[svm]) \n\t"
1796                 "mov %%r13, %c[r13](%[svm]) \n\t"
1797                 "mov %%r14, %c[r14](%[svm]) \n\t"
1798                 "mov %%r15, %c[r15](%[svm]) \n\t"
1799 #endif
1800                 "pop %%"R"bp"
1801                 :
1802                 : [svm]"a"(svm),
1803                   [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
1804                   [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
1805                   [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
1806                   [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
1807                   [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
1808                   [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
1809                   [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
1810 #ifdef CONFIG_X86_64
1811                   , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
1812                   [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
1813                   [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
1814                   [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
1815                   [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
1816                   [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
1817                   [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
1818                   [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
1819 #endif
1820                 : "cc", "memory"
1821                 , R"bx", R"cx", R"dx", R"si", R"di"
1822 #ifdef CONFIG_X86_64
1823                 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
1824 #endif
1825                 );
1826
1827         if ((svm->vmcb->save.dr7 & 0xff))
1828                 load_db_regs(svm->host_db_regs);
1829
1830         vcpu->arch.cr2 = svm->vmcb->save.cr2;
1831         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
1832         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
1833         vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
1834
1835         write_dr6(svm->host_dr6);
1836         write_dr7(svm->host_dr7);
1837         kvm_write_cr2(svm->host_cr2);
1838
1839         kvm_load_fs(fs_selector);
1840         kvm_load_gs(gs_selector);
1841         kvm_load_ldt(ldt_selector);
1842         load_host_msrs(vcpu);
1843
1844         reload_tss(vcpu);
1845
1846         local_irq_disable();
1847
1848         stgi();
1849
1850         sync_cr8_to_lapic(vcpu);
1851
1852         svm->next_rip = 0;
1853 }
1854
1855 #undef R
1856
1857 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
1858 {
1859         struct vcpu_svm *svm = to_svm(vcpu);
1860
1861         if (npt_enabled) {
1862                 svm->vmcb->control.nested_cr3 = root;
1863                 force_new_asid(vcpu);
1864                 return;
1865         }
1866
1867         svm->vmcb->save.cr3 = root;
1868         force_new_asid(vcpu);
1869
1870         if (vcpu->fpu_active) {
1871                 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
1872                 svm->vmcb->save.cr0 |= X86_CR0_TS;
1873                 vcpu->fpu_active = 0;
1874         }
1875 }
1876
1877 static int is_disabled(void)
1878 {
1879         u64 vm_cr;
1880
1881         rdmsrl(MSR_VM_CR, vm_cr);
1882         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
1883                 return 1;
1884
1885         return 0;
1886 }
1887
1888 static void
1889 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
1890 {
1891         /*
1892          * Patch in the VMMCALL instruction:
1893          */
1894         hypercall[0] = 0x0f;
1895         hypercall[1] = 0x01;
1896         hypercall[2] = 0xd9;
1897 }
1898
1899 static void svm_check_processor_compat(void *rtn)
1900 {
1901         *(int *)rtn = 0;
1902 }
1903
1904 static bool svm_cpu_has_accelerated_tpr(void)
1905 {
1906         return false;
1907 }
1908
1909 static int get_npt_level(void)
1910 {
1911 #ifdef CONFIG_X86_64
1912         return PT64_ROOT_LEVEL;
1913 #else
1914         return PT32E_ROOT_LEVEL;
1915 #endif
1916 }
1917
1918 static int svm_get_mt_mask_shift(void)
1919 {
1920         return 0;
1921 }
1922
1923 static struct kvm_x86_ops svm_x86_ops = {
1924         .cpu_has_kvm_support = has_svm,
1925         .disabled_by_bios = is_disabled,
1926         .hardware_setup = svm_hardware_setup,
1927         .hardware_unsetup = svm_hardware_unsetup,
1928         .check_processor_compatibility = svm_check_processor_compat,
1929         .hardware_enable = svm_hardware_enable,
1930         .hardware_disable = svm_hardware_disable,
1931         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
1932
1933         .vcpu_create = svm_create_vcpu,
1934         .vcpu_free = svm_free_vcpu,
1935         .vcpu_reset = svm_vcpu_reset,
1936
1937         .prepare_guest_switch = svm_prepare_guest_switch,
1938         .vcpu_load = svm_vcpu_load,
1939         .vcpu_put = svm_vcpu_put,
1940
1941         .set_guest_debug = svm_guest_debug,
1942         .get_msr = svm_get_msr,
1943         .set_msr = svm_set_msr,
1944         .get_segment_base = svm_get_segment_base,
1945         .get_segment = svm_get_segment,
1946         .set_segment = svm_set_segment,
1947         .get_cpl = svm_get_cpl,
1948         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
1949         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
1950         .set_cr0 = svm_set_cr0,
1951         .set_cr3 = svm_set_cr3,
1952         .set_cr4 = svm_set_cr4,
1953         .set_efer = svm_set_efer,
1954         .get_idt = svm_get_idt,
1955         .set_idt = svm_set_idt,
1956         .get_gdt = svm_get_gdt,
1957         .set_gdt = svm_set_gdt,
1958         .get_dr = svm_get_dr,
1959         .set_dr = svm_set_dr,
1960         .get_rflags = svm_get_rflags,
1961         .set_rflags = svm_set_rflags,
1962
1963         .tlb_flush = svm_flush_tlb,
1964
1965         .run = svm_vcpu_run,
1966         .handle_exit = handle_exit,
1967         .skip_emulated_instruction = skip_emulated_instruction,
1968         .patch_hypercall = svm_patch_hypercall,
1969         .get_irq = svm_get_irq,
1970         .set_irq = svm_set_irq,
1971         .queue_exception = svm_queue_exception,
1972         .exception_injected = svm_exception_injected,
1973         .inject_pending_irq = svm_intr_assist,
1974         .inject_pending_vectors = do_interrupt_requests,
1975
1976         .set_tss_addr = svm_set_tss_addr,
1977         .get_tdp_level = get_npt_level,
1978         .get_mt_mask_shift = svm_get_mt_mask_shift,
1979 };
1980
1981 static int __init svm_init(void)
1982 {
1983         return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
1984                               THIS_MODULE);
1985 }
1986
1987 static void __exit svm_exit(void)
1988 {
1989         kvm_exit();
1990 }
1991
1992 module_init(svm_init)
1993 module_exit(svm_exit)