git.oblomov.eu Git - linux-2.6/blob - drivers/video/radeonfb.c

   1 /*
   2  *      drivers/video/radeonfb.c
   3  *      framebuffer driver for ATI Radeon chipset video boards
   4  *
   5  *      Copyright 2000  Ani Joshi <ajoshi@kernel.crashing.org>
   6  *
   7  *
   8  *      ChangeLog:
   9  *      2000-08-03      initial version 0.0.1
  10  *      2000-09-10      more bug fixes, public release 0.0.5
  11  *      2001-02-19      mode bug fixes, 0.0.7
  12  *      2001-07-05      fixed scrolling issues, engine initialization,
  13  *                      and minor mode tweaking, 0.0.9
  14  *      2001-09-07      Radeon VE support, Nick Kurshev
  15  *                      blanking, pan_display, and cmap fixes, 0.1.0
  16  *      2001-10-10      Radeon 7500 and 8500 support, and experimental
  17  *                      flat panel support, 0.1.1
  18  *      2001-11-17      Radeon M6 (ppc) support, Daniel Berlin, 0.1.2
  19  *      2001-11-18      DFP fixes, Kevin Hendricks, 0.1.3
  20  *      2001-11-29      more cmap, backlight fixes, Benjamin Herrenschmidt
  21  *      2002-01-18      DFP panel detection via BIOS, Michael Clark, 0.1.4
  22  *      2002-06-02      console switching, mode set fixes, accel fixes
  23  *      2002-06-03      MTRR support, Peter Horton, 0.1.5
  24  *      2002-09-21      rv250, r300, m9 initial support,
  25  *                      added mirror option, 0.1.6
  26  *
  27  *      Special thanks to ATI DevRel team for their hardware donations.
  28  *
  29  */
  30
  31
  32 #define RADEON_VERSION  "0.1.6"
  33
  34
  35 #include <linux/config.h>
  36 #include <linux/module.h>
  37 #include <linux/kernel.h>
  38 #include <linux/errno.h>
  39 #include <linux/string.h>
  40 #include <linux/mm.h>
  41 #include <linux/tty.h>
  42 #include <linux/slab.h>
  43 #include <linux/delay.h>
  44 #include <linux/fb.h>
  45 #include <linux/ioport.h>
  46 #include <linux/init.h>
  47 #include <linux/pci.h>
  48 #include <linux/vmalloc.h>
  49
  50 #include <asm/io.h>
  51 #include <asm/uaccess.h>
  52 #if defined(__powerpc__)
  53 #include <asm/prom.h>
  54 #include <asm/pci-bridge.h>
  55 #include "macmodes.h"
  56
  57 #ifdef CONFIG_NVRAM
  58 #include <linux/nvram.h>
  59 #endif
  60
  61 #ifdef CONFIG_PMAC_BACKLIGHT
  62 #include <asm/backlight.h>
  63 #endif
  64
  65 #ifdef CONFIG_BOOTX_TEXT
  66 #include <asm/btext.h>
  67 #endif
  68
  69 #ifdef CONFIG_ADB_PMU
  70 #include <linux/adb.h>
  71 #include <linux/pmu.h>
  72 #endif
  73
  74 #endif /* __powerpc__ */
  75
  76 #ifdef CONFIG_MTRR
  77 #include <asm/mtrr.h>
  78 #endif
  79
  80 #include <video/radeon.h>
  81 #include <linux/radeonfb.h>
  82
  83 #define DEBUG  0
  84
  85 #if DEBUG
  86 #define RTRACE          printk
  87 #else
  88 #define RTRACE          if(0) printk
  89 #endif
  90
  91 // XXX
  92 #undef CONFIG_PMAC_PBOOK
  93
  94
  95 enum radeon_chips {
  96         RADEON_QD,
  97         RADEON_QE,
  98         RADEON_QF,
  99         RADEON_QG,
 100         RADEON_QY,
 101         RADEON_QZ,
 102         RADEON_LW,
 103         RADEON_LX,
 104         RADEON_LY,
 105         RADEON_LZ,
 106         RADEON_QL,
 107         RADEON_QN,
 108         RADEON_QO,
 109         RADEON_Ql,
 110         RADEON_BB,
 111         RADEON_QW,
 112         RADEON_QX,
 113         RADEON_Id,
 114         RADEON_Ie,
 115         RADEON_If,
 116         RADEON_Ig,
 117         RADEON_Ya,
 118         RADEON_Yd,
 119         RADEON_Ld,
 120         RADEON_Le,
 121         RADEON_Lf,
 122         RADEON_Lg,
 123         RADEON_ND,
 124         RADEON_NE,
 125         RADEON_NF,
 126         RADEON_NG,
 127         RADEON_QM
 128 };
 129
 130 enum radeon_arch {
 131         RADEON_R100,
 132         RADEON_RV100,
 133         RADEON_R200,
 134         RADEON_RV200,
 135         RADEON_RV250,
 136         RADEON_R300,
 137         RADEON_M6,
 138         RADEON_M7,
 139         RADEON_M9
 140 };
 141
 142 static struct radeon_chip_info {
 143         const char *name;
 144         unsigned char arch;
 145 } radeon_chip_info[] __devinitdata = {
 146         { "QD", RADEON_R100 },
 147         { "QE", RADEON_R100 },
 148         { "QF", RADEON_R100 },
 149         { "QG", RADEON_R100 },
 150         { "VE QY", RADEON_RV100 },
 151         { "VE QZ", RADEON_RV100 },
 152         { "M7 LW", RADEON_M7 },
 153         { "M7 LX", RADEON_M7 },
 154         { "M6 LY", RADEON_M6 },
 155         { "M6 LZ", RADEON_M6 },
 156         { "8500 QL", RADEON_R200 },
 157         { "8500 QN", RADEON_R200 },
 158         { "8500 QO", RADEON_R200 },
 159         { "8500 Ql", RADEON_R200 },
 160         { "8500 BB", RADEON_R200 },
 161         { "7500 QW", RADEON_RV200 },
 162         { "7500 QX", RADEON_RV200 },
 163         { "9000 Id", RADEON_RV250 },
 164         { "9000 Ie", RADEON_RV250 },
 165         { "9000 If", RADEON_RV250 },
 166         { "9000 Ig", RADEON_RV250 },
 167         { "M9 Ld", RADEON_M9 },
 168         { "M9 Le", RADEON_M9 },
 169         { "M9 Lf", RADEON_M9 },
 170         { "M9 Lg", RADEON_M9 },
 171         { "9700 ND", RADEON_R300 },
 172         { "9700 NE", RADEON_R300 },
 173         { "9700 NF", RADEON_R300 },
 174         { "9700 NG", RADEON_R300 },
 175         { "9100 QM", RADEON_R200 }
 176 };
 177
 178
 179 enum radeon_montype
 180 {
 181         MT_NONE,
 182         MT_CRT,         /* CRT */
 183         MT_LCD,         /* LCD */
 184         MT_DFP,         /* DVI */
 185         MT_CTV,         /* composite TV */
 186         MT_STV          /* S-Video out */
 187 };
 188
 189
 190 static struct pci_device_id radeonfb_pci_table[] = {
 191         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QD},
 192         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QE},
 193         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QF},
 194         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QG, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QG},
 195         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QY, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QY},
 196         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QZ, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QZ},
 197         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_LW, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_LW},
 198         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_LX, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_LX},
 199         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_LY, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_LY},
 200         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_LZ, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_LZ},
 201         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QL, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QL},
 202         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QN, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QN},
 203         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QO, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QO},
 204         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_Ql, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_Ql},
 205         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_BB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_BB},
 206         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QW, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QW},
 207         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QX, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QX},
 208         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_Id, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_Id},
 209         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_Ie, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_Ie},
 210         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_If, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_If},
 211         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_Ig, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_Ig},
 212         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_Ya, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_Ya},
 213         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_Yd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_Yd},
 214         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_Ld, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_Ld},
 215         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_Le, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_Le},
 216         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_Lf, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_Lf},
 217         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_Lg, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_Lg},
 218         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_ND, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_ND},
 219         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_NE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_NE},
 220         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_NF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_NF},
 221         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_NG, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_NG},
 222         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QM, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QM},
 223         { 0, }
 224 };
 225 MODULE_DEVICE_TABLE(pci, radeonfb_pci_table);
 226
 227
 228 typedef struct {
 229         u16 reg;
 230         u32 val;
 231 } reg_val;
 232
 233
 234 /* these common regs are cleared before mode setting so they do not
 235  * interfere with anything
 236  */
 237 static reg_val common_regs[] = {
 238         { OVR_CLR, 0 },
 239         { OVR_WID_LEFT_RIGHT, 0 },
 240         { OVR_WID_TOP_BOTTOM, 0 },
 241         { OV0_SCALE_CNTL, 0 },
 242         { SUBPIC_CNTL, 0 },
 243         { VIPH_CONTROL, 0 },
 244         { I2C_CNTL_1, 0 },
 245         { GEN_INT_CNTL, 0 },
 246         { CAP0_TRIG_CNTL, 0 },
 247 };
 248
 249 static reg_val common_regs_m6[] = {
 250         { OVR_CLR,      0 },
 251         { OVR_WID_LEFT_RIGHT,   0 },
 252         { OVR_WID_TOP_BOTTOM,   0 },
 253         { OV0_SCALE_CNTL,   0 },
 254         { SUBPIC_CNTL,      0 },
 255         { GEN_INT_CNTL,     0 },
 256         { CAP0_TRIG_CNTL,   0 }
 257 };
 258
 259 typedef struct {
 260         u8 clock_chip_type;
 261         u8 struct_size;
 262         u8 accelerator_entry;
 263         u8 VGA_entry;
 264         u16 VGA_table_offset;
 265         u16 POST_table_offset;
 266         u16 XCLK;
 267         u16 MCLK;
 268         u8 num_PLL_blocks;
 269         u8 size_PLL_blocks;
 270         u16 PCLK_ref_freq;
 271         u16 PCLK_ref_divider;
 272         u32 PCLK_min_freq;
 273         u32 PCLK_max_freq;
 274         u16 MCLK_ref_freq;
 275         u16 MCLK_ref_divider;
 276         u32 MCLK_min_freq;
 277         u32 MCLK_max_freq;
 278         u16 XCLK_ref_freq;
 279         u16 XCLK_ref_divider;
 280         u32 XCLK_min_freq;
 281         u32 XCLK_max_freq;
 282 } __attribute__ ((packed)) PLL_BLOCK;
 283
 284
 285 struct pll_info {
 286         int ppll_max;
 287         int ppll_min;
 288         int xclk;
 289         int ref_div;
 290         int ref_clk;
 291 };
 292
 293
 294 struct ram_info {
 295         int ml;
 296         int mb;
 297         int trcd;
 298         int trp;
 299         int twr;
 300         int cl;
 301         int tr2w;
 302         int loop_latency;
 303         int rloop;
 304 };
 305
 306
 307 struct radeon_regs {
 308         /* CRTC regs */
 309         u32 crtc_h_total_disp;
 310         u32 crtc_h_sync_strt_wid;
 311         u32 crtc_v_total_disp;
 312         u32 crtc_v_sync_strt_wid;
 313         u32 crtc_pitch;
 314         u32 crtc_gen_cntl;
 315         u32 crtc_ext_cntl;
 316         u32 dac_cntl;
 317
 318         u32 flags;
 319         u32 pix_clock;
 320         int xres, yres;
 321
 322         /* DDA regs */
 323         u32 dda_config;
 324         u32 dda_on_off;
 325
 326         /* PLL regs */
 327         u32 ppll_div_3;
 328         u32 ppll_ref_div;
 329         u32 vclk_ecp_cntl;
 330
 331         /* Flat panel regs */
 332         u32 fp_crtc_h_total_disp;
 333         u32 fp_crtc_v_total_disp;
 334         u32 fp_gen_cntl;
 335         u32 fp_h_sync_strt_wid;
 336         u32 fp_horz_stretch;
 337         u32 fp_panel_cntl;
 338         u32 fp_v_sync_strt_wid;
 339         u32 fp_vert_stretch;
 340         u32 lvds_gen_cntl;
 341         u32 lvds_pll_cntl;
 342         u32 tmds_crc;
 343         u32 tmds_transmitter_cntl;
 344
 345 #if defined(__BIG_ENDIAN)
 346         u32 surface_cntl;
 347 #endif
 348 };
 349
 350
 351 struct radeonfb_info {
 352         struct fb_info info;
 353
 354         struct radeon_regs state;
 355         struct radeon_regs init_state;
 356
 357         char name[32];
 358         char ram_type[12];
 359
 360         unsigned long mmio_base_phys;
 361         unsigned long fb_base_phys;
 362
 363         void __iomem *mmio_base;
 364         void __iomem *fb_base;
 365
 366         struct pci_dev *pdev;
 367
 368         unsigned char *EDID;
 369         unsigned char __iomem *bios_seg;
 370
 371         u32 pseudo_palette[17];
 372         struct { u8 red, green, blue, pad; } palette[256];
 373
 374         int chipset;
 375         unsigned char arch;
 376         int video_ram;
 377         u8 rev;
 378         int pitch, bpp, depth;
 379         int xres, yres, pixclock;
 380         int xres_virtual, yres_virtual;
 381         u32 accel_flags;
 382
 383         int use_default_var;
 384         int got_dfpinfo;
 385
 386         int hasCRTC2;
 387         int crtDisp_type;
 388         int dviDisp_type;
 389
 390         int panel_xres, panel_yres;
 391         int clock;
 392         int hOver_plus, hSync_width, hblank;
 393         int vOver_plus, vSync_width, vblank;
 394         int hAct_high, vAct_high, interlaced;
 395         int synct, misc;
 396
 397         u32 dp_gui_master_cntl;
 398
 399         struct pll_info pll;
 400         int pll_output_freq, post_div, fb_div;
 401
 402         struct ram_info ram;
 403
 404         int mtrr_hdl;
 405
 406 #ifdef CONFIG_PMAC_PBOOK
 407         int pm_reg;
 408         u32 save_regs[64];
 409         u32 mdll, mdll2;
 410 #endif /* CONFIG_PMAC_PBOOK */
 411         int asleep;
 412
 413         struct radeonfb_info *next;
 414 };
 415
 416
 417 static struct fb_var_screeninfo radeonfb_default_var = {
 418         640, 480, 640, 480, 0, 0, 8, 0,
 419         {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0},
 420         0, 0, -1, -1, 0, 39721, 40, 24, 32, 11, 96, 2,
 421         0, FB_VMODE_NONINTERLACED
 422 };
 423
 424 /*
 425  * IO macros
 426  */
 427
 428 #define INREG8(addr)            readb((rinfo->mmio_base)+addr)
 429 #define OUTREG8(addr,val)       writeb(val, (rinfo->mmio_base)+addr)
 430 #define INREG(addr)             readl((rinfo->mmio_base)+addr)
 431 #define OUTREG(addr,val)        writel(val, (rinfo->mmio_base)+addr)
 432
 433 #define OUTPLL(addr,val)        \
 434         do {    \
 435                 OUTREG8(CLOCK_CNTL_INDEX, (addr & 0x0000003f) | 0x00000080); \
 436                 OUTREG(CLOCK_CNTL_DATA, val); \
 437         } while(0)
 438
 439 #define OUTPLLP(addr,val,mask)                                          \
 440         do {                                                            \
 441                 unsigned int _tmp = INPLL(addr);                        \
 442                 _tmp &= (mask);                                         \
 443                 _tmp |= (val);                                          \
 444                 OUTPLL(addr, _tmp);                                     \
 445         } while (0)
 446
 447 #define OUTREGP(addr,val,mask)                                          \
 448         do {                                                            \
 449                 unsigned int _tmp = INREG(addr);                        \
 450                 _tmp &= (mask);                                         \
 451                 _tmp |= (val);                                          \
 452                 OUTREG(addr, _tmp);                                     \
 453         } while (0)
 454
 455
 456 static __inline__ u32 _INPLL(struct radeonfb_info *rinfo, u32 addr)
 457 {
 458         OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000003f);
 459         return (INREG(CLOCK_CNTL_DATA));
 460 }
 461
 462 #define INPLL(addr)             _INPLL(rinfo, addr)
 463
 464 #define PRIMARY_MONITOR(rinfo)  ((rinfo->dviDisp_type != MT_NONE) &&    \
 465                                  (rinfo->dviDisp_type != MT_STV) &&     \
 466                                  (rinfo->dviDisp_type != MT_CTV) ?      \
 467                                  rinfo->dviDisp_type : rinfo->crtDisp_type)
 468
 469 static char *GET_MON_NAME(int type)
 470 {
 471         char *pret = NULL;
 472
 473         switch (type) {
 474                 case MT_NONE:
 475                         pret = "no";
 476                         break;
 477                 case MT_CRT:
 478                         pret = "CRT";
 479                         break;
 480                 case MT_DFP:
 481                         pret = "DFP";
 482                         break;
 483                 case MT_LCD:
 484                         pret = "LCD";
 485                         break;
 486                 case MT_CTV:
 487                         pret = "CTV";
 488                         break;
 489                 case MT_STV:
 490                         pret = "STV";
 491                         break;
 492         }
 493
 494         return pret;
 495 }
 496
 497
 498 /*
 499  * 2D engine routines
 500  */
 501
 502 static __inline__ void radeon_engine_flush (struct radeonfb_info *rinfo)
 503 {
 504         int i;
 505
 506         /* initiate flush */
 507         OUTREGP(RB2D_DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL,
 508                 ~RB2D_DC_FLUSH_ALL);
 509
 510         for (i=0; i < 2000000; i++) {
 511                 if (!(INREG(RB2D_DSTCACHE_CTLSTAT) & RB2D_DC_BUSY))
 512                         break;
 513         }
 514 }
 515
 516
 517 static __inline__ void _radeon_fifo_wait (struct radeonfb_info *rinfo, int entries)
 518 {
 519         int i;
 520
 521         for (i=0; i<2000000; i++)
 522                 if ((INREG(RBBM_STATUS) & 0x7f) >= entries)
 523                         return;
 524 }
 525
 526
 527 static __inline__ void _radeon_engine_idle (struct radeonfb_info *rinfo)
 528 {
 529         int i;
 530
 531         /* ensure FIFO is empty before waiting for idle */
 532         _radeon_fifo_wait (rinfo, 64);
 533
 534         for (i=0; i<2000000; i++) {
 535                 if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) {
 536                         radeon_engine_flush (rinfo);
 537                         return;
 538                 }
 539         }
 540 }
 541
 542
 543 #define radeon_engine_idle()            _radeon_engine_idle(rinfo)
 544 #define radeon_fifo_wait(entries)       _radeon_fifo_wait(rinfo,entries)
 545
 546
 547
 548 /*
 549  * helper routines
 550  */
 551
 552 static __inline__ u32 radeon_get_dstbpp(u16 depth)
 553 {
 554         switch (depth) {
 555                 case 8:
 556                         return DST_8BPP;
 557                 case 15:
 558                         return DST_15BPP;
 559                 case 16:
 560                         return DST_16BPP;
 561                 case 32:
 562                         return DST_32BPP;
 563                 default:
 564                         return 0;
 565         }
 566 }
 567
 568
 569 static inline int var_to_depth(const struct fb_var_screeninfo *var)
 570 {
 571         if (var->bits_per_pixel != 16)
 572                 return var->bits_per_pixel;
 573         return (var->green.length == 6) ? 16 : 15;
 574 }
 575
 576
 577 static void _radeon_engine_reset(struct radeonfb_info *rinfo)
 578 {
 579         u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset;
 580
 581         radeon_engine_flush (rinfo);
 582
 583         clock_cntl_index = INREG(CLOCK_CNTL_INDEX);
 584         mclk_cntl = INPLL(MCLK_CNTL);
 585
 586         OUTPLL(MCLK_CNTL, (mclk_cntl |
 587                            FORCEON_MCLKA |
 588                            FORCEON_MCLKB |
 589                            FORCEON_YCLKA |
 590                            FORCEON_YCLKB |
 591                            FORCEON_MC |
 592                            FORCEON_AIC));
 593         rbbm_soft_reset = INREG(RBBM_SOFT_RESET);
 594
 595         OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset |
 596                                 SOFT_RESET_CP |
 597                                 SOFT_RESET_HI |
 598                                 SOFT_RESET_SE |
 599                                 SOFT_RESET_RE |
 600                                 SOFT_RESET_PP |
 601                                 SOFT_RESET_E2 |
 602                                 SOFT_RESET_RB);
 603         INREG(RBBM_SOFT_RESET);
 604         OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset & (u32)
 605                                 ~(SOFT_RESET_CP |
 606                                   SOFT_RESET_HI |
 607                                   SOFT_RESET_SE |
 608                                   SOFT_RESET_RE |
 609                                   SOFT_RESET_PP |
 610                                   SOFT_RESET_E2 |
 611                                   SOFT_RESET_RB));
 612         INREG(RBBM_SOFT_RESET);
 613
 614         OUTPLL(MCLK_CNTL, mclk_cntl);
 615         OUTREG(CLOCK_CNTL_INDEX, clock_cntl_index);
 616         OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset);
 617
 618         return;
 619 }
 620
 621 #define radeon_engine_reset()           _radeon_engine_reset(rinfo)
 622
 623
 624 static __inline__ int round_div(int num, int den)
 625 {
 626         return (num + (den / 2)) / den;
 627 }
 628
 629
 630
 631 static __inline__ int min_bits_req(int val)
 632 {
 633         int bits_req = 0;
 634
 635         if (val == 0)
 636                 bits_req = 1;
 637
 638         while (val) {
 639                 val >>= 1;
 640                 bits_req++;
 641         }
 642
 643         return (bits_req);
 644 }
 645
 646
 647 static __inline__ int _max(int val1, int val2)
 648 {
 649         if (val1 >= val2)
 650                 return val1;
 651         else
 652                 return val2;
 653 }
 654
 655
 656
 657 /*
 658  * globals
 659  */
 660
 661 #ifndef MODULE
 662 static char *mode_option;
 663 #endif
 664
 665 static char noaccel = 0;
 666 static char mirror = 0;
 667 static int panel_yres = 0;
 668 static char force_dfp = 0;
 669 static struct radeonfb_info *board_list = NULL;
 670 static char nomtrr = 0;
 671
 672 /*
 673  * prototypes
 674  */
 675
 676 static void radeon_save_state (struct radeonfb_info *rinfo,
 677                                struct radeon_regs *save);
 678 static void radeon_engine_init (struct radeonfb_info *rinfo);
 679 static void radeon_write_mode (struct radeonfb_info *rinfo,
 680                                struct radeon_regs *mode);
 681 static int __devinit radeon_set_fbinfo (struct radeonfb_info *rinfo);
 682 static int __devinit radeon_init_disp (struct radeonfb_info *rinfo);
 683 static int radeon_init_disp_var (struct radeonfb_info *rinfo, struct fb_var_screeninfo *var);
 684 static void __iomem *radeon_find_rom(struct radeonfb_info *rinfo);
 685 static void radeon_get_pllinfo(struct radeonfb_info *rinfo, void __iomem *bios_seg);
 686 static void radeon_get_moninfo (struct radeonfb_info *rinfo);
 687 static int radeon_get_dfpinfo (struct radeonfb_info *rinfo);
 688 static int radeon_get_dfpinfo_BIOS(struct radeonfb_info *rinfo);
 689 static void radeon_get_EDID(struct radeonfb_info *rinfo);
 690 static int radeon_dfp_parse_EDID(struct radeonfb_info *rinfo);
 691 static void radeon_update_default_var(struct radeonfb_info *rinfo);
 692
 693 #ifdef CONFIG_PPC_OF
 694
 695 static int radeon_read_OF (struct radeonfb_info *rinfo);
 696 static int radeon_get_EDID_OF(struct radeonfb_info *rinfo);
 697 extern struct device_node *pci_device_to_OF_node(struct pci_dev *dev);
 698
 699 #ifdef CONFIG_PMAC_PBOOK
 700 int radeon_sleep_notify(struct pmu_sleep_notifier *self, int when);
 701 static struct pmu_sleep_notifier radeon_sleep_notifier = {
 702         radeon_sleep_notify, SLEEP_LEVEL_VIDEO,
 703 };
 704 #endif /* CONFIG_PMAC_PBOOK */
 705 #ifdef CONFIG_PMAC_BACKLIGHT
 706 static int radeon_set_backlight_enable(int on, int level, void *data);
 707 static int radeon_set_backlight_level(int level, void *data);
 708 static struct backlight_controller radeon_backlight_controller = {
 709         radeon_set_backlight_enable,
 710         radeon_set_backlight_level
 711 };
 712 #endif /* CONFIG_PMAC_BACKLIGHT */
 713
 714 #endif /* CONFIG_PPC_OF */
 715
 716
 717 static void __iomem *radeon_find_rom(struct radeonfb_info *rinfo)
 718 {
 719 #if defined(__i386__)
 720         u32  segstart;
 721         char __iomem *rom_base;
 722         char __iomem *rom;
 723         int  stage;
 724         int  i,j;
 725         char aty_rom_sig[] = "761295520";
 726         char *radeon_sig[] = {
 727           "RG6",
 728           "RADEON"
 729         };
 730
 731         for(segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) {
 732
 733                 stage = 1;
 734
 735                 rom_base = ioremap(segstart, 0x1000);
 736
 737                 if ((*rom_base == 0x55) && (((*(rom_base + 1)) & 0xff) == 0xaa))
 738                         stage = 2;
 739
 740
 741                 if (stage != 2) {
 742                         iounmap(rom_base);
 743                         continue;
 744                 }
 745
 746                 rom = rom_base;
 747
 748                 for (i = 0; (i < 128 - strlen(aty_rom_sig)) && (stage != 3); i++) {
 749                         if (aty_rom_sig[0] == *rom)
 750                                 if (strncmp(aty_rom_sig, rom,
 751                                                 strlen(aty_rom_sig)) == 0)
 752                                         stage = 3;
 753                         rom++;
 754                 }
 755                 if (stage != 3) {
 756                         iounmap(rom_base);
 757                         continue;
 758                 }
 759                 rom = rom_base;
 760
 761                 for (i = 0; (i < 512) && (stage != 4); i++) {
 762                     for(j = 0;j < sizeof(radeon_sig)/sizeof(char *);j++) {
 763                         if (radeon_sig[j][0] == *rom)
 764                                 if (strncmp(radeon_sig[j], rom,
 765                                             strlen(radeon_sig[j])) == 0) {
 766                                               stage = 4;
 767                                               break;
 768                                             }
 769                     }
 770                         rom++;
 771                 }
 772                 if (stage != 4) {
 773                         iounmap(rom_base);
 774                         continue;
 775                 }
 776
 777                 return rom_base;
 778         }
 779 #endif
 780         return NULL;
 781 }
 782
 783
 784
 785
 786 static void radeon_get_pllinfo(struct radeonfb_info *rinfo, void __iomem *bios_seg)
 787 {
 788         void __iomem *bios_header;
 789         void __iomem *header_ptr;
 790         u16 bios_header_offset, pll_info_offset;
 791         PLL_BLOCK pll;
 792
 793         if (bios_seg) {
 794                 bios_header = bios_seg + 0x48L;
 795                 header_ptr  = bios_header;
 796
 797                 bios_header_offset = readw(header_ptr);
 798                 bios_header = bios_seg + bios_header_offset;
 799                 bios_header += 0x30;
 800
 801                 header_ptr = bios_header;
 802                 pll_info_offset = readw(header_ptr);
 803                 header_ptr = bios_seg + pll_info_offset;
 804
 805                 memcpy_fromio(&pll, header_ptr, 50);
 806
 807                 rinfo->pll.xclk = (u32)pll.XCLK;
 808                 rinfo->pll.ref_clk = (u32)pll.PCLK_ref_freq;
 809                 rinfo->pll.ref_div = (u32)pll.PCLK_ref_divider;
 810                 rinfo->pll.ppll_min = pll.PCLK_min_freq;
 811                 rinfo->pll.ppll_max = pll.PCLK_max_freq;
 812
 813                 printk("radeonfb: ref_clk=%d, ref_div=%d, xclk=%d from BIOS\n",
 814                         rinfo->pll.ref_clk, rinfo->pll.ref_div, rinfo->pll.xclk);
 815         } else {
 816 #ifdef CONFIG_PPC_OF
 817                 if (radeon_read_OF(rinfo)) {
 818                         unsigned int tmp, Nx, M, ref_div, xclk;
 819
 820                         tmp = INPLL(M_SPLL_REF_FB_DIV);
 821                         ref_div = INPLL(PPLL_REF_DIV) & 0x3ff;
 822
 823                         Nx = (tmp & 0xff00) >> 8;
 824                         M = (tmp & 0xff);
 825                         xclk = ((((2 * Nx * rinfo->pll.ref_clk) + (M)) /
 826                                 (2 * M)));
 827
 828                         rinfo->pll.xclk = xclk;
 829                         rinfo->pll.ref_div = ref_div;
 830                         rinfo->pll.ppll_min = 12000;
 831                         rinfo->pll.ppll_max = 35000;
 832
 833                         printk("radeonfb: ref_clk=%d, ref_div=%d, xclk=%d from OF\n",
 834                                 rinfo->pll.ref_clk, rinfo->pll.ref_div, rinfo->pll.xclk);
 835
 836                         return;
 837                 }
 838 #endif
 839                 /* no BIOS or BIOS not found, use defaults */
 840                 switch (rinfo->chipset) {
 841                         case PCI_DEVICE_ID_ATI_RADEON_QW:
 842                         case PCI_DEVICE_ID_ATI_RADEON_QX:
 843                                 rinfo->pll.ppll_max = 35000;
 844                                 rinfo->pll.ppll_min = 12000;
 845                                 rinfo->pll.xclk = 23000;
 846                                 rinfo->pll.ref_div = 12;
 847                                 rinfo->pll.ref_clk = 2700;
 848                                 break;
 849                         case PCI_DEVICE_ID_ATI_RADEON_QL:
 850                         case PCI_DEVICE_ID_ATI_RADEON_QN:
 851                         case PCI_DEVICE_ID_ATI_RADEON_QO:
 852                         case PCI_DEVICE_ID_ATI_RADEON_Ql:
 853                         case PCI_DEVICE_ID_ATI_RADEON_BB:
 854                                 rinfo->pll.ppll_max = 35000;
 855                                 rinfo->pll.ppll_min = 12000;
 856                                 rinfo->pll.xclk = 27500;
 857                                 rinfo->pll.ref_div = 12;
 858                                 rinfo->pll.ref_clk = 2700;
 859                                 break;
 860                         case PCI_DEVICE_ID_ATI_RADEON_Id:
 861                         case PCI_DEVICE_ID_ATI_RADEON_Ie:
 862                         case PCI_DEVICE_ID_ATI_RADEON_If:
 863                         case PCI_DEVICE_ID_ATI_RADEON_Ig:
 864                                 rinfo->pll.ppll_max = 35000;
 865                                 rinfo->pll.ppll_min = 12000;
 866                                 rinfo->pll.xclk = 25000;
 867                                 rinfo->pll.ref_div = 12;
 868                                 rinfo->pll.ref_clk = 2700;
 869                                 break;
 870                         case PCI_DEVICE_ID_ATI_RADEON_ND:
 871                         case PCI_DEVICE_ID_ATI_RADEON_NE:
 872                         case PCI_DEVICE_ID_ATI_RADEON_NF:
 873                         case PCI_DEVICE_ID_ATI_RADEON_NG:
 874                                 rinfo->pll.ppll_max = 40000;
 875                                 rinfo->pll.ppll_min = 20000;
 876                                 rinfo->pll.xclk = 27000;
 877                                 rinfo->pll.ref_div = 12;
 878                                 rinfo->pll.ref_clk = 2700;
 879                                 break;
 880                         case PCI_DEVICE_ID_ATI_RADEON_QD:
 881                         case PCI_DEVICE_ID_ATI_RADEON_QE:
 882                         case PCI_DEVICE_ID_ATI_RADEON_QF:
 883                         case PCI_DEVICE_ID_ATI_RADEON_QG:
 884                         default:
 885                                 rinfo->pll.ppll_max = 35000;
 886                                 rinfo->pll.ppll_min = 12000;
 887                                 rinfo->pll.xclk = 16600;
 888                                 rinfo->pll.ref_div = 67;
 889                                 rinfo->pll.ref_clk = 2700;
 890                                 break;
 891                 }
 892
 893                 printk("radeonfb: ref_clk=%d, ref_div=%d, xclk=%d defaults\n",
 894                         rinfo->pll.ref_clk, rinfo->pll.ref_div, rinfo->pll.xclk);
 895         }
 896 }
 897
 898
 899 static void radeon_get_moninfo (struct radeonfb_info *rinfo)
 900 {
 901         unsigned int tmp;
 902
 903         if (force_dfp) {
 904                 rinfo->dviDisp_type = MT_DFP;
 905                 return;
 906         }
 907
 908         tmp = INREG(BIOS_4_SCRATCH);
 909         printk(KERN_DEBUG "radeon_get_moninfo: bios 4 scratch = %x\n", tmp);
 910
 911         if (rinfo->hasCRTC2) {
 912                 /* primary DVI port */
 913                 if (tmp & 0x08)
 914                         rinfo->dviDisp_type = MT_DFP;
 915                 else if (tmp & 0x4)
 916                         rinfo->dviDisp_type = MT_LCD;
 917                 else if (tmp & 0x200)
 918                         rinfo->dviDisp_type = MT_CRT;
 919                 else if (tmp & 0x10)
 920                         rinfo->dviDisp_type = MT_CTV;
 921                 else if (tmp & 0x20)
 922                         rinfo->dviDisp_type = MT_STV;
 923
 924                 /* secondary CRT port */
 925                 if (tmp & 0x2)
 926                         rinfo->crtDisp_type = MT_CRT;
 927                 else if (tmp & 0x800)
 928                         rinfo->crtDisp_type = MT_DFP;
 929                 else if (tmp & 0x400)
 930                         rinfo->crtDisp_type = MT_LCD;
 931                 else if (tmp & 0x1000)
 932                         rinfo->crtDisp_type = MT_CTV;
 933                 else if (tmp & 0x2000)
 934                         rinfo->crtDisp_type = MT_STV;
 935         } else {
 936                 rinfo->dviDisp_type = MT_NONE;
 937
 938                 tmp = INREG(FP_GEN_CNTL);
 939
 940                 if (tmp & FP_EN_TMDS)
 941                         rinfo->crtDisp_type = MT_DFP;
 942                 else
 943                         rinfo->crtDisp_type = MT_CRT;
 944         }
 945 }
 946
 947
 948
 949 static void radeon_get_EDID(struct radeonfb_info *rinfo)
 950 {
 951 #ifdef CONFIG_PPC_OF
 952         if (!radeon_get_EDID_OF(rinfo))
 953                 RTRACE("radeonfb: could not retrieve EDID from OF\n");
 954 #else
 955         /* XXX use other methods later */
 956 #endif
 957 }
 958
 959
 960 #ifdef CONFIG_PPC_OF
 961 static int radeon_get_EDID_OF(struct radeonfb_info *rinfo)
 962 {
 963         struct device_node *dp;
 964         unsigned char *pedid = NULL;
 965         static char *propnames[] = { "DFP,EDID", "LCD,EDID", "EDID", "EDID1", NULL };
 966         int i;
 967
 968         dp = pci_device_to_OF_node(rinfo->pdev);
 969         while (dp != NULL) {
 970                 for (i = 0; propnames[i] != NULL; ++i) {
 971                         pedid = (unsigned char *)
 972                                 get_property(dp, propnames[i], NULL);
 973                         if (pedid != NULL) {
 974                                 rinfo->EDID = pedid;
 975                                 return 1;
 976                         }
 977                 }
 978                 dp = dp->child;
 979         }
 980         return 0;
 981 }
 982 #endif /* CONFIG_PPC_OF */
 983
 984
 985 static int radeon_dfp_parse_EDID(struct radeonfb_info *rinfo)
 986 {
 987         unsigned char *block = rinfo->EDID;
 988
 989         if (!block)
 990                 return 0;
 991
 992         /* jump to the detailed timing block section */
 993         block += 54;
 994
 995         rinfo->clock = (block[0] + (block[1] << 8));
 996         rinfo->panel_xres = (block[2] + ((block[4] & 0xf0) << 4));
 997         rinfo->hblank = (block[3] + ((block[4] & 0x0f) << 8));
 998         rinfo->panel_yres = (block[5] + ((block[7] & 0xf0) << 4));
 999         rinfo->vblank = (block[6] + ((block[7] & 0x0f) << 8));
1000         rinfo->hOver_plus = (block[8] + ((block[11] & 0xc0) << 2));
1001         rinfo->hSync_width = (block[9] + ((block[11] & 0x30) << 4));
1002         rinfo->vOver_plus = ((block[10] >> 4) + ((block[11] & 0x0c) << 2));
1003         rinfo->vSync_width = ((block[10] & 0x0f) + ((block[11] & 0x03) << 4));
1004         rinfo->interlaced = ((block[17] & 0x80) >> 7);
1005         rinfo->synct = ((block[17] & 0x18) >> 3);
1006         rinfo->misc = ((block[17] & 0x06) >> 1);
1007         rinfo->hAct_high = rinfo->vAct_high = 0;
1008         if (rinfo->synct == 3) {
1009                 if (rinfo->misc & 2)
1010                         rinfo->hAct_high = 1;
1011                 if (rinfo->misc & 1)
1012                         rinfo->vAct_high = 1;
1013         }
1014
1015         printk("radeonfb: detected DFP panel size from EDID: %dx%d\n",
1016                 rinfo->panel_xres, rinfo->panel_yres);
1017
1018         rinfo->got_dfpinfo = 1;
1019
1020         return 1;
1021 }
1022
1023
1024 static void radeon_update_default_var(struct radeonfb_info *rinfo)
1025 {
1026         struct fb_var_screeninfo *var = &radeonfb_default_var;
1027
1028         var->xres = rinfo->panel_xres;
1029         var->yres = rinfo->panel_yres;
1030         var->xres_virtual = rinfo->panel_xres;
1031         var->yres_virtual = rinfo->panel_yres;
1032         var->xoffset = var->yoffset = 0;
1033         var->bits_per_pixel = 8;
1034         var->pixclock = 100000000 / rinfo->clock;
1035         var->left_margin = (rinfo->hblank - rinfo->hOver_plus - rinfo->hSync_width);
1036         var->right_margin = rinfo->hOver_plus;
1037         var->upper_margin = (rinfo->vblank - rinfo->vOver_plus - rinfo->vSync_width);
1038         var->lower_margin = rinfo->vOver_plus;
1039         var->hsync_len = rinfo->hSync_width;
1040         var->vsync_len = rinfo->vSync_width;
1041         var->sync = 0;
1042         if (rinfo->synct == 3) {
1043                 if (rinfo->hAct_high)
1044                         var->sync |= FB_SYNC_HOR_HIGH_ACT;
1045                 if (rinfo->vAct_high)
1046                         var->sync |= FB_SYNC_VERT_HIGH_ACT;
1047         }
1048
1049         var->vmode = 0;
1050         if (rinfo->interlaced)
1051                 var->vmode |= FB_VMODE_INTERLACED;
1052
1053         rinfo->use_default_var = 1;
1054 }
1055
1056
1057 static int radeon_get_dfpinfo_BIOS(struct radeonfb_info *rinfo)
1058 {
1059         char __iomem *fpbiosstart, *tmp, *tmp0;
1060         char stmp[30];
1061         int i;
1062
1063         if (!rinfo->bios_seg)
1064                 return 0;
1065
1066         if (!(fpbiosstart = rinfo->bios_seg + readw(rinfo->bios_seg + 0x48))) {
1067                 printk("radeonfb: Failed to detect DFP panel info using BIOS\n");
1068                 return 0;
1069         }
1070
1071         if (!(tmp = rinfo->bios_seg + readw(fpbiosstart + 0x40))) {
1072                 printk("radeonfb: Failed to detect DFP panel info using BIOS\n");
1073                 return 0;
1074         }
1075
1076         for(i=0; i<24; i++)
1077                 stmp[i] = readb(tmp+i+1);
1078         stmp[24] = 0;
1079         printk("radeonfb: panel ID string: %s\n", stmp);
1080         rinfo->panel_xres = readw(tmp + 25);
1081         rinfo->panel_yres = readw(tmp + 27);
1082         printk("radeonfb: detected DFP panel size from BIOS: %dx%d\n",
1083                 rinfo->panel_xres, rinfo->panel_yres);
1084
1085         for(i=0; i<32; i++) {
1086                 tmp0 = rinfo->bios_seg + readw(tmp+64+i*2);
1087                 if (tmp0 == 0)
1088                         break;
1089                 if ((readw(tmp0) == rinfo->panel_xres) &&
1090                     (readw(tmp0+2) == rinfo->panel_yres)) {
1091                         rinfo->hblank = (readw(tmp0+17) - readw(tmp0+19)) * 8;
1092                         rinfo->hOver_plus = ((readw(tmp0+21) - readw(tmp0+19) -1) * 8) & 0x7fff;
1093                         rinfo->hSync_width = readb(tmp0+23) * 8;
1094                         rinfo->vblank = readw(tmp0+24) - readw(tmp0+26);
1095                         rinfo->vOver_plus = (readw(tmp0+28) & 0x7ff) - readw(tmp0+26);
1096                         rinfo->vSync_width = (readw(tmp0+28) & 0xf800) >> 11;
1097                         rinfo->clock = readw(tmp0+9);
1098
1099                         rinfo->got_dfpinfo = 1;
1100                         return 1;
1101                 }
1102         }
1103
1104         return 0;
1105 }
1106
1107
1108
1109 static int radeon_get_dfpinfo (struct radeonfb_info *rinfo)
1110 {
1111         unsigned int tmp;
1112         unsigned short a, b;
1113
1114         if (radeon_get_dfpinfo_BIOS(rinfo))
1115                 radeon_update_default_var(rinfo);
1116
1117         if (radeon_dfp_parse_EDID(rinfo))
1118                 radeon_update_default_var(rinfo);
1119
1120         if (!rinfo->got_dfpinfo) {
1121                 /*
1122                  * it seems all else has failed now and we
1123                  * resort to probing registers for our DFP info
1124                  */
1125                 if (panel_yres) {
1126                         rinfo->panel_yres = panel_yres;
1127                 } else {
1128                         tmp = INREG(FP_VERT_STRETCH);
1129                         tmp &= 0x00fff000;
1130                         rinfo->panel_yres = (unsigned short)(tmp >> 0x0c) + 1;
1131                 }
1132
1133                 switch (rinfo->panel_yres) {
1134                         case 480:
1135                                 rinfo->panel_xres = 640;
1136                                 break;
1137                         case 600:
1138                                 rinfo->panel_xres = 800;
1139                                 break;
1140                         case 768:
1141 #if defined(__powerpc__)
1142                                 if (rinfo->dviDisp_type == MT_LCD)
1143                                         rinfo->panel_xres = 1152;
1144                                 else
1145 #endif
1146                                 rinfo->panel_xres = 1024;
1147                                 break;
1148                         case 1024:
1149                                 rinfo->panel_xres = 1280;
1150                                 break;
1151                         case 1050:
1152                                 rinfo->panel_xres = 1400;
1153                                 break;
1154                         case 1200:
1155                                 rinfo->panel_xres = 1600;
1156                                 break;
1157                         default:
1158                                 printk("radeonfb: Failed to detect DFP panel size\n");
1159                                 return 0;
1160                 }
1161
1162                 printk("radeonfb: detected DFP panel size from registers: %dx%d\n",
1163                         rinfo->panel_xres, rinfo->panel_yres);
1164
1165                 tmp = INREG(FP_CRTC_H_TOTAL_DISP);
1166                 a = (tmp & FP_CRTC_H_TOTAL_MASK) + 4;
1167                 b = (tmp & 0x01ff0000) >> FP_CRTC_H_DISP_SHIFT;
1168                 rinfo->hblank = (a - b + 1) * 8;
1169
1170                 tmp = INREG(FP_H_SYNC_STRT_WID);
1171                 rinfo->hOver_plus = (unsigned short) ((tmp & FP_H_SYNC_STRT_CHAR_MASK) >>
1172                                         FP_H_SYNC_STRT_CHAR_SHIFT) - b - 1;
1173                 rinfo->hOver_plus *= 8;
1174                 rinfo->hSync_width = (unsigned short) ((tmp & FP_H_SYNC_WID_MASK) >>
1175                                         FP_H_SYNC_WID_SHIFT);
1176                 rinfo->hSync_width *= 8;
1177                 tmp = INREG(FP_CRTC_V_TOTAL_DISP);
1178                 a = (tmp & FP_CRTC_V_TOTAL_MASK) + 1;
1179                 b = (tmp & FP_CRTC_V_DISP_MASK) >> FP_CRTC_V_DISP_SHIFT;
1180                 rinfo->vblank = a - b /* + 24 */ ;
1181
1182                 tmp = INREG(FP_V_SYNC_STRT_WID);
1183                 rinfo->vOver_plus = (unsigned short) (tmp & FP_V_SYNC_STRT_MASK)
1184                                         - b + 1;
1185                 rinfo->vSync_width = (unsigned short) ((tmp & FP_V_SYNC_WID_MASK) >>
1186                                         FP_V_SYNC_WID_SHIFT);
1187
1188                 return 1;
1189         }
1190
1191         return 1;
1192 }
1193
1194
1195 #ifdef CONFIG_PPC_OF
1196 static int radeon_read_OF (struct radeonfb_info *rinfo)
1197 {
1198         struct device_node *dp;
1199         unsigned int *xtal;
1200
1201         dp = pci_device_to_OF_node(rinfo->pdev);
1202
1203         xtal = (unsigned int *) get_property(dp, "ATY,RefCLK", NULL);
1204
1205         rinfo->pll.ref_clk = *xtal / 10;
1206
1207         if (*xtal)
1208                 return 1;
1209         else
1210                 return 0;
1211 }
1212 #endif
1213
1214
1215 static void radeon_engine_init (struct radeonfb_info *rinfo)
1216 {
1217         u32 temp;
1218
1219         /* disable 3D engine */
1220         OUTREG(RB3D_CNTL, 0);
1221
1222         radeon_engine_reset ();
1223
1224         radeon_fifo_wait (1);
1225         OUTREG(RB2D_DSTCACHE_MODE, 0);
1226
1227         radeon_fifo_wait (1);
1228         temp = INREG(DEFAULT_PITCH_OFFSET);
1229         OUTREG(DEFAULT_PITCH_OFFSET, ((temp & 0xc0000000) |
1230                                       (rinfo->pitch << 0x16)));
1231
1232         radeon_fifo_wait (1);
1233         OUTREGP(DP_DATATYPE, 0, ~HOST_BIG_ENDIAN_EN);
1234
1235         radeon_fifo_wait (1);
1236         OUTREG(DEFAULT_SC_BOTTOM_RIGHT, (DEFAULT_SC_RIGHT_MAX |
1237                                          DEFAULT_SC_BOTTOM_MAX));
1238
1239         temp = radeon_get_dstbpp(rinfo->depth);
1240         rinfo->dp_gui_master_cntl = ((temp << 8) | GMC_CLR_CMP_CNTL_DIS);
1241         radeon_fifo_wait (1);
1242         OUTREG(DP_GUI_MASTER_CNTL, (rinfo->dp_gui_master_cntl |
1243                                     GMC_BRUSH_SOLID_COLOR |
1244                                     GMC_SRC_DATATYPE_COLOR));
1245
1246         radeon_fifo_wait (7);
1247
1248         /* clear line drawing regs */
1249         OUTREG(DST_LINE_START, 0);
1250         OUTREG(DST_LINE_END, 0);
1251
1252         /* set brush color regs */
1253         OUTREG(DP_BRUSH_FRGD_CLR, 0xffffffff);
1254         OUTREG(DP_BRUSH_BKGD_CLR, 0x00000000);
1255
1256         /* set source color regs */
1257         OUTREG(DP_SRC_FRGD_CLR, 0xffffffff);
1258         OUTREG(DP_SRC_BKGD_CLR, 0x00000000);
1259
1260         /* default write mask */
1261         OUTREG(DP_WRITE_MSK, 0xffffffff);
1262
1263         radeon_engine_idle ();
1264 }
1265
1266
1267 static int __devinit radeon_init_disp (struct radeonfb_info *rinfo)
1268 {
1269         struct fb_info *info = &rinfo->info;
1270         struct fb_var_screeninfo var;
1271
1272         var = radeonfb_default_var;
1273         if ((radeon_init_disp_var(rinfo, &var)) < 0)
1274                 return -1;
1275
1276         rinfo->depth = var_to_depth(&var);
1277         rinfo->bpp = var.bits_per_pixel;
1278
1279         info->var = var;
1280         fb_alloc_cmap(&info->cmap, 256, 0);
1281
1282         var.activate = FB_ACTIVATE_NOW;
1283         return 0;
1284 }
1285
1286
1287 static int radeon_init_disp_var (struct radeonfb_info *rinfo,
1288                                  struct fb_var_screeninfo *var)
1289 {
1290 #ifndef MODULE
1291         if (mode_option)
1292                 fb_find_mode (var, &rinfo->info, mode_option,
1293                               NULL, 0, NULL, 8);
1294         else
1295 #endif
1296         if (rinfo->use_default_var)
1297                 /* We will use the modified default far */
1298                 *var = radeonfb_default_var;
1299         else
1300
1301                 fb_find_mode (var, &rinfo->info, "640x480-8@60",
1302                               NULL, 0, NULL, 0);
1303
1304         if (noaccel)
1305                 var->accel_flags &= ~FB_ACCELF_TEXT;
1306         else
1307                 var->accel_flags |= FB_ACCELF_TEXT;
1308
1309         return 0;
1310 }
1311
1312
1313 static int radeon_do_maximize(struct radeonfb_info *rinfo,
1314                                 struct fb_var_screeninfo *var,
1315                                 struct fb_var_screeninfo *v,
1316                                 int nom, int den)
1317 {
1318         static struct {
1319                 int xres, yres;
1320         } modes[] = {
1321                 {1600, 1280},
1322                 {1280, 1024},
1323                 {1024, 768},
1324                 {800, 600},
1325                 {640, 480},
1326                 {-1, -1}
1327         };
1328         int i;
1329
1330         /* use highest possible virtual resolution */
1331         if (v->xres_virtual == -1 && v->yres_virtual == -1) {
1332                 printk("radeonfb: using max available virtual resolution\n");
1333                 for (i=0; modes[i].xres != -1; i++) {
1334                         if (modes[i].xres * nom / den * modes[i].yres <
1335                             rinfo->video_ram / 2)
1336                                 break;
1337                 }
1338                 if (modes[i].xres == -1) {
1339                         printk("radeonfb: could not find virtual resolution that fits into video memory!\n");
1340                         return -EINVAL;
1341                 }
1342                 v->xres_virtual = modes[i].xres;
1343                 v->yres_virtual = modes[i].yres;
1344
1345                 printk("radeonfb: virtual resolution set to max of %dx%d\n",
1346                         v->xres_virtual, v->yres_virtual);
1347         } else if (v->xres_virtual == -1) {
1348                 v->xres_virtual = (rinfo->video_ram * den /
1349                                 (nom * v->yres_virtual * 2)) & ~15;
1350         } else if (v->yres_virtual == -1) {
1351                 v->xres_virtual = (v->xres_virtual + 15) & ~15;
1352                 v->yres_virtual = rinfo->video_ram * den /
1353                         (nom * v->xres_virtual *2);
1354         } else {
1355                 if (v->xres_virtual * nom / den * v->yres_virtual >
1356                         rinfo->video_ram) {
1357                         return -EINVAL;
1358                 }
1359         }
1360
1361         if (v->xres_virtual * nom / den >= 8192) {
1362                 v->xres_virtual = 8192 * den / nom - 16;
1363         }
1364
1365         if (v->xres_virtual < v->xres)
1366                 return -EINVAL;
1367
1368         if (v->yres_virtual < v->yres)
1369                 return -EINVAL;
1370
1371         return 0;
1372 }
1373
1374
1375 static int radeonfb_check_var (struct fb_var_screeninfo *var, struct fb_info *info)
1376 {
1377         struct radeonfb_info *rinfo = (struct radeonfb_info *) info->par;
1378         struct fb_var_screeninfo v;
1379         int nom, den;
1380
1381         memcpy (&v, var, sizeof (v));
1382
1383         switch (v.bits_per_pixel) {
1384                 case 0 ... 8:
1385                         v.bits_per_pixel = 8;
1386                         break;
1387                 case 9 ... 16:
1388                         v.bits_per_pixel = 16;
1389                         break;
1390                 case 17 ... 24:
1391 #if 0 /* Doesn't seem to work */
1392                         v.bits_per_pixel = 24;
1393                         break;
1394 #endif
1395                         return -EINVAL;
1396                 case 25 ... 32:
1397                         v.bits_per_pixel = 32;
1398                         break;
1399                 default:
1400                         return -EINVAL;
1401         }
1402
1403         switch (var_to_depth(&v)) {
1404                 case 8:
1405                         nom = den = 1;
1406                         v.red.offset = v.green.offset = v.blue.offset = 0;
1407                         v.red.length = v.green.length = v.blue.length = 8;
1408                         v.transp.offset = v.transp.length = 0;
1409                         break;
1410                 case 15:
1411                         nom = 2;
1412                         den = 1;
1413                         v.red.offset = 10;
1414                         v.green.offset = 5;
1415                         v.blue.offset = 0;
1416                         v.red.length = v.green.length = v.blue.length = 5;
1417                         v.transp.offset = v.transp.length = 0;
1418                         break;
1419                 case 16:
1420                         nom = 2;
1421                         den = 1;
1422                         v.red.offset = 11;
1423                         v.green.offset = 5;
1424                         v.blue.offset = 0;
1425                         v.red.length = 5;
1426                         v.green.length = 6;
1427                         v.blue.length = 5;
1428                         v.transp.offset = v.transp.length = 0;
1429                         break;
1430                 case 24:
1431                         nom = 4;
1432                         den = 1;
1433                         v.red.offset = 16;
1434                         v.green.offset = 8;
1435                         v.blue.offset = 0;
1436                         v.red.length = v.blue.length = v.green.length = 8;
1437                         v.transp.offset = v.transp.length = 0;
1438                         break;
1439                 case 32:
1440                         nom = 4;
1441                         den = 1;
1442                         v.red.offset = 16;
1443                         v.green.offset = 8;
1444                         v.blue.offset = 0;
1445                         v.red.length = v.blue.length = v.green.length = 8;
1446                         v.transp.offset = 24;
1447                         v.transp.length = 8;
1448                         break;
1449                 default:
1450                         printk ("radeonfb: mode %dx%dx%d rejected, color depth invalid\n",
1451                                 var->xres, var->yres, var->bits_per_pixel);
1452                         return -EINVAL;
1453         }
1454
1455         if (radeon_do_maximize(rinfo, var, &v, nom, den) < 0)
1456                 return -EINVAL;
1457
1458         if (v.xoffset < 0)
1459                 v.xoffset = 0;
1460         if (v.yoffset < 0)
1461                 v.yoffset = 0;
1462
1463         if (v.xoffset > v.xres_virtual - v.xres)
1464                 v.xoffset = v.xres_virtual - v.xres - 1;
1465
1466         if (v.yoffset > v.yres_virtual - v.yres)
1467                 v.yoffset = v.yres_virtual - v.yres - 1;
1468
1469         v.red.msb_right = v.green.msb_right = v.blue.msb_right =
1470                           v.transp.offset = v.transp.length =
1471                           v.transp.msb_right = 0;
1472
1473         if (noaccel)
1474                 v.accel_flags = 0;
1475
1476         memcpy(var, &v, sizeof(v));
1477
1478         return 0;
1479 }
1480
1481
1482 static int radeonfb_pan_display (struct fb_var_screeninfo *var,
1483                                  struct fb_info *info)
1484 {
1485         struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
1486
1487         if ((var->xoffset + var->xres > var->xres_virtual)
1488             || (var->yoffset + var->yres > var->yres_virtual))
1489                return -EINVAL;
1490
1491         if (rinfo->asleep)
1492                 return 0;
1493
1494         OUTREG(CRTC_OFFSET, ((var->yoffset * var->xres_virtual + var->xoffset)
1495                              * var->bits_per_pixel / 8) & ~7);
1496         return 0;
1497 }
1498
1499
1500 static int radeonfb_ioctl (struct inode *inode, struct file *file, unsigned int cmd,
1501                            unsigned long arg, struct fb_info *info)
1502 {
1503         struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
1504         unsigned int tmp;
1505         u32 value = 0;
1506         int rc;
1507
1508         switch (cmd) {
1509                 /*
1510                  * TODO:  set mirror accordingly for non-Mobility chipsets with 2 CRTC's
1511                  */
1512                 case FBIO_RADEON_SET_MIRROR:
1513                         switch (rinfo->arch) {
1514                                 case RADEON_R100:
1515                                 case RADEON_RV100:
1516                                 case RADEON_R200:
1517                                 case RADEON_RV200:
1518                                 case RADEON_RV250:
1519                                 case RADEON_R300:
1520                                         return -EINVAL;
1521                                 default:
1522                                         /* RADEON M6, RADEON_M7, RADEON_M9 */
1523                                         break;
1524                         }
1525
1526                         rc = get_user(value, (__u32 __user *)arg);
1527
1528                         if (rc)
1529                                 return rc;
1530
1531                         if (value & 0x01) {
1532                                 tmp = INREG(LVDS_GEN_CNTL);
1533
1534                                 tmp |= (LVDS_ON | LVDS_BLON);
1535                         } else {
1536                                 tmp = INREG(LVDS_GEN_CNTL);
1537
1538                                 tmp &= ~(LVDS_ON | LVDS_BLON);
1539                         }
1540
1541                         OUTREG(LVDS_GEN_CNTL, tmp);
1542
1543                         if (value & 0x02) {
1544                                 tmp = INREG(CRTC_EXT_CNTL);
1545                                 tmp |= CRTC_CRT_ON;
1546
1547                                 mirror = 1;
1548                         } else {
1549                                 tmp = INREG(CRTC_EXT_CNTL);
1550                                 tmp &= ~CRTC_CRT_ON;
1551
1552                                 mirror = 0;
1553                         }
1554
1555                         OUTREG(CRTC_EXT_CNTL, tmp);
1556
1557                         break;
1558                 case FBIO_RADEON_GET_MIRROR:
1559                         switch (rinfo->arch) {
1560                                 case RADEON_R100:
1561                                 case RADEON_RV100:
1562                                 case RADEON_R200:
1563                                 case RADEON_RV200:
1564                                 case RADEON_RV250:
1565                                 case RADEON_R300:
1566                                         return -EINVAL;
1567                                 default:
1568                                         /* RADEON M6, RADEON_M7, RADEON_M9 */
1569                                         break;
1570                         }
1571
1572                         tmp = INREG(LVDS_GEN_CNTL);
1573                         if ((LVDS_ON | LVDS_BLON) & tmp)
1574                                 value |= 0x01;
1575
1576                         tmp = INREG(CRTC_EXT_CNTL);
1577                         if (CRTC_CRT_ON & tmp)
1578                                 value |= 0x02;
1579
1580                         return put_user(value, (__u32 __user *)arg);
1581                 default:
1582                         return -EINVAL;
1583         }
1584
1585         return -EINVAL;
1586 }
1587
1588
1589 static int radeonfb_blank (int blank, struct fb_info *info)
1590 {
1591         struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
1592         u32 val = INREG(CRTC_EXT_CNTL);
1593         u32 val2 = INREG(LVDS_GEN_CNTL);
1594
1595         if (rinfo->asleep)
1596                 return 0;
1597
1598 #ifdef CONFIG_PMAC_BACKLIGHT
1599         if (rinfo->dviDisp_type == MT_LCD && _machine == _MACH_Pmac) {
1600                 set_backlight_enable(!blank);
1601                 return 0;
1602         }
1603 #endif
1604
1605         /* reset it */
1606         val &= ~(CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS |
1607                  CRTC_VSYNC_DIS);
1608         val2 &= ~(LVDS_DISPLAY_DIS);
1609
1610         switch (blank) {
1611                 case FB_BLANK_UNBLANK:
1612                 case FB_BLANK_NORMAL:
1613                         break;
1614                 case FB_BLANK_VSYNC_SUSPEND:
1615                         val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS);
1616                         break;
1617                 case FB_BLANK_HSYNC_SUSPEND:
1618                         val |= (CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS);
1619                         break;
1620                 case FB_BLANK_POWERDOWN:
1621                         val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS |
1622                                 CRTC_HSYNC_DIS);
1623                         val2 |= (LVDS_DISPLAY_DIS);
1624                         break;
1625         }
1626
1627         switch (rinfo->dviDisp_type) {
1628                 case MT_LCD:
1629                         OUTREG(LVDS_GEN_CNTL, val2);
1630                         break;
1631                 case MT_CRT:
1632                 default:
1633                         OUTREG(CRTC_EXT_CNTL, val);
1634                         break;
1635         }
1636
1637         /* let fbcon do a soft blank for us */
1638         return (blank == FB_BLANK_NORMAL) ? 1 : 0;
1639 }
1640
1641
1642 static int radeonfb_setcolreg (unsigned regno, unsigned red, unsigned green,
1643                              unsigned blue, unsigned transp, struct fb_info *info)
1644 {
1645         struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
1646         u32 pindex, vclk_cntl;
1647         unsigned int i;
1648
1649         if (regno > 255)
1650                 return 1;
1651
1652         red >>= 8;
1653         green >>= 8;
1654         blue >>= 8;
1655         rinfo->palette[regno].red = red;
1656         rinfo->palette[regno].green = green;
1657         rinfo->palette[regno].blue = blue;
1658
1659         /* default */
1660         pindex = regno;
1661
1662         if (!rinfo->asleep) {
1663                 vclk_cntl = INPLL(VCLK_ECP_CNTL);
1664                 OUTPLL(VCLK_ECP_CNTL, vclk_cntl & ~PIXCLK_DAC_ALWAYS_ONb);
1665
1666                 if (rinfo->bpp == 16) {
1667                         pindex = regno * 8;
1668
1669                         if (rinfo->depth == 16 && regno > 63)
1670                                 return 1;
1671                         if (rinfo->depth == 15 && regno > 31)
1672                                 return 1;
1673
1674                         /* For 565, the green component is mixed one order below */
1675                         if (rinfo->depth == 16) {
1676                                 OUTREG(PALETTE_INDEX, pindex>>1);
1677                                 OUTREG(PALETTE_DATA, (rinfo->palette[regno>>1].red << 16) |
1678                                         (green << 8) | (rinfo->palette[regno>>1].blue));
1679                                 green = rinfo->palette[regno<<1].green;
1680                         }
1681                 }
1682
1683                 if (rinfo->depth != 16 || regno < 32) {
1684                         OUTREG(PALETTE_INDEX, pindex);
1685                         OUTREG(PALETTE_DATA, (red << 16) | (green << 8) | blue);
1686                 }
1687
1688                 OUTPLL(VCLK_ECP_CNTL, vclk_cntl);
1689         }
1690         if (regno < 16) {
1691                 switch (rinfo->depth) {
1692                 case 15:
1693                         ((u16 *) (info->pseudo_palette))[regno] =
1694                             (regno << 10) | (regno << 5) | regno;
1695                         break;
1696                 case 16:
1697                         ((u16 *) (info->pseudo_palette))[regno] =
1698                             (regno << 11) | (regno << 6) | regno;
1699                         break;
1700                 case 24:
1701                         ((u32 *) (info->pseudo_palette))[regno] =
1702                             (regno << 16) | (regno << 8) | regno;
1703                         break;
1704                 case 32:
1705                         i = (regno << 8) | regno;
1706                         ((u32 *) (info->pseudo_palette))[regno] =
1707                             (i << 16) | i;
1708                         break;
1709                 }
1710         }
1711         return 0;
1712 }
1713
1714
1715
1716 static void radeon_save_state (struct radeonfb_info *rinfo,
1717                                struct radeon_regs *save)
1718 {
1719         /* CRTC regs */
1720         save->crtc_gen_cntl = INREG(CRTC_GEN_CNTL);
1721         save->crtc_ext_cntl = INREG(CRTC_EXT_CNTL);
1722         save->dac_cntl = INREG(DAC_CNTL);
1723         save->crtc_h_total_disp = INREG(CRTC_H_TOTAL_DISP);
1724         save->crtc_h_sync_strt_wid = INREG(CRTC_H_SYNC_STRT_WID);
1725         save->crtc_v_total_disp = INREG(CRTC_V_TOTAL_DISP);
1726         save->crtc_v_sync_strt_wid = INREG(CRTC_V_SYNC_STRT_WID);
1727         save->crtc_pitch = INREG(CRTC_PITCH);
1728 #if defined(__BIG_ENDIAN)
1729         save->surface_cntl = INREG(SURFACE_CNTL);
1730 #endif
1731
1732         /* FP regs */
1733         save->fp_crtc_h_total_disp = INREG(FP_CRTC_H_TOTAL_DISP);
1734         save->fp_crtc_v_total_disp = INREG(FP_CRTC_V_TOTAL_DISP);
1735         save->fp_gen_cntl = INREG(FP_GEN_CNTL);
1736         save->fp_h_sync_strt_wid = INREG(FP_H_SYNC_STRT_WID);
1737         save->fp_horz_stretch = INREG(FP_HORZ_STRETCH);
1738         save->fp_v_sync_strt_wid = INREG(FP_V_SYNC_STRT_WID);
1739         save->fp_vert_stretch = INREG(FP_VERT_STRETCH);
1740         save->lvds_gen_cntl = INREG(LVDS_GEN_CNTL);
1741         save->lvds_pll_cntl = INREG(LVDS_PLL_CNTL);
1742         save->tmds_crc = INREG(TMDS_CRC);
1743         save->tmds_transmitter_cntl = INREG(TMDS_TRANSMITTER_CNTL);
1744         save->vclk_ecp_cntl = INPLL(VCLK_ECP_CNTL);
1745 }
1746
1747
1748
1749 static int radeonfb_set_par (struct fb_info *info)
1750 {
1751         struct radeonfb_info *rinfo = (struct radeonfb_info *)info->par;
1752         struct fb_var_screeninfo *mode = &info->var;
1753         struct radeon_regs newmode;
1754         int hTotal, vTotal, hSyncStart, hSyncEnd,
1755             hSyncPol, vSyncStart, vSyncEnd, vSyncPol, cSync;
1756         u8 hsync_adj_tab[] = {0, 0x12, 9, 9, 6, 5};
1757         u8 hsync_fudge_fp[] = {2, 2, 0, 0, 5, 5};
1758         u32 dotClock = 1000000000 / mode->pixclock,
1759             sync, h_sync_pol, v_sync_pol;
1760         int freq = dotClock / 10;  /* x 100 */
1761         int xclk_freq, vclk_freq, xclk_per_trans, xclk_per_trans_precise;
1762         int useable_precision, roff, ron;
1763         int min_bits, format = 0;
1764         int hsync_start, hsync_fudge, bytpp, hsync_wid, vsync_wid;
1765         int primary_mon = PRIMARY_MONITOR(rinfo);
1766         int depth = var_to_depth(mode);
1767         int accel = (mode->accel_flags & FB_ACCELF_TEXT) != 0;
1768
1769         rinfo->xres = mode->xres;
1770         rinfo->yres = mode->yres;
1771         rinfo->xres_virtual = mode->xres_virtual;
1772         rinfo->yres_virtual = mode->yres_virtual;
1773         rinfo->pixclock = mode->pixclock;
1774
1775         hSyncStart = mode->xres + mode->right_margin;
1776         hSyncEnd = hSyncStart + mode->hsync_len;
1777         hTotal = hSyncEnd + mode->left_margin;
1778
1779         vSyncStart = mode->yres + mode->lower_margin;
1780         vSyncEnd = vSyncStart + mode->vsync_len;
1781         vTotal = vSyncEnd + mode->upper_margin;
1782
1783         if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1784                 if (rinfo->panel_xres < mode->xres)
1785                         rinfo->xres = mode->xres = rinfo->panel_xres;
1786                 if (rinfo->panel_yres < mode->yres)
1787                         rinfo->yres = mode->yres = rinfo->panel_yres;
1788
1789                 hTotal = mode->xres + rinfo->hblank;
1790                 hSyncStart = mode->xres + rinfo->hOver_plus;
1791                 hSyncEnd = hSyncStart + rinfo->hSync_width;
1792
1793                 vTotal = mode->yres + rinfo->vblank;
1794                 vSyncStart = mode->yres + rinfo->vOver_plus;
1795                 vSyncEnd = vSyncStart + rinfo->vSync_width;
1796         }
1797
1798         sync = mode->sync;
1799         h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
1800         v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
1801
1802         RTRACE("hStart = %d, hEnd = %d, hTotal = %d\n",
1803                 hSyncStart, hSyncEnd, hTotal);
1804         RTRACE("vStart = %d, vEnd = %d, vTotal = %d\n",
1805                 vSyncStart, vSyncEnd, vTotal);
1806
1807         hsync_wid = (hSyncEnd - hSyncStart) / 8;
1808         vsync_wid = vSyncEnd - vSyncStart;
1809         if (hsync_wid == 0)
1810                 hsync_wid = 1;
1811         else if (hsync_wid > 0x3f)      /* max */
1812                 hsync_wid = 0x3f;
1813
1814         if (vsync_wid == 0)
1815                 vsync_wid = 1;
1816         else if (vsync_wid > 0x1f)      /* max */
1817                 vsync_wid = 0x1f;
1818
1819         hSyncPol = mode->sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
1820         vSyncPol = mode->sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
1821
1822         cSync = mode->sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0;
1823
1824         format = radeon_get_dstbpp(depth);
1825         bytpp = mode->bits_per_pixel >> 3;
1826
1827         if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD))
1828                 hsync_fudge = hsync_fudge_fp[format-1];
1829         else
1830                 hsync_fudge = hsync_adj_tab[format-1];
1831
1832         hsync_start = hSyncStart - 8 + hsync_fudge;
1833
1834         newmode.crtc_gen_cntl = CRTC_EXT_DISP_EN | CRTC_EN |
1835                                 (format << 8);
1836
1837         if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1838                 newmode.crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN;
1839                 if (mirror)
1840                         newmode.crtc_ext_cntl |= CRTC_CRT_ON;
1841
1842                 newmode.crtc_gen_cntl &= ~(CRTC_DBL_SCAN_EN |
1843                                            CRTC_INTERLACE_EN);
1844         } else {
1845                 newmode.crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN |
1846                                         CRTC_CRT_ON;
1847         }
1848
1849         newmode.dac_cntl = /* INREG(DAC_CNTL) | */ DAC_MASK_ALL | DAC_VGA_ADR_EN |
1850                            DAC_8BIT_EN;
1851
1852         newmode.crtc_h_total_disp = ((((hTotal / 8) - 1) & 0x3ff) |
1853                                      (((mode->xres / 8) - 1) << 16));
1854
1855         newmode.crtc_h_sync_strt_wid = ((hsync_start & 0x1fff) |
1856                                         (hsync_wid << 16) | (h_sync_pol << 23));
1857
1858         newmode.crtc_v_total_disp = ((vTotal - 1) & 0xffff) |
1859                                     ((mode->yres - 1) << 16);
1860
1861         newmode.crtc_v_sync_strt_wid = (((vSyncStart - 1) & 0xfff) |
1862                                          (vsync_wid << 16) | (v_sync_pol  << 23));
1863
1864         if (accel) {
1865                 /* We first calculate the engine pitch */
1866                 rinfo->pitch = ((mode->xres_virtual * ((mode->bits_per_pixel + 1) / 8) + 0x3f)
1867                                 & ~(0x3f)) >> 6;
1868
1869                 /* Then, re-multiply it to get the CRTC pitch */
1870                 newmode.crtc_pitch = (rinfo->pitch << 3) / ((mode->bits_per_pixel + 1) / 8);
1871         } else
1872                 newmode.crtc_pitch = (mode->xres_virtual >> 3);
1873         newmode.crtc_pitch |= (newmode.crtc_pitch << 16);
1874
1875 #if defined(__BIG_ENDIAN)
1876         /*
1877          * It looks like recent chips have a problem with SURFACE_CNTL,
1878          * setting SURF_TRANSLATION_DIS completely disables the
1879          * swapper as well, so we leave it unset now.
1880          */
1881         newmode.surface_cntl = 0;
1882
1883         /* Setup swapping on both apertures, though we currently
1884          * only use aperture 0, enabling swapper on aperture 1
1885          * won't harm
1886          */
1887         switch (mode->bits_per_pixel) {
1888                 case 16:
1889                         newmode.surface_cntl |= NONSURF_AP0_SWP_16BPP;
1890                         newmode.surface_cntl |= NONSURF_AP1_SWP_16BPP;
1891                         break;
1892                 case 24:
1893                 case 32:
1894                         newmode.surface_cntl |= NONSURF_AP0_SWP_32BPP;
1895                         newmode.surface_cntl |= NONSURF_AP1_SWP_32BPP;
1896                         break;
1897         }
1898 #endif
1899
1900         rinfo->pitch = ((mode->xres_virtual * ((mode->bits_per_pixel + 1) / 8) + 0x3f)
1901                         & ~(0x3f)) / 64;
1902
1903         RTRACE("h_total_disp = 0x%x\t   hsync_strt_wid = 0x%x\n",
1904                 newmode.crtc_h_total_disp, newmode.crtc_h_sync_strt_wid);
1905         RTRACE("v_total_disp = 0x%x\t   vsync_strt_wid = 0x%x\n",
1906                 newmode.crtc_v_total_disp, newmode.crtc_v_sync_strt_wid);
1907
1908         newmode.xres = mode->xres;
1909         newmode.yres = mode->yres;
1910
1911         rinfo->bpp = mode->bits_per_pixel;
1912         rinfo->depth = depth;
1913
1914         if (freq > rinfo->pll.ppll_max)
1915                 freq = rinfo->pll.ppll_max;
1916         if (freq*12 < rinfo->pll.ppll_min)
1917                 freq = rinfo->pll.ppll_min / 12;
1918
1919         {
1920                 struct {
1921                         int divider;
1922                         int bitvalue;
1923                 } *post_div,
1924                   post_divs[] = {
1925                         { 1,  0 },
1926                         { 2,  1 },
1927                         { 4,  2 },
1928                         { 8,  3 },
1929                         { 3,  4 },
1930                         { 16, 5 },
1931                         { 6,  6 },
1932                         { 12, 7 },
1933                         { 0,  0 },
1934                 };
1935
1936                 for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
1937                         rinfo->pll_output_freq = post_div->divider * freq;
1938                         if (rinfo->pll_output_freq >= rinfo->pll.ppll_min  &&
1939                             rinfo->pll_output_freq <= rinfo->pll.ppll_max)
1940                                 break;
1941                 }
1942
1943                 rinfo->post_div = post_div->divider;
1944                 rinfo->fb_div = round_div(rinfo->pll.ref_div*rinfo->pll_output_freq,
1945                                           rinfo->pll.ref_clk);
1946                 newmode.ppll_ref_div = rinfo->pll.ref_div;
1947                 newmode.ppll_div_3 = rinfo->fb_div | (post_div->bitvalue << 16);
1948         }
1949         newmode.vclk_ecp_cntl = rinfo->init_state.vclk_ecp_cntl;
1950
1951 #ifdef CONFIG_PPC_OF
1952         /* Gross hack for iBook with M7 until I find out a proper fix */
1953         if (machine_is_compatible("PowerBook4,3") && rinfo->arch == RADEON_M7)
1954                 newmode.ppll_div_3 = 0x000600ad;
1955 #endif /* CONFIG_PPC_OF */
1956
1957         RTRACE("post div = 0x%x\n", rinfo->post_div);
1958         RTRACE("fb_div = 0x%x\n", rinfo->fb_div);
1959         RTRACE("ppll_div_3 = 0x%x\n", newmode.ppll_div_3);
1960
1961         /* DDA */
1962         vclk_freq = round_div(rinfo->pll.ref_clk * rinfo->fb_div,
1963                               rinfo->pll.ref_div * rinfo->post_div);
1964         xclk_freq = rinfo->pll.xclk;
1965
1966         xclk_per_trans = round_div(xclk_freq * 128, vclk_freq * mode->bits_per_pixel);
1967
1968         min_bits = min_bits_req(xclk_per_trans);
1969         useable_precision = min_bits + 1;
1970
1971         xclk_per_trans_precise = round_div((xclk_freq * 128) << (11 - useable_precision),
1972                                            vclk_freq * mode->bits_per_pixel);
1973
1974         ron = (4 * rinfo->ram.mb + 3 * _max(rinfo->ram.trcd - 2, 0) +
1975                2 * rinfo->ram.trp + rinfo->ram.twr + rinfo->ram.cl + rinfo->ram.tr2w +
1976                xclk_per_trans) << (11 - useable_precision);
1977         roff = xclk_per_trans_precise * (32 - 4);
1978
1979         RTRACE("ron = %d, roff = %d\n", ron, roff);
1980         RTRACE("vclk_freq = %d, per = %d\n", vclk_freq, xclk_per_trans_precise);
1981
1982         if ((ron + rinfo->ram.rloop) >= roff) {
1983                 printk("radeonfb: error ron out of range\n");
1984                 return -EINVAL;
1985         }
1986
1987         newmode.dda_config = (xclk_per_trans_precise |
1988                               (useable_precision << 16) |
1989                               (rinfo->ram.rloop << 20));
1990         newmode.dda_on_off = (ron << 16) | roff;
1991
1992         if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1993                 unsigned int hRatio, vRatio;
1994
1995                 /* We force the pixel clock to be always enabled. Allowing it
1996                  * to be power managed during blanking would save power, but has
1997                  * nasty interactions with the 2D engine & sleep code that haven't
1998                  * been solved yet. --BenH
1999                  */
2000                 newmode.vclk_ecp_cntl &= ~PIXCLK_DAC_ALWAYS_ONb;
2001
2002                 if (mode->xres > rinfo->panel_xres)
2003                         mode->xres = rinfo->panel_xres;
2004                 if (mode->yres > rinfo->panel_yres)
2005                         mode->yres = rinfo->panel_yres;
2006
2007                 newmode.fp_horz_stretch = (((rinfo->panel_xres / 8) - 1)
2008                                            << HORZ_PANEL_SHIFT);
2009                 newmode.fp_vert_stretch = ((rinfo->panel_yres - 1)
2010                                            << VERT_PANEL_SHIFT);
2011
2012                 if (mode->xres != rinfo->panel_xres) {
2013                         hRatio = round_div(mode->xres * HORZ_STRETCH_RATIO_MAX,
2014                                            rinfo->panel_xres);
2015                         newmode.fp_horz_stretch = (((((unsigned long)hRatio) & HORZ_STRETCH_RATIO_MASK)) |
2016                                                    (newmode.fp_horz_stretch &
2017                                                     (HORZ_PANEL_SIZE | HORZ_FP_LOOP_STRETCH |
2018                                                      HORZ_AUTO_RATIO_INC)));
2019                         newmode.fp_horz_stretch |= (HORZ_STRETCH_BLEND |
2020                                                     HORZ_STRETCH_ENABLE);
2021                 }
2022                 newmode.fp_horz_stretch &= ~HORZ_AUTO_RATIO;
2023
2024                 if (mode->yres != rinfo->panel_yres) {
2025                         vRatio = round_div(mode->yres * VERT_STRETCH_RATIO_MAX,
2026                                            rinfo->panel_yres);
2027                         newmode.fp_vert_stretch = (((((unsigned long)vRatio) & VERT_STRETCH_RATIO_MASK)) |
2028                                                    (newmode.fp_vert_stretch &
2029                                                    (VERT_PANEL_SIZE | VERT_STRETCH_RESERVED)));
2030                         newmode.fp_vert_stretch |= (VERT_STRETCH_BLEND |
2031                                                     VERT_STRETCH_ENABLE);
2032                 }
2033                 newmode.fp_vert_stretch &= ~VERT_AUTO_RATIO_EN;
2034
2035                 newmode.fp_gen_cntl = (rinfo->init_state.fp_gen_cntl & (u32)
2036                                        ~(FP_SEL_CRTC2 |
2037                                          FP_RMX_HVSYNC_CONTROL_EN |
2038                                          FP_DFP_SYNC_SEL |
2039                                          FP_CRT_SYNC_SEL |
2040                                          FP_CRTC_LOCK_8DOT |
2041                                          FP_USE_SHADOW_EN |
2042                                          FP_CRTC_USE_SHADOW_VEND |
2043                                          FP_CRT_SYNC_ALT));
2044
2045                 newmode.fp_gen_cntl |= (FP_CRTC_DONT_SHADOW_VPAR |
2046                                         FP_CRTC_DONT_SHADOW_HEND);
2047
2048                 newmode.lvds_gen_cntl = rinfo->init_state.lvds_gen_cntl;
2049                 newmode.lvds_pll_cntl = rinfo->init_state.lvds_pll_cntl;
2050                 newmode.tmds_crc = rinfo->init_state.tmds_crc;
2051                 newmode.tmds_transmitter_cntl = rinfo->init_state.tmds_transmitter_cntl;
2052
2053                 if (primary_mon == MT_LCD) {
2054                         newmode.lvds_gen_cntl |= (LVDS_ON | LVDS_BLON);
2055                         newmode.fp_gen_cntl &= ~(FP_FPON | FP_TMDS_EN);
2056                 } else {
2057                         /* DFP */
2058                         newmode.fp_gen_cntl |= (FP_FPON | FP_TMDS_EN);
2059                         newmode.tmds_transmitter_cntl = (TMDS_RAN_PAT_RST |
2060                                                          TMDS_ICHCSEL | TMDS_PLL_EN) &
2061                                                          ~(TMDS_PLLRST);
2062                         newmode.crtc_ext_cntl &= ~CRTC_CRT_ON;
2063                 }
2064
2065                 newmode.fp_crtc_h_total_disp = (((rinfo->hblank / 8) & 0x3ff) |
2066                                 (((mode->xres / 8) - 1) << 16));
2067                 newmode.fp_crtc_v_total_disp = (rinfo->vblank & 0xffff) |
2068                                 ((mode->yres - 1) << 16);
2069                 newmode.fp_h_sync_strt_wid = ((rinfo->hOver_plus & 0x1fff) |
2070                                 (hsync_wid << 16) | (h_sync_pol << 23));
2071                 newmode.fp_v_sync_strt_wid = ((rinfo->vOver_plus & 0xfff) |
2072                                 (vsync_wid << 16) | (v_sync_pol  << 23));
2073         }
2074
2075         /* do it! */
2076         if (!rinfo->asleep) {
2077                 radeon_write_mode (rinfo, &newmode);
2078                 /* (re)initialize the engine */
2079                 if (noaccel)
2080                         radeon_engine_init (rinfo);
2081
2082         }
2083         /* Update fix */
2084         if (accel)
2085                 info->fix.line_length = rinfo->pitch*64;
2086         else
2087                 info->fix.line_length = mode->xres_virtual * ((mode->bits_per_pixel + 1) / 8);
2088         info->fix.visual = rinfo->depth == 8 ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
2089
2090 #ifdef CONFIG_BOOTX_TEXT
2091         /* Update debug text engine */
2092         btext_update_display(rinfo->fb_base_phys, mode->xres, mode->yres,
2093                              rinfo->depth, info->fix.line_length);
2094 #endif
2095
2096         return 0;
2097 }
2098
2099
2100 static void radeon_write_mode (struct radeonfb_info *rinfo,
2101                                struct radeon_regs *mode)
2102 {
2103         int i;
2104         int primary_mon = PRIMARY_MONITOR(rinfo);
2105
2106         radeonfb_blank(VESA_POWERDOWN, (struct fb_info *)rinfo);
2107
2108
2109         if (rinfo->arch == RADEON_M6) {
2110                 for (i=0; i<7; i++)
2111                         OUTREG(common_regs_m6[i].reg, common_regs_m6[i].val);
2112         } else {
2113                 for (i=0; i<9; i++)
2114                         OUTREG(common_regs[i].reg, common_regs[i].val);
2115         }
2116
2117         OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl);
2118         OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl,
2119                 CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS);
2120         OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING);
2121         OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp);
2122         OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid);
2123         OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp);
2124         OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid);
2125         OUTREG(CRTC_OFFSET, 0);
2126         OUTREG(CRTC_OFFSET_CNTL, 0);
2127         OUTREG(CRTC_PITCH, mode->crtc_pitch);
2128
2129 #if defined(__BIG_ENDIAN)
2130         OUTREG(SURFACE_CNTL, mode->surface_cntl);
2131 #endif
2132
2133         while ((INREG(CLOCK_CNTL_INDEX) & PPLL_DIV_SEL_MASK) !=
2134                PPLL_DIV_SEL_MASK) {
2135                 OUTREGP(CLOCK_CNTL_INDEX, PPLL_DIV_SEL_MASK, 0xffff);
2136         }
2137
2138         OUTPLLP(PPLL_CNTL, PPLL_RESET, 0xffff);
2139
2140         while ((INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK) !=
2141                (mode->ppll_ref_div & PPLL_REF_DIV_MASK)) {
2142                 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, ~PPLL_REF_DIV_MASK);
2143         }
2144
2145         while ((INPLL(PPLL_DIV_3) & PPLL_FB3_DIV_MASK) !=
2146                (mode->ppll_div_3 & PPLL_FB3_DIV_MASK)) {
2147                 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_FB3_DIV_MASK);
2148         }
2149
2150         while ((INPLL(PPLL_DIV_3) & PPLL_POST3_DIV_MASK) !=
2151                (mode->ppll_div_3 & PPLL_POST3_DIV_MASK)) {
2152                 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_POST3_DIV_MASK);
2153         }
2154
2155         OUTPLL(HTOTAL_CNTL, 0);
2156
2157         OUTPLLP(PPLL_CNTL, 0, ~PPLL_RESET);
2158
2159 //      OUTREG(DDA_CONFIG, mode->dda_config);
2160 //      OUTREG(DDA_ON_OFF, mode->dda_on_off);
2161
2162         if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
2163                 OUTREG(FP_CRTC_H_TOTAL_DISP, mode->fp_crtc_h_total_disp);
2164                 OUTREG(FP_CRTC_V_TOTAL_DISP, mode->fp_crtc_v_total_disp);
2165                 OUTREG(FP_H_SYNC_STRT_WID, mode->fp_h_sync_strt_wid);
2166                 OUTREG(FP_V_SYNC_STRT_WID, mode->fp_v_sync_strt_wid);
2167                 OUTREG(FP_HORZ_STRETCH, mode->fp_horz_stretch);
2168                 OUTREG(FP_VERT_STRETCH, mode->fp_vert_stretch);
2169                 OUTREG(FP_GEN_CNTL, mode->fp_gen_cntl);
2170                 OUTREG(TMDS_CRC, mode->tmds_crc);
2171                 OUTREG(TMDS_TRANSMITTER_CNTL, mode->tmds_transmitter_cntl);
2172
2173                 if (primary_mon == MT_LCD) {
2174                         unsigned int tmp = INREG(LVDS_GEN_CNTL);
2175
2176                         mode->lvds_gen_cntl &= ~LVDS_STATE_MASK;
2177                         mode->lvds_gen_cntl |= (rinfo->init_state.lvds_gen_cntl & LVDS_STATE_MASK);
2178
2179                         if ((tmp & (LVDS_ON | LVDS_BLON)) ==
2180                             (mode->lvds_gen_cntl & (LVDS_ON | LVDS_BLON))) {
2181                                 OUTREG(LVDS_GEN_CNTL, mode->lvds_gen_cntl);
2182                         } else {
2183                                 if (mode->lvds_gen_cntl & (LVDS_ON | LVDS_BLON)) {
2184                                         udelay(1000);
2185                                         OUTREG(LVDS_GEN_CNTL, mode->lvds_gen_cntl);
2186                                 } else {
2187                                         OUTREG(LVDS_GEN_CNTL, mode->lvds_gen_cntl |
2188                                                LVDS_BLON);
2189                                         udelay(1000);
2190                                         OUTREG(LVDS_GEN_CNTL, mode->lvds_gen_cntl);
2191                                 }
2192                         }
2193                 }
2194         }
2195
2196         radeonfb_blank(VESA_NO_BLANKING, (struct fb_info *)rinfo);
2197
2198         OUTPLL(VCLK_ECP_CNTL, mode->vclk_ecp_cntl);
2199
2200         return;
2201 }
2202
2203 static struct fb_ops radeonfb_ops = {
2204         .owner                  = THIS_MODULE,
2205         .fb_check_var           = radeonfb_check_var,
2206         .fb_set_par             = radeonfb_set_par,
2207         .fb_setcolreg           = radeonfb_setcolreg,
2208         .fb_pan_display         = radeonfb_pan_display,
2209         .fb_blank               = radeonfb_blank,
2210         .fb_ioctl               = radeonfb_ioctl,
2211 #if 0
2212         .fb_fillrect    = radeonfb_fillrect,
2213         .fb_copyarea    = radeonfb_copyarea,
2214         .fb_imageblit   = radeonfb_imageblit,
2215         .fb_rasterimg   = radeonfb_rasterimg,
2216 #else
2217         .fb_fillrect    = cfb_fillrect,
2218         .fb_copyarea    = cfb_copyarea,
2219         .fb_imageblit   = cfb_imageblit,
2220 #endif
2221 };
2222
2223
2224 static int __devinit radeon_set_fbinfo (struct radeonfb_info *rinfo)
2225 {
2226         struct fb_info *info;
2227
2228         info = &rinfo->info;
2229
2230         info->par = rinfo;
2231         info->pseudo_palette = rinfo->pseudo_palette;
2232         info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
2233         info->fbops = &radeonfb_ops;
2234         info->screen_base = rinfo->fb_base;
2235
2236         /* Fill fix common fields */
2237         strlcpy(info->fix.id, rinfo->name, sizeof(info->fix.id));
2238         info->fix.smem_start = rinfo->fb_base_phys;
2239         info->fix.smem_len = rinfo->video_ram;
2240         info->fix.type = FB_TYPE_PACKED_PIXELS;
2241         info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
2242         info->fix.xpanstep = 8;
2243         info->fix.ypanstep = 1;
2244         info->fix.ywrapstep = 0;
2245         info->fix.type_aux = 0;
2246         info->fix.mmio_start = rinfo->mmio_base_phys;
2247         info->fix.mmio_len = RADEON_REGSIZE;
2248         if (noaccel)
2249                 info->fix.accel = FB_ACCEL_NONE;
2250         else
2251                 info->fix.accel = FB_ACCEL_ATI_RADEON;
2252
2253         if (radeon_init_disp (rinfo) < 0)
2254                 return -1;
2255
2256         return 0;
2257 }
2258
2259
2260 #ifdef CONFIG_PMAC_BACKLIGHT
2261
2262 /* TODO: Dbl check these tables, we don't go up to full ON backlight
2263  * in these, possibly because we noticed MacOS doesn't, but I'd prefer
2264  * having some more official numbers from ATI
2265  */
2266 static int backlight_conv_m6[] = {
2267         0xff, 0xc0, 0xb5, 0xaa, 0x9f, 0x94, 0x89, 0x7e,
2268         0x73, 0x68, 0x5d, 0x52, 0x47, 0x3c, 0x31, 0x24
2269 };
2270 static int backlight_conv_m7[] = {
2271         0x00, 0x3f, 0x4a, 0x55, 0x60, 0x6b, 0x76, 0x81,
2272         0x8c, 0x97, 0xa2, 0xad, 0xb8, 0xc3, 0xce, 0xd9
2273 };
2274
2275 #define BACKLIGHT_LVDS_OFF
2276 #undef BACKLIGHT_DAC_OFF
2277
2278 /* We turn off the LCD completely instead of just dimming the backlight.
2279  * This provides some greater power saving and the display is useless
2280  * without backlight anyway.
2281  */
2282
2283 static int radeon_set_backlight_enable(int on, int level, void *data)
2284 {
2285         struct radeonfb_info *rinfo = (struct radeonfb_info *)data;
2286         unsigned int lvds_gen_cntl = INREG(LVDS_GEN_CNTL);
2287         int* conv_table;
2288
2289         /* Pardon me for that hack... maybe some day we can figure
2290          * out in what direction backlight should work on a given
2291          * panel ?
2292          */
2293         if ((rinfo->arch == RADEON_M7 || rinfo->arch == RADEON_M9)
2294                 && !machine_is_compatible("PowerBook4,3"))
2295                 conv_table = backlight_conv_m7;
2296         else
2297                 conv_table = backlight_conv_m6;
2298
2299         lvds_gen_cntl |= (LVDS_BL_MOD_EN | LVDS_BLON);
2300         if (on && (level > BACKLIGHT_OFF)) {
2301                 lvds_gen_cntl |= LVDS_DIGON;
2302                 if (!(lvds_gen_cntl & LVDS_ON)) {
2303                         lvds_gen_cntl &= ~LVDS_BLON;
2304                         OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);
2305                         (void)INREG(LVDS_GEN_CNTL);
2306                         mdelay(10);
2307                         lvds_gen_cntl |= LVDS_BLON;
2308                         OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);
2309                 }
2310                 lvds_gen_cntl &= ~LVDS_BL_MOD_LEVEL_MASK;
2311                 lvds_gen_cntl |= (conv_table[level] <<
2312                                   LVDS_BL_MOD_LEVEL_SHIFT);
2313                 lvds_gen_cntl |= (LVDS_ON | LVDS_EN);
2314                 lvds_gen_cntl &= ~LVDS_DISPLAY_DIS;
2315         } else {
2316                 lvds_gen_cntl &= ~LVDS_BL_MOD_LEVEL_MASK;
2317                 lvds_gen_cntl |= (conv_table[0] <<
2318                                   LVDS_BL_MOD_LEVEL_SHIFT);
2319                 lvds_gen_cntl |= LVDS_DISPLAY_DIS;
2320                 OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);
2321                 udelay(10);
2322                 lvds_gen_cntl &= ~(LVDS_ON | LVDS_EN | LVDS_BLON | LVDS_DIGON);
2323         }
2324
2325         OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);
2326         rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;
2327         rinfo->init_state.lvds_gen_cntl |= (lvds_gen_cntl & LVDS_STATE_MASK);
2328
2329         return 0;
2330 }
2331
2332 static int radeon_set_backlight_level(int level, void *data)
2333 {
2334         return radeon_set_backlight_enable(1, level, data);
2335 }
2336 #endif /* CONFIG_PMAC_BACKLIGHT */
2337
2338
2339 #ifdef CONFIG_PMAC_PBOOK
2340
2341 static u32 dbg_clk;
2342
2343 /*
2344  * Radeon M6 Power Management code. This code currently only supports
2345  * the mobile chips, it's based from some informations provided by ATI
2346  * along with hours of tracing of MacOS drivers
2347  */
2348
2349 static void radeon_pm_save_regs(struct radeonfb_info *rinfo)
2350 {
2351         rinfo->save_regs[0] = INPLL(PLL_PWRMGT_CNTL);
2352         rinfo->save_regs[1] = INPLL(CLK_PWRMGT_CNTL);
2353         rinfo->save_regs[2] = INPLL(MCLK_CNTL);
2354         rinfo->save_regs[3] = INPLL(SCLK_CNTL);
2355         rinfo->save_regs[4] = INPLL(CLK_PIN_CNTL);
2356         rinfo->save_regs[5] = INPLL(VCLK_ECP_CNTL);
2357         rinfo->save_regs[6] = INPLL(PIXCLKS_CNTL);
2358         rinfo->save_regs[7] = INPLL(MCLK_MISC);
2359         rinfo->save_regs[8] = INPLL(P2PLL_CNTL);
2360
2361         rinfo->save_regs[9] = INREG(DISP_MISC_CNTL);
2362         rinfo->save_regs[10] = INREG(DISP_PWR_MAN);
2363         rinfo->save_regs[11] = INREG(LVDS_GEN_CNTL);
2364         rinfo->save_regs[12] = INREG(LVDS_PLL_CNTL);
2365         rinfo->save_regs[13] = INREG(TV_DAC_CNTL);
2366         rinfo->save_regs[14] = INREG(BUS_CNTL1);
2367         rinfo->save_regs[15] = INREG(CRTC_OFFSET_CNTL);
2368         rinfo->save_regs[16] = INREG(AGP_CNTL);
2369         rinfo->save_regs[17] = (INREG(CRTC_GEN_CNTL) & 0xfdffffff) | 0x04000000;
2370         rinfo->save_regs[18] = (INREG(CRTC2_GEN_CNTL) & 0xfdffffff) | 0x04000000;
2371         rinfo->save_regs[19] = INREG(GPIOPAD_A);
2372         rinfo->save_regs[20] = INREG(GPIOPAD_EN);
2373         rinfo->save_regs[21] = INREG(GPIOPAD_MASK);
2374         rinfo->save_regs[22] = INREG(ZV_LCDPAD_A);
2375         rinfo->save_regs[23] = INREG(ZV_LCDPAD_EN);
2376         rinfo->save_regs[24] = INREG(ZV_LCDPAD_MASK);
2377         rinfo->save_regs[25] = INREG(GPIO_VGA_DDC);
2378         rinfo->save_regs[26] = INREG(GPIO_DVI_DDC);
2379         rinfo->save_regs[27] = INREG(GPIO_MONID);
2380         rinfo->save_regs[28] = INREG(GPIO_CRT2_DDC);
2381
2382         rinfo->save_regs[29] = INREG(SURFACE_CNTL);
2383         rinfo->save_regs[30] = INREG(MC_FB_LOCATION);
2384         rinfo->save_regs[31] = INREG(DISPLAY_BASE_ADDR);
2385         rinfo->save_regs[32] = INREG(MC_AGP_LOCATION);
2386         rinfo->save_regs[33] = INREG(CRTC2_DISPLAY_BASE_ADDR);
2387 }
2388
2389 static void radeon_pm_restore_regs(struct radeonfb_info *rinfo)
2390 {
2391         OUTPLL(P2PLL_CNTL, rinfo->save_regs[8] & 0xFFFFFFFE); /* First */
2392
2393         OUTPLL(PLL_PWRMGT_CNTL, rinfo->save_regs[0]);
2394         OUTPLL(CLK_PWRMGT_CNTL, rinfo->save_regs[1]);
2395         OUTPLL(MCLK_CNTL, rinfo->save_regs[2]);
2396         OUTPLL(SCLK_CNTL, rinfo->save_regs[3]);
2397         OUTPLL(CLK_PIN_CNTL, rinfo->save_regs[4]);
2398         OUTPLL(VCLK_ECP_CNTL, rinfo->save_regs[5]);
2399         OUTPLL(PIXCLKS_CNTL, rinfo->save_regs[6]);
2400         OUTPLL(MCLK_MISC, rinfo->save_regs[7]);
2401
2402         OUTREG(DISP_MISC_CNTL, rinfo->save_regs[9]);
2403         OUTREG(DISP_PWR_MAN, rinfo->save_regs[10]);
2404         OUTREG(LVDS_GEN_CNTL, rinfo->save_regs[11]);
2405         OUTREG(LVDS_PLL_CNTL,rinfo->save_regs[12]);
2406         OUTREG(TV_DAC_CNTL, rinfo->save_regs[13]);
2407         OUTREG(BUS_CNTL1, rinfo->save_regs[14]);
2408         OUTREG(CRTC_OFFSET_CNTL, rinfo->save_regs[15]);
2409         OUTREG(AGP_CNTL, rinfo->save_regs[16]);
2410         OUTREG(CRTC_GEN_CNTL, rinfo->save_regs[17]);
2411         OUTREG(CRTC2_GEN_CNTL, rinfo->save_regs[18]);
2412
2413         // wait VBL before that one  ?
2414         OUTPLL(P2PLL_CNTL, rinfo->save_regs[8]);
2415
2416         OUTREG(GPIOPAD_A, rinfo->save_regs[19]);
2417         OUTREG(GPIOPAD_EN, rinfo->save_regs[20]);
2418         OUTREG(GPIOPAD_MASK, rinfo->save_regs[21]);
2419         OUTREG(ZV_LCDPAD_A, rinfo->save_regs[22]);
2420         OUTREG(ZV_LCDPAD_EN, rinfo->save_regs[23]);
2421         OUTREG(ZV_LCDPAD_MASK, rinfo->save_regs[24]);
2422         OUTREG(GPIO_VGA_DDC, rinfo->save_regs[25]);
2423         OUTREG(GPIO_DVI_DDC, rinfo->save_regs[26]);
2424         OUTREG(GPIO_MONID, rinfo->save_regs[27]);
2425         OUTREG(GPIO_CRT2_DDC, rinfo->save_regs[28]);
2426 }
2427
2428 static void radeon_pm_disable_iopad(struct radeonfb_info *rinfo)
2429 {
2430         OUTREG(GPIOPAD_MASK, 0x0001ffff);
2431         OUTREG(GPIOPAD_EN, 0x00000400);
2432         OUTREG(GPIOPAD_A, 0x00000000);
2433         OUTREG(ZV_LCDPAD_MASK, 0x00000000);
2434         OUTREG(ZV_LCDPAD_EN, 0x00000000);
2435         OUTREG(ZV_LCDPAD_A, 0x00000000);
2436         OUTREG(GPIO_VGA_DDC, 0x00030000);
2437         OUTREG(GPIO_DVI_DDC, 0x00000000);
2438         OUTREG(GPIO_MONID, 0x00030000);
2439         OUTREG(GPIO_CRT2_DDC, 0x00000000);
2440 }
2441
2442 static void radeon_pm_program_v2clk(struct radeonfb_info *rinfo)
2443 {
2444 //
2445 //      u32 reg;
2446 //
2447 //      OUTPLL(P2PLL_REF_DIV, 0x0c);
2448 //
2449 //      .../... figure out what macos does here
2450 }
2451
2452 static void radeon_pm_low_current(struct radeonfb_info *rinfo)
2453 {
2454         u32 reg;
2455
2456         reg  = INREG(BUS_CNTL1);
2457         reg &= ~BUS_CNTL1_MOBILE_PLATFORM_SEL_MASK;
2458         reg |= BUS_CNTL1_AGPCLK_VALID | (1<<BUS_CNTL1_MOBILE_PLATFORM_SEL_SHIFT);
2459         OUTREG(BUS_CNTL1, reg);
2460
2461         reg  = INPLL(PLL_PWRMGT_CNTL);
2462         reg |= PLL_PWRMGT_CNTL_SPLL_TURNOFF | PLL_PWRMGT_CNTL_PPLL_TURNOFF |
2463                 PLL_PWRMGT_CNTL_P2PLL_TURNOFF | PLL_PWRMGT_CNTL_TVPLL_TURNOFF;
2464         reg &= ~PLL_PWRMGT_CNTL_SU_MCLK_USE_BCLK;
2465         reg &= ~PLL_PWRMGT_CNTL_MOBILE_SU;
2466         OUTPLL(PLL_PWRMGT_CNTL, reg);
2467
2468 //      reg  = INPLL(TV_PLL_CNTL1);
2469 //      reg |= TV_PLL_CNTL1__TVPLL_RESET | TV_PLL_CNTL1__TVPLL_SLEEP;
2470 //      OUTPLL(TV_PLL_CNTL1, reg);
2471
2472         reg  = INREG(TV_DAC_CNTL);
2473         reg &= ~(TV_DAC_CNTL_BGADJ_MASK |TV_DAC_CNTL_DACADJ_MASK);
2474         reg |=TV_DAC_CNTL_BGSLEEP | TV_DAC_CNTL_RDACPD | TV_DAC_CNTL_GDACPD |
2475                 TV_DAC_CNTL_BDACPD |
2476                 (8<<TV_DAC_CNTL_BGADJ__SHIFT) | (8<<TV_DAC_CNTL_DACADJ__SHIFT);
2477         OUTREG(TV_DAC_CNTL, reg);
2478
2479         reg  = INREG(TMDS_TRANSMITTER_CNTL);
2480         reg &= ~(TMDS_PLL_EN |TMDS_PLLRST);
2481         OUTREG(TMDS_TRANSMITTER_CNTL, reg);
2482
2483 //      lvds_pll_cntl  = regr32(g, LVDS_PLL_CNTL);
2484 //      lvds_pll_cntl &= ~LVDS_PLL_CNTL__LVDS_PLL_EN;
2485 //      lvds_pll_cntl |=  LVDS_PLL_CNTL__LVDS_PLL_RESET;
2486 //      regw32(g, LVDS_PLL_CNTL, lvds_pll_cntl);
2487
2488         reg = INREG(DAC_CNTL);
2489         reg &= ~DAC_CMP_EN;
2490         OUTREG(DAC_CNTL, reg);
2491
2492         reg = INREG(DAC_CNTL2);
2493         reg &= ~DAC2_CMP_EN;
2494         OUTREG(DAC_CNTL2, reg);
2495
2496         reg  = INREG(TV_DAC_CNTL);
2497         reg &= ~TV_DAC_CNTL_DETECT;
2498         OUTREG(TV_DAC_CNTL, reg);
2499 }
2500
2501 static void radeon_pm_setup_for_suspend(struct radeonfb_info *rinfo)
2502 {
2503         /* This code is disabled. It does what is in the pm_init
2504          * function of the MacOS driver code ATI sent me. However,
2505          * it doesn't fix my sleep problem, and is causing other issues
2506          * on wakeup (bascially the machine dying when switching consoles
2507          * I haven't had time to investigate this yet
2508          */
2509 #if 0
2510         u32 disp_misc_cntl;
2511         u32 disp_pwr_man;
2512         u32 temp;
2513
2514         // set SPLL, MPLL, PPLL, P2PLL, TVPLL, SCLK, MCLK, PCLK, P2CLK,
2515         // TCLK and TEST_MODE to 0
2516         temp = INPLL(CLK_PWRMGT_CNTL);
2517         OUTPLL(CLK_PWRMGT_CNTL , temp & ~0xc00002ff);
2518
2519         // Turn on Power Management
2520         temp = INPLL(CLK_PWRMGT_CNTL);
2521         OUTPLL(CLK_PWRMGT_CNTL , temp | 0x00000400);
2522
2523         // Turn off display clock if using mobile chips
2524         temp = INPLL(CLK_PWRMGT_CNTL);
2525         OUTREG(CLK_PWRMGT_CNTL , temp | 0x00100000);
2526
2527         // Force PIXCLK_ALWAYS_ON and PIXCLK_DAC_ALWAYS_ON
2528         temp = INPLL(VCLK_ECP_CNTL);
2529         OUTPLL(VCLK_ECP_CNTL, temp & ~0x000000c0);
2530
2531         // Force ECP_FORCE_ON to 1
2532         temp = INPLL(VCLK_ECP_CNTL);
2533         OUTPLL(VCLK_ECP_CNTL, temp | 0x00040000);
2534
2535         // Force PIXCLK_BLEND_ALWAYS_ON and PIXCLK_GV_ALWAYS_ON
2536         temp = INPLL(PIXCLKS_CNTL);
2537         OUTPLL(PIXCLKS_CNTL, temp & ~0x00001800);
2538
2539         // Forcing SCLK_CNTL to ON
2540         OUTPLL(SCLK_CNTL, (INPLL(SCLK_CNTL)& 0x00000007) | 0xffff8000 );
2541
2542         // Set PM control over XTALIN pad
2543         temp = INPLL(CLK_PIN_CNTL);
2544         OUTPLL(CLK_PIN_CNTL, temp | 0x00080000);
2545
2546         // Force MCLK and YCLK and MC as dynamic
2547         temp = INPLL(MCLK_CNTL);
2548         OUTPLL(MCLK_CNTL, temp & 0xffeaffff);
2549
2550         // PLL_TURNOFF
2551         temp = INPLL(PLL_PWRMGT_CNTL);
2552         OUTPLL(PLL_PWRMGT_CNTL, temp | 0x0000001f);
2553
2554         // set MOBILE_SU to 1 if M6 or DDR64 is detected
2555         temp = INPLL(PLL_PWRMGT_CNTL);
2556         OUTPLL(PLL_PWRMGT_CNTL, temp | 0x00010000);
2557
2558         // select PM access mode (PM_MODE_SEL) (use ACPI mode)
2559 //      temp = INPLL(PLL_PWRMGT_CNTL);
2560 //      OUTPLL(PLL_PWRMGT_CNTL, temp | 0x00002000);
2561         temp = INPLL(PLL_PWRMGT_CNTL);
2562         OUTPLL(PLL_PWRMGT_CNTL, temp & ~0x00002000);
2563
2564         // set DISP_MISC_CNTL register
2565         disp_misc_cntl = INREG(DISP_MISC_CNTL);
2566         disp_misc_cntl &= ~(    DISP_MISC_CNTL_SOFT_RESET_GRPH_PP |
2567                                 DISP_MISC_CNTL_SOFT_RESET_SUBPIC_PP |
2568                                 DISP_MISC_CNTL_SOFT_RESET_OV0_PP |
2569                                 DISP_MISC_CNTL_SOFT_RESET_GRPH_SCLK |
2570                                 DISP_MISC_CNTL_SOFT_RESET_SUBPIC_SCLK |
2571                                 DISP_MISC_CNTL_SOFT_RESET_OV0_SCLK |
2572                                 DISP_MISC_CNTL_SOFT_RESET_GRPH2_PP |
2573                                 DISP_MISC_CNTL_SOFT_RESET_GRPH2_SCLK |
2574                                 DISP_MISC_CNTL_SOFT_RESET_LVDS |
2575                                 DISP_MISC_CNTL_SOFT_RESET_TMDS |
2576                                 DISP_MISC_CNTL_SOFT_RESET_DIG_TMDS |
2577                                 DISP_MISC_CNTL_SOFT_RESET_TV);
2578         OUTREG(DISP_MISC_CNTL, disp_misc_cntl);
2579
2580         // set DISP_PWR_MAN register
2581         disp_pwr_man = INREG(DISP_PWR_MAN);
2582         // clau - 9.29.2000 - changes made to bit23:18 to set to 1 as requested by George
2583         disp_pwr_man |= (DISP_PWR_MAN_DIG_TMDS_ENABLE_RST |
2584                     DISP_PWR_MAN_TV_ENABLE_RST |
2585  //                 DISP_PWR_MAN_AUTO_PWRUP_EN |
2586                     DISP_PWR_MAN_DISP_D3_GRPH_RST |
2587                     DISP_PWR_MAN_DISP_D3_SUBPIC_RST |
2588                     DISP_PWR_MAN_DISP_D3_OV0_RST |
2589                     DISP_PWR_MAN_DISP_D1D2_GRPH_RST |
2590                     DISP_PWR_MAN_DISP_D1D2_SUBPIC_RST |
2591                     DISP_PWR_MAN_DISP_D1D2_OV0_RST);
2592         disp_pwr_man &= ~(DISP_PWR_MAN_DISP_PWR_MAN_D3_CRTC_EN |
2593                     DISP_PWR_MAN_DISP2_PWR_MAN_D3_CRTC2_EN|
2594                     DISP_PWR_MAN_DISP_D3_RST |
2595                     DISP_PWR_MAN_DISP_D3_REG_RST);
2596         OUTREG(DISP_PWR_MAN, disp_pwr_man);
2597
2598         // clau - 10.24.2000
2599         // - add in setting for BUS_CNTL1 b27:26 = 0x01 and b31 = 0x1
2600         // - add in setting for AGP_CNTL  b7:0 = 0x20
2601         // - add in setting for DVI_DDC_DATA_OUT_EN b17:16 = 0x0
2602
2603         // the following settings (two lines) are applied at a later part of this function, only on mobile platform
2604         // requres -mobile flag
2605         OUTREG(BUS_CNTL1, (INREG(BUS_CNTL1) & 0xf3ffffff) | 0x04000000);
2606         OUTREG(BUS_CNTL1,  INREG(BUS_CNTL1) | 0x80000000);
2607         OUTREG(AGP_CNTL, (INREG(AGP_CNTL) & 0xffffff00) | 0x20);
2608         OUTREG(GPIO_DVI_DDC, INREG(GPIO_DVI_DDC) & 0xfffcffff);
2609
2610         // yulee - 12.12.2000
2611         // A12 only
2612         // EN_MCLK_TRISTATE_IN_SUSPEND@MCLK_MISC = 1
2613         // ACCESS_REGS_IN_SUSPEND@CLK_PIN_CNTL = 0
2614         // only on mobile platform
2615         OUTPLL(MCLK_MISC, INPLL(MCLK_MISC) | 0x00040000 );
2616
2617         // yulee -12.12.2000
2618         // AGPCLK_VALID@BUS_CNTL1 = 1
2619         // MOBILE_PLATFORM_SEL@BUS_CNTL1 = 01
2620         // CRTC_STEREO_SYNC_OUT_EN@CRTC_OFFSET_CNTL = 0
2621         // CG_CLK_TO_OUTPIN@CLK_PIN_CNTL = 0
2622         // only on mobile platform
2623         OUTPLL(CLK_PIN_CNTL, INPLL(CLK_PIN_CNTL ) & 0xFFFFF7FF );
2624         OUTREG(BUS_CNTL1, (INREG(BUS_CNTL1 ) & 0xF3FFFFFF) | 0x84000000 );
2625         OUTREG(CRTC_OFFSET_CNTL, INREG(CRTC_OFFSET_CNTL ) & 0xFFEFFFFF );
2626
2627         mdelay(100);
2628 #endif
2629
2630         /* Disable CRTCs */
2631         OUTREG(CRTC_GEN_CNTL, (INREG(CRTC_GEN_CNTL) & ~CRTC_EN) | CRTC_DISP_REQ_EN_B);
2632         OUTREG(CRTC2_GEN_CNTL, (INREG(CRTC2_GEN_CNTL) & ~CRTC2_EN) | CRTC2_DISP_REQ_EN_B);
2633         (void)INREG(CRTC2_GEN_CNTL);
2634         mdelay(17);
2635 }
2636
2637 static void radeon_set_suspend(struct radeonfb_info *rinfo, int suspend)
2638 {
2639         u16 pwr_cmd;
2640
2641         if (!rinfo->pm_reg)
2642                 return;
2643
2644         /* Set the chip into appropriate suspend mode (we use D2,
2645          * D3 would require a compete re-initialization of the chip,
2646          * including PCI config registers, clocks, AGP conf, ...)
2647          */
2648         if (suspend) {
2649                 /* According to ATI, we should program V2CLK here, I have
2650                  * to verify what's up exactly
2651                  */
2652                 /* Save some registers */
2653                 radeon_pm_save_regs(rinfo);
2654
2655                 /* Check that on M7 too, might work might not. M7 may also
2656                  * need explicit enabling of PM
2657                  */
2658                 if (rinfo->arch == RADEON_M6) {
2659                         /* Program V2CLK */
2660                         radeon_pm_program_v2clk(rinfo);
2661
2662                         /* Disable IO PADs */
2663                         radeon_pm_disable_iopad(rinfo);
2664
2665                         /* Set low current */
2666                         radeon_pm_low_current(rinfo);
2667
2668                         /* Prepare chip for power management */
2669                         radeon_pm_setup_for_suspend(rinfo);
2670
2671                         /* Reset the MDLL */
2672                         OUTPLL(MDLL_CKO, INPLL(MDLL_CKO) | MCKOA_RESET);
2673                         (void)INPLL(MDLL_RDCKA);
2674                         OUTPLL(MDLL_CKO, INPLL(MDLL_CKO) & ~MCKOA_RESET);
2675                         (void)INPLL(MDLL_RDCKA);
2676                 }
2677
2678                 /* Switch PCI power managment to D2. */
2679                 for (;;) {
2680                         pci_read_config_word(
2681                                 rinfo->pdev, rinfo->pm_reg+PCI_PM_CTRL,
2682                                 &pwr_cmd);
2683                         if (pwr_cmd & 2)
2684                                 break;
2685                         pci_write_config_word(
2686                                 rinfo->pdev, rinfo->pm_reg+PCI_PM_CTRL,
2687                                 (pwr_cmd & ~PCI_PM_CTRL_STATE_MASK) | 2);
2688                         mdelay(500);
2689                 }
2690         } else {
2691                 /* Switch back PCI powermanagment to D0 */
2692                 mdelay(200);
2693                 pci_write_config_word(rinfo->pdev, rinfo->pm_reg+PCI_PM_CTRL, 0);
2694                 mdelay(500);
2695
2696                 dbg_clk = INPLL(1);
2697
2698                 /* Do we need that on M7 ? */
2699                 if (rinfo->arch == RADEON_M6) {
2700                         /* Restore the MDLL */
2701                         OUTPLL(MDLL_CKO, INPLL(MDLL_CKO) & ~MCKOA_RESET);
2702                         (void)INPLL(MDLL_CKO);
2703                 }
2704
2705                 /* Restore some registers */
2706                 radeon_pm_restore_regs(rinfo);
2707         }
2708 }
2709
2710 /*
2711  * Save the contents of the framebuffer when we go to sleep,
2712  * and restore it when we wake up again.
2713  */
2714
2715 int radeon_sleep_notify(struct pmu_sleep_notifier *self, int when)
2716 {
2717         struct radeonfb_info *rinfo;
2718
2719         for (rinfo = board_list; rinfo != NULL; rinfo = rinfo->next) {
2720                 struct fb_fix_screeninfo fix;
2721                 int nb;
2722                 struct display *disp;
2723
2724                 disp = (rinfo->currcon < 0) ? rinfo->info.disp : &fb_display[rinfo->currcon];
2725
2726                 switch (rinfo->arch) {
2727                         case RADEON_M6:
2728                         case RADEON_M7:
2729                         case RADEON_M9:
2730                                 break;
2731                         default:
2732                                 return PBOOK_SLEEP_REFUSE;
2733                 }
2734
2735                 radeonfb_get_fix(&fix, fg_console, (struct fb_info *)rinfo);
2736                 nb = fb_display[fg_console].var.yres * fix.line_length;
2737
2738                 switch (when) {
2739                         case PBOOK_SLEEP_NOW:
2740                                 acquire_console_sem();
2741                                 disp->dispsw = &fbcon_dummy;
2742
2743                                 if (!noaccel) {
2744                                         /* Make sure engine is reset */
2745                                         radeon_engine_reset();
2746                                         radeon_engine_idle();
2747                                 }
2748
2749                                 /* Blank display and LCD */
2750                                 radeonfb_blank(VESA_POWERDOWN+1,
2751                                                (struct fb_info *)rinfo);
2752
2753                                 /* Sleep */
2754                                 rinfo->asleep = 1;
2755                                 radeon_set_suspend(rinfo, 1);
2756                                 release_console_sem();
2757
2758                                 break;
2759                         case PBOOK_WAKE:
2760                                 acquire_console_sem();
2761                                 /* Wakeup */
2762                                 radeon_set_suspend(rinfo, 0);
2763
2764                                 if (!noaccel)
2765                                         radeon_engine_init(rinfo);
2766                                 rinfo->asleep = 0;
2767                                 radeon_set_dispsw(rinfo, disp);
2768                                 radeon_load_video_mode(rinfo, &disp->var);
2769                                 do_install_cmap(rinfo->currcon < 0 ? 0 : rinfo->currcon,
2770                                                 (struct fb_info *)rinfo);
2771
2772                                 radeonfb_blank(0, (struct fb_info *)rinfo);
2773                                 release_console_sem();
2774                                 printk("CLK_PIN_CNTL on wakeup was: %08x\n", dbg_clk);
2775                                 break;
2776                 }
2777         }
2778
2779         return PBOOK_SLEEP_OK;
2780 }
2781
2782 #endif /* CONFIG_PMAC_PBOOK */
2783
2784 static int radeonfb_pci_register (struct pci_dev *pdev,
2785                                   const struct pci_device_id *ent)
2786 {
2787         struct radeonfb_info *rinfo;
2788         struct radeon_chip_info *rci = &radeon_chip_info[ent->driver_data];
2789         u32 tmp;
2790
2791         RTRACE("radeonfb_pci_register BEGIN\n");
2792
2793         /* Enable device in PCI config */
2794         if (pci_enable_device(pdev) != 0) {
2795                 printk(KERN_ERR "radeonfb: Cannot enable PCI device\n");
2796                 return -ENODEV;
2797         }
2798
2799         rinfo = kmalloc (sizeof (struct radeonfb_info), GFP_KERNEL);
2800         if (!rinfo) {
2801                 printk ("radeonfb: could not allocate memory\n");
2802                 return -ENODEV;
2803         }
2804
2805         memset (rinfo, 0, sizeof (struct radeonfb_info));
2806         //info = &rinfo->info;
2807         rinfo->pdev = pdev;
2808         strcpy(rinfo->name, rci->name);
2809         rinfo->arch = rci->arch;
2810
2811         /* Set base addrs */
2812         rinfo->fb_base_phys = pci_resource_start (pdev, 0);
2813         rinfo->mmio_base_phys = pci_resource_start (pdev, 2);
2814
2815         /* request the mem regions */
2816         if (!request_mem_region (rinfo->fb_base_phys,
2817                                  pci_resource_len(pdev, 0), "radeonfb")) {
2818                 printk ("radeonfb: cannot reserve FB region\n");
2819                 kfree (rinfo);
2820                 return -ENODEV;
2821         }
2822
2823         if (!request_mem_region (rinfo->mmio_base_phys,
2824                                  pci_resource_len(pdev, 2), "radeonfb")) {
2825                 printk ("radeonfb: cannot reserve MMIO region\n");
2826                 release_mem_region (rinfo->fb_base_phys,
2827                                     pci_resource_len(pdev, 0));
2828                 kfree (rinfo);
2829                 return -ENODEV;
2830         }
2831
2832         /* map the regions */
2833         rinfo->mmio_base = ioremap (rinfo->mmio_base_phys, RADEON_REGSIZE);
2834         if (!rinfo->mmio_base) {
2835                 printk ("radeonfb: cannot map MMIO\n");
2836                 release_mem_region (rinfo->mmio_base_phys,
2837                                     pci_resource_len(pdev, 2));
2838                 release_mem_region (rinfo->fb_base_phys,
2839                                     pci_resource_len(pdev, 0));
2840                 kfree (rinfo);
2841                 return -ENODEV;
2842         }
2843
2844         rinfo->chipset = pdev->device;
2845
2846         switch (rinfo->arch) {
2847                 case RADEON_R100:
2848                         rinfo->hasCRTC2 = 0;
2849                         break;
2850                 default:
2851                         /* all the rest have it */
2852                         rinfo->hasCRTC2 = 1;
2853                         break;
2854         }
2855 #if 0
2856         if (rinfo->arch == RADEON_M7) {
2857                 /*
2858                  * Noticed some errors in accel with M7, will have to work these out...
2859                  */
2860                 noaccel = 1;
2861         }
2862 #endif
2863         if (mirror)
2864                 printk("radeonfb: mirroring display to CRT\n");
2865
2866         /* framebuffer size */
2867         tmp = INREG(CONFIG_MEMSIZE);
2868
2869         /* mem size is bits [28:0], mask off the rest */
2870         rinfo->video_ram = tmp & CONFIG_MEMSIZE_MASK;
2871
2872         /* ram type */
2873         tmp = INREG(MEM_SDRAM_MODE_REG);
2874         switch ((MEM_CFG_TYPE & tmp) >> 30) {
2875                 case 0:
2876                         /* SDR SGRAM (2:1) */
2877                         strcpy(rinfo->ram_type, "SDR SGRAM");
2878                         rinfo->ram.ml = 4;
2879                         rinfo->ram.mb = 4;
2880                         rinfo->ram.trcd = 1;
2881                         rinfo->ram.trp = 2;
2882                         rinfo->ram.twr = 1;
2883                         rinfo->ram.cl = 2;
2884                         rinfo->ram.loop_latency = 16;
2885                         rinfo->ram.rloop = 16;
2886
2887                         break;
2888                 case 1:
2889                         /* DDR SGRAM */
2890                         strcpy(rinfo->ram_type, "DDR SGRAM");
2891                         rinfo->ram.ml = 4;
2892                         rinfo->ram.mb = 4;
2893                         rinfo->ram.trcd = 3;
2894                         rinfo->ram.trp = 3;
2895                         rinfo->ram.twr = 2;
2896                         rinfo->ram.cl = 3;
2897                         rinfo->ram.tr2w = 1;
2898                         rinfo->ram.loop_latency = 16;
2899                         rinfo->ram.rloop = 16;
2900
2901                         break;
2902                 default:
2903                         /* 64-bit SDR SGRAM */
2904                         strcpy(rinfo->ram_type, "SDR SGRAM 64");
2905                         rinfo->ram.ml = 4;
2906                         rinfo->ram.mb = 8;
2907                         rinfo->ram.trcd = 3;
2908                         rinfo->ram.trp = 3;
2909                         rinfo->ram.twr = 1;
2910                         rinfo->ram.cl = 3;
2911                         rinfo->ram.tr2w = 1;
2912                         rinfo->ram.loop_latency = 17;
2913                         rinfo->ram.rloop = 17;
2914
2915                         break;
2916         }
2917
2918         rinfo->bios_seg = radeon_find_rom(rinfo);
2919         radeon_get_pllinfo(rinfo, rinfo->bios_seg);
2920
2921         /*
2922          * Hack to get around some busted production M6's
2923          * reporting no ram
2924          */
2925         if (rinfo->video_ram == 0) {
2926                 switch (pdev->device) {
2927                         case PCI_DEVICE_ID_ATI_RADEON_LY:
2928                         case PCI_DEVICE_ID_ATI_RADEON_LZ:
2929                                 rinfo->video_ram = 8192 * 1024;
2930                                 break;
2931                         default:
2932                                 break;
2933                 }
2934         }
2935
2936
2937         RTRACE("radeonfb: probed %s %dk videoram\n", (rinfo->ram_type), (rinfo->video_ram/1024));
2938
2939 #if !defined(__powerpc__)
2940         radeon_get_moninfo(rinfo);
2941 #else
2942         switch (pdev->device) {
2943                 case PCI_DEVICE_ID_ATI_RADEON_LW:
2944                 case PCI_DEVICE_ID_ATI_RADEON_LX:
2945                 case PCI_DEVICE_ID_ATI_RADEON_LY:
2946                 case PCI_DEVICE_ID_ATI_RADEON_LZ:
2947                         rinfo->dviDisp_type = MT_LCD;
2948                         break;
2949                 default:
2950                         radeon_get_moninfo(rinfo);
2951                         break;
2952         }
2953 #endif
2954
2955         radeon_get_EDID(rinfo);
2956
2957         if ((rinfo->dviDisp_type == MT_DFP) || (rinfo->dviDisp_type == MT_LCD) ||
2958             (rinfo->crtDisp_type == MT_DFP)) {
2959                 if (!radeon_get_dfpinfo(rinfo)) {
2960                         iounmap(rinfo->mmio_base);
2961                         release_mem_region (rinfo->mmio_base_phys,
2962                                             pci_resource_len(pdev, 2));
2963                         release_mem_region (rinfo->fb_base_phys,
2964                                             pci_resource_len(pdev, 0));
2965                         kfree (rinfo);
2966                         return -ENODEV;
2967                 }
2968         }
2969
2970         rinfo->fb_base = ioremap (rinfo->fb_base_phys, rinfo->video_ram);
2971         if (!rinfo->fb_base) {
2972                 printk ("radeonfb: cannot map FB\n");
2973                 iounmap(rinfo->mmio_base);
2974                 release_mem_region (rinfo->mmio_base_phys,
2975                                     pci_resource_len(pdev, 2));
2976                 release_mem_region (rinfo->fb_base_phys,
2977                                     pci_resource_len(pdev, 0));
2978                 kfree (rinfo);
2979                 return -ENODEV;
2980         }
2981
2982         /* I SHOULD FIX THAT CRAP ! I should probably mimmic XFree DRI
2983          * driver setup here.
2984          *
2985          * On PPC, OF based cards setup the internal memory
2986          * mapping in strange ways. We change it so that the
2987          * framebuffer is mapped at 0 and given half of the card's
2988          * address space (2Gb). AGP is mapped high (0xe0000000) and
2989          * can use up to 512Mb. Once DRI is fully implemented, we
2990          * will have to setup the PCI remapper to remap the agp_special_page
2991          * memory page somewhere between those regions so that the card
2992          * use a normal PCI bus master cycle to access the ring read ptr.
2993          * --BenH.
2994          */
2995 #ifdef CONFIG_ALL_PPC
2996         if (rinfo->hasCRTC2)
2997                 OUTREG(CRTC2_GEN_CNTL,
2998                         (INREG(CRTC2_GEN_CNTL) & ~CRTC2_EN) | CRTC2_DISP_REQ_EN_B);
2999         OUTREG(CRTC_EXT_CNTL, INREG(CRTC_EXT_CNTL) | CRTC_DISPLAY_DIS);
3000         OUTREG(MC_FB_LOCATION, 0x7fff0000);
3001         OUTREG(MC_AGP_LOCATION, 0xffffe000);
3002         OUTREG(DISPLAY_BASE_ADDR, 0x00000000);
3003         if (rinfo->hasCRTC2)
3004                 OUTREG(CRTC2_DISPLAY_BASE_ADDR, 0x00000000);
3005         OUTREG(SRC_OFFSET, 0x00000000);
3006         OUTREG(DST_OFFSET, 0x00000000);
3007         mdelay(10);
3008         OUTREG(CRTC_EXT_CNTL, INREG(CRTC_EXT_CNTL) & ~CRTC_DISPLAY_DIS);
3009 #endif /* CONFIG_ALL_PPC */
3010
3011         /* save current mode regs before we switch into the new one
3012          * so we can restore this upon __exit
3013          */
3014         radeon_save_state (rinfo, &rinfo->init_state);
3015
3016         /* set all the vital stuff */
3017         radeon_set_fbinfo (rinfo);
3018
3019         pci_set_drvdata(pdev, rinfo);
3020         rinfo->next = board_list;
3021         board_list = rinfo;
3022         ((struct fb_info *) rinfo)->device = &pdev->dev;
3023         if (register_framebuffer ((struct fb_info *) rinfo) < 0) {
3024                 printk ("radeonfb: could not register framebuffer\n");
3025                 iounmap(rinfo->fb_base);
3026                 iounmap(rinfo->mmio_base);
3027                 release_mem_region (rinfo->mmio_base_phys,
3028                                     pci_resource_len(pdev, 2));
3029                 release_mem_region (rinfo->fb_base_phys,
3030                                     pci_resource_len(pdev, 0));
3031                 kfree (rinfo);
3032                 return -ENODEV;
3033         }
3034
3035 #ifdef CONFIG_MTRR
3036         rinfo->mtrr_hdl = nomtrr ? -1 : mtrr_add(rinfo->fb_base_phys,
3037                                                  rinfo->video_ram,
3038                                                  MTRR_TYPE_WRCOMB, 1);
3039 #endif
3040
3041 #ifdef CONFIG_PMAC_BACKLIGHT
3042         if (rinfo->dviDisp_type == MT_LCD)
3043                 register_backlight_controller(&radeon_backlight_controller,
3044                                               rinfo, "ati");
3045 #endif
3046
3047 #ifdef CONFIG_PMAC_PBOOK
3048         if (rinfo->dviDisp_type == MT_LCD) {
3049                 rinfo->pm_reg = pci_find_capability(pdev, PCI_CAP_ID_PM);
3050                 pmu_register_sleep_notifier(&radeon_sleep_notifier);
3051         }
3052 #endif
3053
3054         printk ("radeonfb: ATI Radeon %s %s %d MB\n", rinfo->name, rinfo->ram_type,
3055                 (rinfo->video_ram/(1024*1024)));
3056
3057         if (rinfo->hasCRTC2) {
3058                 printk("radeonfb: DVI port %s monitor connected\n",
3059                         GET_MON_NAME(rinfo->dviDisp_type));
3060                 printk("radeonfb: CRT port %s monitor connected\n",
3061                         GET_MON_NAME(rinfo->crtDisp_type));
3062         } else {
3063                 printk("radeonfb: CRT port %s monitor connected\n",
3064                         GET_MON_NAME(rinfo->crtDisp_type));
3065         }
3066
3067         RTRACE("radeonfb_pci_register END\n");
3068
3069         return 0;
3070 }
3071
3072
3073
3074 static void __devexit radeonfb_pci_unregister (struct pci_dev *pdev)
3075 {
3076         struct radeonfb_info *rinfo = pci_get_drvdata(pdev);
3077
3078         if (!rinfo)
3079                 return;
3080
3081         /* restore original state
3082          *
3083          * Doesn't quite work yet, possibly because of the PPC hacking
3084          * I do on startup, disable for now. --BenH
3085          */
3086         radeon_write_mode (rinfo, &rinfo->init_state);
3087
3088 #ifdef CONFIG_MTRR
3089         if (rinfo->mtrr_hdl >= 0)
3090                 mtrr_del(rinfo->mtrr_hdl, 0, 0);
3091 #endif
3092
3093         unregister_framebuffer ((struct fb_info *) rinfo);
3094
3095         iounmap(rinfo->mmio_base);
3096         iounmap(rinfo->fb_base);
3097
3098         release_mem_region (rinfo->mmio_base_phys,
3099                             pci_resource_len(pdev, 2));
3100         release_mem_region (rinfo->fb_base_phys,
3101                             pci_resource_len(pdev, 0));
3102
3103         kfree (rinfo);
3104 }
3105
3106
3107 static struct pci_driver radeonfb_driver = {
3108         .name           = "radeonfb",
3109         .id_table       = radeonfb_pci_table,
3110         .probe          = radeonfb_pci_register,
3111         .remove         = __devexit_p(radeonfb_pci_unregister),
3112 };
3113
3114 #ifndef MODULE
3115 static int __init radeonfb_old_setup (char *options)
3116 {
3117         char *this_opt;
3118
3119         if (!options || !*options)
3120                 return 0;
3121
3122         while ((this_opt = strsep (&options, ",")) != NULL) {
3123                 if (!*this_opt)
3124                         continue;
3125                 if (!strncmp(this_opt, "noaccel", 7)) {
3126                         noaccel = 1;
3127                 } else if (!strncmp(this_opt, "mirror", 6)) {
3128                         mirror = 1;
3129                 } else if (!strncmp(this_opt, "dfp", 3)) {
3130                         force_dfp = 1;
3131                 } else if (!strncmp(this_opt, "panel_yres:", 11)) {
3132                         panel_yres = simple_strtoul((this_opt+11), NULL, 0);
3133                 } else if (!strncmp(this_opt, "nomtrr", 6)) {
3134                         nomtrr = 1;
3135                 } else
3136                         mode_option = this_opt;
3137         }
3138
3139         return 0;
3140 }
3141 #endif  /*  MODULE  */
3142
3143 static int __init radeonfb_old_init (void)
3144 {
3145 #ifndef MODULE
3146         char *option = NULL;
3147
3148         if (fb_get_options("radeonfb_old", &option))
3149                 return -ENODEV;
3150         radeonfb_old_setup(option);
3151 #endif
3152         return pci_register_driver (&radeonfb_driver);
3153 }
3154
3155
3156 static void __exit radeonfb_old_exit (void)
3157 {
3158         pci_unregister_driver (&radeonfb_driver);
3159 }
3160
3161 module_init(radeonfb_old_init);
3162 module_exit(radeonfb_old_exit);
3163
3164
3165 MODULE_AUTHOR("Ani Joshi");
3166 MODULE_DESCRIPTION("framebuffer driver for ATI Radeon chipset");
3167 MODULE_LICENSE("GPL");