2 * MPC8540 ADS Device Tree Source
4 * Copyright 2006, 2008 Freescale Semiconductor Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
16 compatible = "MPC8540ADS", "MPC85xxADS";
36 d-cache-line-size = <32>; // 32 bytes
37 i-cache-line-size = <32>; // 32 bytes
38 d-cache-size = <0x8000>; // L1, 32K
39 i-cache-size = <0x8000>; // L1, 32K
40 timebase-frequency = <0>; // 33 MHz, from uboot
41 bus-frequency = <0>; // 166 MHz
42 clock-frequency = <0>; // 825 MHz, from uboot
43 next-level-cache = <&L2>;
48 device_type = "memory";
49 reg = <0x0 0x8000000>; // 128M at 0x0
56 compatible = "simple-bus";
57 ranges = <0x0 0xe0000000 0x100000>;
58 reg = <0xe0000000 0x100000>; // CCSRBAR 1M
61 memory-controller@2000 {
62 compatible = "fsl,8540-memory-controller";
63 reg = <0x2000 0x1000>;
64 interrupt-parent = <&mpic>;
68 L2: l2-cache-controller@20000 {
69 compatible = "fsl,8540-l2-cache-controller";
70 reg = <0x20000 0x1000>;
71 cache-line-size = <32>; // 32 bytes
72 cache-size = <0x40000>; // L2, 256K
73 interrupt-parent = <&mpic>;
81 compatible = "fsl-i2c";
84 interrupt-parent = <&mpic>;
91 compatible = "fsl,mpc8540-dma", "fsl,eloplus-dma";
93 ranges = <0x0 0x21100 0x200>;
96 compatible = "fsl,mpc8540-dma-channel",
97 "fsl,eloplus-dma-channel";
100 interrupt-parent = <&mpic>;
104 compatible = "fsl,mpc8540-dma-channel",
105 "fsl,eloplus-dma-channel";
108 interrupt-parent = <&mpic>;
112 compatible = "fsl,mpc8540-dma-channel",
113 "fsl,eloplus-dma-channel";
116 interrupt-parent = <&mpic>;
120 compatible = "fsl,mpc8540-dma-channel",
121 "fsl,eloplus-dma-channel";
124 interrupt-parent = <&mpic>;
130 #address-cells = <1>;
132 compatible = "fsl,gianfar-mdio";
133 reg = <0x24520 0x20>;
135 phy0: ethernet-phy@0 {
136 interrupt-parent = <&mpic>;
139 device_type = "ethernet-phy";
141 phy1: ethernet-phy@1 {
142 interrupt-parent = <&mpic>;
145 device_type = "ethernet-phy";
147 phy3: ethernet-phy@3 {
148 interrupt-parent = <&mpic>;
151 device_type = "ethernet-phy";
155 device_type = "tbi-phy";
160 #address-cells = <1>;
162 compatible = "fsl,gianfar-tbi";
163 reg = <0x25520 0x20>;
167 device_type = "tbi-phy";
172 #address-cells = <1>;
174 compatible = "fsl,gianfar-tbi";
175 reg = <0x26520 0x20>;
179 device_type = "tbi-phy";
183 enet0: ethernet@24000 {
185 device_type = "network";
187 compatible = "gianfar";
188 reg = <0x24000 0x1000>;
189 local-mac-address = [ 00 00 00 00 00 00 ];
190 interrupts = <29 2 30 2 34 2>;
191 interrupt-parent = <&mpic>;
192 tbi-handle = <&tbi0>;
193 phy-handle = <&phy0>;
196 enet1: ethernet@25000 {
198 device_type = "network";
200 compatible = "gianfar";
201 reg = <0x25000 0x1000>;
202 local-mac-address = [ 00 00 00 00 00 00 ];
203 interrupts = <35 2 36 2 40 2>;
204 interrupt-parent = <&mpic>;
205 tbi-handle = <&tbi1>;
206 phy-handle = <&phy1>;
209 enet2: ethernet@26000 {
211 device_type = "network";
213 compatible = "gianfar";
214 reg = <0x26000 0x1000>;
215 local-mac-address = [ 00 00 00 00 00 00 ];
217 interrupt-parent = <&mpic>;
218 tbi-handle = <&tbi2>;
219 phy-handle = <&phy3>;
222 serial0: serial@4500 {
224 device_type = "serial";
225 compatible = "ns16550";
226 reg = <0x4500 0x100>; // reg base, size
227 clock-frequency = <0>; // should we fill in in uboot?
229 interrupt-parent = <&mpic>;
232 serial1: serial@4600 {
234 device_type = "serial";
235 compatible = "ns16550";
236 reg = <0x4600 0x100>; // reg base, size
237 clock-frequency = <0>; // should we fill in in uboot?
239 interrupt-parent = <&mpic>;
242 interrupt-controller;
243 #address-cells = <0>;
244 #interrupt-cells = <2>;
245 reg = <0x40000 0x40000>;
246 compatible = "chrp,open-pic";
247 device_type = "open-pic";
253 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
257 0x1000 0x0 0x0 0x1 &mpic 0x1 0x1
258 0x1000 0x0 0x0 0x2 &mpic 0x2 0x1
259 0x1000 0x0 0x0 0x3 &mpic 0x3 0x1
260 0x1000 0x0 0x0 0x4 &mpic 0x4 0x1
263 0x1800 0x0 0x0 0x1 &mpic 0x4 0x1
264 0x1800 0x0 0x0 0x2 &mpic 0x1 0x1
265 0x1800 0x0 0x0 0x3 &mpic 0x2 0x1
266 0x1800 0x0 0x0 0x4 &mpic 0x3 0x1
269 0x2000 0x0 0x0 0x1 &mpic 0x3 0x1
270 0x2000 0x0 0x0 0x2 &mpic 0x4 0x1
271 0x2000 0x0 0x0 0x3 &mpic 0x1 0x1
272 0x2000 0x0 0x0 0x4 &mpic 0x2 0x1
275 0x2800 0x0 0x0 0x1 &mpic 0x2 0x1
276 0x2800 0x0 0x0 0x2 &mpic 0x3 0x1
277 0x2800 0x0 0x0 0x3 &mpic 0x4 0x1
278 0x2800 0x0 0x0 0x4 &mpic 0x1 0x1
281 0x6000 0x0 0x0 0x1 &mpic 0x1 0x1
282 0x6000 0x0 0x0 0x2 &mpic 0x2 0x1
283 0x6000 0x0 0x0 0x3 &mpic 0x3 0x1
284 0x6000 0x0 0x0 0x4 &mpic 0x4 0x1
287 0x6800 0x0 0x0 0x1 &mpic 0x4 0x1
288 0x6800 0x0 0x0 0x2 &mpic 0x1 0x1
289 0x6800 0x0 0x0 0x3 &mpic 0x2 0x1
290 0x6800 0x0 0x0 0x4 &mpic 0x3 0x1
293 0x7000 0x0 0x0 0x1 &mpic 0x3 0x1
294 0x7000 0x0 0x0 0x2 &mpic 0x4 0x1
295 0x7000 0x0 0x0 0x3 &mpic 0x1 0x1
296 0x7000 0x0 0x0 0x4 &mpic 0x2 0x1
299 0x7800 0x0 0x0 0x1 &mpic 0x2 0x1
300 0x7800 0x0 0x0 0x2 &mpic 0x3 0x1
301 0x7800 0x0 0x0 0x3 &mpic 0x4 0x1
302 0x7800 0x0 0x0 0x4 &mpic 0x1 0x1
305 0x9000 0x0 0x0 0x1 &mpic 0x1 0x1
306 0x9000 0x0 0x0 0x2 &mpic 0x2 0x1
307 0x9000 0x0 0x0 0x3 &mpic 0x3 0x1
308 0x9000 0x0 0x0 0x4 &mpic 0x4 0x1
311 0x9800 0x0 0x0 0x1 &mpic 0x4 0x1
312 0x9800 0x0 0x0 0x2 &mpic 0x1 0x1
313 0x9800 0x0 0x0 0x3 &mpic 0x2 0x1
314 0x9800 0x0 0x0 0x4 &mpic 0x3 0x1
317 0xa000 0x0 0x0 0x1 &mpic 0x3 0x1
318 0xa000 0x0 0x0 0x2 &mpic 0x4 0x1
319 0xa000 0x0 0x0 0x3 &mpic 0x1 0x1
320 0xa000 0x0 0x0 0x4 &mpic 0x2 0x1
323 0xa800 0x0 0x0 0x1 &mpic 0x2 0x1
324 0xa800 0x0 0x0 0x2 &mpic 0x3 0x1
325 0xa800 0x0 0x0 0x3 &mpic 0x4 0x1
326 0xa800 0x0 0x0 0x4 &mpic 0x1 0x1>;
327 interrupt-parent = <&mpic>;
330 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
331 0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>;
332 clock-frequency = <66666666>;
333 #interrupt-cells = <1>;
335 #address-cells = <3>;
336 reg = <0xe0008000 0x1000>;
337 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";