2 * etrap.S: Preparing for entry into the kernel on Sparc V9.
4 * Copyright (C) 1996, 1997 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1997, 1998, 1999 Jakub Jelinek (jj@ultra.linux.cz)
10 #include <asm/pstate.h>
11 #include <asm/ptrace.h>
13 #include <asm/spitfire.h>
15 #include <asm/processor.h>
18 #define TASK_REGOFF (THREAD_SIZE-TRACEREG_SZ-STACKFRAME_SZ)
19 #define ETRAP_PSTATE1 (PSTATE_RMO | PSTATE_PRIV)
20 #define ETRAP_PSTATE2 \
21 (PSTATE_RMO | PSTATE_PEF | PSTATE_PRIV | PSTATE_IE)
24 * On entry, %g7 is return address - 0x4.
25 * %g4 and %g5 will be preserved %l4 and %l5 respectively.
30 .globl etrap_syscall, etrap, etrap_irq, etraptl1
33 etrap_syscall: TRAP_LOAD_THREAD_REG(%g6, %g1)
37 andcc %g1, TSTATE_PRIV, %g0
40 sub %sp, STACKFRAME_SZ+TRACEREG_SZ-STACK_BIAS, %g2
41 wrpr %g0, 7, %cleanwin
43 sethi %hi(TASK_REGOFF), %g2
44 sethi %hi(TSTATE_PEF), %g3
45 or %g2, %lo(TASK_REGOFF), %g2
52 stx %g1, [%g2 + STACKFRAME_SZ + PT_V9_TSTATE]
54 stx %g3, [%g2 + STACKFRAME_SZ + PT_V9_TPC]
56 stx %g1, [%g2 + STACKFRAME_SZ + PT_V9_TNPC]
58 st %g3, [%g2 + STACKFRAME_SZ + PT_V9_Y]
59 sethi %hi(PT_REGS_MAGIC), %g3
61 st %g1, [%g2 + STACKFRAME_SZ + PT_V9_MAGIC]
64 brnz,pt %g1, etrap_save
70 be,pt %xcc, etrap_user_spill
74 brz %g3, etrap_kernel_spill
80 ldx [%g6 + TI_FLAGS], %g3
81 and %g3, _TIF_32BIT, %g3
82 brnz,pt %g3, etrap_user_spill_32bit
84 ba,a,pt %xcc, etrap_user_spill_64bit
86 etrap_save: save %g2, -STACK_BIAS, %sp
90 mov PRIMARY_CONTEXT, %l4
93 wrpr %g0, 0, %canrestore
96 stb %l5, [%l6 + TI_FPDEPTH]
98 wrpr %g3, 0, %otherwin
100 sethi %hi(sparc64_kern_pri_context), %g2
101 ldx [%g2 + %lo(sparc64_kern_pri_context)], %g3
103 661: stxa %g3, [%l4] ASI_DMMU
104 .section .sun4v_1insn_patch, "ax"
106 stxa %g3, [%l4] ASI_MMU
109 sethi %hi(KERNBASE), %l4
116 /* Go to trap time globals so we can save them. */
117 661: wrpr %g0, ETRAP_PSTATE1, %pstate
118 .section .sun4v_1insn_patch, "ax"
123 stx %g1, [%sp + PTREGS_OFF + PT_V9_G1]
124 stx %g2, [%sp + PTREGS_OFF + PT_V9_G2]
126 stx %g3, [%sp + PTREGS_OFF + PT_V9_G3]
128 stx %g4, [%sp + PTREGS_OFF + PT_V9_G4]
129 stx %g5, [%sp + PTREGS_OFF + PT_V9_G5]
130 stx %g6, [%sp + PTREGS_OFF + PT_V9_G6]
131 stx %g7, [%sp + PTREGS_OFF + PT_V9_G7]
133 sethi %hi(TSTATE_RMO | TSTATE_PEF), %l0
136 wrpr %l7, (TSTATE_PRIV | TSTATE_IE), %tstate
137 stx %i0, [%sp + PTREGS_OFF + PT_V9_I0]
138 stx %i1, [%sp + PTREGS_OFF + PT_V9_I1]
139 stx %i2, [%sp + PTREGS_OFF + PT_V9_I2]
140 stx %i3, [%sp + PTREGS_OFF + PT_V9_I3]
141 stx %i4, [%sp + PTREGS_OFF + PT_V9_I4]
142 stx %i5, [%sp + PTREGS_OFF + PT_V9_I5]
143 stx %i6, [%sp + PTREGS_OFF + PT_V9_I6]
145 stx %i7, [%sp + PTREGS_OFF + PT_V9_I7]
146 LOAD_PER_CPU_BASE(%g5, %g6, %g4, %g3, %l1)
147 ldx [%g6 + TI_TASK], %g4
151 ldub [%l6 + TI_FPDEPTH], %l5
152 add %l6, TI_FPSAVED + 1, %l4
155 stb %l5, [%l6 + TI_FPDEPTH]
160 etraptl1: /* Save tstate/tpc/tnpc of TL 1-->4 and the tl register itself.
161 * We place this right after pt_regs on the trap stack.
171 TRAP_LOAD_THREAD_REG(%g6, %g1)
172 sub %sp, ((4 * 8) * 4) + 8, %g2
177 stx %g3, [%g2 + STACK_BIAS + 0x00]
179 stx %g3, [%g2 + STACK_BIAS + 0x08]
181 stx %g3, [%g2 + STACK_BIAS + 0x10]
183 stx %g3, [%g2 + STACK_BIAS + 0x18]
187 stx %g3, [%g2 + STACK_BIAS + 0x20]
189 stx %g3, [%g2 + STACK_BIAS + 0x28]
191 stx %g3, [%g2 + STACK_BIAS + 0x30]
193 stx %g3, [%g2 + STACK_BIAS + 0x38]
195 sethi %hi(is_sun4v), %g3
196 lduw [%g3 + %lo(is_sun4v)], %g3
197 brnz,pn %g3, finish_tl1_capture
202 stx %g3, [%g2 + STACK_BIAS + 0x40]
204 stx %g3, [%g2 + STACK_BIAS + 0x48]
206 stx %g3, [%g2 + STACK_BIAS + 0x50]
208 stx %g3, [%g2 + STACK_BIAS + 0x58]
212 stx %g3, [%g2 + STACK_BIAS + 0x60]
214 stx %g3, [%g2 + STACK_BIAS + 0x68]
216 stx %g3, [%g2 + STACK_BIAS + 0x70]
218 stx %g3, [%g2 + STACK_BIAS + 0x78]
220 stx %g1, [%g2 + STACK_BIAS + 0x80]
225 .section .sun4v_1insn_patch, "ax"
231 sub %g2, STACKFRAME_SZ + TRACEREG_SZ - STACK_BIAS, %g2
233 andcc %g1, TSTATE_PRIV, %g0