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   1 /*
   2  * tg3.c: Broadcom Tigon3 ethernet driver.
   3  *
   4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
   5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
   6  * Copyright (C) 2004 Sun Microsystems Inc.
   7  * Copyright (C) 2005-2007 Broadcom Corporation.
   8  *
   9  * Firmware is:
  10  *      Derived from proprietary unpublished source code,
  11  *      Copyright (C) 2000-2003 Broadcom Corporation.
  12  *
  13  *      Permission is hereby granted for the distribution of this firmware
  14  *      data in hexadecimal or equivalent format, provided this copyright
  15  *      notice is accompanying it.
  16  */
  17
  18
  19 #include <linux/module.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/kernel.h>
  22 #include <linux/types.h>
  23 #include <linux/compiler.h>
  24 #include <linux/slab.h>
  25 #include <linux/delay.h>
  26 #include <linux/in.h>
  27 #include <linux/init.h>
  28 #include <linux/ioport.h>
  29 #include <linux/pci.h>
  30 #include <linux/netdevice.h>
  31 #include <linux/etherdevice.h>
  32 #include <linux/skbuff.h>
  33 #include <linux/ethtool.h>
  34 #include <linux/mii.h>
  35 #include <linux/phy.h>
  36 #include <linux/brcmphy.h>
  37 #include <linux/if_vlan.h>
  38 #include <linux/ip.h>
  39 #include <linux/tcp.h>
  40 #include <linux/workqueue.h>
  41 #include <linux/prefetch.h>
  42 #include <linux/dma-mapping.h>
  43
  44 #include <net/checksum.h>
  45 #include <net/ip.h>
  46
  47 #include <asm/system.h>
  48 #include <asm/io.h>
  49 #include <asm/byteorder.h>
  50 #include <asm/uaccess.h>
  51
  52 #ifdef CONFIG_SPARC
  53 #include <asm/idprom.h>
  54 #include <asm/prom.h>
  55 #endif
  56
  57 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  58 #define TG3_VLAN_TAG_USED 1
  59 #else
  60 #define TG3_VLAN_TAG_USED 0
  61 #endif
  62
  63 #define TG3_TSO_SUPPORT 1
  64
  65 #include "tg3.h"
  66
  67 #define DRV_MODULE_NAME         "tg3"
  68 #define PFX DRV_MODULE_NAME     ": "
  69 #define DRV_MODULE_VERSION      "3.94"
  70 #define DRV_MODULE_RELDATE      "August 14, 2008"
  71
  72 #define TG3_DEF_MAC_MODE        0
  73 #define TG3_DEF_RX_MODE         0
  74 #define TG3_DEF_TX_MODE         0
  75 #define TG3_DEF_MSG_ENABLE        \
  76         (NETIF_MSG_DRV          | \
  77          NETIF_MSG_PROBE        | \
  78          NETIF_MSG_LINK         | \
  79          NETIF_MSG_TIMER        | \
  80          NETIF_MSG_IFDOWN       | \
  81          NETIF_MSG_IFUP         | \
  82          NETIF_MSG_RX_ERR       | \
  83          NETIF_MSG_TX_ERR)
  84
  85 /* length of time before we decide the hardware is borked,
  86  * and dev->tx_timeout() should be called to fix the problem
  87  */
  88 #define TG3_TX_TIMEOUT                  (5 * HZ)
  89
  90 /* hardware minimum and maximum for a single frame's data payload */
  91 #define TG3_MIN_MTU                     60
  92 #define TG3_MAX_MTU(tp) \
  93         ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
  94
  95 /* These numbers seem to be hard coded in the NIC firmware somehow.
  96  * You can't change the ring sizes, but you can change where you place
  97  * them in the NIC onboard memory.
  98  */
  99 #define TG3_RX_RING_SIZE                512
 100 #define TG3_DEF_RX_RING_PENDING         200
 101 #define TG3_RX_JUMBO_RING_SIZE          256
 102 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
 103
 104 /* Do not place this n-ring entries value into the tp struct itself,
 105  * we really want to expose these constants to GCC so that modulo et
 106  * al.  operations are done with shifts and masks instead of with
 107  * hw multiply/modulo instructions.  Another solution would be to
 108  * replace things like '% foo' with '& (foo - 1)'.
 109  */
 110 #define TG3_RX_RCB_RING_SIZE(tp)        \
 111         ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ?  512 : 1024)
 112
 113 #define TG3_TX_RING_SIZE                512
 114 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
 115
 116 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
 117                                  TG3_RX_RING_SIZE)
 118 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
 119                                  TG3_RX_JUMBO_RING_SIZE)
 120 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
 121                                    TG3_RX_RCB_RING_SIZE(tp))
 122 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
 123                                  TG3_TX_RING_SIZE)
 124 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
 125
 126 #define RX_PKT_BUF_SZ           (1536 + tp->rx_offset + 64)
 127 #define RX_JUMBO_PKT_BUF_SZ     (9046 + tp->rx_offset + 64)
 128
 129 /* minimum number of free TX descriptors required to wake up TX process */
 130 #define TG3_TX_WAKEUP_THRESH(tp)                ((tp)->tx_pending / 4)
 131
 132 /* number of ETHTOOL_GSTATS u64's */
 133 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
 134
 135 #define TG3_NUM_TEST            6
 136
 137 static char version[] __devinitdata =
 138         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
 139
 140 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
 141 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
 142 MODULE_LICENSE("GPL");
 143 MODULE_VERSION(DRV_MODULE_VERSION);
 144
 145 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
 146 module_param(tg3_debug, int, 0);
 147 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
 148
 149 static struct pci_device_id tg3_pci_tbl[] = {
 150         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
 151         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
 152         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
 153         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
 154         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
 155         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
 156         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
 157         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
 158         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
 159         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
 160         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
 161         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
 162         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
 163         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
 164         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
 165         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
 166         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
 167         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
 168         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
 169         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
 170         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
 171         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
 172         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
 173         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
 174         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
 175         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
 176         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
 177         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
 178         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
 179         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
 180         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
 181         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
 182         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
 183         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
 184         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
 185         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
 186         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
 187         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
 188         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
 189         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
 190         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
 191         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
 192         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
 193         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
 194         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
 195         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
 196         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
 197         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
 198         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
 199         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
 200         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
 201         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
 202         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
 203         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
 204         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
 205         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
 206         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
 207         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
 208         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5785)},
 209         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
 210         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
 211         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
 212         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
 213         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
 214         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
 215         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
 216         {}
 217 };
 218
 219 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
 220
 221 static const struct {
 222         const char string[ETH_GSTRING_LEN];
 223 } ethtool_stats_keys[TG3_NUM_STATS] = {
 224         { "rx_octets" },
 225         { "rx_fragments" },
 226         { "rx_ucast_packets" },
 227         { "rx_mcast_packets" },
 228         { "rx_bcast_packets" },
 229         { "rx_fcs_errors" },
 230         { "rx_align_errors" },
 231         { "rx_xon_pause_rcvd" },
 232         { "rx_xoff_pause_rcvd" },
 233         { "rx_mac_ctrl_rcvd" },
 234         { "rx_xoff_entered" },
 235         { "rx_frame_too_long_errors" },
 236         { "rx_jabbers" },
 237         { "rx_undersize_packets" },
 238         { "rx_in_length_errors" },
 239         { "rx_out_length_errors" },
 240         { "rx_64_or_less_octet_packets" },
 241         { "rx_65_to_127_octet_packets" },
 242         { "rx_128_to_255_octet_packets" },
 243         { "rx_256_to_511_octet_packets" },
 244         { "rx_512_to_1023_octet_packets" },
 245         { "rx_1024_to_1522_octet_packets" },
 246         { "rx_1523_to_2047_octet_packets" },
 247         { "rx_2048_to_4095_octet_packets" },
 248         { "rx_4096_to_8191_octet_packets" },
 249         { "rx_8192_to_9022_octet_packets" },
 250
 251         { "tx_octets" },
 252         { "tx_collisions" },
 253
 254         { "tx_xon_sent" },
 255         { "tx_xoff_sent" },
 256         { "tx_flow_control" },
 257         { "tx_mac_errors" },
 258         { "tx_single_collisions" },
 259         { "tx_mult_collisions" },
 260         { "tx_deferred" },
 261         { "tx_excessive_collisions" },
 262         { "tx_late_collisions" },
 263         { "tx_collide_2times" },
 264         { "tx_collide_3times" },
 265         { "tx_collide_4times" },
 266         { "tx_collide_5times" },
 267         { "tx_collide_6times" },
 268         { "tx_collide_7times" },
 269         { "tx_collide_8times" },
 270         { "tx_collide_9times" },
 271         { "tx_collide_10times" },
 272         { "tx_collide_11times" },
 273         { "tx_collide_12times" },
 274         { "tx_collide_13times" },
 275         { "tx_collide_14times" },
 276         { "tx_collide_15times" },
 277         { "tx_ucast_packets" },
 278         { "tx_mcast_packets" },
 279         { "tx_bcast_packets" },
 280         { "tx_carrier_sense_errors" },
 281         { "tx_discards" },
 282         { "tx_errors" },
 283
 284         { "dma_writeq_full" },
 285         { "dma_write_prioq_full" },
 286         { "rxbds_empty" },
 287         { "rx_discards" },
 288         { "rx_errors" },
 289         { "rx_threshold_hit" },
 290
 291         { "dma_readq_full" },
 292         { "dma_read_prioq_full" },
 293         { "tx_comp_queue_full" },
 294
 295         { "ring_set_send_prod_index" },
 296         { "ring_status_update" },
 297         { "nic_irqs" },
 298         { "nic_avoided_irqs" },
 299         { "nic_tx_threshold_hit" }
 300 };
 301
 302 static const struct {
 303         const char string[ETH_GSTRING_LEN];
 304 } ethtool_test_keys[TG3_NUM_TEST] = {
 305         { "nvram test     (online) " },
 306         { "link test      (online) " },
 307         { "register test  (offline)" },
 308         { "memory test    (offline)" },
 309         { "loopback test  (offline)" },
 310         { "interrupt test (offline)" },
 311 };
 312
 313 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
 314 {
 315         writel(val, tp->regs + off);
 316 }
 317
 318 static u32 tg3_read32(struct tg3 *tp, u32 off)
 319 {
 320         return (readl(tp->regs + off));
 321 }
 322
 323 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
 324 {
 325         writel(val, tp->aperegs + off);
 326 }
 327
 328 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
 329 {
 330         return (readl(tp->aperegs + off));
 331 }
 332
 333 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
 334 {
 335         unsigned long flags;
 336
 337         spin_lock_irqsave(&tp->indirect_lock, flags);
 338         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 339         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 340         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 341 }
 342
 343 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
 344 {
 345         writel(val, tp->regs + off);
 346         readl(tp->regs + off);
 347 }
 348
 349 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
 350 {
 351         unsigned long flags;
 352         u32 val;
 353
 354         spin_lock_irqsave(&tp->indirect_lock, flags);
 355         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 356         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 357         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 358         return val;
 359 }
 360
 361 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
 362 {
 363         unsigned long flags;
 364
 365         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
 366                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
 367                                        TG3_64BIT_REG_LOW, val);
 368                 return;
 369         }
 370         if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
 371                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
 372                                        TG3_64BIT_REG_LOW, val);
 373                 return;
 374         }
 375
 376         spin_lock_irqsave(&tp->indirect_lock, flags);
 377         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 378         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 379         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 380
 381         /* In indirect mode when disabling interrupts, we also need
 382          * to clear the interrupt bit in the GRC local ctrl register.
 383          */
 384         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
 385             (val == 0x1)) {
 386                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
 387                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
 388         }
 389 }
 390
 391 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
 392 {
 393         unsigned long flags;
 394         u32 val;
 395
 396         spin_lock_irqsave(&tp->indirect_lock, flags);
 397         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 398         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 399         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 400         return val;
 401 }
 402
 403 /* usec_wait specifies the wait time in usec when writing to certain registers
 404  * where it is unsafe to read back the register without some delay.
 405  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
 406  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
 407  */
 408 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
 409 {
 410         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
 411             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 412                 /* Non-posted methods */
 413                 tp->write32(tp, off, val);
 414         else {
 415                 /* Posted method */
 416                 tg3_write32(tp, off, val);
 417                 if (usec_wait)
 418                         udelay(usec_wait);
 419                 tp->read32(tp, off);
 420         }
 421         /* Wait again after the read for the posted method to guarantee that
 422          * the wait time is met.
 423          */
 424         if (usec_wait)
 425                 udelay(usec_wait);
 426 }
 427
 428 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
 429 {
 430         tp->write32_mbox(tp, off, val);
 431         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
 432             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 433                 tp->read32_mbox(tp, off);
 434 }
 435
 436 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
 437 {
 438         void __iomem *mbox = tp->regs + off;
 439         writel(val, mbox);
 440         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
 441                 writel(val, mbox);
 442         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
 443                 readl(mbox);
 444 }
 445
 446 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
 447 {
 448         return (readl(tp->regs + off + GRCMBOX_BASE));
 449 }
 450
 451 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
 452 {
 453         writel(val, tp->regs + off + GRCMBOX_BASE);
 454 }
 455
 456 #define tw32_mailbox(reg, val)  tp->write32_mbox(tp, reg, val)
 457 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
 458 #define tw32_rx_mbox(reg, val)  tp->write32_rx_mbox(tp, reg, val)
 459 #define tw32_tx_mbox(reg, val)  tp->write32_tx_mbox(tp, reg, val)
 460 #define tr32_mailbox(reg)       tp->read32_mbox(tp, reg)
 461
 462 #define tw32(reg,val)           tp->write32(tp, reg, val)
 463 #define tw32_f(reg,val)         _tw32_flush(tp,(reg),(val), 0)
 464 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
 465 #define tr32(reg)               tp->read32(tp, reg)
 466
 467 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
 468 {
 469         unsigned long flags;
 470
 471         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 472             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
 473                 return;
 474
 475         spin_lock_irqsave(&tp->indirect_lock, flags);
 476         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 477                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 478                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 479
 480                 /* Always leave this as zero. */
 481                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 482         } else {
 483                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 484                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
 485
 486                 /* Always leave this as zero. */
 487                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 488         }
 489         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 490 }
 491
 492 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 493 {
 494         unsigned long flags;
 495
 496         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 497             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
 498                 *val = 0;
 499                 return;
 500         }
 501
 502         spin_lock_irqsave(&tp->indirect_lock, flags);
 503         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 504                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 505                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 506
 507                 /* Always leave this as zero. */
 508                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 509         } else {
 510                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 511                 *val = tr32(TG3PCI_MEM_WIN_DATA);
 512
 513                 /* Always leave this as zero. */
 514                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 515         }
 516         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 517 }
 518
 519 static void tg3_ape_lock_init(struct tg3 *tp)
 520 {
 521         int i;
 522
 523         /* Make sure the driver hasn't any stale locks. */
 524         for (i = 0; i < 8; i++)
 525                 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
 526                                 APE_LOCK_GRANT_DRIVER);
 527 }
 528
 529 static int tg3_ape_lock(struct tg3 *tp, int locknum)
 530 {
 531         int i, off;
 532         int ret = 0;
 533         u32 status;
 534
 535         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 536                 return 0;
 537
 538         switch (locknum) {
 539                 case TG3_APE_LOCK_GRC:
 540                 case TG3_APE_LOCK_MEM:
 541                         break;
 542                 default:
 543                         return -EINVAL;
 544         }
 545
 546         off = 4 * locknum;
 547
 548         tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
 549
 550         /* Wait for up to 1 millisecond to acquire lock. */
 551         for (i = 0; i < 100; i++) {
 552                 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
 553                 if (status == APE_LOCK_GRANT_DRIVER)
 554                         break;
 555                 udelay(10);
 556         }
 557
 558         if (status != APE_LOCK_GRANT_DRIVER) {
 559                 /* Revoke the lock request. */
 560                 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
 561                                 APE_LOCK_GRANT_DRIVER);
 562
 563                 ret = -EBUSY;
 564         }
 565
 566         return ret;
 567 }
 568
 569 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
 570 {
 571         int off;
 572
 573         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 574                 return;
 575
 576         switch (locknum) {
 577                 case TG3_APE_LOCK_GRC:
 578                 case TG3_APE_LOCK_MEM:
 579                         break;
 580                 default:
 581                         return;
 582         }
 583
 584         off = 4 * locknum;
 585         tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
 586 }
 587
 588 static void tg3_disable_ints(struct tg3 *tp)
 589 {
 590         tw32(TG3PCI_MISC_HOST_CTRL,
 591              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
 592         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
 593 }
 594
 595 static inline void tg3_cond_int(struct tg3 *tp)
 596 {
 597         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 598             (tp->hw_status->status & SD_STATUS_UPDATED))
 599                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
 600         else
 601                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 602                      (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
 603 }
 604
 605 static void tg3_enable_ints(struct tg3 *tp)
 606 {
 607         tp->irq_sync = 0;
 608         wmb();
 609
 610         tw32(TG3PCI_MISC_HOST_CTRL,
 611              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 612         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 613                        (tp->last_tag << 24));
 614         if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
 615                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 616                                (tp->last_tag << 24));
 617         tg3_cond_int(tp);
 618 }
 619
 620 static inline unsigned int tg3_has_work(struct tg3 *tp)
 621 {
 622         struct tg3_hw_status *sblk = tp->hw_status;
 623         unsigned int work_exists = 0;
 624
 625         /* check for phy events */
 626         if (!(tp->tg3_flags &
 627               (TG3_FLAG_USE_LINKCHG_REG |
 628                TG3_FLAG_POLL_SERDES))) {
 629                 if (sblk->status & SD_STATUS_LINK_CHG)
 630                         work_exists = 1;
 631         }
 632         /* check for RX/TX work to do */
 633         if (sblk->idx[0].tx_consumer != tp->tx_cons ||
 634             sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
 635                 work_exists = 1;
 636
 637         return work_exists;
 638 }
 639
 640 /* tg3_restart_ints
 641  *  similar to tg3_enable_ints, but it accurately determines whether there
 642  *  is new work pending and can return without flushing the PIO write
 643  *  which reenables interrupts
 644  */
 645 static void tg3_restart_ints(struct tg3 *tp)
 646 {
 647         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 648                      tp->last_tag << 24);
 649         mmiowb();
 650
 651         /* When doing tagged status, this work check is unnecessary.
 652          * The last_tag we write above tells the chip which piece of
 653          * work we've completed.
 654          */
 655         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 656             tg3_has_work(tp))
 657                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 658                      (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
 659 }
 660
 661 static inline void tg3_netif_stop(struct tg3 *tp)
 662 {
 663         tp->dev->trans_start = jiffies; /* prevent tx timeout */
 664         napi_disable(&tp->napi);
 665         netif_tx_disable(tp->dev);
 666 }
 667
 668 static inline void tg3_netif_start(struct tg3 *tp)
 669 {
 670         netif_wake_queue(tp->dev);
 671         /* NOTE: unconditional netif_wake_queue is only appropriate
 672          * so long as all callers are assured to have free tx slots
 673          * (such as after tg3_init_hw)
 674          */
 675         napi_enable(&tp->napi);
 676         tp->hw_status->status |= SD_STATUS_UPDATED;
 677         tg3_enable_ints(tp);
 678 }
 679
 680 static void tg3_switch_clocks(struct tg3 *tp)
 681 {
 682         u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
 683         u32 orig_clock_ctrl;
 684
 685         if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
 686             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
 687                 return;
 688
 689         orig_clock_ctrl = clock_ctrl;
 690         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
 691                        CLOCK_CTRL_CLKRUN_OENABLE |
 692                        0x1f);
 693         tp->pci_clock_ctrl = clock_ctrl;
 694
 695         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
 696                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
 697                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
 698                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
 699                 }
 700         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
 701                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 702                             clock_ctrl |
 703                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
 704                             40);
 705                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 706                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
 707                             40);
 708         }
 709         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
 710 }
 711
 712 #define PHY_BUSY_LOOPS  5000
 713
 714 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
 715 {
 716         u32 frame_val;
 717         unsigned int loops;
 718         int ret;
 719
 720         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 721                 tw32_f(MAC_MI_MODE,
 722                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 723                 udelay(80);
 724         }
 725
 726         *val = 0x0;
 727
 728         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
 729                       MI_COM_PHY_ADDR_MASK);
 730         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 731                       MI_COM_REG_ADDR_MASK);
 732         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
 733
 734         tw32_f(MAC_MI_COM, frame_val);
 735
 736         loops = PHY_BUSY_LOOPS;
 737         while (loops != 0) {
 738                 udelay(10);
 739                 frame_val = tr32(MAC_MI_COM);
 740
 741                 if ((frame_val & MI_COM_BUSY) == 0) {
 742                         udelay(5);
 743                         frame_val = tr32(MAC_MI_COM);
 744                         break;
 745                 }
 746                 loops -= 1;
 747         }
 748
 749         ret = -EBUSY;
 750         if (loops != 0) {
 751                 *val = frame_val & MI_COM_DATA_MASK;
 752                 ret = 0;
 753         }
 754
 755         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 756                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 757                 udelay(80);
 758         }
 759
 760         return ret;
 761 }
 762
 763 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
 764 {
 765         u32 frame_val;
 766         unsigned int loops;
 767         int ret;
 768
 769         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
 770             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
 771                 return 0;
 772
 773         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 774                 tw32_f(MAC_MI_MODE,
 775                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 776                 udelay(80);
 777         }
 778
 779         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
 780                       MI_COM_PHY_ADDR_MASK);
 781         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 782                       MI_COM_REG_ADDR_MASK);
 783         frame_val |= (val & MI_COM_DATA_MASK);
 784         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
 785
 786         tw32_f(MAC_MI_COM, frame_val);
 787
 788         loops = PHY_BUSY_LOOPS;
 789         while (loops != 0) {
 790                 udelay(10);
 791                 frame_val = tr32(MAC_MI_COM);
 792                 if ((frame_val & MI_COM_BUSY) == 0) {
 793                         udelay(5);
 794                         frame_val = tr32(MAC_MI_COM);
 795                         break;
 796                 }
 797                 loops -= 1;
 798         }
 799
 800         ret = -EBUSY;
 801         if (loops != 0)
 802                 ret = 0;
 803
 804         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 805                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 806                 udelay(80);
 807         }
 808
 809         return ret;
 810 }
 811
 812 static int tg3_bmcr_reset(struct tg3 *tp)
 813 {
 814         u32 phy_control;
 815         int limit, err;
 816
 817         /* OK, reset it, and poll the BMCR_RESET bit until it
 818          * clears or we time out.
 819          */
 820         phy_control = BMCR_RESET;
 821         err = tg3_writephy(tp, MII_BMCR, phy_control);
 822         if (err != 0)
 823                 return -EBUSY;
 824
 825         limit = 5000;
 826         while (limit--) {
 827                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
 828                 if (err != 0)
 829                         return -EBUSY;
 830
 831                 if ((phy_control & BMCR_RESET) == 0) {
 832                         udelay(40);
 833                         break;
 834                 }
 835                 udelay(10);
 836         }
 837         if (limit <= 0)
 838                 return -EBUSY;
 839
 840         return 0;
 841 }
 842
 843 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
 844 {
 845         struct tg3 *tp = (struct tg3 *)bp->priv;
 846         u32 val;
 847
 848         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
 849                 return -EAGAIN;
 850
 851         if (tg3_readphy(tp, reg, &val))
 852                 return -EIO;
 853
 854         return val;
 855 }
 856
 857 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
 858 {
 859         struct tg3 *tp = (struct tg3 *)bp->priv;
 860
 861         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
 862                 return -EAGAIN;
 863
 864         if (tg3_writephy(tp, reg, val))
 865                 return -EIO;
 866
 867         return 0;
 868 }
 869
 870 static int tg3_mdio_reset(struct mii_bus *bp)
 871 {
 872         return 0;
 873 }
 874
 875 static void tg3_mdio_config(struct tg3 *tp)
 876 {
 877         u32 val;
 878
 879         if (tp->mdio_bus.phy_map[PHY_ADDR]->interface !=
 880             PHY_INTERFACE_MODE_RGMII)
 881                 return;
 882
 883         val = tr32(MAC_PHYCFG1) & ~(MAC_PHYCFG1_RGMII_EXT_RX_DEC |
 884                                     MAC_PHYCFG1_RGMII_SND_STAT_EN);
 885         if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE) {
 886                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
 887                         val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
 888                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
 889                         val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
 890         }
 891         tw32(MAC_PHYCFG1, val | MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV);
 892
 893         val = tr32(MAC_PHYCFG2) & ~(MAC_PHYCFG2_INBAND_ENABLE);
 894         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
 895                 val |= MAC_PHYCFG2_INBAND_ENABLE;
 896         tw32(MAC_PHYCFG2, val);
 897
 898         val = tr32(MAC_EXT_RGMII_MODE);
 899         val &= ~(MAC_RGMII_MODE_RX_INT_B |
 900                  MAC_RGMII_MODE_RX_QUALITY |
 901                  MAC_RGMII_MODE_RX_ACTIVITY |
 902                  MAC_RGMII_MODE_RX_ENG_DET |
 903                  MAC_RGMII_MODE_TX_ENABLE |
 904                  MAC_RGMII_MODE_TX_LOWPWR |
 905                  MAC_RGMII_MODE_TX_RESET);
 906         if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE) {
 907                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
 908                         val |= MAC_RGMII_MODE_RX_INT_B |
 909                                MAC_RGMII_MODE_RX_QUALITY |
 910                                MAC_RGMII_MODE_RX_ACTIVITY |
 911                                MAC_RGMII_MODE_RX_ENG_DET;
 912                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
 913                         val |= MAC_RGMII_MODE_TX_ENABLE |
 914                                MAC_RGMII_MODE_TX_LOWPWR |
 915                                MAC_RGMII_MODE_TX_RESET;
 916         }
 917         tw32(MAC_EXT_RGMII_MODE, val);
 918 }
 919
 920 static void tg3_mdio_start(struct tg3 *tp)
 921 {
 922         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
 923                 mutex_lock(&tp->mdio_bus.mdio_lock);
 924                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
 925                 mutex_unlock(&tp->mdio_bus.mdio_lock);
 926         }
 927
 928         tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
 929         tw32_f(MAC_MI_MODE, tp->mi_mode);
 930         udelay(80);
 931
 932         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED)
 933                 tg3_mdio_config(tp);
 934 }
 935
 936 static void tg3_mdio_stop(struct tg3 *tp)
 937 {
 938         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
 939                 mutex_lock(&tp->mdio_bus.mdio_lock);
 940                 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_PAUSED;
 941                 mutex_unlock(&tp->mdio_bus.mdio_lock);
 942         }
 943 }
 944
 945 static int tg3_mdio_init(struct tg3 *tp)
 946 {
 947         int i;
 948         u32 reg;
 949         struct phy_device *phydev;
 950         struct mii_bus *mdio_bus = &tp->mdio_bus;
 951
 952         tg3_mdio_start(tp);
 953
 954         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
 955             (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
 956                 return 0;
 957
 958         memset(mdio_bus, 0, sizeof(*mdio_bus));
 959
 960         mdio_bus->name     = "tg3 mdio bus";
 961         snprintf(mdio_bus->id, MII_BUS_ID_SIZE, "%x",
 962                  (tp->pdev->bus->number << 8) | tp->pdev->devfn);
 963         mdio_bus->priv     = tp;
 964         mdio_bus->dev      = &tp->pdev->dev;
 965         mdio_bus->read     = &tg3_mdio_read;
 966         mdio_bus->write    = &tg3_mdio_write;
 967         mdio_bus->reset    = &tg3_mdio_reset;
 968         mdio_bus->phy_mask = ~(1 << PHY_ADDR);
 969         mdio_bus->irq      = &tp->mdio_irq[0];
 970
 971         for (i = 0; i < PHY_MAX_ADDR; i++)
 972                 mdio_bus->irq[i] = PHY_POLL;
 973
 974         /* The bus registration will look for all the PHYs on the mdio bus.
 975          * Unfortunately, it does not ensure the PHY is powered up before
 976          * accessing the PHY ID registers.  A chip reset is the
 977          * quickest way to bring the device back to an operational state..
 978          */
 979         if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
 980                 tg3_bmcr_reset(tp);
 981
 982         i = mdiobus_register(mdio_bus);
 983         if (i) {
 984                 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
 985                         tp->dev->name, i);
 986                 return i;
 987         }
 988
 989         tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
 990
 991         phydev = tp->mdio_bus.phy_map[PHY_ADDR];
 992
 993         switch (phydev->phy_id) {
 994         case TG3_PHY_ID_BCM50610:
 995                 phydev->interface = PHY_INTERFACE_MODE_RGMII;
 996                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
 997                         phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
 998                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
 999                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1000                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1001                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1002                 break;
1003         case TG3_PHY_ID_BCMAC131:
1004                 phydev->interface = PHY_INTERFACE_MODE_MII;
1005                 break;
1006         }
1007
1008         tg3_mdio_config(tp);
1009
1010         return 0;
1011 }
1012
1013 static void tg3_mdio_fini(struct tg3 *tp)
1014 {
1015         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1016                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1017                 mdiobus_unregister(&tp->mdio_bus);
1018                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
1019         }
1020 }
1021
1022 /* tp->lock is held. */
1023 static inline void tg3_generate_fw_event(struct tg3 *tp)
1024 {
1025         u32 val;
1026
1027         val = tr32(GRC_RX_CPU_EVENT);
1028         val |= GRC_RX_CPU_DRIVER_EVENT;
1029         tw32_f(GRC_RX_CPU_EVENT, val);
1030
1031         tp->last_event_jiffies = jiffies;
1032 }
1033
1034 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1035
1036 /* tp->lock is held. */
1037 static void tg3_wait_for_event_ack(struct tg3 *tp)
1038 {
1039         int i;
1040         unsigned int delay_cnt;
1041         long time_remain;
1042
1043         /* If enough time has passed, no wait is necessary. */
1044         time_remain = (long)(tp->last_event_jiffies + 1 +
1045                       usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1046                       (long)jiffies;
1047         if (time_remain < 0)
1048                 return;
1049
1050         /* Check if we can shorten the wait time. */
1051         delay_cnt = jiffies_to_usecs(time_remain);
1052         if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1053                 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1054         delay_cnt = (delay_cnt >> 3) + 1;
1055
1056         for (i = 0; i < delay_cnt; i++) {
1057                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1058                         break;
1059                 udelay(8);
1060         }
1061 }
1062
1063 /* tp->lock is held. */
1064 static void tg3_ump_link_report(struct tg3 *tp)
1065 {
1066         u32 reg;
1067         u32 val;
1068
1069         if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1070             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
1071                 return;
1072
1073         tg3_wait_for_event_ack(tp);
1074
1075         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1076
1077         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1078
1079         val = 0;
1080         if (!tg3_readphy(tp, MII_BMCR, &reg))
1081                 val = reg << 16;
1082         if (!tg3_readphy(tp, MII_BMSR, &reg))
1083                 val |= (reg & 0xffff);
1084         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1085
1086         val = 0;
1087         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1088                 val = reg << 16;
1089         if (!tg3_readphy(tp, MII_LPA, &reg))
1090                 val |= (reg & 0xffff);
1091         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1092
1093         val = 0;
1094         if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1095                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1096                         val = reg << 16;
1097                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1098                         val |= (reg & 0xffff);
1099         }
1100         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1101
1102         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1103                 val = reg << 16;
1104         else
1105                 val = 0;
1106         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1107
1108         tg3_generate_fw_event(tp);
1109 }
1110
1111 static void tg3_link_report(struct tg3 *tp)
1112 {
1113         if (!netif_carrier_ok(tp->dev)) {
1114                 if (netif_msg_link(tp))
1115                         printk(KERN_INFO PFX "%s: Link is down.\n",
1116                                tp->dev->name);
1117                 tg3_ump_link_report(tp);
1118         } else if (netif_msg_link(tp)) {
1119                 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1120                        tp->dev->name,
1121                        (tp->link_config.active_speed == SPEED_1000 ?
1122                         1000 :
1123                         (tp->link_config.active_speed == SPEED_100 ?
1124                          100 : 10)),
1125                        (tp->link_config.active_duplex == DUPLEX_FULL ?
1126                         "full" : "half"));
1127
1128                 printk(KERN_INFO PFX
1129                        "%s: Flow control is %s for TX and %s for RX.\n",
1130                        tp->dev->name,
1131                        (tp->link_config.active_flowctrl & TG3_FLOW_CTRL_TX) ?
1132                        "on" : "off",
1133                        (tp->link_config.active_flowctrl & TG3_FLOW_CTRL_RX) ?
1134                        "on" : "off");
1135                 tg3_ump_link_report(tp);
1136         }
1137 }
1138
1139 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1140 {
1141         u16 miireg;
1142
1143         if ((flow_ctrl & TG3_FLOW_CTRL_TX) && (flow_ctrl & TG3_FLOW_CTRL_RX))
1144                 miireg = ADVERTISE_PAUSE_CAP;
1145         else if (flow_ctrl & TG3_FLOW_CTRL_TX)
1146                 miireg = ADVERTISE_PAUSE_ASYM;
1147         else if (flow_ctrl & TG3_FLOW_CTRL_RX)
1148                 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1149         else
1150                 miireg = 0;
1151
1152         return miireg;
1153 }
1154
1155 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1156 {
1157         u16 miireg;
1158
1159         if ((flow_ctrl & TG3_FLOW_CTRL_TX) && (flow_ctrl & TG3_FLOW_CTRL_RX))
1160                 miireg = ADVERTISE_1000XPAUSE;
1161         else if (flow_ctrl & TG3_FLOW_CTRL_TX)
1162                 miireg = ADVERTISE_1000XPSE_ASYM;
1163         else if (flow_ctrl & TG3_FLOW_CTRL_RX)
1164                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1165         else
1166                 miireg = 0;
1167
1168         return miireg;
1169 }
1170
1171 static u8 tg3_resolve_flowctrl_1000T(u16 lcladv, u16 rmtadv)
1172 {
1173         u8 cap = 0;
1174
1175         if (lcladv & ADVERTISE_PAUSE_CAP) {
1176                 if (lcladv & ADVERTISE_PAUSE_ASYM) {
1177                         if (rmtadv & LPA_PAUSE_CAP)
1178                                 cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
1179                         else if (rmtadv & LPA_PAUSE_ASYM)
1180                                 cap = TG3_FLOW_CTRL_RX;
1181                 } else {
1182                         if (rmtadv & LPA_PAUSE_CAP)
1183                                 cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
1184                 }
1185         } else if (lcladv & ADVERTISE_PAUSE_ASYM) {
1186                 if ((rmtadv & LPA_PAUSE_CAP) && (rmtadv & LPA_PAUSE_ASYM))
1187                         cap = TG3_FLOW_CTRL_TX;
1188         }
1189
1190         return cap;
1191 }
1192
1193 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1194 {
1195         u8 cap = 0;
1196
1197         if (lcladv & ADVERTISE_1000XPAUSE) {
1198                 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1199                         if (rmtadv & LPA_1000XPAUSE)
1200                                 cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
1201                         else if (rmtadv & LPA_1000XPAUSE_ASYM)
1202                                 cap = TG3_FLOW_CTRL_RX;
1203                 } else {
1204                         if (rmtadv & LPA_1000XPAUSE)
1205                                 cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
1206                 }
1207         } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1208                 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1209                         cap = TG3_FLOW_CTRL_TX;
1210         }
1211
1212         return cap;
1213 }
1214
1215 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1216 {
1217         u8 autoneg;
1218         u8 flowctrl = 0;
1219         u32 old_rx_mode = tp->rx_mode;
1220         u32 old_tx_mode = tp->tx_mode;
1221
1222         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1223                 autoneg = tp->mdio_bus.phy_map[PHY_ADDR]->autoneg;
1224         else
1225                 autoneg = tp->link_config.autoneg;
1226
1227         if (autoneg == AUTONEG_ENABLE &&
1228             (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1229                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1230                         flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1231                 else
1232                         flowctrl = tg3_resolve_flowctrl_1000T(lcladv, rmtadv);
1233         } else
1234                 flowctrl = tp->link_config.flowctrl;
1235
1236         tp->link_config.active_flowctrl = flowctrl;
1237
1238         if (flowctrl & TG3_FLOW_CTRL_RX)
1239                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1240         else
1241                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1242
1243         if (old_rx_mode != tp->rx_mode)
1244                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1245
1246         if (flowctrl & TG3_FLOW_CTRL_TX)
1247                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1248         else
1249                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1250
1251         if (old_tx_mode != tp->tx_mode)
1252                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1253 }
1254
1255 static void tg3_adjust_link(struct net_device *dev)
1256 {
1257         u8 oldflowctrl, linkmesg = 0;
1258         u32 mac_mode, lcl_adv, rmt_adv;
1259         struct tg3 *tp = netdev_priv(dev);
1260         struct phy_device *phydev = tp->mdio_bus.phy_map[PHY_ADDR];
1261
1262         spin_lock(&tp->lock);
1263
1264         mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1265                                     MAC_MODE_HALF_DUPLEX);
1266
1267         oldflowctrl = tp->link_config.active_flowctrl;
1268
1269         if (phydev->link) {
1270                 lcl_adv = 0;
1271                 rmt_adv = 0;
1272
1273                 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1274                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1275                 else
1276                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
1277
1278                 if (phydev->duplex == DUPLEX_HALF)
1279                         mac_mode |= MAC_MODE_HALF_DUPLEX;
1280                 else {
1281                         lcl_adv = tg3_advert_flowctrl_1000T(
1282                                   tp->link_config.flowctrl);
1283
1284                         if (phydev->pause)
1285                                 rmt_adv = LPA_PAUSE_CAP;
1286                         if (phydev->asym_pause)
1287                                 rmt_adv |= LPA_PAUSE_ASYM;
1288                 }
1289
1290                 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1291         } else
1292                 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1293
1294         if (mac_mode != tp->mac_mode) {
1295                 tp->mac_mode = mac_mode;
1296                 tw32_f(MAC_MODE, tp->mac_mode);
1297                 udelay(40);
1298         }
1299
1300         if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1301                 tw32(MAC_TX_LENGTHS,
1302                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1303                       (6 << TX_LENGTHS_IPG_SHIFT) |
1304                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1305         else
1306                 tw32(MAC_TX_LENGTHS,
1307                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1308                       (6 << TX_LENGTHS_IPG_SHIFT) |
1309                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1310
1311         if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1312             (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1313             phydev->speed != tp->link_config.active_speed ||
1314             phydev->duplex != tp->link_config.active_duplex ||
1315             oldflowctrl != tp->link_config.active_flowctrl)
1316             linkmesg = 1;
1317
1318         tp->link_config.active_speed = phydev->speed;
1319         tp->link_config.active_duplex = phydev->duplex;
1320
1321         spin_unlock(&tp->lock);
1322
1323         if (linkmesg)
1324                 tg3_link_report(tp);
1325 }
1326
1327 static int tg3_phy_init(struct tg3 *tp)
1328 {
1329         struct phy_device *phydev;
1330
1331         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1332                 return 0;
1333
1334         /* Bring the PHY back to a known state. */
1335         tg3_bmcr_reset(tp);
1336
1337         phydev = tp->mdio_bus.phy_map[PHY_ADDR];
1338
1339         /* Attach the MAC to the PHY. */
1340         phydev = phy_connect(tp->dev, phydev->dev.bus_id, tg3_adjust_link,
1341                              phydev->dev_flags, phydev->interface);
1342         if (IS_ERR(phydev)) {
1343                 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1344                 return PTR_ERR(phydev);
1345         }
1346
1347         tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
1348
1349         /* Mask with MAC supported features. */
1350         phydev->supported &= (PHY_GBIT_FEATURES |
1351                               SUPPORTED_Pause |
1352                               SUPPORTED_Asym_Pause);
1353
1354         phydev->advertising = phydev->supported;
1355
1356         printk(KERN_INFO
1357                "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
1358                tp->dev->name, phydev->drv->name, phydev->dev.bus_id);
1359
1360         return 0;
1361 }
1362
1363 static void tg3_phy_start(struct tg3 *tp)
1364 {
1365         struct phy_device *phydev;
1366
1367         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1368                 return;
1369
1370         phydev = tp->mdio_bus.phy_map[PHY_ADDR];
1371
1372         if (tp->link_config.phy_is_low_power) {
1373                 tp->link_config.phy_is_low_power = 0;
1374                 phydev->speed = tp->link_config.orig_speed;
1375                 phydev->duplex = tp->link_config.orig_duplex;
1376                 phydev->autoneg = tp->link_config.orig_autoneg;
1377                 phydev->advertising = tp->link_config.orig_advertising;
1378         }
1379
1380         phy_start(phydev);
1381
1382         phy_start_aneg(phydev);
1383 }
1384
1385 static void tg3_phy_stop(struct tg3 *tp)
1386 {
1387         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1388                 return;
1389
1390         phy_stop(tp->mdio_bus.phy_map[PHY_ADDR]);
1391 }
1392
1393 static void tg3_phy_fini(struct tg3 *tp)
1394 {
1395         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
1396                 phy_disconnect(tp->mdio_bus.phy_map[PHY_ADDR]);
1397                 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1398         }
1399 }
1400
1401 static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1402 {
1403         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1404         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1405 }
1406
1407 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1408 {
1409         u32 phy;
1410
1411         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1412             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1413                 return;
1414
1415         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1416                 u32 ephy;
1417
1418                 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &ephy)) {
1419                         tg3_writephy(tp, MII_TG3_EPHY_TEST,
1420                                      ephy | MII_TG3_EPHY_SHADOW_EN);
1421                         if (!tg3_readphy(tp, MII_TG3_EPHYTST_MISCCTRL, &phy)) {
1422                                 if (enable)
1423                                         phy |= MII_TG3_EPHYTST_MISCCTRL_MDIX;
1424                                 else
1425                                         phy &= ~MII_TG3_EPHYTST_MISCCTRL_MDIX;
1426                                 tg3_writephy(tp, MII_TG3_EPHYTST_MISCCTRL, phy);
1427                         }
1428                         tg3_writephy(tp, MII_TG3_EPHY_TEST, ephy);
1429                 }
1430         } else {
1431                 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1432                       MII_TG3_AUXCTL_SHDWSEL_MISC;
1433                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1434                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1435                         if (enable)
1436                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1437                         else
1438                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1439                         phy |= MII_TG3_AUXCTL_MISC_WREN;
1440                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1441                 }
1442         }
1443 }
1444
1445 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1446 {
1447         u32 val;
1448
1449         if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1450                 return;
1451
1452         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1453             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1454                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1455                              (val | (1 << 15) | (1 << 4)));
1456 }
1457
1458 static void tg3_phy_apply_otp(struct tg3 *tp)
1459 {
1460         u32 otp, phy;
1461
1462         if (!tp->phy_otp)
1463                 return;
1464
1465         otp = tp->phy_otp;
1466
1467         /* Enable SM_DSP clock and tx 6dB coding. */
1468         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1469               MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1470               MII_TG3_AUXCTL_ACTL_TX_6DB;
1471         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1472
1473         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1474         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1475         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1476
1477         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1478               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1479         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1480
1481         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1482         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1483         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1484
1485         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1486         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1487
1488         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1489         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1490
1491         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1492               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1493         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1494
1495         /* Turn off SM_DSP clock. */
1496         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1497               MII_TG3_AUXCTL_ACTL_TX_6DB;
1498         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1499 }
1500
1501 static int tg3_wait_macro_done(struct tg3 *tp)
1502 {
1503         int limit = 100;
1504
1505         while (limit--) {
1506                 u32 tmp32;
1507
1508                 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1509                         if ((tmp32 & 0x1000) == 0)
1510                                 break;
1511                 }
1512         }
1513         if (limit <= 0)
1514                 return -EBUSY;
1515
1516         return 0;
1517 }
1518
1519 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1520 {
1521         static const u32 test_pat[4][6] = {
1522         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1523         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1524         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1525         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1526         };
1527         int chan;
1528
1529         for (chan = 0; chan < 4; chan++) {
1530                 int i;
1531
1532                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1533                              (chan * 0x2000) | 0x0200);
1534                 tg3_writephy(tp, 0x16, 0x0002);
1535
1536                 for (i = 0; i < 6; i++)
1537                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1538                                      test_pat[chan][i]);
1539
1540                 tg3_writephy(tp, 0x16, 0x0202);
1541                 if (tg3_wait_macro_done(tp)) {
1542                         *resetp = 1;
1543                         return -EBUSY;
1544                 }
1545
1546                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1547                              (chan * 0x2000) | 0x0200);
1548                 tg3_writephy(tp, 0x16, 0x0082);
1549                 if (tg3_wait_macro_done(tp)) {
1550                         *resetp = 1;
1551                         return -EBUSY;
1552                 }
1553
1554                 tg3_writephy(tp, 0x16, 0x0802);
1555                 if (tg3_wait_macro_done(tp)) {
1556                         *resetp = 1;
1557                         return -EBUSY;
1558                 }
1559
1560                 for (i = 0; i < 6; i += 2) {
1561                         u32 low, high;
1562
1563                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1564                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1565                             tg3_wait_macro_done(tp)) {
1566                                 *resetp = 1;
1567                                 return -EBUSY;
1568                         }
1569                         low &= 0x7fff;
1570                         high &= 0x000f;
1571                         if (low != test_pat[chan][i] ||
1572                             high != test_pat[chan][i+1]) {
1573                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1574                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1575                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1576
1577                                 return -EBUSY;
1578                         }
1579                 }
1580         }
1581
1582         return 0;
1583 }
1584
1585 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1586 {
1587         int chan;
1588
1589         for (chan = 0; chan < 4; chan++) {
1590                 int i;
1591
1592                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1593                              (chan * 0x2000) | 0x0200);
1594                 tg3_writephy(tp, 0x16, 0x0002);
1595                 for (i = 0; i < 6; i++)
1596                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1597                 tg3_writephy(tp, 0x16, 0x0202);
1598                 if (tg3_wait_macro_done(tp))
1599                         return -EBUSY;
1600         }
1601
1602         return 0;
1603 }
1604
1605 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1606 {
1607         u32 reg32, phy9_orig;
1608         int retries, do_phy_reset, err;
1609
1610         retries = 10;
1611         do_phy_reset = 1;
1612         do {
1613                 if (do_phy_reset) {
1614                         err = tg3_bmcr_reset(tp);
1615                         if (err)
1616                                 return err;
1617                         do_phy_reset = 0;
1618                 }
1619
1620                 /* Disable transmitter and interrupt.  */
1621                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1622                         continue;
1623
1624                 reg32 |= 0x3000;
1625                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1626
1627                 /* Set full-duplex, 1000 mbps.  */
1628                 tg3_writephy(tp, MII_BMCR,
1629                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1630
1631                 /* Set to master mode.  */
1632                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1633                         continue;
1634
1635                 tg3_writephy(tp, MII_TG3_CTRL,
1636                              (MII_TG3_CTRL_AS_MASTER |
1637                               MII_TG3_CTRL_ENABLE_AS_MASTER));
1638
1639                 /* Enable SM_DSP_CLOCK and 6dB.  */
1640                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1641
1642                 /* Block the PHY control access.  */
1643                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1644                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1645
1646                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1647                 if (!err)
1648                         break;
1649         } while (--retries);
1650
1651         err = tg3_phy_reset_chanpat(tp);
1652         if (err)
1653                 return err;
1654
1655         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1656         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1657
1658         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1659         tg3_writephy(tp, 0x16, 0x0000);
1660
1661         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1662             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1663                 /* Set Extended packet length bit for jumbo frames */
1664                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1665         }
1666         else {
1667                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1668         }
1669
1670         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1671
1672         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1673                 reg32 &= ~0x3000;
1674                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1675         } else if (!err)
1676                 err = -EBUSY;
1677
1678         return err;
1679 }
1680
1681 /* This will reset the tigon3 PHY if there is no valid
1682  * link unless the FORCE argument is non-zero.
1683  */
1684 static int tg3_phy_reset(struct tg3 *tp)
1685 {
1686         u32 cpmuctrl;
1687         u32 phy_status;
1688         int err;
1689
1690         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1691                 u32 val;
1692
1693                 val = tr32(GRC_MISC_CFG);
1694                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1695                 udelay(40);
1696         }
1697         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
1698         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1699         if (err != 0)
1700                 return -EBUSY;
1701
1702         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1703                 netif_carrier_off(tp->dev);
1704                 tg3_link_report(tp);
1705         }
1706
1707         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1708             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1709             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1710                 err = tg3_phy_reset_5703_4_5(tp);
1711                 if (err)
1712                         return err;
1713                 goto out;
1714         }
1715
1716         cpmuctrl = 0;
1717         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1718             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1719                 cpmuctrl = tr32(TG3_CPMU_CTRL);
1720                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1721                         tw32(TG3_CPMU_CTRL,
1722                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1723         }
1724
1725         err = tg3_bmcr_reset(tp);
1726         if (err)
1727                 return err;
1728
1729         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1730                 u32 phy;
1731
1732                 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1733                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1734
1735                 tw32(TG3_CPMU_CTRL, cpmuctrl);
1736         }
1737
1738         if (tp->tg3_flags3 & TG3_FLG3_5761_5784_AX_FIXES) {
1739                 u32 val;
1740
1741                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1742                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1743                     CPMU_LSPD_1000MB_MACCLK_12_5) {
1744                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1745                         udelay(40);
1746                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1747                 }
1748
1749                 /* Disable GPHY autopowerdown. */
1750                 tg3_writephy(tp, MII_TG3_MISC_SHDW,
1751                              MII_TG3_MISC_SHDW_WREN |
1752                              MII_TG3_MISC_SHDW_APD_SEL |
1753                              MII_TG3_MISC_SHDW_APD_WKTM_84MS);
1754         }
1755
1756         tg3_phy_apply_otp(tp);
1757
1758 out:
1759         if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1760                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1761                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1762                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1763                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1764                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1765                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1766         }
1767         if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1768                 tg3_writephy(tp, 0x1c, 0x8d68);
1769                 tg3_writephy(tp, 0x1c, 0x8d68);
1770         }
1771         if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1772                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1773                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1774                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1775                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1776                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1777                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1778                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1779                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1780         }
1781         else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1782                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1783                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1784                 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1785                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1786                         tg3_writephy(tp, MII_TG3_TEST1,
1787                                      MII_TG3_TEST1_TRIM_EN | 0x4);
1788                 } else
1789                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1790                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1791         }
1792         /* Set Extended packet length bit (bit 14) on all chips that */
1793         /* support jumbo frames */
1794         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1795                 /* Cannot do read-modify-write on 5401 */
1796                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1797         } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1798                 u32 phy_reg;
1799
1800                 /* Set bit 14 with read-modify-write to preserve other bits */
1801                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1802                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1803                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1804         }
1805
1806         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1807          * jumbo frames transmission.
1808          */
1809         if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1810                 u32 phy_reg;
1811
1812                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1813                     tg3_writephy(tp, MII_TG3_EXT_CTRL,
1814                                  phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1815         }
1816
1817         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1818                 /* adjust output voltage */
1819                 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x12);
1820         }
1821
1822         tg3_phy_toggle_automdix(tp, 1);
1823         tg3_phy_set_wirespeed(tp);
1824         return 0;
1825 }
1826
1827 static void tg3_frob_aux_power(struct tg3 *tp)
1828 {
1829         struct tg3 *tp_peer = tp;
1830
1831         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1832                 return;
1833
1834         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1835             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1836                 struct net_device *dev_peer;
1837
1838                 dev_peer = pci_get_drvdata(tp->pdev_peer);
1839                 /* remove_one() may have been run on the peer. */
1840                 if (!dev_peer)
1841                         tp_peer = tp;
1842                 else
1843                         tp_peer = netdev_priv(dev_peer);
1844         }
1845
1846         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1847             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1848             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1849             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1850                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1851                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1852                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1853                                     (GRC_LCLCTRL_GPIO_OE0 |
1854                                      GRC_LCLCTRL_GPIO_OE1 |
1855                                      GRC_LCLCTRL_GPIO_OE2 |
1856                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
1857                                      GRC_LCLCTRL_GPIO_OUTPUT1),
1858                                     100);
1859                 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761) {
1860                         /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
1861                         u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
1862                                              GRC_LCLCTRL_GPIO_OE1 |
1863                                              GRC_LCLCTRL_GPIO_OE2 |
1864                                              GRC_LCLCTRL_GPIO_OUTPUT0 |
1865                                              GRC_LCLCTRL_GPIO_OUTPUT1 |
1866                                              tp->grc_local_ctrl;
1867                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1868
1869                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
1870                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1871
1872                         grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
1873                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1874                 } else {
1875                         u32 no_gpio2;
1876                         u32 grc_local_ctrl = 0;
1877
1878                         if (tp_peer != tp &&
1879                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1880                                 return;
1881
1882                         /* Workaround to prevent overdrawing Amps. */
1883                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1884                             ASIC_REV_5714) {
1885                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
1886                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1887                                             grc_local_ctrl, 100);
1888                         }
1889
1890                         /* On 5753 and variants, GPIO2 cannot be used. */
1891                         no_gpio2 = tp->nic_sram_data_cfg &
1892                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
1893
1894                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1895                                          GRC_LCLCTRL_GPIO_OE1 |
1896                                          GRC_LCLCTRL_GPIO_OE2 |
1897                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
1898                                          GRC_LCLCTRL_GPIO_OUTPUT2;
1899                         if (no_gpio2) {
1900                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
1901                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
1902                         }
1903                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1904                                                     grc_local_ctrl, 100);
1905
1906                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
1907
1908                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1909                                                     grc_local_ctrl, 100);
1910
1911                         if (!no_gpio2) {
1912                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
1913                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1914                                             grc_local_ctrl, 100);
1915                         }
1916                 }
1917         } else {
1918                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
1919                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
1920                         if (tp_peer != tp &&
1921                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1922                                 return;
1923
1924                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1925                                     (GRC_LCLCTRL_GPIO_OE1 |
1926                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1927
1928                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1929                                     GRC_LCLCTRL_GPIO_OE1, 100);
1930
1931                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1932                                     (GRC_LCLCTRL_GPIO_OE1 |
1933                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1934                 }
1935         }
1936 }
1937
1938 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
1939 {
1940         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
1941                 return 1;
1942         else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
1943                 if (speed != SPEED_10)
1944                         return 1;
1945         } else if (speed == SPEED_10)
1946                 return 1;
1947
1948         return 0;
1949 }
1950
1951 static int tg3_setup_phy(struct tg3 *, int);
1952
1953 #define RESET_KIND_SHUTDOWN     0
1954 #define RESET_KIND_INIT         1
1955 #define RESET_KIND_SUSPEND      2
1956
1957 static void tg3_write_sig_post_reset(struct tg3 *, int);
1958 static int tg3_halt_cpu(struct tg3 *, u32);
1959 static int tg3_nvram_lock(struct tg3 *);
1960 static void tg3_nvram_unlock(struct tg3 *);
1961
1962 static void tg3_power_down_phy(struct tg3 *tp)
1963 {
1964         u32 val;
1965
1966         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
1967                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1968                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
1969                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
1970
1971                         sg_dig_ctrl |=
1972                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
1973                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
1974                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
1975                 }
1976                 return;
1977         }
1978
1979         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1980                 tg3_bmcr_reset(tp);
1981                 val = tr32(GRC_MISC_CFG);
1982                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
1983                 udelay(40);
1984                 return;
1985         } else if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
1986                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1987                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
1988                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2);
1989         }
1990
1991         /* The PHY should not be powered down on some chips because
1992          * of bugs.
1993          */
1994         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1995             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1996             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
1997              (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
1998                 return;
1999
2000         if (tp->tg3_flags3 & TG3_FLG3_5761_5784_AX_FIXES) {
2001                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2002                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2003                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2004                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2005         }
2006
2007         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2008 }
2009
2010 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2011 {
2012         u32 misc_host_ctrl;
2013
2014         /* Make sure register accesses (indirect or otherwise)
2015          * will function correctly.
2016          */
2017         pci_write_config_dword(tp->pdev,
2018                                TG3PCI_MISC_HOST_CTRL,
2019                                tp->misc_host_ctrl);
2020
2021         switch (state) {
2022         case PCI_D0:
2023                 pci_enable_wake(tp->pdev, state, false);
2024                 pci_set_power_state(tp->pdev, PCI_D0);
2025
2026                 /* Switch out of Vaux if it is a NIC */
2027                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2028                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2029
2030                 return 0;
2031
2032         case PCI_D1:
2033         case PCI_D2:
2034         case PCI_D3hot:
2035                 break;
2036
2037         default:
2038                 printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n",
2039                         tp->dev->name, state);
2040                 return -EINVAL;
2041         }
2042         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2043         tw32(TG3PCI_MISC_HOST_CTRL,
2044              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2045
2046         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2047                 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2048                     !tp->link_config.phy_is_low_power) {
2049                         struct phy_device *phydev;
2050                         u32 advertising;
2051
2052                         phydev = tp->mdio_bus.phy_map[PHY_ADDR];
2053
2054                         tp->link_config.phy_is_low_power = 1;
2055
2056                         tp->link_config.orig_speed = phydev->speed;
2057                         tp->link_config.orig_duplex = phydev->duplex;
2058                         tp->link_config.orig_autoneg = phydev->autoneg;
2059                         tp->link_config.orig_advertising = phydev->advertising;
2060
2061                         advertising = ADVERTISED_TP |
2062                                       ADVERTISED_Pause |
2063                                       ADVERTISED_Autoneg |
2064                                       ADVERTISED_10baseT_Half;
2065
2066                         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2067                             (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)) {
2068                                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2069                                         advertising |=
2070                                                 ADVERTISED_100baseT_Half |
2071                                                 ADVERTISED_100baseT_Full |
2072                                                 ADVERTISED_10baseT_Full;
2073                                 else
2074                                         advertising |= ADVERTISED_10baseT_Full;
2075                         }
2076
2077                         phydev->advertising = advertising;
2078
2079                         phy_start_aneg(phydev);
2080                 }
2081         } else {
2082                 if (tp->link_config.phy_is_low_power == 0) {
2083                         tp->link_config.phy_is_low_power = 1;
2084                         tp->link_config.orig_speed = tp->link_config.speed;
2085                         tp->link_config.orig_duplex = tp->link_config.duplex;
2086                         tp->link_config.orig_autoneg = tp->link_config.autoneg;
2087                 }
2088
2089                 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2090                         tp->link_config.speed = SPEED_10;
2091                         tp->link_config.duplex = DUPLEX_HALF;
2092                         tp->link_config.autoneg = AUTONEG_ENABLE;
2093                         tg3_setup_phy(tp, 0);
2094                 }
2095         }
2096
2097         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2098                 u32 val;
2099
2100                 val = tr32(GRC_VCPU_EXT_CTRL);
2101                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2102         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2103                 int i;
2104                 u32 val;
2105
2106                 for (i = 0; i < 200; i++) {
2107                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2108                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2109                                 break;
2110                         msleep(1);
2111                 }
2112         }
2113         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2114                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2115                                                      WOL_DRV_STATE_SHUTDOWN |
2116                                                      WOL_DRV_WOL |
2117                                                      WOL_SET_MAGIC_PKT);
2118
2119         if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) {
2120                 u32 mac_mode;
2121
2122                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
2123                         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
2124                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2125                                 udelay(40);
2126                         }
2127
2128                         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2129                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
2130                         else
2131                                 mac_mode = MAC_MODE_PORT_MODE_MII;
2132
2133                         mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2134                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2135                             ASIC_REV_5700) {
2136                                 u32 speed = (tp->tg3_flags &
2137                                              TG3_FLAG_WOL_SPEED_100MB) ?
2138                                              SPEED_100 : SPEED_10;
2139                                 if (tg3_5700_link_polarity(tp, speed))
2140                                         mac_mode |= MAC_MODE_LINK_POLARITY;
2141                                 else
2142                                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
2143                         }
2144                 } else {
2145                         mac_mode = MAC_MODE_PORT_MODE_TBI;
2146                 }
2147
2148                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2149                         tw32(MAC_LED_CTRL, tp->led_ctrl);
2150
2151                 if (pci_pme_capable(tp->pdev, state) &&
2152                      (tp->tg3_flags & TG3_FLAG_WOL_ENABLE))
2153                         mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2154
2155                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2156                         mac_mode |= tp->mac_mode &
2157                                     (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2158                         if (mac_mode & MAC_MODE_APE_TX_EN)
2159                                 mac_mode |= MAC_MODE_TDE_ENABLE;
2160                 }
2161
2162                 tw32_f(MAC_MODE, mac_mode);
2163                 udelay(100);
2164
2165                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2166                 udelay(10);
2167         }
2168
2169         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2170             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2171              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2172                 u32 base_val;
2173
2174                 base_val = tp->pci_clock_ctrl;
2175                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2176                              CLOCK_CTRL_TXCLK_DISABLE);
2177
2178                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2179                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
2180         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2181                    (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2182                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2183                 /* do nothing */
2184         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2185                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2186                 u32 newbits1, newbits2;
2187
2188                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2189                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2190                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2191                                     CLOCK_CTRL_TXCLK_DISABLE |
2192                                     CLOCK_CTRL_ALTCLK);
2193                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2194                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2195                         newbits1 = CLOCK_CTRL_625_CORE;
2196                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2197                 } else {
2198                         newbits1 = CLOCK_CTRL_ALTCLK;
2199                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2200                 }
2201
2202                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2203                             40);
2204
2205                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2206                             40);
2207
2208                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2209                         u32 newbits3;
2210
2211                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2212                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2213                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2214                                             CLOCK_CTRL_TXCLK_DISABLE |
2215                                             CLOCK_CTRL_44MHZ_CORE);
2216                         } else {
2217                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2218                         }
2219
2220                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
2221                                     tp->pci_clock_ctrl | newbits3, 40);
2222                 }
2223         }
2224
2225         if (!(tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
2226             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
2227             !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
2228                 tg3_power_down_phy(tp);
2229
2230         tg3_frob_aux_power(tp);
2231
2232         /* Workaround for unstable PLL clock */
2233         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2234             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2235                 u32 val = tr32(0x7d00);
2236
2237                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2238                 tw32(0x7d00, val);
2239                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2240                         int err;
2241
2242                         err = tg3_nvram_lock(tp);
2243                         tg3_halt_cpu(tp, RX_CPU_BASE);
2244                         if (!err)
2245                                 tg3_nvram_unlock(tp);
2246                 }
2247         }
2248
2249         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2250
2251         if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)
2252                 pci_enable_wake(tp->pdev, state, true);
2253
2254         /* Finally, set the new power state. */
2255         pci_set_power_state(tp->pdev, state);
2256
2257         return 0;
2258 }
2259
2260 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2261 {
2262         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2263         case MII_TG3_AUX_STAT_10HALF:
2264                 *speed = SPEED_10;
2265                 *duplex = DUPLEX_HALF;
2266                 break;
2267
2268         case MII_TG3_AUX_STAT_10FULL:
2269                 *speed = SPEED_10;
2270                 *duplex = DUPLEX_FULL;
2271                 break;
2272
2273         case MII_TG3_AUX_STAT_100HALF:
2274                 *speed = SPEED_100;
2275                 *duplex = DUPLEX_HALF;
2276                 break;
2277
2278         case MII_TG3_AUX_STAT_100FULL:
2279                 *speed = SPEED_100;
2280                 *duplex = DUPLEX_FULL;
2281                 break;
2282
2283         case MII_TG3_AUX_STAT_1000HALF:
2284                 *speed = SPEED_1000;
2285                 *duplex = DUPLEX_HALF;
2286                 break;
2287
2288         case MII_TG3_AUX_STAT_1000FULL:
2289                 *speed = SPEED_1000;
2290                 *duplex = DUPLEX_FULL;
2291                 break;
2292
2293         default:
2294                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2295                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2296                                  SPEED_10;
2297                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2298                                   DUPLEX_HALF;
2299                         break;
2300                 }
2301                 *speed = SPEED_INVALID;
2302                 *duplex = DUPLEX_INVALID;
2303                 break;
2304         }
2305 }
2306
2307 static void tg3_phy_copper_begin(struct tg3 *tp)
2308 {
2309         u32 new_adv;
2310         int i;
2311
2312         if (tp->link_config.phy_is_low_power) {
2313                 /* Entering low power mode.  Disable gigabit and
2314                  * 100baseT advertisements.
2315                  */
2316                 tg3_writephy(tp, MII_TG3_CTRL, 0);
2317
2318                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2319                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2320                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2321                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2322
2323                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2324         } else if (tp->link_config.speed == SPEED_INVALID) {
2325                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2326                         tp->link_config.advertising &=
2327                                 ~(ADVERTISED_1000baseT_Half |
2328                                   ADVERTISED_1000baseT_Full);
2329
2330                 new_adv = ADVERTISE_CSMA;
2331                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2332                         new_adv |= ADVERTISE_10HALF;
2333                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2334                         new_adv |= ADVERTISE_10FULL;
2335                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2336                         new_adv |= ADVERTISE_100HALF;
2337                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2338                         new_adv |= ADVERTISE_100FULL;
2339
2340                 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2341
2342                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2343
2344                 if (tp->link_config.advertising &
2345                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2346                         new_adv = 0;
2347                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2348                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2349                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2350                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2351                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2352                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2353                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2354                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2355                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2356                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2357                 } else {
2358                         tg3_writephy(tp, MII_TG3_CTRL, 0);
2359                 }
2360         } else {
2361                 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2362                 new_adv |= ADVERTISE_CSMA;
2363
2364                 /* Asking for a specific link mode. */
2365                 if (tp->link_config.speed == SPEED_1000) {
2366                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2367
2368                         if (tp->link_config.duplex == DUPLEX_FULL)
2369                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2370                         else
2371                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2372                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2373                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2374                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2375                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2376                 } else {
2377                         if (tp->link_config.speed == SPEED_100) {
2378                                 if (tp->link_config.duplex == DUPLEX_FULL)
2379                                         new_adv |= ADVERTISE_100FULL;
2380                                 else
2381                                         new_adv |= ADVERTISE_100HALF;
2382                         } else {
2383                                 if (tp->link_config.duplex == DUPLEX_FULL)
2384                                         new_adv |= ADVERTISE_10FULL;
2385                                 else
2386                                         new_adv |= ADVERTISE_10HALF;
2387                         }
2388                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2389
2390                         new_adv = 0;
2391                 }
2392
2393                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2394         }
2395
2396         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2397             tp->link_config.speed != SPEED_INVALID) {
2398                 u32 bmcr, orig_bmcr;
2399
2400                 tp->link_config.active_speed = tp->link_config.speed;
2401                 tp->link_config.active_duplex = tp->link_config.duplex;
2402
2403                 bmcr = 0;
2404                 switch (tp->link_config.speed) {
2405                 default:
2406                 case SPEED_10:
2407                         break;
2408
2409                 case SPEED_100:
2410                         bmcr |= BMCR_SPEED100;
2411                         break;
2412
2413                 case SPEED_1000:
2414                         bmcr |= TG3_BMCR_SPEED1000;
2415                         break;
2416                 }
2417
2418                 if (tp->link_config.duplex == DUPLEX_FULL)
2419                         bmcr |= BMCR_FULLDPLX;
2420
2421                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2422                     (bmcr != orig_bmcr)) {
2423                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2424                         for (i = 0; i < 1500; i++) {
2425                                 u32 tmp;
2426
2427                                 udelay(10);
2428                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2429                                     tg3_readphy(tp, MII_BMSR, &tmp))
2430                                         continue;
2431                                 if (!(tmp & BMSR_LSTATUS)) {
2432                                         udelay(40);
2433                                         break;
2434                                 }
2435                         }
2436                         tg3_writephy(tp, MII_BMCR, bmcr);
2437                         udelay(40);
2438                 }
2439         } else {
2440                 tg3_writephy(tp, MII_BMCR,
2441                              BMCR_ANENABLE | BMCR_ANRESTART);
2442         }
2443 }
2444
2445 static int tg3_init_5401phy_dsp(struct tg3 *tp)
2446 {
2447         int err;
2448
2449         /* Turn off tap power management. */
2450         /* Set Extended packet length bit */
2451         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2452
2453         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2454         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2455
2456         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2457         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2458
2459         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2460         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2461
2462         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2463         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2464
2465         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2466         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2467
2468         udelay(40);
2469
2470         return err;
2471 }
2472
2473 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
2474 {
2475         u32 adv_reg, all_mask = 0;
2476
2477         if (mask & ADVERTISED_10baseT_Half)
2478                 all_mask |= ADVERTISE_10HALF;
2479         if (mask & ADVERTISED_10baseT_Full)
2480                 all_mask |= ADVERTISE_10FULL;
2481         if (mask & ADVERTISED_100baseT_Half)
2482                 all_mask |= ADVERTISE_100HALF;
2483         if (mask & ADVERTISED_100baseT_Full)
2484                 all_mask |= ADVERTISE_100FULL;
2485
2486         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2487                 return 0;
2488
2489         if ((adv_reg & all_mask) != all_mask)
2490                 return 0;
2491         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2492                 u32 tg3_ctrl;
2493
2494                 all_mask = 0;
2495                 if (mask & ADVERTISED_1000baseT_Half)
2496                         all_mask |= ADVERTISE_1000HALF;
2497                 if (mask & ADVERTISED_1000baseT_Full)
2498                         all_mask |= ADVERTISE_1000FULL;
2499
2500                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2501                         return 0;
2502
2503                 if ((tg3_ctrl & all_mask) != all_mask)
2504                         return 0;
2505         }
2506         return 1;
2507 }
2508
2509 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2510 {
2511         u32 curadv, reqadv;
2512
2513         if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2514                 return 1;
2515
2516         curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2517         reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2518
2519         if (tp->link_config.active_duplex == DUPLEX_FULL) {
2520                 if (curadv != reqadv)
2521                         return 0;
2522
2523                 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
2524                         tg3_readphy(tp, MII_LPA, rmtadv);
2525         } else {
2526                 /* Reprogram the advertisement register, even if it
2527                  * does not affect the current link.  If the link
2528                  * gets renegotiated in the future, we can save an
2529                  * additional renegotiation cycle by advertising
2530                  * it correctly in the first place.
2531                  */
2532                 if (curadv != reqadv) {
2533                         *lcladv &= ~(ADVERTISE_PAUSE_CAP |
2534                                      ADVERTISE_PAUSE_ASYM);
2535                         tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
2536                 }
2537         }
2538
2539         return 1;
2540 }
2541
2542 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
2543 {
2544         int current_link_up;
2545         u32 bmsr, dummy;
2546         u32 lcl_adv, rmt_adv;
2547         u16 current_speed;
2548         u8 current_duplex;
2549         int i, err;
2550
2551         tw32(MAC_EVENT, 0);
2552
2553         tw32_f(MAC_STATUS,
2554              (MAC_STATUS_SYNC_CHANGED |
2555               MAC_STATUS_CFG_CHANGED |
2556               MAC_STATUS_MI_COMPLETION |
2557               MAC_STATUS_LNKSTATE_CHANGED));
2558         udelay(40);
2559
2560         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
2561                 tw32_f(MAC_MI_MODE,
2562                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
2563                 udelay(80);
2564         }
2565
2566         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
2567
2568         /* Some third-party PHYs need to be reset on link going
2569          * down.
2570          */
2571         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2572              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2573              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
2574             netif_carrier_ok(tp->dev)) {
2575                 tg3_readphy(tp, MII_BMSR, &bmsr);
2576                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2577                     !(bmsr & BMSR_LSTATUS))
2578                         force_reset = 1;
2579         }
2580         if (force_reset)
2581                 tg3_phy_reset(tp);
2582
2583         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
2584                 tg3_readphy(tp, MII_BMSR, &bmsr);
2585                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
2586                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
2587                         bmsr = 0;
2588
2589                 if (!(bmsr & BMSR_LSTATUS)) {
2590                         err = tg3_init_5401phy_dsp(tp);
2591                         if (err)
2592                                 return err;
2593
2594                         tg3_readphy(tp, MII_BMSR, &bmsr);
2595                         for (i = 0; i < 1000; i++) {
2596                                 udelay(10);
2597                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2598                                     (bmsr & BMSR_LSTATUS)) {
2599                                         udelay(40);
2600                                         break;
2601                                 }
2602                         }
2603
2604                         if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
2605                             !(bmsr & BMSR_LSTATUS) &&
2606                             tp->link_config.active_speed == SPEED_1000) {
2607                                 err = tg3_phy_reset(tp);
2608                                 if (!err)
2609                                         err = tg3_init_5401phy_dsp(tp);
2610                                 if (err)
2611                                         return err;
2612                         }
2613                 }
2614         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2615                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
2616                 /* 5701 {A0,B0} CRC bug workaround */
2617                 tg3_writephy(tp, 0x15, 0x0a75);
2618                 tg3_writephy(tp, 0x1c, 0x8c68);
2619                 tg3_writephy(tp, 0x1c, 0x8d68);
2620                 tg3_writephy(tp, 0x1c, 0x8c68);
2621         }
2622
2623         /* Clear pending interrupts... */
2624         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
2625         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
2626
2627         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
2628                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
2629         else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
2630                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
2631
2632         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2633             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2634                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
2635                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
2636                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
2637                 else
2638                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
2639         }
2640
2641         current_link_up = 0;
2642         current_speed = SPEED_INVALID;
2643         current_duplex = DUPLEX_INVALID;
2644
2645         if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
2646                 u32 val;
2647
2648                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
2649                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
2650                 if (!(val & (1 << 10))) {
2651                         val |= (1 << 10);
2652                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
2653                         goto relink;
2654                 }
2655         }
2656
2657         bmsr = 0;
2658         for (i = 0; i < 100; i++) {
2659                 tg3_readphy(tp, MII_BMSR, &bmsr);
2660                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2661                     (bmsr & BMSR_LSTATUS))
2662                         break;
2663                 udelay(40);
2664         }
2665
2666         if (bmsr & BMSR_LSTATUS) {
2667                 u32 aux_stat, bmcr;
2668
2669                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
2670                 for (i = 0; i < 2000; i++) {
2671                         udelay(10);
2672                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
2673                             aux_stat)
2674                                 break;
2675                 }
2676
2677                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
2678                                              &current_speed,
2679                                              &current_duplex);
2680
2681                 bmcr = 0;
2682                 for (i = 0; i < 200; i++) {
2683                         tg3_readphy(tp, MII_BMCR, &bmcr);
2684                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
2685                                 continue;
2686                         if (bmcr && bmcr != 0x7fff)
2687                                 break;
2688                         udelay(10);
2689                 }
2690
2691                 lcl_adv = 0;
2692                 rmt_adv = 0;
2693
2694                 tp->link_config.active_speed = current_speed;
2695                 tp->link_config.active_duplex = current_duplex;
2696
2697                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2698                         if ((bmcr & BMCR_ANENABLE) &&
2699                             tg3_copper_is_advertising_all(tp,
2700                                                 tp->link_config.advertising)) {
2701                                 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
2702                                                                   &rmt_adv))
2703                                         current_link_up = 1;
2704                         }
2705                 } else {
2706                         if (!(bmcr & BMCR_ANENABLE) &&
2707                             tp->link_config.speed == current_speed &&
2708                             tp->link_config.duplex == current_duplex &&
2709                             tp->link_config.flowctrl ==
2710                             tp->link_config.active_flowctrl) {
2711                                 current_link_up = 1;
2712                         }
2713                 }
2714
2715                 if (current_link_up == 1 &&
2716                     tp->link_config.active_duplex == DUPLEX_FULL)
2717                         tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
2718         }
2719
2720 relink:
2721         if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
2722                 u32 tmp;
2723
2724                 tg3_phy_copper_begin(tp);
2725
2726                 tg3_readphy(tp, MII_BMSR, &tmp);
2727                 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
2728                     (tmp & BMSR_LSTATUS))
2729                         current_link_up = 1;
2730         }
2731
2732         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
2733         if (current_link_up == 1) {
2734                 if (tp->link_config.active_speed == SPEED_100 ||
2735                     tp->link_config.active_speed == SPEED_10)
2736                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
2737                 else
2738                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2739         } else
2740                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2741
2742         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
2743         if (tp->link_config.active_duplex == DUPLEX_HALF)
2744                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
2745
2746         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
2747                 if (current_link_up == 1 &&
2748                     tg3_5700_link_polarity(tp, tp->link_config.active_speed))
2749                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
2750                 else
2751                         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
2752         }
2753
2754         /* ??? Without this setting Netgear GA302T PHY does not
2755          * ??? send/receive packets...
2756          */
2757         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
2758             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
2759                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
2760                 tw32_f(MAC_MI_MODE, tp->mi_mode);
2761                 udelay(80);
2762         }
2763
2764         tw32_f(MAC_MODE, tp->mac_mode);
2765         udelay(40);
2766
2767         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
2768                 /* Polled via timer. */
2769                 tw32_f(MAC_EVENT, 0);
2770         } else {
2771                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2772         }
2773         udelay(40);
2774
2775         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
2776             current_link_up == 1 &&
2777             tp->link_config.active_speed == SPEED_1000 &&
2778             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
2779              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
2780                 udelay(120);
2781                 tw32_f(MAC_STATUS,
2782                      (MAC_STATUS_SYNC_CHANGED |
2783                       MAC_STATUS_CFG_CHANGED));
2784                 udelay(40);
2785                 tg3_write_mem(tp,
2786                               NIC_SRAM_FIRMWARE_MBOX,
2787                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
2788         }
2789
2790         if (current_link_up != netif_carrier_ok(tp->dev)) {
2791                 if (current_link_up)
2792                         netif_carrier_on(tp->dev);
2793                 else
2794                         netif_carrier_off(tp->dev);
2795                 tg3_link_report(tp);
2796         }
2797
2798         return 0;
2799 }
2800
2801 struct tg3_fiber_aneginfo {
2802         int state;
2803 #define ANEG_STATE_UNKNOWN              0
2804 #define ANEG_STATE_AN_ENABLE            1
2805 #define ANEG_STATE_RESTART_INIT         2
2806 #define ANEG_STATE_RESTART              3
2807 #define ANEG_STATE_DISABLE_LINK_OK      4
2808 #define ANEG_STATE_ABILITY_DETECT_INIT  5
2809 #define ANEG_STATE_ABILITY_DETECT       6
2810 #define ANEG_STATE_ACK_DETECT_INIT      7
2811 #define ANEG_STATE_ACK_DETECT           8
2812 #define ANEG_STATE_COMPLETE_ACK_INIT    9
2813 #define ANEG_STATE_COMPLETE_ACK         10
2814 #define ANEG_STATE_IDLE_DETECT_INIT     11
2815 #define ANEG_STATE_IDLE_DETECT          12
2816 #define ANEG_STATE_LINK_OK              13
2817 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
2818 #define ANEG_STATE_NEXT_PAGE_WAIT       15
2819
2820         u32 flags;
2821 #define MR_AN_ENABLE            0x00000001
2822 #define MR_RESTART_AN           0x00000002
2823 #define MR_AN_COMPLETE          0x00000004
2824 #define MR_PAGE_RX              0x00000008
2825 #define MR_NP_LOADED            0x00000010
2826 #define MR_TOGGLE_TX            0x00000020
2827 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
2828 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
2829 #define MR_LP_ADV_SYM_PAUSE     0x00000100
2830 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
2831 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
2832 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
2833 #define MR_LP_ADV_NEXT_PAGE     0x00001000
2834 #define MR_TOGGLE_RX            0x00002000
2835 #define MR_NP_RX                0x00004000
2836
2837 #define MR_LINK_OK              0x80000000
2838
2839         unsigned long link_time, cur_time;
2840
2841         u32 ability_match_cfg;
2842         int ability_match_count;
2843
2844         char ability_match, idle_match, ack_match;
2845
2846         u32 txconfig, rxconfig;
2847 #define ANEG_CFG_NP             0x00000080
2848 #define ANEG_CFG_ACK            0x00000040
2849 #define ANEG_CFG_RF2            0x00000020
2850 #define ANEG_CFG_RF1            0x00000010
2851 #define ANEG_CFG_PS2            0x00000001
2852 #define ANEG_CFG_PS1            0x00008000
2853 #define ANEG_CFG_HD             0x00004000
2854 #define ANEG_CFG_FD             0x00002000
2855 #define ANEG_CFG_INVAL          0x00001f06
2856
2857 };
2858 #define ANEG_OK         0
2859 #define ANEG_DONE       1
2860 #define ANEG_TIMER_ENAB 2
2861 #define ANEG_FAILED     -1
2862
2863 #define ANEG_STATE_SETTLE_TIME  10000
2864
2865 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
2866                                    struct tg3_fiber_aneginfo *ap)
2867 {
2868         u16 flowctrl;
2869         unsigned long delta;
2870         u32 rx_cfg_reg;
2871         int ret;
2872
2873         if (ap->state == ANEG_STATE_UNKNOWN) {
2874                 ap->rxconfig = 0;
2875                 ap->link_time = 0;
2876                 ap->cur_time = 0;
2877                 ap->ability_match_cfg = 0;
2878                 ap->ability_match_count = 0;
2879                 ap->ability_match = 0;
2880                 ap->idle_match = 0;
2881                 ap->ack_match = 0;
2882         }
2883         ap->cur_time++;
2884
2885         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
2886                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
2887
2888                 if (rx_cfg_reg != ap->ability_match_cfg) {
2889                         ap->ability_match_cfg = rx_cfg_reg;
2890                         ap->ability_match = 0;
2891                         ap->ability_match_count = 0;
2892                 } else {
2893                         if (++ap->ability_match_count > 1) {
2894                                 ap->ability_match = 1;
2895                                 ap->ability_match_cfg = rx_cfg_reg;
2896                         }
2897                 }
2898                 if (rx_cfg_reg & ANEG_CFG_ACK)
2899                         ap->ack_match = 1;
2900                 else
2901                         ap->ack_match = 0;
2902
2903                 ap->idle_match = 0;
2904         } else {
2905                 ap->idle_match = 1;
2906                 ap->ability_match_cfg = 0;
2907                 ap->ability_match_count = 0;
2908                 ap->ability_match = 0;
2909                 ap->ack_match = 0;
2910
2911                 rx_cfg_reg = 0;
2912         }
2913
2914         ap->rxconfig = rx_cfg_reg;
2915         ret = ANEG_OK;
2916
2917         switch(ap->state) {
2918         case ANEG_STATE_UNKNOWN:
2919                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
2920                         ap->state = ANEG_STATE_AN_ENABLE;
2921
2922                 /* fallthru */
2923         case ANEG_STATE_AN_ENABLE:
2924                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
2925                 if (ap->flags & MR_AN_ENABLE) {
2926                         ap->link_time = 0;
2927                         ap->cur_time = 0;
2928                         ap->ability_match_cfg = 0;
2929                         ap->ability_match_count = 0;
2930                         ap->ability_match = 0;
2931                         ap->idle_match = 0;
2932                         ap->ack_match = 0;
2933
2934                         ap->state = ANEG_STATE_RESTART_INIT;
2935                 } else {
2936                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
2937                 }
2938                 break;
2939
2940         case ANEG_STATE_RESTART_INIT:
2941                 ap->link_time = ap->cur_time;
2942                 ap->flags &= ~(MR_NP_LOADED);
2943                 ap->txconfig = 0;
2944                 tw32(MAC_TX_AUTO_NEG, 0);
2945                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2946                 tw32_f(MAC_MODE, tp->mac_mode);
2947                 udelay(40);
2948
2949                 ret = ANEG_TIMER_ENAB;
2950                 ap->state = ANEG_STATE_RESTART;
2951
2952                 /* fallthru */
2953         case ANEG_STATE_RESTART:
2954                 delta = ap->cur_time - ap->link_time;
2955                 if (delta > ANEG_STATE_SETTLE_TIME) {
2956                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
2957                 } else {
2958                         ret = ANEG_TIMER_ENAB;
2959                 }
2960                 break;
2961
2962         case ANEG_STATE_DISABLE_LINK_OK:
2963                 ret = ANEG_DONE;
2964                 break;
2965
2966         case ANEG_STATE_ABILITY_DETECT_INIT:
2967                 ap->flags &= ~(MR_TOGGLE_TX);
2968                 ap->txconfig = ANEG_CFG_FD;
2969                 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
2970                 if (flowctrl & ADVERTISE_1000XPAUSE)
2971                         ap->txconfig |= ANEG_CFG_PS1;
2972                 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
2973                         ap->txconfig |= ANEG_CFG_PS2;
2974                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2975                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2976                 tw32_f(MAC_MODE, tp->mac_mode);
2977                 udelay(40);
2978
2979                 ap->state = ANEG_STATE_ABILITY_DETECT;
2980                 break;
2981
2982         case ANEG_STATE_ABILITY_DETECT:
2983                 if (ap->ability_match != 0 && ap->rxconfig != 0) {
2984                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
2985                 }
2986                 break;
2987
2988         case ANEG_STATE_ACK_DETECT_INIT:
2989                 ap->txconfig |= ANEG_CFG_ACK;
2990                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2991                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2992                 tw32_f(MAC_MODE, tp->mac_mode);
2993                 udelay(40);
2994
2995                 ap->state = ANEG_STATE_ACK_DETECT;
2996
2997                 /* fallthru */
2998         case ANEG_STATE_ACK_DETECT:
2999                 if (ap->ack_match != 0) {
3000                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3001                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3002                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3003                         } else {
3004                                 ap->state = ANEG_STATE_AN_ENABLE;
3005                         }
3006                 } else if (ap->ability_match != 0 &&
3007                            ap->rxconfig == 0) {
3008                         ap->state = ANEG_STATE_AN_ENABLE;
3009                 }
3010                 break;
3011
3012         case ANEG_STATE_COMPLETE_ACK_INIT:
3013                 if (ap->rxconfig & ANEG_CFG_INVAL) {
3014                         ret = ANEG_FAILED;
3015                         break;
3016                 }
3017                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3018                                MR_LP_ADV_HALF_DUPLEX |
3019                                MR_LP_ADV_SYM_PAUSE |
3020                                MR_LP_ADV_ASYM_PAUSE |
3021                                MR_LP_ADV_REMOTE_FAULT1 |
3022                                MR_LP_ADV_REMOTE_FAULT2 |
3023                                MR_LP_ADV_NEXT_PAGE |
3024                                MR_TOGGLE_RX |
3025                                MR_NP_RX);
3026                 if (ap->rxconfig & ANEG_CFG_FD)
3027                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3028                 if (ap->rxconfig & ANEG_CFG_HD)
3029                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3030                 if (ap->rxconfig & ANEG_CFG_PS1)
3031                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
3032                 if (ap->rxconfig & ANEG_CFG_PS2)
3033                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3034                 if (ap->rxconfig & ANEG_CFG_RF1)
3035                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3036                 if (ap->rxconfig & ANEG_CFG_RF2)
3037                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3038                 if (ap->rxconfig & ANEG_CFG_NP)
3039                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
3040
3041                 ap->link_time = ap->cur_time;
3042
3043                 ap->flags ^= (MR_TOGGLE_TX);
3044                 if (ap->rxconfig & 0x0008)
3045                         ap->flags |= MR_TOGGLE_RX;
3046                 if (ap->rxconfig & ANEG_CFG_NP)
3047                         ap->flags |= MR_NP_RX;
3048                 ap->flags |= MR_PAGE_RX;
3049
3050                 ap->state = ANEG_STATE_COMPLETE_ACK;
3051                 ret = ANEG_TIMER_ENAB;
3052                 break;
3053
3054         case ANEG_STATE_COMPLETE_ACK:
3055                 if (ap->ability_match != 0 &&
3056                     ap->rxconfig == 0) {
3057                         ap->state = ANEG_STATE_AN_ENABLE;
3058                         break;
3059                 }
3060                 delta = ap->cur_time - ap->link_time;
3061                 if (delta > ANEG_STATE_SETTLE_TIME) {
3062                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3063                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3064                         } else {
3065                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3066                                     !(ap->flags & MR_NP_RX)) {
3067                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3068                                 } else {
3069                                         ret = ANEG_FAILED;
3070                                 }
3071                         }
3072                 }
3073                 break;
3074
3075         case ANEG_STATE_IDLE_DETECT_INIT:
3076                 ap->link_time = ap->cur_time;
3077                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3078                 tw32_f(MAC_MODE, tp->mac_mode);
3079                 udelay(40);
3080
3081                 ap->state = ANEG_STATE_IDLE_DETECT;
3082                 ret = ANEG_TIMER_ENAB;
3083                 break;
3084
3085         case ANEG_STATE_IDLE_DETECT:
3086                 if (ap->ability_match != 0 &&
3087                     ap->rxconfig == 0) {
3088                         ap->state = ANEG_STATE_AN_ENABLE;
3089                         break;
3090                 }
3091                 delta = ap->cur_time - ap->link_time;
3092                 if (delta > ANEG_STATE_SETTLE_TIME) {
3093                         /* XXX another gem from the Broadcom driver :( */
3094                         ap->state = ANEG_STATE_LINK_OK;
3095                 }
3096                 break;
3097
3098         case ANEG_STATE_LINK_OK:
3099                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3100                 ret = ANEG_DONE;
3101                 break;
3102
3103         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3104                 /* ??? unimplemented */
3105                 break;
3106
3107         case ANEG_STATE_NEXT_PAGE_WAIT:
3108                 /* ??? unimplemented */
3109                 break;
3110
3111         default:
3112                 ret = ANEG_FAILED;
3113                 break;
3114         }
3115
3116         return ret;
3117 }
3118
3119 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3120 {
3121         int res = 0;
3122         struct tg3_fiber_aneginfo aninfo;
3123         int status = ANEG_FAILED;
3124         unsigned int tick;
3125         u32 tmp;
3126
3127         tw32_f(MAC_TX_AUTO_NEG, 0);
3128
3129         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3130         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3131         udelay(40);
3132
3133         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3134         udelay(40);
3135
3136         memset(&aninfo, 0, sizeof(aninfo));
3137         aninfo.flags |= MR_AN_ENABLE;
3138         aninfo.state = ANEG_STATE_UNKNOWN;
3139         aninfo.cur_time = 0;
3140         tick = 0;
3141         while (++tick < 195000) {
3142                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3143                 if (status == ANEG_DONE || status == ANEG_FAILED)
3144                         break;
3145
3146                 udelay(1);
3147         }
3148
3149         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3150         tw32_f(MAC_MODE, tp->mac_mode);
3151         udelay(40);
3152
3153         *txflags = aninfo.txconfig;
3154         *rxflags = aninfo.flags;
3155
3156         if (status == ANEG_DONE &&
3157             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3158                              MR_LP_ADV_FULL_DUPLEX)))
3159                 res = 1;
3160
3161         return res;
3162 }
3163
3164 static void tg3_init_bcm8002(struct tg3 *tp)
3165 {
3166         u32 mac_status = tr32(MAC_STATUS);
3167         int i;
3168
3169         /* Reset when initting first time or we have a link. */
3170         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3171             !(mac_status & MAC_STATUS_PCS_SYNCED))
3172                 return;
3173
3174         /* Set PLL lock range. */
3175         tg3_writephy(tp, 0x16, 0x8007);
3176
3177         /* SW reset */
3178         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3179
3180         /* Wait for reset to complete. */
3181         /* XXX schedule_timeout() ... */
3182         for (i = 0; i < 500; i++)
3183                 udelay(10);
3184
3185         /* Config mode; select PMA/Ch 1 regs. */
3186         tg3_writephy(tp, 0x10, 0x8411);
3187
3188         /* Enable auto-lock and comdet, select txclk for tx. */
3189         tg3_writephy(tp, 0x11, 0x0a10);
3190
3191         tg3_writephy(tp, 0x18, 0x00a0);
3192         tg3_writephy(tp, 0x16, 0x41ff);
3193
3194         /* Assert and deassert POR. */
3195         tg3_writephy(tp, 0x13, 0x0400);
3196         udelay(40);
3197         tg3_writephy(tp, 0x13, 0x0000);
3198
3199         tg3_writephy(tp, 0x11, 0x0a50);
3200         udelay(40);
3201         tg3_writephy(tp, 0x11, 0x0a10);
3202
3203         /* Wait for signal to stabilize */
3204         /* XXX schedule_timeout() ... */
3205         for (i = 0; i < 15000; i++)
3206                 udelay(10);
3207
3208         /* Deselect the channel register so we can read the PHYID
3209          * later.
3210          */
3211         tg3_writephy(tp, 0x10, 0x8011);
3212 }
3213
3214 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3215 {
3216         u16 flowctrl;
3217         u32 sg_dig_ctrl, sg_dig_status;
3218         u32 serdes_cfg, expected_sg_dig_ctrl;
3219         int workaround, port_a;
3220         int current_link_up;
3221
3222         serdes_cfg = 0;
3223         expected_sg_dig_ctrl = 0;
3224         workaround = 0;
3225         port_a = 1;
3226         current_link_up = 0;
3227
3228         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3229             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3230                 workaround = 1;
3231                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3232                         port_a = 0;
3233
3234                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3235                 /* preserve bits 20-23 for voltage regulator */
3236                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3237         }
3238
3239         sg_dig_ctrl = tr32(SG_DIG_CTRL);
3240
3241         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3242                 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3243                         if (workaround) {
3244                                 u32 val = serdes_cfg;
3245
3246                                 if (port_a)
3247                                         val |= 0xc010000;
3248                                 else
3249                                         val |= 0x4010000;
3250                                 tw32_f(MAC_SERDES_CFG, val);
3251                         }
3252
3253                         tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3254                 }
3255                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3256                         tg3_setup_flow_control(tp, 0, 0);
3257                         current_link_up = 1;
3258                 }
3259                 goto out;
3260         }
3261
3262         /* Want auto-negotiation.  */
3263         expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3264
3265         flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3266         if (flowctrl & ADVERTISE_1000XPAUSE)
3267                 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3268         if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3269                 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3270
3271         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3272                 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3273                     tp->serdes_counter &&
3274                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
3275                                     MAC_STATUS_RCVD_CFG)) ==
3276                      MAC_STATUS_PCS_SYNCED)) {
3277                         tp->serdes_counter--;
3278                         current_link_up = 1;
3279                         goto out;
3280                 }
3281 restart_autoneg:
3282                 if (workaround)
3283                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3284                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3285                 udelay(5);
3286                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3287
3288                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3289                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3290         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3291                                  MAC_STATUS_SIGNAL_DET)) {
3292                 sg_dig_status = tr32(SG_DIG_STATUS);
3293                 mac_status = tr32(MAC_STATUS);
3294
3295                 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3296                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
3297                         u32 local_adv = 0, remote_adv = 0;
3298
3299                         if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3300                                 local_adv |= ADVERTISE_1000XPAUSE;
3301                         if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3302                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3303
3304                         if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3305                                 remote_adv |= LPA_1000XPAUSE;
3306                         if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3307                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3308
3309                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3310                         current_link_up = 1;
3311                         tp->serdes_counter = 0;
3312                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3313                 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3314                         if (tp->serdes_counter)
3315                                 tp->serdes_counter--;
3316                         else {
3317                                 if (workaround) {
3318                                         u32 val = serdes_cfg;
3319
3320                                         if (port_a)
3321                                                 val |= 0xc010000;
3322                                         else
3323                                                 val |= 0x4010000;
3324
3325                                         tw32_f(MAC_SERDES_CFG, val);
3326                                 }
3327
3328                                 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3329                                 udelay(40);
3330
3331                                 /* Link parallel detection - link is up */
3332                                 /* only if we have PCS_SYNC and not */
3333                                 /* receiving config code words */
3334                                 mac_status = tr32(MAC_STATUS);
3335                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3336                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
3337                                         tg3_setup_flow_control(tp, 0, 0);
3338                                         current_link_up = 1;
3339                                         tp->tg3_flags2 |=
3340                                                 TG3_FLG2_PARALLEL_DETECT;
3341                                         tp->serdes_counter =
3342                                                 SERDES_PARALLEL_DET_TIMEOUT;
3343                                 } else
3344                                         goto restart_autoneg;
3345                         }
3346                 }
3347         } else {
3348                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3349                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3350         }
3351
3352 out:
3353         return current_link_up;
3354 }
3355
3356 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3357 {
3358         int current_link_up = 0;
3359
3360         if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3361                 goto out;
3362
3363         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3364                 u32 txflags, rxflags;
3365                 int i;
3366
3367                 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3368                         u32 local_adv = 0, remote_adv = 0;
3369
3370                         if (txflags & ANEG_CFG_PS1)
3371                                 local_adv |= ADVERTISE_1000XPAUSE;
3372                         if (txflags & ANEG_CFG_PS2)
3373                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3374
3375                         if (rxflags & MR_LP_ADV_SYM_PAUSE)
3376                                 remote_adv |= LPA_1000XPAUSE;
3377                         if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3378                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3379
3380                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3381
3382                         current_link_up = 1;
3383                 }
3384                 for (i = 0; i < 30; i++) {
3385                         udelay(20);
3386                         tw32_f(MAC_STATUS,
3387                                (MAC_STATUS_SYNC_CHANGED |
3388                                 MAC_STATUS_CFG_CHANGED));
3389                         udelay(40);
3390                         if ((tr32(MAC_STATUS) &
3391                              (MAC_STATUS_SYNC_CHANGED |
3392                               MAC_STATUS_CFG_CHANGED)) == 0)
3393                                 break;
3394                 }
3395
3396                 mac_status = tr32(MAC_STATUS);
3397                 if (current_link_up == 0 &&
3398                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
3399                     !(mac_status & MAC_STATUS_RCVD_CFG))
3400                         current_link_up = 1;
3401         } else {
3402                 tg3_setup_flow_control(tp, 0, 0);
3403
3404                 /* Forcing 1000FD link up. */
3405                 current_link_up = 1;
3406
3407                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3408                 udelay(40);
3409
3410                 tw32_f(MAC_MODE, tp->mac_mode);
3411                 udelay(40);
3412         }
3413
3414 out:
3415         return current_link_up;
3416 }
3417
3418 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3419 {
3420         u32 orig_pause_cfg;
3421         u16 orig_active_speed;
3422         u8 orig_active_duplex;
3423         u32 mac_status;
3424         int current_link_up;
3425         int i;
3426
3427         orig_pause_cfg = tp->link_config.active_flowctrl;
3428         orig_active_speed = tp->link_config.active_speed;
3429         orig_active_duplex = tp->link_config.active_duplex;
3430
3431         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3432             netif_carrier_ok(tp->dev) &&
3433             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3434                 mac_status = tr32(MAC_STATUS);
3435                 mac_status &= (MAC_STATUS_PCS_SYNCED |
3436                                MAC_STATUS_SIGNAL_DET |
3437                                MAC_STATUS_CFG_CHANGED |
3438                                MAC_STATUS_RCVD_CFG);
3439                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3440                                    MAC_STATUS_SIGNAL_DET)) {
3441                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3442                                             MAC_STATUS_CFG_CHANGED));
3443                         return 0;
3444                 }
3445         }
3446
3447         tw32_f(MAC_TX_AUTO_NEG, 0);
3448
3449         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3450         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3451         tw32_f(MAC_MODE, tp->mac_mode);
3452         udelay(40);
3453
3454         if (tp->phy_id == PHY_ID_BCM8002)
3455                 tg3_init_bcm8002(tp);
3456
3457         /* Enable link change event even when serdes polling.  */
3458         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3459         udelay(40);
3460
3461         current_link_up = 0;
3462         mac_status = tr32(MAC_STATUS);
3463
3464         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3465                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3466         else
3467                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3468
3469         tp->hw_status->status =
3470                 (SD_STATUS_UPDATED |
3471                  (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
3472
3473         for (i = 0; i < 100; i++) {
3474                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3475                                     MAC_STATUS_CFG_CHANGED));
3476                 udelay(5);
3477                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3478                                          MAC_STATUS_CFG_CHANGED |
3479                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
3480                         break;
3481         }
3482
3483         mac_status = tr32(MAC_STATUS);
3484         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3485                 current_link_up = 0;
3486                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3487                     tp->serdes_counter == 0) {
3488                         tw32_f(MAC_MODE, (tp->mac_mode |
3489                                           MAC_MODE_SEND_CONFIGS));
3490                         udelay(1);
3491                         tw32_f(MAC_MODE, tp->mac_mode);
3492                 }
3493         }
3494
3495         if (current_link_up == 1) {
3496                 tp->link_config.active_speed = SPEED_1000;
3497                 tp->link_config.active_duplex = DUPLEX_FULL;
3498                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3499                                     LED_CTRL_LNKLED_OVERRIDE |
3500                                     LED_CTRL_1000MBPS_ON));
3501         } else {
3502                 tp->link_config.active_speed = SPEED_INVALID;
3503                 tp->link_config.active_duplex = DUPLEX_INVALID;
3504                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3505                                     LED_CTRL_LNKLED_OVERRIDE |
3506                                     LED_CTRL_TRAFFIC_OVERRIDE));
3507         }
3508
3509         if (current_link_up != netif_carrier_ok(tp->dev)) {
3510                 if (current_link_up)
3511                         netif_carrier_on(tp->dev);
3512                 else
3513                         netif_carrier_off(tp->dev);
3514                 tg3_link_report(tp);
3515         } else {
3516                 u32 now_pause_cfg = tp->link_config.active_flowctrl;
3517                 if (orig_pause_cfg != now_pause_cfg ||
3518                     orig_active_speed != tp->link_config.active_speed ||
3519                     orig_active_duplex != tp->link_config.active_duplex)
3520                         tg3_link_report(tp);
3521         }
3522
3523         return 0;
3524 }
3525
3526 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
3527 {
3528         int current_link_up, err = 0;
3529         u32 bmsr, bmcr;
3530         u16 current_speed;
3531         u8 current_duplex;
3532         u32 local_adv, remote_adv;
3533
3534         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3535         tw32_f(MAC_MODE, tp->mac_mode);
3536         udelay(40);
3537
3538         tw32(MAC_EVENT, 0);
3539
3540         tw32_f(MAC_STATUS,
3541              (MAC_STATUS_SYNC_CHANGED |
3542               MAC_STATUS_CFG_CHANGED |
3543               MAC_STATUS_MI_COMPLETION |
3544               MAC_STATUS_LNKSTATE_CHANGED));
3545         udelay(40);
3546
3547         if (force_reset)
3548                 tg3_phy_reset(tp);
3549
3550         current_link_up = 0;
3551         current_speed = SPEED_INVALID;
3552         current_duplex = DUPLEX_INVALID;
3553
3554         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3555         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3556         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
3557                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
3558                         bmsr |= BMSR_LSTATUS;
3559                 else
3560                         bmsr &= ~BMSR_LSTATUS;
3561         }
3562
3563         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
3564
3565         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
3566             (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
3567                 /* do nothing, just check for link up at the end */
3568         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3569                 u32 adv, new_adv;
3570
3571                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
3572                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
3573                                   ADVERTISE_1000XPAUSE |
3574                                   ADVERTISE_1000XPSE_ASYM |
3575                                   ADVERTISE_SLCT);
3576
3577                 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3578
3579                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
3580                         new_adv |= ADVERTISE_1000XHALF;
3581                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
3582                         new_adv |= ADVERTISE_1000XFULL;
3583
3584                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
3585                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
3586                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
3587                         tg3_writephy(tp, MII_BMCR, bmcr);
3588
3589                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3590                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
3591                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3592
3593                         return err;
3594                 }
3595         } else {
3596                 u32 new_bmcr;
3597
3598                 bmcr &= ~BMCR_SPEED1000;
3599                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
3600
3601                 if (tp->link_config.duplex == DUPLEX_FULL)
3602                         new_bmcr |= BMCR_FULLDPLX;
3603
3604                 if (new_bmcr != bmcr) {
3605                         /* BMCR_SPEED1000 is a reserved bit that needs
3606                          * to be set on write.
3607                          */
3608                         new_bmcr |= BMCR_SPEED1000;
3609
3610                         /* Force a linkdown */
3611                         if (netif_carrier_ok(tp->dev)) {
3612                                 u32 adv;
3613
3614                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
3615                                 adv &= ~(ADVERTISE_1000XFULL |
3616                                          ADVERTISE_1000XHALF |
3617                                          ADVERTISE_SLCT);
3618                                 tg3_writephy(tp, MII_ADVERTISE, adv);
3619                                 tg3_writephy(tp, MII_BMCR, bmcr |
3620                                                            BMCR_ANRESTART |
3621                                                            BMCR_ANENABLE);
3622                                 udelay(10);
3623                                 netif_carrier_off(tp->dev);
3624                         }
3625                         tg3_writephy(tp, MII_BMCR, new_bmcr);
3626                         bmcr = new_bmcr;
3627                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3628                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3629                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
3630                             ASIC_REV_5714) {
3631                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
3632                                         bmsr |= BMSR_LSTATUS;
3633                                 else
3634                                         bmsr &= ~BMSR_LSTATUS;
3635                         }
3636                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3637                 }
3638         }
3639
3640         if (bmsr & BMSR_LSTATUS) {
3641                 current_speed = SPEED_1000;
3642                 current_link_up = 1;
3643                 if (bmcr & BMCR_FULLDPLX)
3644                         current_duplex = DUPLEX_FULL;
3645                 else
3646                         current_duplex = DUPLEX_HALF;
3647
3648                 local_adv = 0;
3649                 remote_adv = 0;
3650
3651                 if (bmcr & BMCR_ANENABLE) {
3652                         u32 common;
3653
3654                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
3655                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
3656                         common = local_adv & remote_adv;
3657                         if (common & (ADVERTISE_1000XHALF |
3658                                       ADVERTISE_1000XFULL)) {
3659                                 if (common & ADVERTISE_1000XFULL)
3660                                         current_duplex = DUPLEX_FULL;
3661                                 else
3662                                         current_duplex = DUPLEX_HALF;
3663                         }
3664                         else
3665                                 current_link_up = 0;
3666                 }
3667         }
3668
3669         if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
3670                 tg3_setup_flow_control(tp, local_adv, remote_adv);
3671
3672         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3673         if (tp->link_config.active_duplex == DUPLEX_HALF)
3674                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3675
3676         tw32_f(MAC_MODE, tp->mac_mode);
3677         udelay(40);
3678
3679         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3680
3681         tp->link_config.active_speed = current_speed;
3682         tp->link_config.active_duplex = current_duplex;
3683
3684         if (current_link_up != netif_carrier_ok(tp->dev)) {
3685                 if (current_link_up)
3686                         netif_carrier_on(tp->dev);
3687                 else {
3688                         netif_carrier_off(tp->dev);
3689                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3690                 }
3691                 tg3_link_report(tp);
3692         }
3693         return err;
3694 }
3695
3696 static void tg3_serdes_parallel_detect(struct tg3 *tp)
3697 {
3698         if (tp->serdes_counter) {
3699                 /* Give autoneg time to complete. */
3700                 tp->serdes_counter--;
3701                 return;
3702         }
3703         if (!netif_carrier_ok(tp->dev) &&
3704             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
3705                 u32 bmcr;
3706
3707                 tg3_readphy(tp, MII_BMCR, &bmcr);
3708                 if (bmcr & BMCR_ANENABLE) {
3709                         u32 phy1, phy2;
3710
3711                         /* Select shadow register 0x1f */
3712                         tg3_writephy(tp, 0x1c, 0x7c00);
3713                         tg3_readphy(tp, 0x1c, &phy1);
3714
3715                         /* Select expansion interrupt status register */
3716                         tg3_writephy(tp, 0x17, 0x0f01);
3717                         tg3_readphy(tp, 0x15, &phy2);
3718                         tg3_readphy(tp, 0x15, &phy2);
3719
3720                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
3721                                 /* We have signal detect and not receiving
3722                                  * config code words, link is up by parallel
3723                                  * detection.
3724                                  */
3725
3726                                 bmcr &= ~BMCR_ANENABLE;
3727                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
3728                                 tg3_writephy(tp, MII_BMCR, bmcr);
3729                                 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
3730                         }
3731                 }
3732         }
3733         else if (netif_carrier_ok(tp->dev) &&
3734                  (tp->link_config.autoneg == AUTONEG_ENABLE) &&
3735                  (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
3736                 u32 phy2;
3737
3738                 /* Select expansion interrupt status register */
3739                 tg3_writephy(tp, 0x17, 0x0f01);
3740                 tg3_readphy(tp, 0x15, &phy2);
3741                 if (phy2 & 0x20) {
3742                         u32 bmcr;
3743
3744                         /* Config code words received, turn on autoneg. */
3745                         tg3_readphy(tp, MII_BMCR, &bmcr);
3746                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
3747
3748                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3749
3750                 }
3751         }
3752 }
3753
3754 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
3755 {
3756         int err;
3757
3758         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
3759                 err = tg3_setup_fiber_phy(tp, force_reset);
3760         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
3761                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
3762         } else {
3763                 err = tg3_setup_copper_phy(tp, force_reset);
3764         }
3765
3766         if (tp->pci_chip_rev_id == CHIPREV_ID_5784_A0 ||
3767             tp->pci_chip_rev_id == CHIPREV_ID_5784_A1) {
3768                 u32 val, scale;
3769
3770                 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
3771                 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
3772                         scale = 65;
3773                 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
3774                         scale = 6;
3775                 else
3776                         scale = 12;
3777
3778                 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
3779                 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
3780                 tw32(GRC_MISC_CFG, val);
3781         }
3782
3783         if (tp->link_config.active_speed == SPEED_1000 &&
3784             tp->link_config.active_duplex == DUPLEX_HALF)
3785                 tw32(MAC_TX_LENGTHS,
3786                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3787                       (6 << TX_LENGTHS_IPG_SHIFT) |
3788                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
3789         else
3790                 tw32(MAC_TX_LENGTHS,
3791                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3792                       (6 << TX_LENGTHS_IPG_SHIFT) |
3793                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
3794
3795         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
3796                 if (netif_carrier_ok(tp->dev)) {
3797                         tw32(HOSTCC_STAT_COAL_TICKS,
3798                              tp->coal.stats_block_coalesce_usecs);
3799                 } else {
3800                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
3801                 }
3802         }
3803
3804         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
3805                 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
3806                 if (!netif_carrier_ok(tp->dev))
3807                         val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
3808                               tp->pwrmgmt_thresh;
3809                 else
3810                         val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
3811                 tw32(PCIE_PWR_MGMT_THRESH, val);
3812         }
3813
3814         return err;
3815 }
3816
3817 /* This is called whenever we suspect that the system chipset is re-
3818  * ordering the sequence of MMIO to the tx send mailbox. The symptom
3819  * is bogus tx completions. We try to recover by setting the
3820  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
3821  * in the workqueue.
3822  */
3823 static void tg3_tx_recover(struct tg3 *tp)
3824 {
3825         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
3826                tp->write32_tx_mbox == tg3_write_indirect_mbox);
3827
3828         printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
3829                "mapped I/O cycles to the network device, attempting to "
3830                "recover. Please report the problem to the driver maintainer "
3831                "and include system chipset information.\n", tp->dev->name);
3832
3833         spin_lock(&tp->lock);
3834         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
3835         spin_unlock(&tp->lock);
3836 }
3837
3838 static inline u32 tg3_tx_avail(struct tg3 *tp)
3839 {
3840         smp_mb();
3841         return (tp->tx_pending -
3842                 ((tp->tx_prod - tp->tx_cons) & (TG3_TX_RING_SIZE - 1)));
3843 }
3844
3845 /* Tigon3 never reports partial packet sends.  So we do not
3846  * need special logic to handle SKBs that have not had all
3847  * of their frags sent yet, like SunGEM does.
3848  */
3849 static void tg3_tx(struct tg3 *tp)
3850 {
3851         u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
3852         u32 sw_idx = tp->tx_cons;
3853
3854         while (sw_idx != hw_idx) {
3855                 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
3856                 struct sk_buff *skb = ri->skb;
3857                 int i, tx_bug = 0;
3858
3859                 if (unlikely(skb == NULL)) {
3860                         tg3_tx_recover(tp);
3861                         return;
3862                 }
3863
3864                 pci_unmap_single(tp->pdev,
3865                                  pci_unmap_addr(ri, mapping),
3866                                  skb_headlen(skb),
3867                                  PCI_DMA_TODEVICE);
3868
3869                 ri->skb = NULL;
3870
3871                 sw_idx = NEXT_TX(sw_idx);
3872
3873                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
3874                         ri = &tp->tx_buffers[sw_idx];
3875                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
3876                                 tx_bug = 1;
3877
3878                         pci_unmap_page(tp->pdev,
3879                                        pci_unmap_addr(ri, mapping),
3880                                        skb_shinfo(skb)->frags[i].size,
3881                                        PCI_DMA_TODEVICE);
3882
3883                         sw_idx = NEXT_TX(sw_idx);
3884                 }
3885
3886                 dev_kfree_skb(skb);
3887
3888                 if (unlikely(tx_bug)) {
3889                         tg3_tx_recover(tp);
3890                         return;
3891                 }
3892         }
3893
3894         tp->tx_cons = sw_idx;
3895
3896         /* Need to make the tx_cons update visible to tg3_start_xmit()
3897          * before checking for netif_queue_stopped().  Without the
3898          * memory barrier, there is a small possibility that tg3_start_xmit()
3899          * will miss it and cause the queue to be stopped forever.
3900          */
3901         smp_mb();
3902
3903         if (unlikely(netif_queue_stopped(tp->dev) &&
3904                      (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))) {
3905                 netif_tx_lock(tp->dev);
3906                 if (netif_queue_stopped(tp->dev) &&
3907                     (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))
3908                         netif_wake_queue(tp->dev);
3909                 netif_tx_unlock(tp->dev);
3910         }
3911 }
3912
3913 /* Returns size of skb allocated or < 0 on error.
3914  *
3915  * We only need to fill in the address because the other members
3916  * of the RX descriptor are invariant, see tg3_init_rings.
3917  *
3918  * Note the purposeful assymetry of cpu vs. chip accesses.  For
3919  * posting buffers we only dirty the first cache line of the RX
3920  * descriptor (containing the address).  Whereas for the RX status
3921  * buffers the cpu only reads the last cacheline of the RX descriptor
3922  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
3923  */
3924 static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
3925                             int src_idx, u32 dest_idx_unmasked)
3926 {
3927         struct tg3_rx_buffer_desc *desc;
3928         struct ring_info *map, *src_map;
3929         struct sk_buff *skb;
3930         dma_addr_t mapping;
3931         int skb_size, dest_idx;
3932
3933         src_map = NULL;
3934         switch (opaque_key) {
3935         case RXD_OPAQUE_RING_STD:
3936                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3937                 desc = &tp->rx_std[dest_idx];
3938                 map = &tp->rx_std_buffers[dest_idx];
3939                 if (src_idx >= 0)
3940                         src_map = &tp->rx_std_buffers[src_idx];
3941                 skb_size = tp->rx_pkt_buf_sz;
3942                 break;
3943
3944         case RXD_OPAQUE_RING_JUMBO:
3945                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3946                 desc = &tp->rx_jumbo[dest_idx];
3947                 map = &tp->rx_jumbo_buffers[dest_idx];
3948                 if (src_idx >= 0)
3949                         src_map = &tp->rx_jumbo_buffers[src_idx];
3950                 skb_size = RX_JUMBO_PKT_BUF_SZ;
3951                 break;
3952
3953         default:
3954                 return -EINVAL;
3955         }
3956
3957         /* Do not overwrite any of the map or rp information
3958          * until we are sure we can commit to a new buffer.
3959          *
3960          * Callers depend upon this behavior and assume that
3961          * we leave everything unchanged if we fail.
3962          */
3963         skb = netdev_alloc_skb(tp->dev, skb_size);
3964         if (skb == NULL)
3965                 return -ENOMEM;
3966
3967         skb_reserve(skb, tp->rx_offset);
3968
3969         mapping = pci_map_single(tp->pdev, skb->data,
3970                                  skb_size - tp->rx_offset,
3971                                  PCI_DMA_FROMDEVICE);
3972
3973         map->skb = skb;
3974         pci_unmap_addr_set(map, mapping, mapping);
3975
3976         if (src_map != NULL)
3977                 src_map->skb = NULL;
3978
3979         desc->addr_hi = ((u64)mapping >> 32);
3980         desc->addr_lo = ((u64)mapping & 0xffffffff);
3981
3982         return skb_size;
3983 }
3984
3985 /* We only need to move over in the address because the other
3986  * members of the RX descriptor are invariant.  See notes above
3987  * tg3_alloc_rx_skb for full details.
3988  */
3989 static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
3990                            int src_idx, u32 dest_idx_unmasked)
3991 {
3992         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
3993         struct ring_info *src_map, *dest_map;
3994         int dest_idx;
3995
3996         switch (opaque_key) {
3997         case RXD_OPAQUE_RING_STD:
3998                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3999                 dest_desc = &tp->rx_std[dest_idx];
4000                 dest_map = &tp->rx_std_buffers[dest_idx];
4001                 src_desc = &tp->rx_std[src_idx];
4002                 src_map = &tp->rx_std_buffers[src_idx];
4003                 break;
4004
4005         case RXD_OPAQUE_RING_JUMBO:
4006                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4007                 dest_desc = &tp->rx_jumbo[dest_idx];
4008                 dest_map = &tp->rx_jumbo_buffers[dest_idx];
4009                 src_desc = &tp->rx_jumbo[src_idx];
4010                 src_map = &tp->rx_jumbo_buffers[src_idx];
4011                 break;
4012
4013         default:
4014                 return;
4015         }
4016
4017         dest_map->skb = src_map->skb;
4018         pci_unmap_addr_set(dest_map, mapping,
4019                            pci_unmap_addr(src_map, mapping));
4020         dest_desc->addr_hi = src_desc->addr_hi;
4021         dest_desc->addr_lo = src_desc->addr_lo;
4022
4023         src_map->skb = NULL;
4024 }
4025
4026 #if TG3_VLAN_TAG_USED
4027 static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
4028 {
4029         return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag);
4030 }
4031 #endif
4032
4033 /* The RX ring scheme is composed of multiple rings which post fresh
4034  * buffers to the chip, and one special ring the chip uses to report
4035  * status back to the host.
4036  *
4037  * The special ring reports the status of received packets to the
4038  * host.  The chip does not write into the original descriptor the
4039  * RX buffer was obtained from.  The chip simply takes the original
4040  * descriptor as provided by the host, updates the status and length
4041  * field, then writes this into the next status ring entry.
4042  *
4043  * Each ring the host uses to post buffers to the chip is described
4044  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
4045  * it is first placed into the on-chip ram.  When the packet's length
4046  * is known, it walks down the TG3_BDINFO entries to select the ring.
4047  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4048  * which is within the range of the new packet's length is chosen.
4049  *
4050  * The "separate ring for rx status" scheme may sound queer, but it makes
4051  * sense from a cache coherency perspective.  If only the host writes
4052  * to the buffer post rings, and only the chip writes to the rx status
4053  * rings, then cache lines never move beyond shared-modified state.
4054  * If both the host and chip were to write into the same ring, cache line
4055  * eviction could occur since both entities want it in an exclusive state.
4056  */
4057 static int tg3_rx(struct tg3 *tp, int budget)
4058 {
4059         u32 work_mask, rx_std_posted = 0;
4060         u32 sw_idx = tp->rx_rcb_ptr;
4061         u16 hw_idx;
4062         int received;
4063
4064         hw_idx = tp->hw_status->idx[0].rx_producer;
4065         /*
4066          * We need to order the read of hw_idx and the read of
4067          * the opaque cookie.
4068          */
4069         rmb();
4070         work_mask = 0;
4071         received = 0;
4072         while (sw_idx != hw_idx && budget > 0) {
4073                 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
4074                 unsigned int len;
4075                 struct sk_buff *skb;
4076                 dma_addr_t dma_addr;
4077                 u32 opaque_key, desc_idx, *post_ptr;
4078
4079                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4080                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4081                 if (opaque_key == RXD_OPAQUE_RING_STD) {
4082                         dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
4083                                                   mapping);
4084                         skb = tp->rx_std_buffers[desc_idx].skb;
4085                         post_ptr = &tp->rx_std_ptr;
4086                         rx_std_posted++;
4087                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4088                         dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
4089                                                   mapping);
4090                         skb = tp->rx_jumbo_buffers[desc_idx].skb;
4091                         post_ptr = &tp->rx_jumbo_ptr;
4092                 }
4093                 else {
4094                         goto next_pkt_nopost;
4095                 }
4096
4097                 work_mask |= opaque_key;
4098
4099                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4100                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4101                 drop_it:
4102                         tg3_recycle_rx(tp, opaque_key,
4103                                        desc_idx, *post_ptr);
4104                 drop_it_no_recycle:
4105                         /* Other statistics kept track of by card. */
4106                         tp->net_stats.rx_dropped++;
4107                         goto next_pkt;
4108                 }
4109
4110                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */
4111
4112                 if (len > RX_COPY_THRESHOLD
4113                         && tp->rx_offset == 2
4114                         /* rx_offset != 2 iff this is a 5701 card running
4115                          * in PCI-X mode [see tg3_get_invariants()] */
4116                 ) {
4117                         int skb_size;
4118
4119                         skb_size = tg3_alloc_rx_skb(tp, opaque_key,
4120                                                     desc_idx, *post_ptr);
4121                         if (skb_size < 0)
4122                                 goto drop_it;
4123
4124                         pci_unmap_single(tp->pdev, dma_addr,
4125                                          skb_size - tp->rx_offset,
4126                                          PCI_DMA_FROMDEVICE);
4127
4128                         skb_put(skb, len);
4129                 } else {
4130                         struct sk_buff *copy_skb;
4131
4132                         tg3_recycle_rx(tp, opaque_key,
4133                                        desc_idx, *post_ptr);
4134
4135                         copy_skb = netdev_alloc_skb(tp->dev, len + 2);
4136                         if (copy_skb == NULL)
4137                                 goto drop_it_no_recycle;
4138
4139                         skb_reserve(copy_skb, 2);
4140                         skb_put(copy_skb, len);
4141                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4142                         skb_copy_from_linear_data(skb, copy_skb->data, len);
4143                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4144
4145                         /* We'll reuse the original ring buffer. */
4146                         skb = copy_skb;
4147                 }
4148
4149                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4150                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4151                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4152                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
4153                         skb->ip_summed = CHECKSUM_UNNECESSARY;
4154                 else
4155                         skb->ip_summed = CHECKSUM_NONE;
4156
4157                 skb->protocol = eth_type_trans(skb, tp->dev);
4158 #if TG3_VLAN_TAG_USED
4159                 if (tp->vlgrp != NULL &&
4160                     desc->type_flags & RXD_FLAG_VLAN) {
4161                         tg3_vlan_rx(tp, skb,
4162                                     desc->err_vlan & RXD_VLAN_MASK);
4163                 } else
4164 #endif
4165                         netif_receive_skb(skb);
4166
4167                 tp->dev->last_rx = jiffies;
4168                 received++;
4169                 budget--;
4170
4171 next_pkt:
4172                 (*post_ptr)++;
4173
4174                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4175                         u32 idx = *post_ptr % TG3_RX_RING_SIZE;
4176
4177                         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
4178                                      TG3_64BIT_REG_LOW, idx);
4179                         work_mask &= ~RXD_OPAQUE_RING_STD;
4180                         rx_std_posted = 0;
4181                 }
4182 next_pkt_nopost:
4183                 sw_idx++;
4184                 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
4185
4186                 /* Refresh hw_idx to see if there is new work */
4187                 if (sw_idx == hw_idx) {
4188                         hw_idx = tp->hw_status->idx[0].rx_producer;
4189                         rmb();
4190                 }
4191         }
4192
4193         /* ACK the status ring. */
4194         tp->rx_rcb_ptr = sw_idx;
4195         tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
4196
4197         /* Refill RX ring(s). */
4198         if (work_mask & RXD_OPAQUE_RING_STD) {
4199                 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
4200                 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
4201                              sw_idx);
4202         }
4203         if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4204                 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
4205                 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
4206                              sw_idx);
4207         }
4208         mmiowb();
4209
4210         return received;
4211 }
4212
4213 static int tg3_poll_work(struct tg3 *tp, int work_done, int budget)
4214 {
4215         struct tg3_hw_status *sblk = tp->hw_status;
4216
4217         /* handle link change and other phy events */
4218         if (!(tp->tg3_flags &
4219               (TG3_FLAG_USE_LINKCHG_REG |
4220                TG3_FLAG_POLL_SERDES))) {
4221                 if (sblk->status & SD_STATUS_LINK_CHG) {
4222                         sblk->status = SD_STATUS_UPDATED |
4223                                 (sblk->status & ~SD_STATUS_LINK_CHG);
4224                         spin_lock(&tp->lock);
4225                         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4226                                 tw32_f(MAC_STATUS,
4227                                      (MAC_STATUS_SYNC_CHANGED |
4228                                       MAC_STATUS_CFG_CHANGED |
4229                                       MAC_STATUS_MI_COMPLETION |
4230                                       MAC_STATUS_LNKSTATE_CHANGED));
4231                                 udelay(40);
4232                         } else
4233                                 tg3_setup_phy(tp, 0);
4234                         spin_unlock(&tp->lock);
4235                 }
4236         }
4237
4238         /* run TX completion thread */
4239         if (sblk->idx[0].tx_consumer != tp->tx_cons) {
4240                 tg3_tx(tp);
4241                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4242                         return work_done;
4243         }
4244
4245         /* run RX thread, within the bounds set by NAPI.
4246          * All RX "locking" is done by ensuring outside
4247          * code synchronizes with tg3->napi.poll()
4248          */
4249         if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
4250                 work_done += tg3_rx(tp, budget - work_done);
4251
4252         return work_done;
4253 }
4254
4255 static int tg3_poll(struct napi_struct *napi, int budget)
4256 {
4257         struct tg3 *tp = container_of(napi, struct tg3, napi);
4258         int work_done = 0;
4259         struct tg3_hw_status *sblk = tp->hw_status;
4260
4261         while (1) {
4262                 work_done = tg3_poll_work(tp, work_done, budget);
4263
4264                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4265                         goto tx_recovery;
4266
4267                 if (unlikely(work_done >= budget))
4268                         break;
4269
4270                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
4271                         /* tp->last_tag is used in tg3_restart_ints() below
4272                          * to tell the hw how much work has been processed,
4273                          * so we must read it before checking for more work.
4274                          */
4275                         tp->last_tag = sblk->status_tag;
4276                         rmb();
4277                 } else
4278                         sblk->status &= ~SD_STATUS_UPDATED;
4279
4280                 if (likely(!tg3_has_work(tp))) {
4281                         netif_rx_complete(tp->dev, napi);
4282                         tg3_restart_ints(tp);
4283                         break;
4284                 }
4285         }
4286
4287         return work_done;
4288
4289 tx_recovery:
4290         /* work_done is guaranteed to be less than budget. */
4291         netif_rx_complete(tp->dev, napi);
4292         schedule_work(&tp->reset_task);
4293         return work_done;
4294 }
4295
4296 static void tg3_irq_quiesce(struct tg3 *tp)
4297 {
4298         BUG_ON(tp->irq_sync);
4299
4300         tp->irq_sync = 1;
4301         smp_mb();
4302
4303         synchronize_irq(tp->pdev->irq);
4304 }
4305
4306 static inline int tg3_irq_sync(struct tg3 *tp)
4307 {
4308         return tp->irq_sync;
4309 }
4310
4311 /* Fully shutdown all tg3 driver activity elsewhere in the system.
4312  * If irq_sync is non-zero, then the IRQ handler must be synchronized
4313  * with as well.  Most of the time, this is not necessary except when
4314  * shutting down the device.
4315  */
4316 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
4317 {
4318         spin_lock_bh(&tp->lock);
4319         if (irq_sync)
4320                 tg3_irq_quiesce(tp);
4321 }
4322
4323 static inline void tg3_full_unlock(struct tg3 *tp)
4324 {
4325         spin_unlock_bh(&tp->lock);
4326 }
4327
4328 /* One-shot MSI handler - Chip automatically disables interrupt
4329  * after sending MSI so driver doesn't have to do it.
4330  */
4331 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
4332 {
4333         struct net_device *dev = dev_id;
4334         struct tg3 *tp = netdev_priv(dev);
4335
4336         prefetch(tp->hw_status);
4337         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4338
4339         if (likely(!tg3_irq_sync(tp)))
4340                 netif_rx_schedule(dev, &tp->napi);
4341
4342         return IRQ_HANDLED;
4343 }
4344
4345 /* MSI ISR - No need to check for interrupt sharing and no need to
4346  * flush status block and interrupt mailbox. PCI ordering rules
4347  * guarantee that MSI will arrive after the status block.
4348  */
4349 static irqreturn_t tg3_msi(int irq, void *dev_id)
4350 {
4351         struct net_device *dev = dev_id;
4352         struct tg3 *tp = netdev_priv(dev);
4353
4354         prefetch(tp->hw_status);
4355         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4356         /*
4357          * Writing any value to intr-mbox-0 clears PCI INTA# and
4358          * chip-internal interrupt pending events.
4359          * Writing non-zero to intr-mbox-0 additional tells the
4360          * NIC to stop sending us irqs, engaging "in-intr-handler"
4361          * event coalescing.
4362          */
4363         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4364         if (likely(!tg3_irq_sync(tp)))
4365                 netif_rx_schedule(dev, &tp->napi);
4366
4367         return IRQ_RETVAL(1);
4368 }
4369
4370 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
4371 {
4372         struct net_device *dev = dev_id;
4373         struct tg3 *tp = netdev_priv(dev);
4374         struct tg3_hw_status *sblk = tp->hw_status;
4375         unsigned int handled = 1;
4376
4377         /* In INTx mode, it is possible for the interrupt to arrive at
4378          * the CPU before the status block posted prior to the interrupt.
4379          * Reading the PCI State register will confirm whether the
4380          * interrupt is ours and will flush the status block.
4381          */
4382         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
4383                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4384                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4385                         handled = 0;
4386                         goto out;
4387                 }
4388         }
4389
4390         /*
4391          * Writing any value to intr-mbox-0 clears PCI INTA# and
4392          * chip-internal interrupt pending events.
4393          * Writing non-zero to intr-mbox-0 additional tells the
4394          * NIC to stop sending us irqs, engaging "in-intr-handler"
4395          * event coalescing.
4396          *
4397          * Flush the mailbox to de-assert the IRQ immediately to prevent
4398          * spurious interrupts.  The flush impacts performance but
4399          * excessive spurious interrupts can be worse in some cases.
4400          */
4401         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4402         if (tg3_irq_sync(tp))
4403                 goto out;
4404         sblk->status &= ~SD_STATUS_UPDATED;
4405         if (likely(tg3_has_work(tp))) {
4406                 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4407                 netif_rx_schedule(dev, &tp->napi);
4408         } else {
4409                 /* No work, shared interrupt perhaps?  re-enable
4410                  * interrupts, and flush that PCI write
4411                  */
4412                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
4413                                0x00000000);
4414         }
4415 out:
4416         return IRQ_RETVAL(handled);
4417 }
4418
4419 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
4420 {
4421         struct net_device *dev = dev_id;
4422         struct tg3 *tp = netdev_priv(dev);
4423         struct tg3_hw_status *sblk = tp->hw_status;
4424         unsigned int handled = 1;
4425
4426         /* In INTx mode, it is possible for the interrupt to arrive at
4427          * the CPU before the status block posted prior to the interrupt.
4428          * Reading the PCI State register will confirm whether the
4429          * interrupt is ours and will flush the status block.
4430          */
4431         if (unlikely(sblk->status_tag == tp->last_tag)) {
4432                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4433                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4434                         handled = 0;
4435                         goto out;
4436                 }
4437         }
4438
4439         /*
4440          * writing any value to intr-mbox-0 clears PCI INTA# and
4441          * chip-internal interrupt pending events.
4442          * writing non-zero to intr-mbox-0 additional tells the
4443          * NIC to stop sending us irqs, engaging "in-intr-handler"
4444          * event coalescing.
4445          *
4446          * Flush the mailbox to de-assert the IRQ immediately to prevent
4447          * spurious interrupts.  The flush impacts performance but
4448          * excessive spurious interrupts can be worse in some cases.
4449          */
4450         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4451         if (tg3_irq_sync(tp))
4452                 goto out;
4453         if (netif_rx_schedule_prep(dev, &tp->napi)) {
4454                 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4455                 /* Update last_tag to mark that this status has been
4456                  * seen. Because interrupt may be shared, we may be
4457                  * racing with tg3_poll(), so only update last_tag
4458                  * if tg3_poll() is not scheduled.
4459                  */
4460                 tp->last_tag = sblk->status_tag;
4461                 __netif_rx_schedule(dev, &tp->napi);
4462         }
4463 out:
4464         return IRQ_RETVAL(handled);
4465 }
4466
4467 /* ISR for interrupt test */
4468 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
4469 {
4470         struct net_device *dev = dev_id;
4471         struct tg3 *tp = netdev_priv(dev);
4472         struct tg3_hw_status *sblk = tp->hw_status;
4473
4474         if ((sblk->status & SD_STATUS_UPDATED) ||
4475             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4476                 tg3_disable_ints(tp);
4477                 return IRQ_RETVAL(1);
4478         }
4479         return IRQ_RETVAL(0);
4480 }
4481
4482 static int tg3_init_hw(struct tg3 *, int);
4483 static int tg3_halt(struct tg3 *, int, int);
4484
4485 /* Restart hardware after configuration changes, self-test, etc.
4486  * Invoked with tp->lock held.
4487  */
4488 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
4489         __releases(tp->lock)
4490         __acquires(tp->lock)
4491 {
4492         int err;
4493
4494         err = tg3_init_hw(tp, reset_phy);
4495         if (err) {
4496                 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
4497                        "aborting.\n", tp->dev->name);
4498                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4499                 tg3_full_unlock(tp);
4500                 del_timer_sync(&tp->timer);
4501                 tp->irq_sync = 0;
4502                 napi_enable(&tp->napi);
4503                 dev_close(tp->dev);
4504                 tg3_full_lock(tp, 0);
4505         }
4506         return err;
4507 }
4508
4509 #ifdef CONFIG_NET_POLL_CONTROLLER
4510 static void tg3_poll_controller(struct net_device *dev)
4511 {
4512         struct tg3 *tp = netdev_priv(dev);
4513
4514         tg3_interrupt(tp->pdev->irq, dev);
4515 }
4516 #endif
4517
4518 static void tg3_reset_task(struct work_struct *work)
4519 {
4520         struct tg3 *tp = container_of(work, struct tg3, reset_task);
4521         int err;
4522         unsigned int restart_timer;
4523
4524         tg3_full_lock(tp, 0);
4525
4526         if (!netif_running(tp->dev)) {
4527                 tg3_full_unlock(tp);
4528                 return;
4529         }
4530
4531         tg3_full_unlock(tp);
4532
4533         tg3_phy_stop(tp);
4534
4535         tg3_netif_stop(tp);
4536
4537         tg3_full_lock(tp, 1);
4538
4539         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
4540         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
4541
4542         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
4543                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
4544                 tp->write32_rx_mbox = tg3_write_flush_reg32;
4545                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
4546                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
4547         }
4548
4549         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
4550         err = tg3_init_hw(tp, 1);
4551         if (err)
4552                 goto out;
4553
4554         tg3_netif_start(tp);
4555
4556         if (restart_timer)
4557                 mod_timer(&tp->timer, jiffies + 1);
4558
4559 out:
4560         tg3_full_unlock(tp);
4561
4562         if (!err)
4563                 tg3_phy_start(tp);
4564 }
4565
4566 static void tg3_dump_short_state(struct tg3 *tp)
4567 {
4568         printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
4569                tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
4570         printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
4571                tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
4572 }
4573
4574 static void tg3_tx_timeout(struct net_device *dev)
4575 {
4576         struct tg3 *tp = netdev_priv(dev);
4577
4578         if (netif_msg_tx_err(tp)) {
4579                 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
4580                        dev->name);
4581                 tg3_dump_short_state(tp);
4582         }
4583
4584         schedule_work(&tp->reset_task);
4585 }
4586
4587 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
4588 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
4589 {
4590         u32 base = (u32) mapping & 0xffffffff;
4591
4592         return ((base > 0xffffdcc0) &&
4593                 (base + len + 8 < base));
4594 }
4595
4596 /* Test for DMA addresses > 40-bit */
4597 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
4598                                           int len)
4599 {
4600 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
4601         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
4602                 return (((u64) mapping + len) > DMA_40BIT_MASK);
4603         return 0;
4604 #else
4605         return 0;
4606 #endif
4607 }
4608
4609 static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
4610
4611 /* Workaround 4GB and 40-bit hardware DMA bugs. */
4612 static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
4613                                        u32 last_plus_one, u32 *start,
4614                                        u32 base_flags, u32 mss)
4615 {
4616         struct sk_buff *new_skb;
4617         dma_addr_t new_addr = 0;
4618         u32 entry = *start;
4619         int i, ret = 0;
4620
4621         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
4622                 new_skb = skb_copy(skb, GFP_ATOMIC);
4623         else {
4624                 int more_headroom = 4 - ((unsigned long)skb->data & 3);
4625
4626                 new_skb = skb_copy_expand(skb,
4627                                           skb_headroom(skb) + more_headroom,
4628                                           skb_tailroom(skb), GFP_ATOMIC);
4629         }
4630
4631         if (!new_skb) {
4632                 ret = -1;
4633         } else {
4634                 /* New SKB is guaranteed to be linear. */
4635                 entry = *start;
4636                 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
4637                                           PCI_DMA_TODEVICE);
4638                 /* Make sure new skb does not cross any 4G boundaries.
4639                  * Drop the packet if it does.
4640                  */
4641                 if (tg3_4g_overflow_test(new_addr, new_skb->len)) {
4642                         ret = -1;
4643                         dev_kfree_skb(new_skb);
4644                         new_skb = NULL;
4645                 } else {
4646                         tg3_set_txd(tp, entry, new_addr, new_skb->len,
4647                                     base_flags, 1 | (mss << 1));
4648                         *start = NEXT_TX(entry);
4649                 }
4650         }
4651
4652         /* Now clean up the sw ring entries. */
4653         i = 0;
4654         while (entry != last_plus_one) {
4655                 int len;
4656
4657                 if (i == 0)
4658                         len = skb_headlen(skb);
4659                 else
4660                         len = skb_shinfo(skb)->frags[i-1].size;
4661                 pci_unmap_single(tp->pdev,
4662                                  pci_unmap_addr(&tp->tx_buffers[entry], mapping),
4663                                  len, PCI_DMA_TODEVICE);
4664                 if (i == 0) {
4665                         tp->tx_buffers[entry].skb = new_skb;
4666                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, new_addr);
4667                 } else {
4668                         tp->tx_buffers[entry].skb = NULL;
4669                 }
4670                 entry = NEXT_TX(entry);
4671                 i++;
4672         }
4673
4674         dev_kfree_skb(skb);
4675
4676         return ret;
4677 }
4678
4679 static void tg3_set_txd(struct tg3 *tp, int entry,
4680                         dma_addr_t mapping, int len, u32 flags,
4681                         u32 mss_and_is_end)
4682 {
4683         struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
4684         int is_end = (mss_and_is_end & 0x1);
4685         u32 mss = (mss_and_is_end >> 1);
4686         u32 vlan_tag = 0;
4687
4688         if (is_end)
4689                 flags |= TXD_FLAG_END;
4690         if (flags & TXD_FLAG_VLAN) {
4691                 vlan_tag = flags >> 16;
4692                 flags &= 0xffff;
4693         }
4694         vlan_tag |= (mss << TXD_MSS_SHIFT);
4695
4696         txd->addr_hi = ((u64) mapping >> 32);
4697         txd->addr_lo = ((u64) mapping & 0xffffffff);
4698         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
4699         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
4700 }
4701
4702 /* hard_start_xmit for devices that don't have any bugs and
4703  * support TG3_FLG2_HW_TSO_2 only.
4704  */
4705 static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
4706 {
4707         struct tg3 *tp = netdev_priv(dev);
4708         dma_addr_t mapping;
4709         u32 len, entry, base_flags, mss;
4710
4711         len = skb_headlen(skb);
4712
4713         /* We are running in BH disabled context with netif_tx_lock
4714          * and TX reclaim runs via tp->napi.poll inside of a software
4715          * interrupt.  Furthermore, IRQ processing runs lockless so we have
4716          * no IRQ context deadlocks to worry about either.  Rejoice!
4717          */
4718         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
4719                 if (!netif_queue_stopped(dev)) {
4720                         netif_stop_queue(dev);
4721
4722                         /* This is a hard error, log it. */
4723                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
4724                                "queue awake!\n", dev->name);
4725                 }
4726                 return NETDEV_TX_BUSY;
4727         }
4728
4729         entry = tp->tx_prod;
4730         base_flags = 0;
4731         mss = 0;
4732         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
4733                 int tcp_opt_len, ip_tcp_len;
4734
4735                 if (skb_header_cloned(skb) &&
4736                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4737                         dev_kfree_skb(skb);
4738                         goto out_unlock;
4739                 }
4740
4741                 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
4742                         mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
4743                 else {
4744                         struct iphdr *iph = ip_hdr(skb);
4745
4746                         tcp_opt_len = tcp_optlen(skb);
4747                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
4748
4749                         iph->check = 0;
4750                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
4751                         mss |= (ip_tcp_len + tcp_opt_len) << 9;
4752                 }
4753
4754                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
4755                                TXD_FLAG_CPU_POST_DMA);
4756
4757                 tcp_hdr(skb)->check = 0;
4758
4759         }
4760         else if (skb->ip_summed == CHECKSUM_PARTIAL)
4761                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
4762 #if TG3_VLAN_TAG_USED
4763         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
4764                 base_flags |= (TXD_FLAG_VLAN |
4765                                (vlan_tx_tag_get(skb) << 16));
4766 #endif
4767
4768         /* Queue skb data, a.k.a. the main skb fragment. */
4769         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
4770
4771         tp->tx_buffers[entry].skb = skb;
4772         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4773
4774         tg3_set_txd(tp, entry, mapping, len, base_flags,
4775                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
4776
4777         entry = NEXT_TX(entry);
4778
4779         /* Now loop through additional data fragments, and queue them. */
4780         if (skb_shinfo(skb)->nr_frags > 0) {
4781                 unsigned int i, last;
4782
4783                 last = skb_shinfo(skb)->nr_frags - 1;
4784                 for (i = 0; i <= last; i++) {
4785                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4786
4787                         len = frag->size;
4788                         mapping = pci_map_page(tp->pdev,
4789                                                frag->page,
4790                                                frag->page_offset,
4791                                                len, PCI_DMA_TODEVICE);
4792
4793                         tp->tx_buffers[entry].skb = NULL;
4794                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4795
4796                         tg3_set_txd(tp, entry, mapping, len,
4797                                     base_flags, (i == last) | (mss << 1));
4798
4799                         entry = NEXT_TX(entry);
4800                 }
4801         }
4802
4803         /* Packets are ready, update Tx producer idx local and on card. */
4804         tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
4805
4806         tp->tx_prod = entry;
4807         if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
4808                 netif_stop_queue(dev);
4809                 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
4810                         netif_wake_queue(tp->dev);
4811         }
4812
4813 out_unlock:
4814         mmiowb();
4815
4816         dev->trans_start = jiffies;
4817
4818         return NETDEV_TX_OK;
4819 }
4820
4821 static int tg3_start_xmit_dma_bug(struct sk_buff *, struct net_device *);
4822
4823 /* Use GSO to workaround a rare TSO bug that may be triggered when the
4824  * TSO header is greater than 80 bytes.
4825  */
4826 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
4827 {
4828         struct sk_buff *segs, *nskb;
4829
4830         /* Estimate the number of fragments in the worst case */
4831         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))) {
4832                 netif_stop_queue(tp->dev);
4833                 if (tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))
4834                         return NETDEV_TX_BUSY;
4835
4836                 netif_wake_queue(tp->dev);
4837         }
4838
4839         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
4840         if (IS_ERR(segs))
4841                 goto tg3_tso_bug_end;
4842
4843         do {
4844                 nskb = segs;
4845                 segs = segs->next;
4846                 nskb->next = NULL;
4847                 tg3_start_xmit_dma_bug(nskb, tp->dev);
4848         } while (segs);
4849
4850 tg3_tso_bug_end:
4851         dev_kfree_skb(skb);
4852
4853         return NETDEV_TX_OK;
4854 }
4855
4856 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
4857  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
4858  */
4859 static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
4860 {
4861         struct tg3 *tp = netdev_priv(dev);
4862         dma_addr_t mapping;
4863         u32 len, entry, base_flags, mss;
4864         int would_hit_hwbug;
4865
4866         len = skb_headlen(skb);
4867
4868         /* We are running in BH disabled context with netif_tx_lock
4869          * and TX reclaim runs via tp->napi.poll inside of a software
4870          * interrupt.  Furthermore, IRQ processing runs lockless so we have
4871          * no IRQ context deadlocks to worry about either.  Rejoice!
4872          */
4873         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
4874                 if (!netif_queue_stopped(dev)) {
4875                         netif_stop_queue(dev);
4876
4877                         /* This is a hard error, log it. */
4878                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
4879                                "queue awake!\n", dev->name);
4880                 }
4881                 return NETDEV_TX_BUSY;
4882         }
4883
4884         entry = tp->tx_prod;
4885         base_flags = 0;
4886         if (skb->ip_summed == CHECKSUM_PARTIAL)
4887                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
4888         mss = 0;
4889         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
4890                 struct iphdr *iph;
4891                 int tcp_opt_len, ip_tcp_len, hdr_len;
4892
4893                 if (skb_header_cloned(skb) &&
4894                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4895                         dev_kfree_skb(skb);
4896                         goto out_unlock;
4897                 }
4898
4899                 tcp_opt_len = tcp_optlen(skb);
4900                 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
4901
4902                 hdr_len = ip_tcp_len + tcp_opt_len;
4903                 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
4904                              (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
4905                         return (tg3_tso_bug(tp, skb));
4906
4907                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
4908                                TXD_FLAG_CPU_POST_DMA);
4909
4910                 iph = ip_hdr(skb);
4911                 iph->check = 0;
4912                 iph->tot_len = htons(mss + hdr_len);
4913                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
4914                         tcp_hdr(skb)->check = 0;
4915                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
4916                 } else
4917                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4918                                                                  iph->daddr, 0,
4919                                                                  IPPROTO_TCP,
4920                                                                  0);
4921
4922                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
4923                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
4924                         if (tcp_opt_len || iph->ihl > 5) {
4925                                 int tsflags;
4926
4927                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
4928                                 mss |= (tsflags << 11);
4929                         }
4930                 } else {
4931                         if (tcp_opt_len || iph->ihl > 5) {
4932                                 int tsflags;
4933
4934                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
4935                                 base_flags |= tsflags << 12;
4936                         }
4937                 }
4938         }
4939 #if TG3_VLAN_TAG_USED
4940         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
4941                 base_flags |= (TXD_FLAG_VLAN |
4942                                (vlan_tx_tag_get(skb) << 16));
4943 #endif
4944
4945         /* Queue skb data, a.k.a. the main skb fragment. */
4946         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
4947
4948         tp->tx_buffers[entry].skb = skb;
4949         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4950
4951         would_hit_hwbug = 0;
4952
4953         if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
4954                 would_hit_hwbug = 1;
4955         else if (tg3_4g_overflow_test(mapping, len))
4956                 would_hit_hwbug = 1;
4957
4958         tg3_set_txd(tp, entry, mapping, len, base_flags,
4959                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
4960
4961         entry = NEXT_TX(entry);
4962
4963         /* Now loop through additional data fragments, and queue them. */
4964         if (skb_shinfo(skb)->nr_frags > 0) {
4965                 unsigned int i, last;
4966
4967                 last = skb_shinfo(skb)->nr_frags - 1;
4968                 for (i = 0; i <= last; i++) {
4969                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4970
4971                         len = frag->size;
4972                         mapping = pci_map_page(tp->pdev,
4973                                                frag->page,
4974                                                frag->page_offset,
4975                                                len, PCI_DMA_TODEVICE);
4976
4977                         tp->tx_buffers[entry].skb = NULL;
4978                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4979
4980                         if (tg3_4g_overflow_test(mapping, len))
4981                                 would_hit_hwbug = 1;
4982
4983                         if (tg3_40bit_overflow_test(tp, mapping, len))
4984                                 would_hit_hwbug = 1;
4985
4986                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
4987                                 tg3_set_txd(tp, entry, mapping, len,
4988                                             base_flags, (i == last)|(mss << 1));
4989                         else
4990                                 tg3_set_txd(tp, entry, mapping, len,
4991                                             base_flags, (i == last));
4992
4993                         entry = NEXT_TX(entry);
4994                 }
4995         }
4996
4997         if (would_hit_hwbug) {
4998                 u32 last_plus_one = entry;
4999                 u32 start;
5000
5001                 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5002                 start &= (TG3_TX_RING_SIZE - 1);
5003
5004                 /* If the workaround fails due to memory/mapping
5005                  * failure, silently drop this packet.
5006                  */
5007                 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
5008                                                 &start, base_flags, mss))
5009                         goto out_unlock;
5010
5011                 entry = start;
5012         }
5013
5014         /* Packets are ready, update Tx producer idx local and on card. */
5015         tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
5016
5017         tp->tx_prod = entry;
5018         if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
5019                 netif_stop_queue(dev);
5020                 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
5021                         netif_wake_queue(tp->dev);
5022         }
5023
5024 out_unlock:
5025         mmiowb();
5026
5027         dev->trans_start = jiffies;
5028
5029         return NETDEV_TX_OK;
5030 }
5031
5032 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5033                                int new_mtu)
5034 {
5035         dev->mtu = new_mtu;
5036
5037         if (new_mtu > ETH_DATA_LEN) {
5038                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
5039                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5040                         ethtool_op_set_tso(dev, 0);
5041                 }
5042                 else
5043                         tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5044         } else {
5045                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
5046                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
5047                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
5048         }
5049 }
5050
5051 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5052 {
5053         struct tg3 *tp = netdev_priv(dev);
5054         int err;
5055
5056         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5057                 return -EINVAL;
5058
5059         if (!netif_running(dev)) {
5060                 /* We'll just catch it later when the
5061                  * device is up'd.
5062                  */
5063                 tg3_set_mtu(dev, tp, new_mtu);
5064                 return 0;
5065         }
5066
5067         tg3_phy_stop(tp);
5068
5069         tg3_netif_stop(tp);
5070
5071         tg3_full_lock(tp, 1);
5072
5073         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5074
5075         tg3_set_mtu(dev, tp, new_mtu);
5076
5077         err = tg3_restart_hw(tp, 0);
5078
5079         if (!err)
5080                 tg3_netif_start(tp);
5081
5082         tg3_full_unlock(tp);
5083
5084         if (!err)
5085                 tg3_phy_start(tp);
5086
5087         return err;
5088 }
5089
5090 /* Free up pending packets in all rx/tx rings.
5091  *
5092  * The chip has been shut down and the driver detached from
5093  * the networking, so no interrupts or new tx packets will
5094  * end up in the driver.  tp->{tx,}lock is not held and we are not
5095  * in an interrupt context and thus may sleep.
5096  */
5097 static void tg3_free_rings(struct tg3 *tp)
5098 {
5099         struct ring_info *rxp;
5100         int i;
5101
5102         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5103                 rxp = &tp->rx_std_buffers[i];
5104
5105                 if (rxp->skb == NULL)
5106                         continue;
5107                 pci_unmap_single(tp->pdev,
5108                                  pci_unmap_addr(rxp, mapping),
5109                                  tp->rx_pkt_buf_sz - tp->rx_offset,
5110                                  PCI_DMA_FROMDEVICE);
5111                 dev_kfree_skb_any(rxp->skb);
5112                 rxp->skb = NULL;
5113         }
5114
5115         for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5116                 rxp = &tp->rx_jumbo_buffers[i];
5117
5118                 if (rxp->skb == NULL)
5119                         continue;
5120                 pci_unmap_single(tp->pdev,
5121                                  pci_unmap_addr(rxp, mapping),
5122                                  RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
5123                                  PCI_DMA_FROMDEVICE);
5124                 dev_kfree_skb_any(rxp->skb);
5125                 rxp->skb = NULL;
5126         }
5127
5128         for (i = 0; i < TG3_TX_RING_SIZE; ) {
5129                 struct tx_ring_info *txp;
5130                 struct sk_buff *skb;
5131                 int j;
5132
5133                 txp = &tp->tx_buffers[i];
5134                 skb = txp->skb;
5135
5136                 if (skb == NULL) {
5137                         i++;
5138                         continue;
5139                 }
5140
5141                 pci_unmap_single(tp->pdev,
5142                                  pci_unmap_addr(txp, mapping),
5143                                  skb_headlen(skb),
5144                                  PCI_DMA_TODEVICE);
5145                 txp->skb = NULL;
5146
5147                 i++;
5148
5149                 for (j = 0; j < skb_shinfo(skb)->nr_frags; j++) {
5150                         txp = &tp->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
5151                         pci_unmap_page(tp->pdev,
5152                                        pci_unmap_addr(txp, mapping),
5153                                        skb_shinfo(skb)->frags[j].size,
5154                                        PCI_DMA_TODEVICE);
5155                         i++;
5156                 }
5157
5158                 dev_kfree_skb_any(skb);
5159         }
5160 }
5161
5162 /* Initialize tx/rx rings for packet processing.
5163  *
5164  * The chip has been shut down and the driver detached from
5165  * the networking, so no interrupts or new tx packets will
5166  * end up in the driver.  tp->{tx,}lock are held and thus
5167  * we may not sleep.
5168  */
5169 static int tg3_init_rings(struct tg3 *tp)
5170 {
5171         u32 i;
5172
5173         /* Free up all the SKBs. */
5174         tg3_free_rings(tp);
5175
5176         /* Zero out all descriptors. */
5177         memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
5178         memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
5179         memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
5180         memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
5181
5182         tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;
5183         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
5184             (tp->dev->mtu > ETH_DATA_LEN))
5185                 tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;
5186
5187         /* Initialize invariants of the rings, we only set this
5188          * stuff once.  This works because the card does not
5189          * write into the rx buffer posting rings.
5190          */
5191         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5192                 struct tg3_rx_buffer_desc *rxd;
5193
5194                 rxd = &tp->rx_std[i];
5195                 rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)
5196                         << RXD_LEN_SHIFT;
5197                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
5198                 rxd->opaque = (RXD_OPAQUE_RING_STD |
5199                                (i << RXD_OPAQUE_INDEX_SHIFT));
5200         }
5201
5202         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
5203                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5204                         struct tg3_rx_buffer_desc *rxd;
5205
5206                         rxd = &tp->rx_jumbo[i];
5207                         rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
5208                                 << RXD_LEN_SHIFT;
5209                         rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
5210                                 RXD_FLAG_JUMBO;
5211                         rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
5212                                (i << RXD_OPAQUE_INDEX_SHIFT));
5213                 }
5214         }
5215
5216         /* Now allocate fresh SKBs for each rx ring. */
5217         for (i = 0; i < tp->rx_pending; i++) {
5218                 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD, -1, i) < 0) {
5219                         printk(KERN_WARNING PFX
5220                                "%s: Using a smaller RX standard ring, "
5221                                "only %d out of %d buffers were allocated "
5222                                "successfully.\n",
5223                                tp->dev->name, i, tp->rx_pending);
5224                         if (i == 0)
5225                                 return -ENOMEM;
5226                         tp->rx_pending = i;
5227                         break;
5228                 }
5229         }
5230
5231         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
5232                 for (i = 0; i < tp->rx_jumbo_pending; i++) {
5233                         if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
5234                                              -1, i) < 0) {
5235                                 printk(KERN_WARNING PFX
5236                                        "%s: Using a smaller RX jumbo ring, "
5237                                        "only %d out of %d buffers were "
5238                                        "allocated successfully.\n",
5239                                        tp->dev->name, i, tp->rx_jumbo_pending);
5240                                 if (i == 0) {
5241                                         tg3_free_rings(tp);
5242                                         return -ENOMEM;
5243                                 }
5244                                 tp->rx_jumbo_pending = i;
5245                                 break;
5246                         }
5247                 }
5248         }
5249         return 0;
5250 }
5251
5252 /*
5253  * Must not be invoked with interrupt sources disabled and
5254  * the hardware shutdown down.
5255  */
5256 static void tg3_free_consistent(struct tg3 *tp)
5257 {
5258         kfree(tp->rx_std_buffers);
5259         tp->rx_std_buffers = NULL;
5260         if (tp->rx_std) {
5261                 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
5262                                     tp->rx_std, tp->rx_std_mapping);
5263                 tp->rx_std = NULL;
5264         }
5265         if (tp->rx_jumbo) {
5266                 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
5267                                     tp->rx_jumbo, tp->rx_jumbo_mapping);
5268                 tp->rx_jumbo = NULL;
5269         }
5270         if (tp->rx_rcb) {
5271                 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5272                                     tp->rx_rcb, tp->rx_rcb_mapping);
5273                 tp->rx_rcb = NULL;
5274         }
5275         if (tp->tx_ring) {
5276                 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
5277                         tp->tx_ring, tp->tx_desc_mapping);
5278                 tp->tx_ring = NULL;
5279         }
5280         if (tp->hw_status) {
5281                 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
5282                                     tp->hw_status, tp->status_mapping);
5283                 tp->hw_status = NULL;
5284         }
5285         if (tp->hw_stats) {
5286                 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
5287                                     tp->hw_stats, tp->stats_mapping);
5288                 tp->hw_stats = NULL;
5289         }
5290 }
5291
5292 /*
5293  * Must not be invoked with interrupt sources disabled and
5294  * the hardware shutdown down.  Can sleep.
5295  */
5296 static int tg3_alloc_consistent(struct tg3 *tp)
5297 {
5298         tp->rx_std_buffers = kzalloc((sizeof(struct ring_info) *
5299                                       (TG3_RX_RING_SIZE +
5300                                        TG3_RX_JUMBO_RING_SIZE)) +
5301                                      (sizeof(struct tx_ring_info) *
5302                                       TG3_TX_RING_SIZE),
5303                                      GFP_KERNEL);
5304         if (!tp->rx_std_buffers)
5305                 return -ENOMEM;
5306
5307         tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
5308         tp->tx_buffers = (struct tx_ring_info *)
5309                 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
5310
5311         tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
5312                                           &tp->rx_std_mapping);
5313         if (!tp->rx_std)
5314                 goto err_out;
5315
5316         tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
5317                                             &tp->rx_jumbo_mapping);
5318
5319         if (!tp->rx_jumbo)
5320                 goto err_out;
5321
5322         tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5323                                           &tp->rx_rcb_mapping);
5324         if (!tp->rx_rcb)
5325                 goto err_out;
5326
5327         tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
5328                                            &tp->tx_desc_mapping);
5329         if (!tp->tx_ring)
5330                 goto err_out;
5331
5332         tp->hw_status = pci_alloc_consistent(tp->pdev,
5333                                              TG3_HW_STATUS_SIZE,
5334                                              &tp->status_mapping);
5335         if (!tp->hw_status)
5336                 goto err_out;
5337
5338         tp->hw_stats = pci_alloc_consistent(tp->pdev,
5339                                             sizeof(struct tg3_hw_stats),
5340                                             &tp->stats_mapping);
5341         if (!tp->hw_stats)
5342                 goto err_out;
5343
5344         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5345         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5346
5347         return 0;
5348
5349 err_out:
5350         tg3_free_consistent(tp);
5351         return -ENOMEM;
5352 }
5353
5354 #define MAX_WAIT_CNT 1000
5355
5356 /* To stop a block, clear the enable bit and poll till it
5357  * clears.  tp->lock is held.
5358  */
5359 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
5360 {
5361         unsigned int i;
5362         u32 val;
5363
5364         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
5365                 switch (ofs) {
5366                 case RCVLSC_MODE:
5367                 case DMAC_MODE:
5368                 case MBFREE_MODE:
5369                 case BUFMGR_MODE:
5370                 case MEMARB_MODE:
5371                         /* We can't enable/disable these bits of the
5372                          * 5705/5750, just say success.
5373                          */
5374                         return 0;
5375
5376                 default:
5377                         break;
5378                 }
5379         }
5380
5381         val = tr32(ofs);
5382         val &= ~enable_bit;
5383         tw32_f(ofs, val);
5384
5385         for (i = 0; i < MAX_WAIT_CNT; i++) {
5386                 udelay(100);
5387                 val = tr32(ofs);
5388                 if ((val & enable_bit) == 0)
5389                         break;
5390         }
5391
5392         if (i == MAX_WAIT_CNT && !silent) {
5393                 printk(KERN_ERR PFX "tg3_stop_block timed out, "
5394                        "ofs=%lx enable_bit=%x\n",
5395                        ofs, enable_bit);
5396                 return -ENODEV;
5397         }
5398
5399         return 0;
5400 }
5401
5402 /* tp->lock is held. */
5403 static int tg3_abort_hw(struct tg3 *tp, int silent)
5404 {
5405         int i, err;
5406
5407         tg3_disable_ints(tp);
5408
5409         tp->rx_mode &= ~RX_MODE_ENABLE;
5410         tw32_f(MAC_RX_MODE, tp->rx_mode);
5411         udelay(10);
5412
5413         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
5414         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
5415         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
5416         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
5417         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
5418         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
5419
5420         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
5421         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
5422         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
5423         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
5424         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
5425         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
5426         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
5427
5428         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
5429         tw32_f(MAC_MODE, tp->mac_mode);
5430         udelay(40);
5431
5432         tp->tx_mode &= ~TX_MODE_ENABLE;
5433         tw32_f(MAC_TX_MODE, tp->tx_mode);
5434
5435         for (i = 0; i < MAX_WAIT_CNT; i++) {
5436                 udelay(100);
5437                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
5438                         break;
5439         }
5440         if (i >= MAX_WAIT_CNT) {
5441                 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
5442                        "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
5443                        tp->dev->name, tr32(MAC_TX_MODE));
5444                 err |= -ENODEV;
5445         }
5446
5447         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
5448         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
5449         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
5450
5451         tw32(FTQ_RESET, 0xffffffff);
5452         tw32(FTQ_RESET, 0x00000000);
5453
5454         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
5455         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
5456
5457         if (tp->hw_status)
5458                 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5459         if (tp->hw_stats)
5460                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5461
5462         return err;
5463 }
5464
5465 /* tp->lock is held. */
5466 static int tg3_nvram_lock(struct tg3 *tp)
5467 {
5468         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
5469                 int i;
5470
5471                 if (tp->nvram_lock_cnt == 0) {
5472                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
5473                         for (i = 0; i < 8000; i++) {
5474                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
5475                                         break;
5476                                 udelay(20);
5477                         }
5478                         if (i == 8000) {
5479                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
5480                                 return -ENODEV;
5481                         }
5482                 }
5483                 tp->nvram_lock_cnt++;
5484         }
5485         return 0;
5486 }
5487
5488 /* tp->lock is held. */
5489 static void tg3_nvram_unlock(struct tg3 *tp)
5490 {
5491         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
5492                 if (tp->nvram_lock_cnt > 0)
5493                         tp->nvram_lock_cnt--;
5494                 if (tp->nvram_lock_cnt == 0)
5495                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
5496         }
5497 }
5498
5499 /* tp->lock is held. */
5500 static void tg3_enable_nvram_access(struct tg3 *tp)
5501 {
5502         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
5503             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
5504                 u32 nvaccess = tr32(NVRAM_ACCESS);
5505
5506                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
5507         }
5508 }
5509
5510 /* tp->lock is held. */
5511 static void tg3_disable_nvram_access(struct tg3 *tp)
5512 {
5513         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
5514             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
5515                 u32 nvaccess = tr32(NVRAM_ACCESS);
5516
5517                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
5518         }
5519 }
5520
5521 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
5522 {
5523         int i;
5524         u32 apedata;
5525
5526         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
5527         if (apedata != APE_SEG_SIG_MAGIC)
5528                 return;
5529
5530         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
5531         if (!(apedata & APE_FW_STATUS_READY))
5532                 return;
5533
5534         /* Wait for up to 1 millisecond for APE to service previous event. */
5535         for (i = 0; i < 10; i++) {
5536                 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
5537                         return;
5538
5539                 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
5540
5541                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5542                         tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
5543                                         event | APE_EVENT_STATUS_EVENT_PENDING);
5544
5545                 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
5546
5547                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5548                         break;
5549
5550                 udelay(100);
5551         }
5552
5553         if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5554                 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
5555 }
5556
5557 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
5558 {
5559         u32 event;
5560         u32 apedata;
5561
5562         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
5563                 return;
5564
5565         switch (kind) {
5566                 case RESET_KIND_INIT:
5567                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
5568                                         APE_HOST_SEG_SIG_MAGIC);
5569                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
5570                                         APE_HOST_SEG_LEN_MAGIC);
5571                         apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
5572                         tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
5573                         tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
5574                                         APE_HOST_DRIVER_ID_MAGIC);
5575                         tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
5576                                         APE_HOST_BEHAV_NO_PHYLOCK);
5577
5578                         event = APE_EVENT_STATUS_STATE_START;
5579                         break;
5580                 case RESET_KIND_SHUTDOWN:
5581                         event = APE_EVENT_STATUS_STATE_UNLOAD;
5582                         break;
5583                 case RESET_KIND_SUSPEND:
5584                         event = APE_EVENT_STATUS_STATE_SUSPEND;
5585                         break;
5586                 default:
5587                         return;
5588         }
5589
5590         event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
5591
5592         tg3_ape_send_event(tp, event);
5593 }
5594
5595 /* tp->lock is held. */
5596 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
5597 {
5598         tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
5599                       NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
5600
5601         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
5602                 switch (kind) {
5603                 case RESET_KIND_INIT:
5604                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5605                                       DRV_STATE_START);
5606                         break;
5607
5608                 case RESET_KIND_SHUTDOWN:
5609                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5610                                       DRV_STATE_UNLOAD);
5611                         break;
5612
5613                 case RESET_KIND_SUSPEND:
5614                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5615                                       DRV_STATE_SUSPEND);
5616                         break;
5617
5618                 default:
5619                         break;
5620                 }
5621         }
5622
5623         if (kind == RESET_KIND_INIT ||
5624             kind == RESET_KIND_SUSPEND)
5625                 tg3_ape_driver_state_change(tp, kind);
5626 }
5627
5628 /* tp->lock is held. */
5629 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
5630 {
5631         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
5632                 switch (kind) {
5633                 case RESET_KIND_INIT:
5634                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5635                                       DRV_STATE_START_DONE);
5636                         break;
5637
5638                 case RESET_KIND_SHUTDOWN:
5639                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5640                                       DRV_STATE_UNLOAD_DONE);
5641                         break;
5642
5643                 default:
5644                         break;
5645                 }
5646         }
5647
5648         if (kind == RESET_KIND_SHUTDOWN)
5649                 tg3_ape_driver_state_change(tp, kind);
5650 }
5651
5652 /* tp->lock is held. */
5653 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
5654 {
5655         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
5656                 switch (kind) {
5657                 case RESET_KIND_INIT:
5658                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5659                                       DRV_STATE_START);
5660                         break;
5661
5662                 case RESET_KIND_SHUTDOWN:
5663                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5664                                       DRV_STATE_UNLOAD);
5665                         break;
5666
5667                 case RESET_KIND_SUSPEND:
5668                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5669                                       DRV_STATE_SUSPEND);
5670                         break;
5671
5672                 default:
5673                         break;
5674                 }
5675         }
5676 }
5677
5678 static int tg3_poll_fw(struct tg3 *tp)
5679 {
5680         int i;
5681         u32 val;
5682
5683         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5684                 /* Wait up to 20ms for init done. */
5685                 for (i = 0; i < 200; i++) {
5686                         if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
5687                                 return 0;
5688                         udelay(100);
5689                 }
5690                 return -ENODEV;
5691         }
5692
5693         /* Wait for firmware initialization to complete. */
5694         for (i = 0; i < 100000; i++) {
5695                 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
5696                 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
5697                         break;
5698                 udelay(10);
5699         }
5700
5701         /* Chip might not be fitted with firmware.  Some Sun onboard
5702          * parts are configured like that.  So don't signal the timeout
5703          * of the above loop as an error, but do report the lack of
5704          * running firmware once.
5705          */
5706         if (i >= 100000 &&
5707             !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
5708                 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
5709
5710                 printk(KERN_INFO PFX "%s: No firmware running.\n",
5711                        tp->dev->name);
5712         }
5713
5714         return 0;
5715 }
5716
5717 /* Save PCI command register before chip reset */
5718 static void tg3_save_pci_state(struct tg3 *tp)
5719 {
5720         pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
5721 }
5722
5723 /* Restore PCI state after chip reset */
5724 static void tg3_restore_pci_state(struct tg3 *tp)
5725 {
5726         u32 val;
5727
5728         /* Re-enable indirect register accesses. */
5729         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
5730                                tp->misc_host_ctrl);
5731
5732         /* Set MAX PCI retry to zero. */
5733         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
5734         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
5735             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
5736                 val |= PCISTATE_RETRY_SAME_DMA;
5737         /* Allow reads and writes to the APE register and memory space. */
5738         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
5739                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
5740                        PCISTATE_ALLOW_APE_SHMEM_WR;
5741         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
5742
5743         pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
5744
5745         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
5746                 pcie_set_readrq(tp->pdev, 4096);
5747         else {
5748                 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
5749                                       tp->pci_cacheline_sz);
5750                 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
5751                                       tp->pci_lat_timer);
5752         }
5753
5754         /* Make sure PCI-X relaxed ordering bit is clear. */
5755         if (tp->pcix_cap) {
5756                 u16 pcix_cmd;
5757
5758                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
5759                                      &pcix_cmd);
5760                 pcix_cmd &= ~PCI_X_CMD_ERO;
5761                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
5762                                       pcix_cmd);
5763         }
5764
5765         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
5766
5767                 /* Chip reset on 5780 will reset MSI enable bit,
5768                  * so need to restore it.
5769                  */
5770                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
5771                         u16 ctrl;
5772
5773                         pci_read_config_word(tp->pdev,
5774                                              tp->msi_cap + PCI_MSI_FLAGS,
5775                                              &ctrl);
5776                         pci_write_config_word(tp->pdev,
5777                                               tp->msi_cap + PCI_MSI_FLAGS,
5778                                               ctrl | PCI_MSI_FLAGS_ENABLE);
5779                         val = tr32(MSGINT_MODE);
5780                         tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
5781                 }
5782         }
5783 }
5784
5785 static void tg3_stop_fw(struct tg3 *);
5786
5787 /* tp->lock is held. */
5788 static int tg3_chip_reset(struct tg3 *tp)
5789 {
5790         u32 val;
5791         void (*write_op)(struct tg3 *, u32, u32);
5792         int err;
5793
5794         tg3_nvram_lock(tp);
5795
5796         tg3_mdio_stop(tp);
5797
5798         tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
5799
5800         /* No matching tg3_nvram_unlock() after this because
5801          * chip reset below will undo the nvram lock.
5802          */
5803         tp->nvram_lock_cnt = 0;
5804
5805         /* GRC_MISC_CFG core clock reset will clear the memory
5806          * enable bit in PCI register 4 and the MSI enable bit
5807          * on some chips, so we save relevant registers here.
5808          */
5809         tg3_save_pci_state(tp);
5810
5811         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
5812             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
5813             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
5814             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
5815             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
5816             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
5817                 tw32(GRC_FASTBOOT_PC, 0);
5818
5819         /*
5820          * We must avoid the readl() that normally takes place.
5821          * It locks machines, causes machine checks, and other
5822          * fun things.  So, temporarily disable the 5701
5823          * hardware workaround, while we do the reset.
5824          */
5825         write_op = tp->write32;
5826         if (write_op == tg3_write_flush_reg32)
5827                 tp->write32 = tg3_write32;
5828
5829         /* Prevent the irq handler from reading or writing PCI registers
5830          * during chip reset when the memory enable bit in the PCI command
5831          * register may be cleared.  The chip does not generate interrupt
5832          * at this time, but the irq handler may still be called due to irq
5833          * sharing or irqpoll.
5834          */
5835         tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
5836         if (tp->hw_status) {
5837                 tp->hw_status->status = 0;
5838                 tp->hw_status->status_tag = 0;
5839         }
5840         tp->last_tag = 0;
5841         smp_mb();
5842         synchronize_irq(tp->pdev->irq);
5843
5844         /* do the reset */
5845         val = GRC_MISC_CFG_CORECLK_RESET;
5846
5847         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
5848                 if (tr32(0x7e2c) == 0x60) {
5849                         tw32(0x7e2c, 0x20);
5850                 }
5851                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
5852                         tw32(GRC_MISC_CFG, (1 << 29));
5853                         val |= (1 << 29);
5854                 }
5855         }
5856
5857         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5858                 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
5859                 tw32(GRC_VCPU_EXT_CTRL,
5860                      tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
5861         }
5862
5863         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
5864                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
5865         tw32(GRC_MISC_CFG, val);
5866
5867         /* restore 5701 hardware bug workaround write method */
5868         tp->write32 = write_op;
5869
5870         /* Unfortunately, we have to delay before the PCI read back.
5871          * Some 575X chips even will not respond to a PCI cfg access
5872          * when the reset command is given to the chip.
5873          *
5874          * How do these hardware designers expect things to work
5875          * properly if the PCI write is posted for a long period
5876          * of time?  It is always necessary to have some method by
5877          * which a register read back can occur to push the write
5878          * out which does the reset.
5879          *
5880          * For most tg3 variants the trick below was working.
5881          * Ho hum...
5882          */
5883         udelay(120);
5884
5885         /* Flush PCI posted writes.  The normal MMIO registers
5886          * are inaccessible at this time so this is the only
5887          * way to make this reliably (actually, this is no longer
5888          * the case, see above).  I tried to use indirect
5889          * register read/write but this upset some 5701 variants.
5890          */
5891         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
5892
5893         udelay(120);
5894
5895         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
5896                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
5897                         int i;
5898                         u32 cfg_val;
5899
5900                         /* Wait for link training to complete.  */
5901                         for (i = 0; i < 5000; i++)
5902                                 udelay(100);
5903
5904                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
5905                         pci_write_config_dword(tp->pdev, 0xc4,
5906                                                cfg_val | (1 << 15));
5907                 }
5908                 /* Set PCIE max payload size and clear error status.  */
5909                 pci_write_config_dword(tp->pdev, 0xd8, 0xf5000);
5910         }
5911
5912         tg3_restore_pci_state(tp);
5913
5914         tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
5915
5916         val = 0;
5917         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
5918                 val = tr32(MEMARB_MODE);
5919         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
5920
5921         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
5922                 tg3_stop_fw(tp);
5923                 tw32(0x5000, 0x400);
5924         }
5925
5926         tw32(GRC_MODE, tp->grc_mode);
5927
5928         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
5929                 val = tr32(0xc4);
5930
5931                 tw32(0xc4, val | (1 << 15));
5932         }
5933
5934         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
5935             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5936                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
5937                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
5938                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
5939                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
5940         }
5941
5942         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
5943                 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
5944                 tw32_f(MAC_MODE, tp->mac_mode);
5945         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
5946                 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
5947                 tw32_f(MAC_MODE, tp->mac_mode);
5948         } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
5949                 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
5950                 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
5951                         tp->mac_mode |= MAC_MODE_TDE_ENABLE;
5952                 tw32_f(MAC_MODE, tp->mac_mode);
5953         } else
5954                 tw32_f(MAC_MODE, 0);
5955         udelay(40);
5956
5957         tg3_mdio_start(tp);
5958
5959         tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
5960
5961         err = tg3_poll_fw(tp);
5962         if (err)
5963                 return err;
5964
5965         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
5966             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
5967                 val = tr32(0x7c00);
5968
5969                 tw32(0x7c00, val | (1 << 25));
5970         }
5971
5972         /* Reprobe ASF enable state.  */
5973         tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
5974         tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
5975         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
5976         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
5977                 u32 nic_cfg;
5978
5979                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
5980                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
5981                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
5982                         tp->last_event_jiffies = jiffies;
5983                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
5984                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
5985                 }
5986         }
5987
5988         return 0;
5989 }
5990
5991 /* tp->lock is held. */
5992 static void tg3_stop_fw(struct tg3 *tp)
5993 {
5994         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
5995            !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
5996                 /* Wait for RX cpu to ACK the previous event. */
5997                 tg3_wait_for_event_ack(tp);
5998
5999                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
6000
6001                 tg3_generate_fw_event(tp);
6002
6003                 /* Wait for RX cpu to ACK this event. */
6004                 tg3_wait_for_event_ack(tp);
6005         }
6006 }
6007
6008 /* tp->lock is held. */
6009 static int tg3_halt(struct tg3 *tp, int kind, int silent)
6010 {
6011         int err;
6012
6013         tg3_stop_fw(tp);
6014
6015         tg3_write_sig_pre_reset(tp, kind);
6016
6017         tg3_abort_hw(tp, silent);
6018         err = tg3_chip_reset(tp);
6019
6020         tg3_write_sig_legacy(tp, kind);
6021         tg3_write_sig_post_reset(tp, kind);
6022
6023         if (err)
6024                 return err;
6025
6026         return 0;
6027 }
6028
6029 #define TG3_FW_RELEASE_MAJOR    0x0
6030 #define TG3_FW_RELASE_MINOR     0x0
6031 #define TG3_FW_RELEASE_FIX      0x0
6032 #define TG3_FW_START_ADDR       0x08000000
6033 #define TG3_FW_TEXT_ADDR        0x08000000
6034 #define TG3_FW_TEXT_LEN         0x9c0
6035 #define TG3_FW_RODATA_ADDR      0x080009c0
6036 #define TG3_FW_RODATA_LEN       0x60
6037 #define TG3_FW_DATA_ADDR        0x08000a40
6038 #define TG3_FW_DATA_LEN         0x20
6039 #define TG3_FW_SBSS_ADDR        0x08000a60
6040 #define TG3_FW_SBSS_LEN         0xc
6041 #define TG3_FW_BSS_ADDR         0x08000a70
6042 #define TG3_FW_BSS_LEN          0x10
6043
6044 static const u32 tg3FwText[(TG3_FW_TEXT_LEN / sizeof(u32)) + 1] = {
6045         0x00000000, 0x10000003, 0x00000000, 0x0000000d, 0x0000000d, 0x3c1d0800,
6046         0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100000, 0x0e000018, 0x00000000,
6047         0x0000000d, 0x3c1d0800, 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100034,
6048         0x0e00021c, 0x00000000, 0x0000000d, 0x00000000, 0x00000000, 0x00000000,
6049         0x27bdffe0, 0x3c1cc000, 0xafbf0018, 0xaf80680c, 0x0e00004c, 0x241b2105,
6050         0x97850000, 0x97870002, 0x9782002c, 0x9783002e, 0x3c040800, 0x248409c0,
6051         0xafa00014, 0x00021400, 0x00621825, 0x00052c00, 0xafa30010, 0x8f860010,
6052         0x00e52825, 0x0e000060, 0x24070102, 0x3c02ac00, 0x34420100, 0x3c03ac01,
6053         0x34630100, 0xaf820490, 0x3c02ffff, 0xaf820494, 0xaf830498, 0xaf82049c,
6054         0x24020001, 0xaf825ce0, 0x0e00003f, 0xaf825d00, 0x0e000140, 0x00000000,
6055         0x8fbf0018, 0x03e00008, 0x27bd0020, 0x2402ffff, 0xaf825404, 0x8f835400,
6056         0x34630400, 0xaf835400, 0xaf825404, 0x3c020800, 0x24420034, 0xaf82541c,
6057         0x03e00008, 0xaf805400, 0x00000000, 0x00000000, 0x3c020800, 0x34423000,
6058         0x3c030800, 0x34633000, 0x3c040800, 0x348437ff, 0x3c010800, 0xac220a64,
6059         0x24020040, 0x3c010800, 0xac220a68, 0x3c010800, 0xac200a60, 0xac600000,
6060         0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
6061         0x00804821, 0x8faa0010, 0x3c020800, 0x8c420a60, 0x3c040800, 0x8c840a68,
6062         0x8fab0014, 0x24430001, 0x0044102b, 0x3c010800, 0xac230a60, 0x14400003,
6063         0x00004021, 0x3c010800, 0xac200a60, 0x3c020800, 0x8c420a60, 0x3c030800,
6064         0x8c630a64, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
6065         0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020800, 0x8c420a60,
6066         0x3c030800, 0x8c630a64, 0x8f84680c, 0x00021140, 0x00431021, 0xac440008,
6067         0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
6068         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6069         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6070         0, 0, 0, 0, 0, 0,
6071         0x02000008, 0x00000000, 0x0a0001e3, 0x3c0a0001, 0x0a0001e3, 0x3c0a0002,
6072         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
6073         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
6074         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
6075         0x0a0001e3, 0x3c0a0007, 0x0a0001e3, 0x3c0a0008, 0x0a0001e3, 0x3c0a0009,
6076         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000b,
6077         0x0a0001e3, 0x3c0a000c, 0x0a0001e3, 0x3c0a000d, 0x0a0001e3, 0x00000000,
6078         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000e, 0x0a0001e3, 0x00000000,
6079         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
6080         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
6081         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a0013, 0x0a0001e3, 0x3c0a0014,
6082         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6083         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6084         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6085         0x27bdffe0, 0x00001821, 0x00001021, 0xafbf0018, 0xafb10014, 0xafb00010,
6086         0x3c010800, 0x00220821, 0xac200a70, 0x3c010800, 0x00220821, 0xac200a74,
6087         0x3c010800, 0x00220821, 0xac200a78, 0x24630001, 0x1860fff5, 0x2442000c,
6088         0x24110001, 0x8f906810, 0x32020004, 0x14400005, 0x24040001, 0x3c020800,
6089         0x8c420a78, 0x18400003, 0x00002021, 0x0e000182, 0x00000000, 0x32020001,
6090         0x10400003, 0x00000000, 0x0e000169, 0x00000000, 0x0a000153, 0xaf915028,
6091         0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x3c050800,
6092         0x8ca50a70, 0x3c060800, 0x8cc60a80, 0x3c070800, 0x8ce70a78, 0x27bdffe0,
6093         0x3c040800, 0x248409d0, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014,
6094         0x0e00017b, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x24020001,
6095         0x8f836810, 0x00821004, 0x00021027, 0x00621824, 0x03e00008, 0xaf836810,
6096         0x27bdffd8, 0xafbf0024, 0x1080002e, 0xafb00020, 0x8f825cec, 0xafa20018,
6097         0x8f825cec, 0x3c100800, 0x26100a78, 0xafa2001c, 0x34028000, 0xaf825cec,
6098         0x8e020000, 0x18400016, 0x00000000, 0x3c020800, 0x94420a74, 0x8fa3001c,
6099         0x000221c0, 0xac830004, 0x8fa2001c, 0x3c010800, 0x0e000201, 0xac220a74,
6100         0x10400005, 0x00000000, 0x8e020000, 0x24420001, 0x0a0001df, 0xae020000,
6101         0x3c020800, 0x8c420a70, 0x00021c02, 0x000321c0, 0x0a0001c5, 0xafa2001c,
6102         0x0e000201, 0x00000000, 0x1040001f, 0x00000000, 0x8e020000, 0x8fa3001c,
6103         0x24420001, 0x3c010800, 0xac230a70, 0x3c010800, 0xac230a74, 0x0a0001df,
6104         0xae020000, 0x3c100800, 0x26100a78, 0x8e020000, 0x18400028, 0x00000000,
6105         0x0e000201, 0x00000000, 0x14400024, 0x00000000, 0x8e020000, 0x3c030800,
6106         0x8c630a70, 0x2442ffff, 0xafa3001c, 0x18400006, 0xae020000, 0x00031402,
6107         0x000221c0, 0x8c820004, 0x3c010800, 0xac220a70, 0x97a2001e, 0x2442ff00,
6108         0x2c420300, 0x1440000b, 0x24024000, 0x3c040800, 0x248409dc, 0xafa00010,
6109         0xafa00014, 0x8fa6001c, 0x24050008, 0x0e000060, 0x00003821, 0x0a0001df,
6110         0x00000000, 0xaf825cf8, 0x3c020800, 0x8c420a40, 0x8fa3001c, 0x24420001,
6111         0xaf835cf8, 0x3c010800, 0xac220a40, 0x8fbf0024, 0x8fb00020, 0x03e00008,
6112         0x27bd0028, 0x27bdffe0, 0x3c040800, 0x248409e8, 0x00002821, 0x00003021,
6113         0x00003821, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x8fbf0018,
6114         0x03e00008, 0x27bd0020, 0x8f82680c, 0x8f85680c, 0x00021827, 0x0003182b,
6115         0x00031823, 0x00431024, 0x00441021, 0x00a2282b, 0x10a00006, 0x00000000,
6116         0x00401821, 0x8f82680c, 0x0043102b, 0x1440fffd, 0x00000000, 0x03e00008,
6117         0x00000000, 0x3c040800, 0x8c840000, 0x3c030800, 0x8c630a40, 0x0064102b,
6118         0x54400002, 0x00831023, 0x00641023, 0x2c420008, 0x03e00008, 0x38420001,
6119         0x27bdffe0, 0x00802821, 0x3c040800, 0x24840a00, 0x00003021, 0x00003821,
6120         0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x0a000216, 0x00000000,
6121         0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000, 0x27bdffe0, 0x3c1cc000,
6122         0xafbf0018, 0x0e00004c, 0xaf80680c, 0x3c040800, 0x24840a10, 0x03802821,
6123         0x00003021, 0x00003821, 0xafa00010, 0x0e000060, 0xafa00014, 0x2402ffff,
6124         0xaf825404, 0x3c0200aa, 0x0e000234, 0xaf825434, 0x8fbf0018, 0x03e00008,
6125         0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe8, 0xafb00010,
6126         0x24100001, 0xafbf0014, 0x3c01c003, 0xac200000, 0x8f826810, 0x30422000,
6127         0x10400003, 0x00000000, 0x0e000246, 0x00000000, 0x0a00023a, 0xaf905428,
6128         0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x27bdfff8, 0x8f845d0c,
6129         0x3c0200ff, 0x3c030800, 0x8c630a50, 0x3442fff8, 0x00821024, 0x1043001e,
6130         0x3c0500ff, 0x34a5fff8, 0x3c06c003, 0x3c074000, 0x00851824, 0x8c620010,
6131         0x3c010800, 0xac230a50, 0x30420008, 0x10400005, 0x00871025, 0x8cc20000,
6132         0x24420001, 0xacc20000, 0x00871025, 0xaf825d0c, 0x8fa20000, 0x24420001,
6133         0xafa20000, 0x8fa20000, 0x8fa20000, 0x24420001, 0xafa20000, 0x8fa20000,
6134         0x8f845d0c, 0x3c030800, 0x8c630a50, 0x00851024, 0x1443ffe8, 0x00851824,
6135         0x27bd0008, 0x03e00008, 0x00000000, 0x00000000, 0x00000000
6136 };
6137
6138 static const u32 tg3FwRodata[(TG3_FW_RODATA_LEN / sizeof(u32)) + 1] = {
6139         0x35373031, 0x726c7341, 0x00000000, 0x00000000, 0x53774576, 0x656e7430,
6140         0x00000000, 0x726c7045, 0x76656e74, 0x31000000, 0x556e6b6e, 0x45766e74,
6141         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
6142         0x00000000, 0x00000000, 0x4d61696e, 0x43707542, 0x00000000, 0x00000000,
6143         0x00000000
6144 };
6145
6146 #if 0 /* All zeros, don't eat up space with it. */
6147 u32 tg3FwData[(TG3_FW_DATA_LEN / sizeof(u32)) + 1] = {
6148         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
6149         0x00000000, 0x00000000, 0x00000000, 0x00000000
6150 };
6151 #endif
6152
6153 #define RX_CPU_SCRATCH_BASE     0x30000
6154 #define RX_CPU_SCRATCH_SIZE     0x04000
6155 #define TX_CPU_SCRATCH_BASE     0x34000
6156 #define TX_CPU_SCRATCH_SIZE     0x04000
6157
6158 /* tp->lock is held. */
6159 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
6160 {
6161         int i;
6162
6163         BUG_ON(offset == TX_CPU_BASE &&
6164             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
6165
6166         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6167                 u32 val = tr32(GRC_VCPU_EXT_CTRL);
6168
6169                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
6170                 return 0;
6171         }
6172         if (offset == RX_CPU_BASE) {
6173                 for (i = 0; i < 10000; i++) {
6174                         tw32(offset + CPU_STATE, 0xffffffff);
6175                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
6176                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6177                                 break;
6178                 }
6179
6180                 tw32(offset + CPU_STATE, 0xffffffff);
6181                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
6182                 udelay(10);
6183         } else {
6184                 for (i = 0; i < 10000; i++) {
6185                         tw32(offset + CPU_STATE, 0xffffffff);
6186                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
6187                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6188                                 break;
6189                 }
6190         }
6191
6192         if (i >= 10000) {
6193                 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
6194                        "and %s CPU\n",
6195                        tp->dev->name,
6196                        (offset == RX_CPU_BASE ? "RX" : "TX"));
6197                 return -ENODEV;
6198         }
6199
6200         /* Clear firmware's nvram arbitration. */
6201         if (tp->tg3_flags & TG3_FLAG_NVRAM)
6202                 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
6203         return 0;
6204 }
6205
6206 struct fw_info {
6207         unsigned int text_base;
6208         unsigned int text_len;
6209         const u32 *text_data;
6210         unsigned int rodata_base;
6211         unsigned int rodata_len;
6212         const u32 *rodata_data;
6213         unsigned int data_base;
6214         unsigned int data_len;
6215         const u32 *data_data;
6216 };
6217
6218 /* tp->lock is held. */
6219 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
6220                                  int cpu_scratch_size, struct fw_info *info)
6221 {
6222         int err, lock_err, i;
6223         void (*write_op)(struct tg3 *, u32, u32);
6224
6225         if (cpu_base == TX_CPU_BASE &&
6226             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6227                 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
6228                        "TX cpu firmware on %s which is 5705.\n",
6229                        tp->dev->name);
6230                 return -EINVAL;
6231         }
6232
6233         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6234                 write_op = tg3_write_mem;
6235         else
6236                 write_op = tg3_write_indirect_reg32;
6237
6238         /* It is possible that bootcode is still loading at this point.
6239          * Get the nvram lock first before halting the cpu.
6240          */
6241         lock_err = tg3_nvram_lock(tp);
6242         err = tg3_halt_cpu(tp, cpu_base);
6243         if (!lock_err)
6244                 tg3_nvram_unlock(tp);
6245         if (err)
6246                 goto out;
6247
6248         for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
6249                 write_op(tp, cpu_scratch_base + i, 0);
6250         tw32(cpu_base + CPU_STATE, 0xffffffff);
6251         tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
6252         for (i = 0; i < (info->text_len / sizeof(u32)); i++)
6253                 write_op(tp, (cpu_scratch_base +
6254                               (info->text_base & 0xffff) +
6255                               (i * sizeof(u32))),
6256                          (info->text_data ?
6257                           info->text_data[i] : 0));
6258         for (i = 0; i < (info->rodata_len / sizeof(u32)); i++)
6259                 write_op(tp, (cpu_scratch_base +
6260                               (info->rodata_base & 0xffff) +
6261                               (i * sizeof(u32))),
6262                          (info->rodata_data ?
6263                           info->rodata_data[i] : 0));
6264         for (i = 0; i < (info->data_len / sizeof(u32)); i++)
6265                 write_op(tp, (cpu_scratch_base +
6266                               (info->data_base & 0xffff) +
6267                               (i * sizeof(u32))),
6268                          (info->data_data ?
6269                           info->data_data[i] : 0));
6270
6271         err = 0;
6272
6273 out:
6274         return err;
6275 }
6276
6277 /* tp->lock is held. */
6278 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
6279 {
6280         struct fw_info info;
6281         int err, i;
6282
6283         info.text_base = TG3_FW_TEXT_ADDR;
6284         info.text_len = TG3_FW_TEXT_LEN;
6285         info.text_data = &tg3FwText[0];
6286         info.rodata_base = TG3_FW_RODATA_ADDR;
6287         info.rodata_len = TG3_FW_RODATA_LEN;
6288         info.rodata_data = &tg3FwRodata[0];
6289         info.data_base = TG3_FW_DATA_ADDR;
6290         info.data_len = TG3_FW_DATA_LEN;
6291         info.data_data = NULL;
6292
6293         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
6294                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
6295                                     &info);
6296         if (err)
6297                 return err;
6298
6299         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
6300                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
6301                                     &info);
6302         if (err)
6303                 return err;
6304
6305         /* Now startup only the RX cpu. */
6306         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6307         tw32_f(RX_CPU_BASE + CPU_PC,    TG3_FW_TEXT_ADDR);
6308
6309         for (i = 0; i < 5; i++) {
6310                 if (tr32(RX_CPU_BASE + CPU_PC) == TG3_FW_TEXT_ADDR)
6311                         break;
6312                 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6313                 tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
6314                 tw32_f(RX_CPU_BASE + CPU_PC,    TG3_FW_TEXT_ADDR);
6315                 udelay(1000);
6316         }
6317         if (i >= 5) {
6318                 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
6319                        "to set RX CPU PC, is %08x should be %08x\n",
6320                        tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
6321                        TG3_FW_TEXT_ADDR);
6322                 return -ENODEV;
6323         }
6324         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6325         tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
6326
6327         return 0;
6328 }
6329
6330
6331 #define TG3_TSO_FW_RELEASE_MAJOR        0x1
6332 #define TG3_TSO_FW_RELASE_MINOR         0x6
6333 #define TG3_TSO_FW_RELEASE_FIX          0x0
6334 #define TG3_TSO_FW_START_ADDR           0x08000000
6335 #define TG3_TSO_FW_TEXT_ADDR            0x08000000
6336 #define TG3_TSO_FW_TEXT_LEN             0x1aa0
6337 #define TG3_TSO_FW_RODATA_ADDR          0x08001aa0
6338 #define TG3_TSO_FW_RODATA_LEN           0x60
6339 #define TG3_TSO_FW_DATA_ADDR            0x08001b20
6340 #define TG3_TSO_FW_DATA_LEN             0x30
6341 #define TG3_TSO_FW_SBSS_ADDR            0x08001b50
6342 #define TG3_TSO_FW_SBSS_LEN             0x2c
6343 #define TG3_TSO_FW_BSS_ADDR             0x08001b80
6344 #define TG3_TSO_FW_BSS_LEN              0x894
6345
6346 static const u32 tg3TsoFwText[(TG3_TSO_FW_TEXT_LEN / 4) + 1] = {
6347         0x0e000003, 0x00000000, 0x08001b24, 0x00000000, 0x10000003, 0x00000000,
6348         0x0000000d, 0x0000000d, 0x3c1d0800, 0x37bd4000, 0x03a0f021, 0x3c100800,
6349         0x26100000, 0x0e000010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
6350         0xafbf0018, 0x0e0005d8, 0x34840002, 0x0e000668, 0x00000000, 0x3c030800,
6351         0x90631b68, 0x24020002, 0x3c040800, 0x24841aac, 0x14620003, 0x24050001,
6352         0x3c040800, 0x24841aa0, 0x24060006, 0x00003821, 0xafa00010, 0x0e00067c,
6353         0xafa00014, 0x8f625c50, 0x34420001, 0xaf625c50, 0x8f625c90, 0x34420001,
6354         0xaf625c90, 0x2402ffff, 0x0e000034, 0xaf625404, 0x8fbf0018, 0x03e00008,
6355         0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c,
6356         0xafb20018, 0xafb10014, 0x0e00005b, 0xafb00010, 0x24120002, 0x24110001,
6357         0x8f706820, 0x32020100, 0x10400003, 0x00000000, 0x0e0000bb, 0x00000000,
6358         0x8f706820, 0x32022000, 0x10400004, 0x32020001, 0x0e0001f0, 0x24040001,
6359         0x32020001, 0x10400003, 0x00000000, 0x0e0000a3, 0x00000000, 0x3c020800,
6360         0x90421b98, 0x14520003, 0x00000000, 0x0e0004c0, 0x00000000, 0x0a00003c,
6361         0xaf715028, 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008,
6362         0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ac0, 0x00002821, 0x00003021,
6363         0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x3c040800,
6364         0x248423d8, 0xa4800000, 0x3c010800, 0xa0201b98, 0x3c010800, 0xac201b9c,
6365         0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
6366         0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bbc, 0x8f624434, 0x3c010800,
6367         0xac221b88, 0x8f624438, 0x3c010800, 0xac221b8c, 0x8f624410, 0xac80f7a8,
6368         0x3c010800, 0xac201b84, 0x3c010800, 0xac2023e0, 0x3c010800, 0xac2023c8,
6369         0x3c010800, 0xac2023cc, 0x3c010800, 0xac202400, 0x3c010800, 0xac221b90,
6370         0x8f620068, 0x24030007, 0x00021702, 0x10430005, 0x00000000, 0x8f620068,
6371         0x00021702, 0x14400004, 0x24020001, 0x3c010800, 0x0a000097, 0xac20240c,
6372         0xac820034, 0x3c040800, 0x24841acc, 0x3c050800, 0x8ca5240c, 0x00003021,
6373         0x00003821, 0xafa00010, 0x0e00067c, 0xafa00014, 0x8fbf0018, 0x03e00008,
6374         0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ad8, 0x00002821, 0x00003021,
6375         0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x0e00005b,
6376         0x00000000, 0x0e0000b4, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020,
6377         0x24020001, 0x8f636820, 0x00821004, 0x00021027, 0x00621824, 0x03e00008,
6378         0xaf636820, 0x27bdffd0, 0xafbf002c, 0xafb60028, 0xafb50024, 0xafb40020,
6379         0xafb3001c, 0xafb20018, 0xafb10014, 0xafb00010, 0x8f675c5c, 0x3c030800,
6380         0x24631bbc, 0x8c620000, 0x14470005, 0x3c0200ff, 0x3c020800, 0x90421b98,
6381         0x14400119, 0x3c0200ff, 0x3442fff8, 0x00e28824, 0xac670000, 0x00111902,
6382         0x306300ff, 0x30e20003, 0x000211c0, 0x00622825, 0x00a04021, 0x00071602,
6383         0x3c030800, 0x90631b98, 0x3044000f, 0x14600036, 0x00804821, 0x24020001,
6384         0x3c010800, 0xa0221b98, 0x00051100, 0x00821025, 0x3c010800, 0xac201b9c,
6385         0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
6386         0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bb0, 0x3c010800, 0xac201bb4,
6387         0x3c010800, 0xa42223d8, 0x9622000c, 0x30437fff, 0x3c010800, 0xa4222410,
6388         0x30428000, 0x3c010800, 0xa4231bc6, 0x10400005, 0x24020001, 0x3c010800,
6389         0xac2223f4, 0x0a000102, 0x2406003e, 0x24060036, 0x3c010800, 0xac2023f4,
6390         0x9622000a, 0x3c030800, 0x94631bc6, 0x3c010800, 0xac2023f0, 0x3c010800,
6391         0xac2023f8, 0x00021302, 0x00021080, 0x00c21021, 0x00621821, 0x3c010800,
6392         0xa42223d0, 0x3c010800, 0x0a000115, 0xa4231b96, 0x9622000c, 0x3c010800,
6393         0xa42223ec, 0x3c040800, 0x24841b9c, 0x8c820000, 0x00021100, 0x3c010800,
6394         0x00220821, 0xac311bc8, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
6395         0xac271bcc, 0x8c820000, 0x25030001, 0x306601ff, 0x00021100, 0x3c010800,
6396         0x00220821, 0xac261bd0, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
6397         0xac291bd4, 0x96230008, 0x3c020800, 0x8c421bac, 0x00432821, 0x3c010800,
6398         0xac251bac, 0x9622000a, 0x30420004, 0x14400018, 0x00061100, 0x8f630c14,
6399         0x3063000f, 0x2c620002, 0x1440000b, 0x3c02c000, 0x8f630c14, 0x3c020800,
6400         0x8c421b40, 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002,
6401         0x1040fff7, 0x3c02c000, 0x00e21825, 0xaf635c5c, 0x8f625c50, 0x30420002,
6402         0x10400014, 0x00000000, 0x0a000147, 0x00000000, 0x3c030800, 0x8c631b80,
6403         0x3c040800, 0x94841b94, 0x01221025, 0x3c010800, 0xa42223da, 0x24020001,
6404         0x3c010800, 0xac221bb8, 0x24630001, 0x0085202a, 0x3c010800, 0x10800003,
6405         0xac231b80, 0x3c010800, 0xa4251b94, 0x3c060800, 0x24c61b9c, 0x8cc20000,
6406         0x24420001, 0xacc20000, 0x28420080, 0x14400005, 0x00000000, 0x0e000656,
6407         0x24040002, 0x0a0001e6, 0x00000000, 0x3c020800, 0x8c421bb8, 0x10400078,
6408         0x24020001, 0x3c050800, 0x90a51b98, 0x14a20072, 0x00000000, 0x3c150800,
6409         0x96b51b96, 0x3c040800, 0x8c841bac, 0x32a3ffff, 0x0083102a, 0x1440006c,
6410         0x00000000, 0x14830003, 0x00000000, 0x3c010800, 0xac2523f0, 0x1060005c,
6411         0x00009021, 0x24d60004, 0x0060a021, 0x24d30014, 0x8ec20000, 0x00028100,
6412         0x3c110800, 0x02308821, 0x0e000625, 0x8e311bc8, 0x00402821, 0x10a00054,
6413         0x00000000, 0x9628000a, 0x31020040, 0x10400005, 0x2407180c, 0x8e22000c,
6414         0x2407188c, 0x00021400, 0xaca20018, 0x3c030800, 0x00701821, 0x8c631bd0,
6415         0x3c020800, 0x00501021, 0x8c421bd4, 0x00031d00, 0x00021400, 0x00621825,
6416         0xaca30014, 0x8ec30004, 0x96220008, 0x00432023, 0x3242ffff, 0x3083ffff,
6417         0x00431021, 0x0282102a, 0x14400002, 0x02b23023, 0x00803021, 0x8e620000,
6418         0x30c4ffff, 0x00441021, 0xae620000, 0x8e220000, 0xaca20000, 0x8e220004,
6419         0x8e63fff4, 0x00431021, 0xaca20004, 0xa4a6000e, 0x8e62fff4, 0x00441021,
6420         0xae62fff4, 0x96230008, 0x0043102a, 0x14400005, 0x02469021, 0x8e62fff0,
6421         0xae60fff4, 0x24420001, 0xae62fff0, 0xaca00008, 0x3242ffff, 0x14540008,
6422         0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x24020905, 0xa4a2000c,
6423         0x0a0001cb, 0x34e70020, 0xa4a2000c, 0x3c020800, 0x8c4223f0, 0x10400003,
6424         0x3c024b65, 0x0a0001d3, 0x34427654, 0x3c02b49a, 0x344289ab, 0xaca2001c,
6425         0x30e2ffff, 0xaca20010, 0x0e0005a2, 0x00a02021, 0x3242ffff, 0x0054102b,
6426         0x1440ffa9, 0x00000000, 0x24020002, 0x3c010800, 0x0a0001e6, 0xa0221b98,
6427         0x8ec2083c, 0x24420001, 0x0a0001e6, 0xaec2083c, 0x0e0004c0, 0x00000000,
6428         0x8fbf002c, 0x8fb60028, 0x8fb50024, 0x8fb40020, 0x8fb3001c, 0x8fb20018,
6429         0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0030, 0x27bdffd0, 0xafbf0028,
6430         0xafb30024, 0xafb20020, 0xafb1001c, 0xafb00018, 0x8f725c9c, 0x3c0200ff,
6431         0x3442fff8, 0x3c070800, 0x24e71bb4, 0x02428824, 0x9623000e, 0x8ce20000,
6432         0x00431021, 0xace20000, 0x8e220010, 0x30420020, 0x14400011, 0x00809821,
6433         0x0e00063b, 0x02202021, 0x3c02c000, 0x02421825, 0xaf635c9c, 0x8f625c90,
6434         0x30420002, 0x1040011e, 0x00000000, 0xaf635c9c, 0x8f625c90, 0x30420002,
6435         0x10400119, 0x00000000, 0x0a00020d, 0x00000000, 0x8e240008, 0x8e230014,
6436         0x00041402, 0x000231c0, 0x00031502, 0x304201ff, 0x2442ffff, 0x3042007f,
6437         0x00031942, 0x30637800, 0x00021100, 0x24424000, 0x00624821, 0x9522000a,
6438         0x3084ffff, 0x30420008, 0x104000b0, 0x000429c0, 0x3c020800, 0x8c422400,
6439         0x14400024, 0x24c50008, 0x94c20014, 0x3c010800, 0xa42223d0, 0x8cc40010,
6440         0x00041402, 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42423d4, 0x94c2000e,
6441         0x3083ffff, 0x00431023, 0x3c010800, 0xac222408, 0x94c2001a, 0x3c010800,
6442         0xac262400, 0x3c010800, 0xac322404, 0x3c010800, 0xac2223fc, 0x3c02c000,
6443         0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e5, 0x00000000,
6444         0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e0, 0x00000000, 0x0a000246,
6445         0x00000000, 0x94c2000e, 0x3c030800, 0x946323d4, 0x00434023, 0x3103ffff,
6446         0x2c620008, 0x1040001c, 0x00000000, 0x94c20014, 0x24420028, 0x00a22821,
6447         0x00031042, 0x1840000b, 0x00002021, 0x24e60848, 0x00403821, 0x94a30000,
6448         0x8cc20000, 0x24840001, 0x00431021, 0xacc20000, 0x0087102a, 0x1440fff9,
6449         0x24a50002, 0x31020001, 0x1040001f, 0x3c024000, 0x3c040800, 0x248423fc,
6450         0xa0a00001, 0x94a30000, 0x8c820000, 0x00431021, 0x0a000285, 0xac820000,
6451         0x8f626800, 0x3c030010, 0x00431024, 0x10400009, 0x00000000, 0x94c2001a,
6452         0x3c030800, 0x8c6323fc, 0x00431021, 0x3c010800, 0xac2223fc, 0x0a000286,
6453         0x3c024000, 0x94c2001a, 0x94c4001c, 0x3c030800, 0x8c6323fc, 0x00441023,
6454         0x00621821, 0x3c010800, 0xac2323fc, 0x3c024000, 0x02421825, 0xaf635c9c,
6455         0x8f625c90, 0x30420002, 0x1440fffc, 0x00000000, 0x9522000a, 0x30420010,
6456         0x1040009b, 0x00000000, 0x3c030800, 0x946323d4, 0x3c070800, 0x24e72400,
6457         0x8ce40000, 0x8f626800, 0x24630030, 0x00832821, 0x3c030010, 0x00431024,
6458         0x1440000a, 0x00000000, 0x94a20004, 0x3c040800, 0x8c842408, 0x3c030800,
6459         0x8c6323fc, 0x00441023, 0x00621821, 0x3c010800, 0xac2323fc, 0x3c040800,
6460         0x8c8423fc, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402, 0x00822021,
6461         0x00041027, 0xa4a20006, 0x3c030800, 0x8c632404, 0x3c0200ff, 0x3442fff8,
6462         0x00628824, 0x96220008, 0x24050001, 0x24034000, 0x000231c0, 0x00801021,
6463         0xa4c2001a, 0xa4c0001c, 0xace00000, 0x3c010800, 0xac251b60, 0xaf635cb8,
6464         0x8f625cb0, 0x30420002, 0x10400003, 0x00000000, 0x3c010800, 0xac201b60,
6465         0x8e220008, 0xaf625cb8, 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000,
6466         0x3c010800, 0xac201b60, 0x3c020800, 0x8c421b60, 0x1040ffec, 0x00000000,
6467         0x3c040800, 0x0e00063b, 0x8c842404, 0x0a00032a, 0x00000000, 0x3c030800,
6468         0x90631b98, 0x24020002, 0x14620003, 0x3c034b65, 0x0a0002e1, 0x00008021,
6469         0x8e22001c, 0x34637654, 0x10430002, 0x24100002, 0x24100001, 0x00c02021,
6470         0x0e000350, 0x02003021, 0x24020003, 0x3c010800, 0xa0221b98, 0x24020002,
6471         0x1202000a, 0x24020001, 0x3c030800, 0x8c6323f0, 0x10620006, 0x00000000,
6472         0x3c020800, 0x944223d8, 0x00021400, 0x0a00031f, 0xae220014, 0x3c040800,
6473         0x248423da, 0x94820000, 0x00021400, 0xae220014, 0x3c020800, 0x8c421bbc,
6474         0x3c03c000, 0x3c010800, 0xa0201b98, 0x00431025, 0xaf625c5c, 0x8f625c50,
6475         0x30420002, 0x10400009, 0x00000000, 0x2484f7e2, 0x8c820000, 0x00431025,
6476         0xaf625c5c, 0x8f625c50, 0x30420002, 0x1440fffa, 0x00000000, 0x3c020800,
6477         0x24421b84, 0x8c430000, 0x24630001, 0xac430000, 0x8f630c14, 0x3063000f,
6478         0x2c620002, 0x1440000c, 0x3c024000, 0x8f630c14, 0x3c020800, 0x8c421b40,
6479         0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7,
6480         0x00000000, 0x3c024000, 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002,
6481         0x1440fffc, 0x00000000, 0x12600003, 0x00000000, 0x0e0004c0, 0x00000000,
6482         0x8fbf0028, 0x8fb30024, 0x8fb20020, 0x8fb1001c, 0x8fb00018, 0x03e00008,
6483         0x27bd0030, 0x8f634450, 0x3c040800, 0x24841b88, 0x8c820000, 0x00031c02,
6484         0x0043102b, 0x14400007, 0x3c038000, 0x8c840004, 0x8f624450, 0x00021c02,
6485         0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
6486         0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3c024000,
6487         0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00000000,
6488         0x03e00008, 0x00000000, 0x27bdffe0, 0x00805821, 0x14c00011, 0x256e0008,
6489         0x3c020800, 0x8c4223f4, 0x10400007, 0x24020016, 0x3c010800, 0xa42223d2,
6490         0x2402002a, 0x3c010800, 0x0a000364, 0xa42223d4, 0x8d670010, 0x00071402,
6491         0x3c010800, 0xa42223d2, 0x3c010800, 0xa42723d4, 0x3c040800, 0x948423d4,
6492         0x3c030800, 0x946323d2, 0x95cf0006, 0x3c020800, 0x944223d0, 0x00832023,
6493         0x01e2c023, 0x3065ffff, 0x24a20028, 0x01c24821, 0x3082ffff, 0x14c0001a,
6494         0x01226021, 0x9582000c, 0x3042003f, 0x3c010800, 0xa42223d6, 0x95820004,
6495         0x95830006, 0x3c010800, 0xac2023e4, 0x3c010800, 0xac2023e8, 0x00021400,
6496         0x00431025, 0x3c010800, 0xac221bc0, 0x95220004, 0x3c010800, 0xa4221bc4,
6497         0x95230002, 0x01e51023, 0x0043102a, 0x10400010, 0x24020001, 0x3c010800,
6498         0x0a000398, 0xac2223f8, 0x3c030800, 0x8c6323e8, 0x3c020800, 0x94421bc4,
6499         0x00431021, 0xa5220004, 0x3c020800, 0x94421bc0, 0xa5820004, 0x3c020800,
6500         0x8c421bc0, 0xa5820006, 0x3c020800, 0x8c4223f0, 0x3c0d0800, 0x8dad23e4,
6501         0x3c0a0800, 0x144000e5, 0x8d4a23e8, 0x3c020800, 0x94421bc4, 0x004a1821,
6502         0x3063ffff, 0x0062182b, 0x24020002, 0x10c2000d, 0x01435023, 0x3c020800,
6503         0x944223d6, 0x30420009, 0x10400008, 0x00000000, 0x9582000c, 0x3042fff6,
6504         0xa582000c, 0x3c020800, 0x944223d6, 0x30420009, 0x01a26823, 0x3c020800,
6505         0x8c4223f8, 0x1040004a, 0x01203821, 0x3c020800, 0x944223d2, 0x00004021,
6506         0xa520000a, 0x01e21023, 0xa5220002, 0x3082ffff, 0x00021042, 0x18400008,
6507         0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021, 0x0103102a,
6508         0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061402,
6509         0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021, 0x2527000c,
6510         0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004, 0x1440fffb,
6511         0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023, 0x01803821,
6512         0x3082ffff, 0xa4e00010, 0x00621821, 0x00021042, 0x18400010, 0x00c33021,
6513         0x00404821, 0x94e20000, 0x24e70002, 0x00c23021, 0x30e2007f, 0x14400006,
6514         0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80, 0x00625824, 0x25670008,
6515         0x0109102a, 0x1440fff3, 0x00000000, 0x30820001, 0x10400005, 0x00061c02,
6516         0xa0e00001, 0x94e20000, 0x00c23021, 0x00061c02, 0x30c2ffff, 0x00623021,
6517         0x00061402, 0x00c23021, 0x0a00047d, 0x30c6ffff, 0x24020002, 0x14c20081,
6518         0x00000000, 0x3c020800, 0x8c42240c, 0x14400007, 0x00000000, 0x3c020800,
6519         0x944223d2, 0x95230002, 0x01e21023, 0x10620077, 0x00000000, 0x3c020800,
6520         0x944223d2, 0x01e21023, 0xa5220002, 0x3c020800, 0x8c42240c, 0x1040001a,
6521         0x31e3ffff, 0x8dc70010, 0x3c020800, 0x94421b96, 0x00e04021, 0x00072c02,
6522         0x00aa2021, 0x00431023, 0x00823823, 0x00072402, 0x30e2ffff, 0x00823821,
6523         0x00071027, 0xa522000a, 0x3102ffff, 0x3c040800, 0x948423d4, 0x00453023,
6524         0x00e02821, 0x00641823, 0x006d1821, 0x00c33021, 0x00061c02, 0x30c2ffff,
6525         0x0a00047d, 0x00623021, 0x01203821, 0x00004021, 0x3082ffff, 0x00021042,
6526         0x18400008, 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021,
6527         0x0103102a, 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021,
6528         0x00061402, 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021,
6529         0x2527000c, 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004,
6530         0x1440fffb, 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023,
6531         0x01803821, 0x3082ffff, 0xa4e00010, 0x3c040800, 0x948423d4, 0x00621821,
6532         0x00c33021, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061c02, 0x3c020800,
6533         0x944223d0, 0x00c34821, 0x00441023, 0x00021fc2, 0x00431021, 0x00021043,
6534         0x18400010, 0x00003021, 0x00402021, 0x94e20000, 0x24e70002, 0x00c23021,
6535         0x30e2007f, 0x14400006, 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80,
6536         0x00625824, 0x25670008, 0x0104102a, 0x1440fff3, 0x00000000, 0x3c020800,
6537         0x944223ec, 0x00c23021, 0x3122ffff, 0x00c23021, 0x00061c02, 0x30c2ffff,
6538         0x00623021, 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010,
6539         0xadc00014, 0x0a00049d, 0xadc00000, 0x8dc70010, 0x00e04021, 0x11400007,
6540         0x00072c02, 0x00aa3021, 0x00061402, 0x30c3ffff, 0x00433021, 0x00061402,
6541         0x00c22821, 0x00051027, 0xa522000a, 0x3c030800, 0x946323d4, 0x3102ffff,
6542         0x01e21021, 0x00433023, 0x00cd3021, 0x00061c02, 0x30c2ffff, 0x00623021,
6543         0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010, 0x3102ffff,
6544         0x00051c00, 0x00431025, 0xadc20010, 0x3c020800, 0x8c4223f4, 0x10400005,
6545         0x2de205eb, 0x14400002, 0x25e2fff2, 0x34028870, 0xa5c20034, 0x3c030800,
6546         0x246323e8, 0x8c620000, 0x24420001, 0xac620000, 0x3c040800, 0x8c8423e4,
6547         0x3c020800, 0x8c421bc0, 0x3303ffff, 0x00832021, 0x00431821, 0x0062102b,
6548         0x3c010800, 0xac2423e4, 0x10400003, 0x2482ffff, 0x3c010800, 0xac2223e4,
6549         0x3c010800, 0xac231bc0, 0x03e00008, 0x27bd0020, 0x27bdffb8, 0x3c050800,
6550         0x24a51b96, 0xafbf0044, 0xafbe0040, 0xafb7003c, 0xafb60038, 0xafb50034,
6551         0xafb40030, 0xafb3002c, 0xafb20028, 0xafb10024, 0xafb00020, 0x94a90000,
6552         0x3c020800, 0x944223d0, 0x3c030800, 0x8c631bb0, 0x3c040800, 0x8c841bac,
6553         0x01221023, 0x0064182a, 0xa7a9001e, 0x106000be, 0xa7a20016, 0x24be0022,
6554         0x97b6001e, 0x24b3001a, 0x24b70016, 0x8fc20000, 0x14400008, 0x00000000,
6555         0x8fc2fff8, 0x97a30016, 0x8fc4fff4, 0x00431021, 0x0082202a, 0x148000b0,
6556         0x00000000, 0x97d50818, 0x32a2ffff, 0x104000a3, 0x00009021, 0x0040a021,
6557         0x00008821, 0x0e000625, 0x00000000, 0x00403021, 0x14c00007, 0x00000000,
6558         0x3c020800, 0x8c4223dc, 0x24420001, 0x3c010800, 0x0a000596, 0xac2223dc,
6559         0x3c100800, 0x02118021, 0x8e101bc8, 0x9608000a, 0x31020040, 0x10400005,
6560         0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x31020080,
6561         0x54400001, 0x34e70010, 0x3c020800, 0x00511021, 0x8c421bd0, 0x3c030800,
6562         0x00711821, 0x8c631bd4, 0x00021500, 0x00031c00, 0x00431025, 0xacc20014,
6563         0x96040008, 0x3242ffff, 0x00821021, 0x0282102a, 0x14400002, 0x02b22823,
6564         0x00802821, 0x8e020000, 0x02459021, 0xacc20000, 0x8e020004, 0x00c02021,
6565         0x26310010, 0xac820004, 0x30e2ffff, 0xac800008, 0xa485000e, 0xac820010,
6566         0x24020305, 0x0e0005a2, 0xa482000c, 0x3242ffff, 0x0054102b, 0x1440ffc5,
6567         0x3242ffff, 0x0a00058e, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
6568         0x10400067, 0x00000000, 0x8e62fff0, 0x00028900, 0x3c100800, 0x02118021,
6569         0x0e000625, 0x8e101bc8, 0x00403021, 0x14c00005, 0x00000000, 0x8e62082c,
6570         0x24420001, 0x0a000596, 0xae62082c, 0x9608000a, 0x31020040, 0x10400005,
6571         0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x3c020800,
6572         0x00511021, 0x8c421bd0, 0x3c030800, 0x00711821, 0x8c631bd4, 0x00021500,
6573         0x00031c00, 0x00431025, 0xacc20014, 0x8e63fff4, 0x96020008, 0x00432023,
6574         0x3242ffff, 0x3083ffff, 0x00431021, 0x02c2102a, 0x10400003, 0x00802821,
6575         0x97a9001e, 0x01322823, 0x8e620000, 0x30a4ffff, 0x00441021, 0xae620000,
6576         0xa4c5000e, 0x8e020000, 0xacc20000, 0x8e020004, 0x8e63fff4, 0x00431021,
6577         0xacc20004, 0x8e63fff4, 0x96020008, 0x00641821, 0x0062102a, 0x14400006,
6578         0x02459021, 0x8e62fff0, 0xae60fff4, 0x24420001, 0x0a000571, 0xae62fff0,
6579         0xae63fff4, 0xacc00008, 0x3242ffff, 0x10560003, 0x31020004, 0x10400006,
6580         0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x34e70020, 0x24020905,
6581         0xa4c2000c, 0x8ee30000, 0x8ee20004, 0x14620007, 0x3c02b49a, 0x8ee20860,
6582         0x54400001, 0x34e70400, 0x3c024b65, 0x0a000588, 0x34427654, 0x344289ab,
6583         0xacc2001c, 0x30e2ffff, 0xacc20010, 0x0e0005a2, 0x00c02021, 0x3242ffff,
6584         0x0056102b, 0x1440ff9b, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
6585         0x1440ff48, 0x00000000, 0x8fbf0044, 0x8fbe0040, 0x8fb7003c, 0x8fb60038,
6586         0x8fb50034, 0x8fb40030, 0x8fb3002c, 0x8fb20028, 0x8fb10024, 0x8fb00020,
6587         0x03e00008, 0x27bd0048, 0x27bdffe8, 0xafbf0014, 0xafb00010, 0x8f624450,
6588         0x8f634410, 0x0a0005b1, 0x00808021, 0x8f626820, 0x30422000, 0x10400003,
6589         0x00000000, 0x0e0001f0, 0x00002021, 0x8f624450, 0x8f634410, 0x3042ffff,
6590         0x0043102b, 0x1440fff5, 0x00000000, 0x8f630c14, 0x3063000f, 0x2c620002,
6591         0x1440000b, 0x00000000, 0x8f630c14, 0x3c020800, 0x8c421b40, 0x3063000f,
6592         0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7, 0x00000000,
6593         0xaf705c18, 0x8f625c10, 0x30420002, 0x10400009, 0x00000000, 0x8f626820,
6594         0x30422000, 0x1040fff8, 0x00000000, 0x0e0001f0, 0x00002021, 0x0a0005c4,
6595         0x00000000, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000,
6596         0x00000000, 0x00000000, 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010,
6597         0xaf60680c, 0x8f626804, 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50,
6598         0x3c010800, 0xac221b54, 0x24020b78, 0x3c010800, 0xac221b64, 0x34630002,
6599         0xaf634000, 0x0e000605, 0x00808021, 0x3c010800, 0xa0221b68, 0x304200ff,
6600         0x24030002, 0x14430005, 0x00000000, 0x3c020800, 0x8c421b54, 0x0a0005f8,
6601         0xac5000c0, 0x3c020800, 0x8c421b54, 0xac5000bc, 0x8f624434, 0x8f634438,
6602         0x8f644410, 0x3c010800, 0xac221b5c, 0x3c010800, 0xac231b6c, 0x3c010800,
6603         0xac241b58, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c040800,
6604         0x8c870000, 0x3c03aa55, 0x3463aa55, 0x3c06c003, 0xac830000, 0x8cc20000,
6605         0x14430007, 0x24050002, 0x3c0355aa, 0x346355aa, 0xac830000, 0x8cc20000,
6606         0x50430001, 0x24050001, 0x3c020800, 0xac470000, 0x03e00008, 0x00a01021,
6607         0x27bdfff8, 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe,
6608         0x00000000, 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008,
6609         0x27bd0008, 0x8f634450, 0x3c020800, 0x8c421b5c, 0x00031c02, 0x0043102b,
6610         0x14400008, 0x3c038000, 0x3c040800, 0x8c841b6c, 0x8f624450, 0x00021c02,
6611         0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
6612         0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff,
6613         0x2442e000, 0x2c422001, 0x14400003, 0x3c024000, 0x0a000648, 0x2402ffff,
6614         0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021,
6615         0x03e00008, 0x00000000, 0x8f624450, 0x3c030800, 0x8c631b58, 0x0a000651,
6616         0x3042ffff, 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000,
6617         0x03e00008, 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040800, 0x24841af0,
6618         0x00003021, 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014,
6619         0x0a000660, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000,
6620         0x00000000, 0x00000000, 0x3c020800, 0x34423000, 0x3c030800, 0x34633000,
6621         0x3c040800, 0x348437ff, 0x3c010800, 0xac221b74, 0x24020040, 0x3c010800,
6622         0xac221b78, 0x3c010800, 0xac201b70, 0xac600000, 0x24630004, 0x0083102b,
6623         0x5040fffd, 0xac600000, 0x03e00008, 0x00000000, 0x00804821, 0x8faa0010,
6624         0x3c020800, 0x8c421b70, 0x3c040800, 0x8c841b78, 0x8fab0014, 0x24430001,
6625         0x0044102b, 0x3c010800, 0xac231b70, 0x14400003, 0x00004021, 0x3c010800,
6626         0xac201b70, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74, 0x91240000,
6627         0x00021140, 0x00431021, 0x00481021, 0x25080001, 0xa0440000, 0x29020008,
6628         0x1440fff4, 0x25290001, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74,
6629         0x8f64680c, 0x00021140, 0x00431021, 0xac440008, 0xac45000c, 0xac460010,
6630         0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c, 0x00000000, 0x00000000,
6631 };
6632
6633 static const u32 tg3TsoFwRodata[] = {
6634         0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
6635         0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x496e0000, 0x73746b6f,
6636         0x66662a2a, 0x00000000, 0x53774576, 0x656e7430, 0x00000000, 0x00000000,
6637         0x00000000, 0x00000000, 0x66617461, 0x6c457272, 0x00000000, 0x00000000,
6638         0x00000000,
6639 };
6640
6641 static const u32 tg3TsoFwData[] = {
6642         0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x362e3000, 0x00000000,
6643         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
6644         0x00000000,
6645 };
6646
6647 /* 5705 needs a special version of the TSO firmware.  */
6648 #define TG3_TSO5_FW_RELEASE_MAJOR       0x1
6649 #define TG3_TSO5_FW_RELASE_MINOR        0x2
6650 #define TG3_TSO5_FW_RELEASE_FIX         0x0
6651 #define TG3_TSO5_FW_START_ADDR          0x00010000
6652 #define TG3_TSO5_FW_TEXT_ADDR           0x00010000
6653 #define TG3_TSO5_FW_TEXT_LEN            0xe90
6654 #define TG3_TSO5_FW_RODATA_ADDR         0x00010e90
6655 #define TG3_TSO5_FW_RODATA_LEN          0x50
6656 #define TG3_TSO5_FW_DATA_ADDR           0x00010f00
6657 #define TG3_TSO5_FW_DATA_LEN            0x20
6658 #define TG3_TSO5_FW_SBSS_ADDR           0x00010f20
6659 #define TG3_TSO5_FW_SBSS_LEN            0x28
6660 #define TG3_TSO5_FW_BSS_ADDR            0x00010f50
6661 #define TG3_TSO5_FW_BSS_LEN             0x88
6662
6663 static const u32 tg3Tso5FwText[(TG3_TSO5_FW_TEXT_LEN / 4) + 1] = {
6664         0x0c004003, 0x00000000, 0x00010f04, 0x00000000, 0x10000003, 0x00000000,
6665         0x0000000d, 0x0000000d, 0x3c1d0001, 0x37bde000, 0x03a0f021, 0x3c100001,
6666         0x26100000, 0x0c004010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
6667         0xafbf0018, 0x0c0042e8, 0x34840002, 0x0c004364, 0x00000000, 0x3c030001,
6668         0x90630f34, 0x24020002, 0x3c040001, 0x24840e9c, 0x14620003, 0x24050001,
6669         0x3c040001, 0x24840e90, 0x24060002, 0x00003821, 0xafa00010, 0x0c004378,
6670         0xafa00014, 0x0c00402c, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020,
6671         0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c, 0xafb20018, 0xafb10014,
6672         0x0c0042d4, 0xafb00010, 0x3c128000, 0x24110001, 0x8f706810, 0x32020400,
6673         0x10400007, 0x00000000, 0x8f641008, 0x00921024, 0x14400003, 0x00000000,
6674         0x0c004064, 0x00000000, 0x3c020001, 0x90420f56, 0x10510003, 0x32020200,
6675         0x1040fff1, 0x00000000, 0x0c0041b4, 0x00000000, 0x08004034, 0x00000000,
6676         0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020,
6677         0x27bdffe0, 0x3c040001, 0x24840eb0, 0x00002821, 0x00003021, 0x00003821,
6678         0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130,
6679         0xaf625000, 0x3c010001, 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018,
6680         0x03e00008, 0x27bd0020, 0x00000000, 0x00000000, 0x3c030001, 0x24630f60,
6681         0x90620000, 0x27bdfff0, 0x14400003, 0x0080c021, 0x08004073, 0x00004821,
6682         0x3c022000, 0x03021024, 0x10400003, 0x24090002, 0x08004073, 0xa0600000,
6683         0x24090001, 0x00181040, 0x30431f80, 0x346f8008, 0x1520004b, 0x25eb0028,
6684         0x3c040001, 0x00832021, 0x8c848010, 0x3c050001, 0x24a50f7a, 0x00041402,
6685         0xa0a20000, 0x3c010001, 0xa0240f7b, 0x3c020001, 0x00431021, 0x94428014,
6686         0x3c010001, 0xa0220f7c, 0x3c0c0001, 0x01836021, 0x8d8c8018, 0x304200ff,
6687         0x24420008, 0x000220c3, 0x24020001, 0x3c010001, 0xa0220f60, 0x0124102b,
6688         0x1040000c, 0x00003821, 0x24a6000e, 0x01602821, 0x8ca20000, 0x8ca30004,
6689         0x24a50008, 0x24e70001, 0xacc20000, 0xacc30004, 0x00e4102b, 0x1440fff8,
6690         0x24c60008, 0x00003821, 0x3c080001, 0x25080f7b, 0x91060000, 0x3c020001,
6691         0x90420f7c, 0x2503000d, 0x00c32821, 0x00461023, 0x00021fc2, 0x00431021,
6692         0x00021043, 0x1840000c, 0x00002021, 0x91020001, 0x00461023, 0x00021fc2,
6693         0x00431021, 0x00021843, 0x94a20000, 0x24e70001, 0x00822021, 0x00e3102a,
6694         0x1440fffb, 0x24a50002, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
6695         0x00822021, 0x3c02ffff, 0x01821024, 0x3083ffff, 0x00431025, 0x3c010001,
6696         0x080040fa, 0xac220f80, 0x3c050001, 0x24a50f7c, 0x90a20000, 0x3c0c0001,
6697         0x01836021, 0x8d8c8018, 0x000220c2, 0x1080000e, 0x00003821, 0x01603021,
6698         0x24a5000c, 0x8ca20000, 0x8ca30004, 0x24a50008, 0x24e70001, 0xacc20000,
6699         0xacc30004, 0x00e4102b, 0x1440fff8, 0x24c60008, 0x3c050001, 0x24a50f7c,
6700         0x90a20000, 0x30430007, 0x24020004, 0x10620011, 0x28620005, 0x10400005,
6701         0x24020002, 0x10620008, 0x000710c0, 0x080040fa, 0x00000000, 0x24020006,
6702         0x1062000e, 0x000710c0, 0x080040fa, 0x00000000, 0x00a21821, 0x9463000c,
6703         0x004b1021, 0x080040fa, 0xa4430000, 0x000710c0, 0x00a21821, 0x8c63000c,
6704         0x004b1021, 0x080040fa, 0xac430000, 0x00a21821, 0x8c63000c, 0x004b2021,
6705         0x00a21021, 0xac830000, 0x94420010, 0xa4820004, 0x95e70006, 0x3c020001,
6706         0x90420f7c, 0x3c030001, 0x90630f7a, 0x00e2c823, 0x3c020001, 0x90420f7b,
6707         0x24630028, 0x01e34021, 0x24420028, 0x15200012, 0x01e23021, 0x94c2000c,
6708         0x3c010001, 0xa4220f78, 0x94c20004, 0x94c30006, 0x3c010001, 0xa4200f76,
6709         0x3c010001, 0xa4200f72, 0x00021400, 0x00431025, 0x3c010001, 0xac220f6c,
6710         0x95020004, 0x3c010001, 0x08004124, 0xa4220f70, 0x3c020001, 0x94420f70,
6711         0x3c030001, 0x94630f72, 0x00431021, 0xa5020004, 0x3c020001, 0x94420f6c,
6712         0xa4c20004, 0x3c020001, 0x8c420f6c, 0xa4c20006, 0x3c040001, 0x94840f72,
6713         0x3c020001, 0x94420f70, 0x3c0a0001, 0x954a0f76, 0x00441821, 0x3063ffff,
6714         0x0062182a, 0x24020002, 0x1122000b, 0x00832023, 0x3c030001, 0x94630f78,
6715         0x30620009, 0x10400006, 0x3062fff6, 0xa4c2000c, 0x3c020001, 0x94420f78,
6716         0x30420009, 0x01425023, 0x24020001, 0x1122001b, 0x29220002, 0x50400005,
6717         0x24020002, 0x11200007, 0x31a2ffff, 0x08004197, 0x00000000, 0x1122001d,
6718         0x24020016, 0x08004197, 0x31a2ffff, 0x3c0e0001, 0x95ce0f80, 0x10800005,
6719         0x01806821, 0x01c42021, 0x00041c02, 0x3082ffff, 0x00627021, 0x000e1027,
6720         0xa502000a, 0x3c030001, 0x90630f7b, 0x31a2ffff, 0x00e21021, 0x0800418d,
6721         0x00432023, 0x3c020001, 0x94420f80, 0x00442021, 0x00041c02, 0x3082ffff,
6722         0x00622021, 0x00807021, 0x00041027, 0x08004185, 0xa502000a, 0x3c050001,
6723         0x24a50f7a, 0x90a30000, 0x14620002, 0x24e2fff2, 0xa5e20034, 0x90a20000,
6724         0x00e21023, 0xa5020002, 0x3c030001, 0x94630f80, 0x3c020001, 0x94420f5a,
6725         0x30e5ffff, 0x00641821, 0x00451023, 0x00622023, 0x00041c02, 0x3082ffff,
6726         0x00622021, 0x00041027, 0xa502000a, 0x3c030001, 0x90630f7c, 0x24620001,
6727         0x14a20005, 0x00807021, 0x01631021, 0x90420000, 0x08004185, 0x00026200,
6728         0x24620002, 0x14a20003, 0x306200fe, 0x004b1021, 0x944c0000, 0x3c020001,
6729         0x94420f82, 0x3183ffff, 0x3c040001, 0x90840f7b, 0x00431021, 0x00e21021,
6730         0x00442023, 0x008a2021, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
6731         0x00822021, 0x00806821, 0x00041027, 0xa4c20010, 0x31a2ffff, 0x000e1c00,
6732         0x00431025, 0x3c040001, 0x24840f72, 0xade20010, 0x94820000, 0x3c050001,
6733         0x94a50f76, 0x3c030001, 0x8c630f6c, 0x24420001, 0x00b92821, 0xa4820000,
6734         0x3322ffff, 0x00622021, 0x0083182b, 0x3c010001, 0xa4250f76, 0x10600003,
6735         0x24a2ffff, 0x3c010001, 0xa4220f76, 0x3c024000, 0x03021025, 0x3c010001,
6736         0xac240f6c, 0xaf621008, 0x03e00008, 0x27bd0010, 0x3c030001, 0x90630f56,
6737         0x27bdffe8, 0x24020001, 0xafbf0014, 0x10620026, 0xafb00010, 0x8f620cf4,
6738         0x2442ffff, 0x3042007f, 0x00021100, 0x8c434000, 0x3c010001, 0xac230f64,
6739         0x8c434008, 0x24444000, 0x8c5c4004, 0x30620040, 0x14400002, 0x24020088,
6740         0x24020008, 0x3c010001, 0xa4220f68, 0x30620004, 0x10400005, 0x24020001,
6741         0x3c010001, 0xa0220f57, 0x080041d5, 0x00031402, 0x3c010001, 0xa0200f57,
6742         0x00031402, 0x3c010001, 0xa4220f54, 0x9483000c, 0x24020001, 0x3c010001,
6743         0xa4200f50, 0x3c010001, 0xa0220f56, 0x3c010001, 0xa4230f62, 0x24020001,
6744         0x1342001e, 0x00000000, 0x13400005, 0x24020003, 0x13420067, 0x00000000,
6745         0x080042cf, 0x00000000, 0x3c020001, 0x94420f62, 0x241a0001, 0x3c010001,
6746         0xa4200f5e, 0x3c010001, 0xa4200f52, 0x304407ff, 0x00021bc2, 0x00031823,
6747         0x3063003e, 0x34630036, 0x00021242, 0x3042003c, 0x00621821, 0x3c010001,
6748         0xa4240f58, 0x00832021, 0x24630030, 0x3c010001, 0xa4240f5a, 0x3c010001,
6749         0xa4230f5c, 0x3c060001, 0x24c60f52, 0x94c50000, 0x94c30002, 0x3c040001,
6750         0x94840f5a, 0x00651021, 0x0044102a, 0x10400013, 0x3c108000, 0x00a31021,
6751         0xa4c20000, 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008,
6752         0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4,
6753         0x00501024, 0x104000b7, 0x00000000, 0x0800420f, 0x00000000, 0x3c030001,
6754         0x94630f50, 0x00851023, 0xa4c40000, 0x00621821, 0x3042ffff, 0x3c010001,
6755         0xa4230f50, 0xaf620ce8, 0x3c020001, 0x94420f68, 0x34420024, 0xaf620cec,
6756         0x94c30002, 0x3c020001, 0x94420f50, 0x14620012, 0x3c028000, 0x3c108000,
6757         0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008, 0x00901024,
6758         0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024,
6759         0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003, 0xaf620cf4, 0x3c108000,
6760         0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000,
6761         0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003,
6762         0x3c070001, 0x24e70f50, 0x94e20000, 0x03821021, 0xaf620ce0, 0x3c020001,
6763         0x8c420f64, 0xaf620ce4, 0x3c050001, 0x94a50f54, 0x94e30000, 0x3c040001,
6764         0x94840f58, 0x3c020001, 0x94420f5e, 0x00a32823, 0x00822023, 0x30a6ffff,
6765         0x3083ffff, 0x00c3102b, 0x14400043, 0x00000000, 0x3c020001, 0x94420f5c,
6766         0x00021400, 0x00621025, 0xaf620ce8, 0x94e20000, 0x3c030001, 0x94630f54,
6767         0x00441021, 0xa4e20000, 0x3042ffff, 0x14430021, 0x3c020008, 0x3c020001,
6768         0x90420f57, 0x10400006, 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624,
6769         0x0800427c, 0x0000d021, 0x3c020001, 0x94420f68, 0x3c030008, 0x34630624,
6770         0x00431025, 0xaf620cec, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
6771         0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
6772         0x00000000, 0x8f620cf4, 0x00501024, 0x10400015, 0x00000000, 0x08004283,
6773         0x00000000, 0x3c030001, 0x94630f68, 0x34420624, 0x3c108000, 0x00621825,
6774         0x3c028000, 0xaf630cec, 0xaf620cf4, 0x8f641008, 0x00901024, 0x14400003,
6775         0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7,
6776         0x00000000, 0x3c010001, 0x080042cf, 0xa4200f5e, 0x3c020001, 0x94420f5c,
6777         0x00021400, 0x00c21025, 0xaf620ce8, 0x3c020001, 0x90420f57, 0x10400009,
6778         0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624, 0x0000d021, 0x00431025,
6779         0xaf620cec, 0x080042c1, 0x3c108000, 0x3c020001, 0x94420f68, 0x3c030008,
6780         0x34630604, 0x00431025, 0xaf620cec, 0x3c020001, 0x94420f5e, 0x00451021,
6781         0x3c010001, 0xa4220f5e, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
6782         0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
6783         0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x8fbf0014,
6784         0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000, 0x27bdffe0, 0x3c040001,
6785         0x24840ec0, 0x00002821, 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010,
6786         0x0c004378, 0xafa00014, 0x0000d021, 0x24020130, 0xaf625000, 0x3c010001,
6787         0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018, 0x03e00008, 0x27bd0020,
6788         0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010, 0xaf60680c, 0x8f626804,
6789         0x34420082, 0xaf626804, 0x8f634000, 0x24020b50, 0x3c010001, 0xac220f20,
6790         0x24020b78, 0x3c010001, 0xac220f30, 0x34630002, 0xaf634000, 0x0c004315,
6791         0x00808021, 0x3c010001, 0xa0220f34, 0x304200ff, 0x24030002, 0x14430005,
6792         0x00000000, 0x3c020001, 0x8c420f20, 0x08004308, 0xac5000c0, 0x3c020001,
6793         0x8c420f20, 0xac5000bc, 0x8f624434, 0x8f634438, 0x8f644410, 0x3c010001,
6794         0xac220f28, 0x3c010001, 0xac230f38, 0x3c010001, 0xac240f24, 0x8fbf0014,
6795         0x8fb00010, 0x03e00008, 0x27bd0018, 0x03e00008, 0x24020001, 0x27bdfff8,
6796         0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe, 0x00000000,
6797         0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008, 0x27bd0008,
6798         0x8f634450, 0x3c020001, 0x8c420f28, 0x00031c02, 0x0043102b, 0x14400008,
6799         0x3c038000, 0x3c040001, 0x8c840f38, 0x8f624450, 0x00021c02, 0x0083102b,
6800         0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024, 0x1440fffd,
6801         0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff, 0x2442e000,
6802         0x2c422001, 0x14400003, 0x3c024000, 0x08004347, 0x2402ffff, 0x00822025,
6803         0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021, 0x03e00008,
6804         0x00000000, 0x8f624450, 0x3c030001, 0x8c630f24, 0x08004350, 0x3042ffff,
6805         0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000, 0x03e00008,
6806         0x00000000, 0x27bdffe0, 0x00802821, 0x3c040001, 0x24840ed0, 0x00003021,
6807         0x00003821, 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0800435f,
6808         0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x3c020001, 0x3442d600,
6809         0x3c030001, 0x3463d600, 0x3c040001, 0x3484ddff, 0x3c010001, 0xac220f40,
6810         0x24020040, 0x3c010001, 0xac220f44, 0x3c010001, 0xac200f3c, 0xac600000,
6811         0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
6812         0x00804821, 0x8faa0010, 0x3c020001, 0x8c420f3c, 0x3c040001, 0x8c840f44,
6813         0x8fab0014, 0x24430001, 0x0044102b, 0x3c010001, 0xac230f3c, 0x14400003,
6814         0x00004021, 0x3c010001, 0xac200f3c, 0x3c020001, 0x8c420f3c, 0x3c030001,
6815         0x8c630f40, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
6816         0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020001, 0x8c420f3c,
6817         0x3c030001, 0x8c630f40, 0x8f64680c, 0x00021140, 0x00431021, 0xac440008,
6818         0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
6819         0x00000000, 0x00000000, 0x00000000,
6820 };
6821
6822 static const u32 tg3Tso5FwRodata[(TG3_TSO5_FW_RODATA_LEN / 4) + 1] = {
6823         0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
6824         0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000,
6825         0x73746b6f, 0x66666c64, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
6826         0x00000000, 0x00000000, 0x00000000,
6827 };
6828
6829 static const u32 tg3Tso5FwData[(TG3_TSO5_FW_DATA_LEN / 4) + 1] = {
6830         0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x322e3000, 0x00000000,
6831         0x00000000, 0x00000000, 0x00000000,
6832 };
6833
6834 /* tp->lock is held. */
6835 static int tg3_load_tso_firmware(struct tg3 *tp)
6836 {
6837         struct fw_info info;
6838         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
6839         int err, i;
6840
6841         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6842                 return 0;
6843
6844         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6845                 info.text_base = TG3_TSO5_FW_TEXT_ADDR;
6846                 info.text_len = TG3_TSO5_FW_TEXT_LEN;
6847                 info.text_data = &tg3Tso5FwText[0];
6848                 info.rodata_base = TG3_TSO5_FW_RODATA_ADDR;
6849                 info.rodata_len = TG3_TSO5_FW_RODATA_LEN;
6850                 info.rodata_data = &tg3Tso5FwRodata[0];
6851                 info.data_base = TG3_TSO5_FW_DATA_ADDR;
6852                 info.data_len = TG3_TSO5_FW_DATA_LEN;
6853                 info.data_data = &tg3Tso5FwData[0];
6854                 cpu_base = RX_CPU_BASE;
6855                 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
6856                 cpu_scratch_size = (info.text_len +
6857                                     info.rodata_len +
6858                                     info.data_len +
6859                                     TG3_TSO5_FW_SBSS_LEN +
6860                                     TG3_TSO5_FW_BSS_LEN);
6861         } else {
6862                 info.text_base = TG3_TSO_FW_TEXT_ADDR;
6863                 info.text_len = TG3_TSO_FW_TEXT_LEN;
6864                 info.text_data = &tg3TsoFwText[0];
6865                 info.rodata_base = TG3_TSO_FW_RODATA_ADDR;
6866                 info.rodata_len = TG3_TSO_FW_RODATA_LEN;
6867                 info.rodata_data = &tg3TsoFwRodata[0];
6868                 info.data_base = TG3_TSO_FW_DATA_ADDR;
6869                 info.data_len = TG3_TSO_FW_DATA_LEN;
6870                 info.data_data = &tg3TsoFwData[0];
6871                 cpu_base = TX_CPU_BASE;
6872                 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
6873                 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
6874         }
6875
6876         err = tg3_load_firmware_cpu(tp, cpu_base,
6877                                     cpu_scratch_base, cpu_scratch_size,
6878                                     &info);
6879         if (err)
6880                 return err;
6881
6882         /* Now startup the cpu. */
6883         tw32(cpu_base + CPU_STATE, 0xffffffff);
6884         tw32_f(cpu_base + CPU_PC,    info.text_base);
6885
6886         for (i = 0; i < 5; i++) {
6887                 if (tr32(cpu_base + CPU_PC) == info.text_base)
6888                         break;
6889                 tw32(cpu_base + CPU_STATE, 0xffffffff);
6890                 tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
6891                 tw32_f(cpu_base + CPU_PC,    info.text_base);
6892                 udelay(1000);
6893         }
6894         if (i >= 5) {
6895                 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
6896                        "to set CPU PC, is %08x should be %08x\n",
6897                        tp->dev->name, tr32(cpu_base + CPU_PC),
6898                        info.text_base);
6899                 return -ENODEV;
6900         }
6901         tw32(cpu_base + CPU_STATE, 0xffffffff);
6902         tw32_f(cpu_base + CPU_MODE,  0x00000000);
6903         return 0;
6904 }
6905
6906
6907 /* tp->lock is held. */
6908 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
6909 {
6910         u32 addr_high, addr_low;
6911         int i;
6912
6913         addr_high = ((tp->dev->dev_addr[0] << 8) |
6914                      tp->dev->dev_addr[1]);
6915         addr_low = ((tp->dev->dev_addr[2] << 24) |
6916                     (tp->dev->dev_addr[3] << 16) |
6917                     (tp->dev->dev_addr[4] <<  8) |
6918                     (tp->dev->dev_addr[5] <<  0));
6919         for (i = 0; i < 4; i++) {
6920                 if (i == 1 && skip_mac_1)
6921                         continue;
6922                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
6923                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
6924         }
6925
6926         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
6927             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
6928                 for (i = 0; i < 12; i++) {
6929                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
6930                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
6931                 }
6932         }
6933
6934         addr_high = (tp->dev->dev_addr[0] +
6935                      tp->dev->dev_addr[1] +
6936                      tp->dev->dev_addr[2] +
6937                      tp->dev->dev_addr[3] +
6938                      tp->dev->dev_addr[4] +
6939                      tp->dev->dev_addr[5]) &
6940                 TX_BACKOFF_SEED_MASK;
6941         tw32(MAC_TX_BACKOFF_SEED, addr_high);
6942 }
6943
6944 static int tg3_set_mac_addr(struct net_device *dev, void *p)
6945 {
6946         struct tg3 *tp = netdev_priv(dev);
6947         struct sockaddr *addr = p;
6948         int err = 0, skip_mac_1 = 0;
6949
6950         if (!is_valid_ether_addr(addr->sa_data))
6951                 return -EINVAL;
6952
6953         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
6954
6955         if (!netif_running(dev))
6956                 return 0;
6957
6958         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6959                 u32 addr0_high, addr0_low, addr1_high, addr1_low;
6960
6961                 addr0_high = tr32(MAC_ADDR_0_HIGH);
6962                 addr0_low = tr32(MAC_ADDR_0_LOW);
6963                 addr1_high = tr32(MAC_ADDR_1_HIGH);
6964                 addr1_low = tr32(MAC_ADDR_1_LOW);
6965
6966                 /* Skip MAC addr 1 if ASF is using it. */
6967                 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
6968                     !(addr1_high == 0 && addr1_low == 0))
6969                         skip_mac_1 = 1;
6970         }
6971         spin_lock_bh(&tp->lock);
6972         __tg3_set_mac_addr(tp, skip_mac_1);
6973         spin_unlock_bh(&tp->lock);
6974
6975         return err;
6976 }
6977
6978 /* tp->lock is held. */
6979 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
6980                            dma_addr_t mapping, u32 maxlen_flags,
6981                            u32 nic_addr)
6982 {
6983         tg3_write_mem(tp,
6984                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
6985                       ((u64) mapping >> 32));
6986         tg3_write_mem(tp,
6987                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
6988                       ((u64) mapping & 0xffffffff));
6989         tg3_write_mem(tp,
6990                       (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
6991                        maxlen_flags);
6992
6993         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6994                 tg3_write_mem(tp,
6995                               (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
6996                               nic_addr);
6997 }
6998
6999 static void __tg3_set_rx_mode(struct net_device *);
7000 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
7001 {
7002         tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7003         tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7004         tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7005         tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7006         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7007                 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7008                 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7009         }
7010         tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7011         tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
7012         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7013                 u32 val = ec->stats_block_coalesce_usecs;
7014
7015                 if (!netif_carrier_ok(tp->dev))
7016                         val = 0;
7017
7018                 tw32(HOSTCC_STAT_COAL_TICKS, val);
7019         }
7020 }
7021
7022 /* tp->lock is held. */
7023 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7024 {
7025         u32 val, rdmac_mode;
7026         int i, err, limit;
7027
7028         tg3_disable_ints(tp);
7029
7030         tg3_stop_fw(tp);
7031
7032         tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7033
7034         if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
7035                 tg3_abort_hw(tp, 1);
7036         }
7037
7038         if (reset_phy &&
7039             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB))
7040                 tg3_phy_reset(tp);
7041
7042         err = tg3_chip_reset(tp);
7043         if (err)
7044                 return err;
7045
7046         tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7047
7048         if (tp->pci_chip_rev_id == CHIPREV_ID_5784_A0 ||
7049             tp->pci_chip_rev_id == CHIPREV_ID_5784_A1) {
7050                 val = tr32(TG3_CPMU_CTRL);
7051                 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7052                 tw32(TG3_CPMU_CTRL, val);
7053
7054                 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7055                 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7056                 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7057                 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7058
7059                 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7060                 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7061                 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7062                 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7063
7064                 val = tr32(TG3_CPMU_HST_ACC);
7065                 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7066                 val |= CPMU_HST_ACC_MACCLK_6_25;
7067                 tw32(TG3_CPMU_HST_ACC, val);
7068         }
7069
7070         /* This works around an issue with Athlon chipsets on
7071          * B3 tigon3 silicon.  This bit has no effect on any
7072          * other revision.  But do not set this on PCI Express
7073          * chips and don't even touch the clocks if the CPMU is present.
7074          */
7075         if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7076                 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7077                         tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7078                 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7079         }
7080
7081         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7082             (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7083                 val = tr32(TG3PCI_PCISTATE);
7084                 val |= PCISTATE_RETRY_SAME_DMA;
7085                 tw32(TG3PCI_PCISTATE, val);
7086         }
7087
7088         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7089                 /* Allow reads and writes to the
7090                  * APE register and memory space.
7091                  */
7092                 val = tr32(TG3PCI_PCISTATE);
7093                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7094                        PCISTATE_ALLOW_APE_SHMEM_WR;
7095                 tw32(TG3PCI_PCISTATE, val);
7096         }
7097
7098         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7099                 /* Enable some hw fixes.  */
7100                 val = tr32(TG3PCI_MSI_DATA);
7101                 val |= (1 << 26) | (1 << 28) | (1 << 29);
7102                 tw32(TG3PCI_MSI_DATA, val);
7103         }
7104
7105         /* Descriptor ring init may make accesses to the
7106          * NIC SRAM area to setup the TX descriptors, so we
7107          * can only do this after the hardware has been
7108          * successfully reset.
7109          */
7110         err = tg3_init_rings(tp);
7111         if (err)
7112                 return err;
7113
7114         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7115             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761 &&
7116             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
7117                 /* This value is determined during the probe time DMA
7118                  * engine test, tg3_test_dma.
7119                  */
7120                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7121         }
7122
7123         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7124                           GRC_MODE_4X_NIC_SEND_RINGS |
7125                           GRC_MODE_NO_TX_PHDR_CSUM |
7126                           GRC_MODE_NO_RX_PHDR_CSUM);
7127         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
7128
7129         /* Pseudo-header checksum is done by hardware logic and not
7130          * the offload processers, so make the chip do the pseudo-
7131          * header checksums on receive.  For transmit it is more
7132          * convenient to do the pseudo-header checksum in software
7133          * as Linux does that on transmit for us in all cases.
7134          */
7135         tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
7136
7137         tw32(GRC_MODE,
7138              tp->grc_mode |
7139              (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7140
7141         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
7142         val = tr32(GRC_MISC_CFG);
7143         val &= ~0xff;
7144         val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7145         tw32(GRC_MISC_CFG, val);
7146
7147         /* Initialize MBUF/DESC pool. */
7148         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7149                 /* Do nothing.  */
7150         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7151                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7152                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7153                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7154                 else
7155                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7156                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7157                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7158         }
7159         else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7160                 int fw_len;
7161
7162                 fw_len = (TG3_TSO5_FW_TEXT_LEN +
7163                           TG3_TSO5_FW_RODATA_LEN +
7164                           TG3_TSO5_FW_DATA_LEN +
7165                           TG3_TSO5_FW_SBSS_LEN +
7166                           TG3_TSO5_FW_BSS_LEN);
7167                 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7168                 tw32(BUFMGR_MB_POOL_ADDR,
7169                      NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7170                 tw32(BUFMGR_MB_POOL_SIZE,
7171                      NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
7172         }
7173
7174         if (tp->dev->mtu <= ETH_DATA_LEN) {
7175                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7176                      tp->bufmgr_config.mbuf_read_dma_low_water);
7177                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7178                      tp->bufmgr_config.mbuf_mac_rx_low_water);
7179                 tw32(BUFMGR_MB_HIGH_WATER,
7180                      tp->bufmgr_config.mbuf_high_water);
7181         } else {
7182                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7183                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
7184                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7185                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
7186                 tw32(BUFMGR_MB_HIGH_WATER,
7187                      tp->bufmgr_config.mbuf_high_water_jumbo);
7188         }
7189         tw32(BUFMGR_DMA_LOW_WATER,
7190              tp->bufmgr_config.dma_low_water);
7191         tw32(BUFMGR_DMA_HIGH_WATER,
7192              tp->bufmgr_config.dma_high_water);
7193
7194         tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
7195         for (i = 0; i < 2000; i++) {
7196                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
7197                         break;
7198                 udelay(10);
7199         }
7200         if (i >= 2000) {
7201                 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
7202                        tp->dev->name);
7203                 return -ENODEV;
7204         }
7205
7206         /* Setup replenish threshold. */
7207         val = tp->rx_pending / 8;
7208         if (val == 0)
7209                 val = 1;
7210         else if (val > tp->rx_std_max_post)
7211                 val = tp->rx_std_max_post;
7212         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7213                 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7214                         tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7215
7216                 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7217                         val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7218         }
7219
7220         tw32(RCVBDI_STD_THRESH, val);
7221
7222         /* Initialize TG3_BDINFO's at:
7223          *  RCVDBDI_STD_BD:     standard eth size rx ring
7224          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
7225          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
7226          *
7227          * like so:
7228          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
7229          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
7230          *                              ring attribute flags
7231          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
7232          *
7233          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7234          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7235          *
7236          * The size of each ring is fixed in the firmware, but the location is
7237          * configurable.
7238          */
7239         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7240              ((u64) tp->rx_std_mapping >> 32));
7241         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7242              ((u64) tp->rx_std_mapping & 0xffffffff));
7243         tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7244              NIC_SRAM_RX_BUFFER_DESC);
7245
7246         /* Don't even try to program the JUMBO/MINI buffer descriptor
7247          * configs on 5705.
7248          */
7249         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
7250                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
7251                      RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
7252         } else {
7253                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
7254                      RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
7255
7256                 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7257                      BDINFO_FLAGS_DISABLED);
7258
7259                 /* Setup replenish threshold. */
7260                 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7261
7262                 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
7263                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7264                              ((u64) tp->rx_jumbo_mapping >> 32));
7265                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7266                              ((u64) tp->rx_jumbo_mapping & 0xffffffff));
7267                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7268                              RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
7269                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7270                              NIC_SRAM_RX_JUMBO_BUFFER_DESC);
7271                 } else {
7272                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7273                              BDINFO_FLAGS_DISABLED);
7274                 }
7275
7276         }
7277
7278         /* There is only one send ring on 5705/5750, no need to explicitly
7279          * disable the others.
7280          */
7281         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7282                 /* Clear out send RCB ring in SRAM. */
7283                 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
7284                         tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
7285                                       BDINFO_FLAGS_DISABLED);
7286         }
7287
7288         tp->tx_prod = 0;
7289         tp->tx_cons = 0;
7290         tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
7291         tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
7292
7293         tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
7294                        tp->tx_desc_mapping,
7295                        (TG3_TX_RING_SIZE <<
7296                         BDINFO_FLAGS_MAXLEN_SHIFT),
7297                        NIC_SRAM_TX_BUFFER_DESC);
7298
7299         /* There is only one receive return ring on 5705/5750, no need
7300          * to explicitly disable the others.
7301          */
7302         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7303                 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
7304                      i += TG3_BDINFO_SIZE) {
7305                         tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
7306                                       BDINFO_FLAGS_DISABLED);
7307                 }
7308         }
7309
7310         tp->rx_rcb_ptr = 0;
7311         tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
7312
7313         tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
7314                        tp->rx_rcb_mapping,
7315                        (TG3_RX_RCB_RING_SIZE(tp) <<
7316                         BDINFO_FLAGS_MAXLEN_SHIFT),
7317                        0);
7318
7319         tp->rx_std_ptr = tp->rx_pending;
7320         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
7321                      tp->rx_std_ptr);
7322
7323         tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
7324                                                 tp->rx_jumbo_pending : 0;
7325         tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
7326                      tp->rx_jumbo_ptr);
7327
7328         /* Initialize MAC address and backoff seed. */
7329         __tg3_set_mac_addr(tp, 0);
7330
7331         /* MTU + ethernet header + FCS + optional VLAN tag */
7332         tw32(MAC_RX_MTU_SIZE, tp->dev->mtu + ETH_HLEN + 8);
7333
7334         /* The slot time is changed by tg3_setup_phy if we
7335          * run at gigabit with half duplex.
7336          */
7337         tw32(MAC_TX_LENGTHS,
7338              (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7339              (6 << TX_LENGTHS_IPG_SHIFT) |
7340              (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7341
7342         /* Receive rules. */
7343         tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7344         tw32(RCVLPC_CONFIG, 0x0181);
7345
7346         /* Calculate RDMAC_MODE setting early, we need it to determine
7347          * the RCVLPC_STATE_ENABLE mask.
7348          */
7349         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7350                       RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7351                       RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7352                       RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7353                       RDMAC_MODE_LNGREAD_ENAB);
7354
7355         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
7356             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
7357                 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7358                               RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7359                               RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7360
7361         /* If statement applies to 5705 and 5750 PCI devices only */
7362         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7363              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7364             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
7365                 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
7366                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7367                         rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7368                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7369                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7370                         rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7371                 }
7372         }
7373
7374         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7375                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7376
7377         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7378                 rdmac_mode |= (1 << 27);
7379
7380         /* Receive/send statistics. */
7381         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7382                 val = tr32(RCVLPC_STATS_ENABLE);
7383                 val &= ~RCVLPC_STATSENAB_DACK_FIX;
7384                 tw32(RCVLPC_STATS_ENABLE, val);
7385         } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
7386                    (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7387                 val = tr32(RCVLPC_STATS_ENABLE);
7388                 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
7389                 tw32(RCVLPC_STATS_ENABLE, val);
7390         } else {
7391                 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
7392         }
7393         tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
7394         tw32(SNDDATAI_STATSENAB, 0xffffff);
7395         tw32(SNDDATAI_STATSCTRL,
7396              (SNDDATAI_SCTRL_ENABLE |
7397               SNDDATAI_SCTRL_FASTUPD));
7398
7399         /* Setup host coalescing engine. */
7400         tw32(HOSTCC_MODE, 0);
7401         for (i = 0; i < 2000; i++) {
7402                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
7403                         break;
7404                 udelay(10);
7405         }
7406
7407         __tg3_set_coalesce(tp, &tp->coal);
7408
7409         /* set status block DMA address */
7410         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7411              ((u64) tp->status_mapping >> 32));
7412         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7413              ((u64) tp->status_mapping & 0xffffffff));
7414
7415         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7416                 /* Status/statistics block address.  See tg3_timer,
7417                  * the tg3_periodic_fetch_stats call there, and
7418                  * tg3_get_stats to see how this works for 5705/5750 chips.
7419                  */
7420                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7421                      ((u64) tp->stats_mapping >> 32));
7422                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7423                      ((u64) tp->stats_mapping & 0xffffffff));
7424                 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
7425                 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
7426         }
7427
7428         tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
7429
7430         tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
7431         tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
7432         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7433                 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
7434
7435         /* Clear statistics/status block in chip, and status block in ram. */
7436         for (i = NIC_SRAM_STATS_BLK;
7437              i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
7438              i += sizeof(u32)) {
7439                 tg3_write_mem(tp, i, 0);
7440                 udelay(40);
7441         }
7442         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
7443
7444         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7445                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
7446                 /* reset to prevent losing 1st rx packet intermittently */
7447                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7448                 udelay(10);
7449         }
7450
7451         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7452                 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
7453         else
7454                 tp->mac_mode = 0;
7455         tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
7456                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
7457         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7458             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7459             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
7460                 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
7461         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
7462         udelay(40);
7463
7464         /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
7465          * If TG3_FLG2_IS_NIC is zero, we should read the
7466          * register to preserve the GPIO settings for LOMs. The GPIOs,
7467          * whether used as inputs or outputs, are set by boot code after
7468          * reset.
7469          */
7470         if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
7471                 u32 gpio_mask;
7472
7473                 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
7474                             GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
7475                             GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
7476
7477                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7478                         gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
7479                                      GRC_LCLCTRL_GPIO_OUTPUT3;
7480
7481                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7482                         gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
7483
7484                 tp->grc_local_ctrl &= ~gpio_mask;
7485                 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
7486
7487                 /* GPIO1 must be driven high for eeprom write protect */
7488                 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
7489                         tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
7490                                                GRC_LCLCTRL_GPIO_OUTPUT1);
7491         }
7492         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7493         udelay(100);
7494
7495         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
7496         tp->last_tag = 0;
7497
7498         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7499                 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
7500                 udelay(40);
7501         }
7502
7503         val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
7504                WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
7505                WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
7506                WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
7507                WDMAC_MODE_LNGREAD_ENAB);
7508
7509         /* If statement applies to 5705 and 5750 PCI devices only */
7510         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7511              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7512             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
7513                 if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) &&
7514                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
7515                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
7516                         /* nothing */
7517                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7518                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
7519                            !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
7520                         val |= WDMAC_MODE_RX_ACCEL;
7521                 }
7522         }
7523
7524         /* Enable host coalescing bug fix */
7525         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) ||
7526             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) ||
7527             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784) ||
7528             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) ||
7529             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785))
7530                 val |= WDMAC_MODE_STATUS_TAG_FIX;
7531
7532         tw32_f(WDMAC_MODE, val);
7533         udelay(40);
7534
7535         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
7536                 u16 pcix_cmd;
7537
7538                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7539                                      &pcix_cmd);
7540                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
7541                         pcix_cmd &= ~PCI_X_CMD_MAX_READ;
7542                         pcix_cmd |= PCI_X_CMD_READ_2K;
7543                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
7544                         pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
7545                         pcix_cmd |= PCI_X_CMD_READ_2K;
7546                 }
7547                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7548                                       pcix_cmd);
7549         }
7550
7551         tw32_f(RDMAC_MODE, rdmac_mode);
7552         udelay(40);
7553
7554         tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
7555         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7556                 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
7557
7558         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
7559                 tw32(SNDDATAC_MODE,
7560                      SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
7561         else
7562                 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
7563
7564         tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
7565         tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
7566         tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
7567         tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
7568         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7569                 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
7570         tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
7571         tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
7572
7573         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7574                 err = tg3_load_5701_a0_firmware_fix(tp);
7575                 if (err)
7576                         return err;
7577         }
7578
7579         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7580                 err = tg3_load_tso_firmware(tp);
7581                 if (err)
7582                         return err;
7583         }
7584
7585         tp->tx_mode = TX_MODE_ENABLE;
7586         tw32_f(MAC_TX_MODE, tp->tx_mode);
7587         udelay(100);
7588
7589         tp->rx_mode = RX_MODE_ENABLE;
7590         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
7591             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
7592             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
7593             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
7594                 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
7595
7596         tw32_f(MAC_RX_MODE, tp->rx_mode);
7597         udelay(10);
7598
7599         tw32(MAC_LED_CTRL, tp->led_ctrl);
7600
7601         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
7602         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7603                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7604                 udelay(10);
7605         }
7606         tw32_f(MAC_RX_MODE, tp->rx_mode);
7607         udelay(10);
7608
7609         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7610                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
7611                         !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
7612                         /* Set drive transmission level to 1.2V  */
7613                         /* only if the signal pre-emphasis bit is not set  */
7614                         val = tr32(MAC_SERDES_CFG);
7615                         val &= 0xfffff000;
7616                         val |= 0x880;
7617                         tw32(MAC_SERDES_CFG, val);
7618                 }
7619                 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
7620                         tw32(MAC_SERDES_CFG, 0x616000);
7621         }
7622
7623         /* Prevent chip from dropping frames when flow control
7624          * is enabled.
7625          */
7626         tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
7627
7628         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
7629             (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
7630                 /* Use hardware link auto-negotiation */
7631                 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
7632         }
7633
7634         if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
7635             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
7636                 u32 tmp;
7637
7638                 tmp = tr32(SERDES_RX_CTRL);
7639                 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
7640                 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
7641                 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
7642                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7643         }
7644
7645         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
7646                 if (tp->link_config.phy_is_low_power) {
7647                         tp->link_config.phy_is_low_power = 0;
7648                         tp->link_config.speed = tp->link_config.orig_speed;
7649                         tp->link_config.duplex = tp->link_config.orig_duplex;
7650                         tp->link_config.autoneg = tp->link_config.orig_autoneg;
7651                 }
7652
7653                 err = tg3_setup_phy(tp, 0);
7654                 if (err)
7655                         return err;
7656
7657                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7658                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) {
7659                         u32 tmp;
7660
7661                         /* Clear CRC stats. */
7662                         if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
7663                                 tg3_writephy(tp, MII_TG3_TEST1,
7664                                              tmp | MII_TG3_TEST1_CRC_EN);
7665                                 tg3_readphy(tp, 0x14, &tmp);
7666                         }
7667                 }
7668         }
7669
7670         __tg3_set_rx_mode(tp->dev);
7671
7672         /* Initialize receive rules. */
7673         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
7674         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
7675         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
7676         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
7677
7678         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7679             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
7680                 limit = 8;
7681         else
7682                 limit = 16;
7683         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
7684                 limit -= 4;
7685         switch (limit) {
7686         case 16:
7687                 tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
7688         case 15:
7689                 tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
7690         case 14:
7691                 tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
7692         case 13:
7693                 tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
7694         case 12:
7695                 tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
7696         case 11:
7697                 tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
7698         case 10:
7699                 tw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);
7700         case 9:
7701                 tw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);
7702         case 8:
7703                 tw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);
7704         case 7:
7705                 tw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);
7706         case 6:
7707                 tw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);
7708         case 5:
7709                 tw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);
7710         case 4:
7711                 /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
7712         case 3:
7713                 /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
7714         case 2:
7715         case 1:
7716
7717         default:
7718                 break;
7719         }
7720
7721         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7722                 /* Write our heartbeat update interval to APE. */
7723                 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
7724                                 APE_HOST_HEARTBEAT_INT_DISABLE);
7725
7726         tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
7727
7728         return 0;
7729 }
7730
7731 /* Called at device open time to get the chip ready for
7732  * packet processing.  Invoked with tp->lock held.
7733  */
7734 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
7735 {
7736         tg3_switch_clocks(tp);
7737
7738         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
7739
7740         return tg3_reset_hw(tp, reset_phy);
7741 }
7742
7743 #define TG3_STAT_ADD32(PSTAT, REG) \
7744 do {    u32 __val = tr32(REG); \
7745         (PSTAT)->low += __val; \
7746         if ((PSTAT)->low < __val) \
7747                 (PSTAT)->high += 1; \
7748 } while (0)
7749
7750 static void tg3_periodic_fetch_stats(struct tg3 *tp)
7751 {
7752         struct tg3_hw_stats *sp = tp->hw_stats;
7753
7754         if (!netif_carrier_ok(tp->dev))
7755                 return;
7756
7757         TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
7758         TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
7759         TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
7760         TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
7761         TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
7762         TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
7763         TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
7764         TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
7765         TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
7766         TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
7767         TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
7768         TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
7769         TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
7770
7771         TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
7772         TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
7773         TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
7774         TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
7775         TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
7776         TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
7777         TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
7778         TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
7779         TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
7780         TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
7781         TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
7782         TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
7783         TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
7784         TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
7785
7786         TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
7787         TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
7788         TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
7789 }
7790
7791 static void tg3_timer(unsigned long __opaque)
7792 {
7793         struct tg3 *tp = (struct tg3 *) __opaque;
7794
7795         if (tp->irq_sync)
7796                 goto restart_timer;
7797
7798         spin_lock(&tp->lock);
7799
7800         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7801                 /* All of this garbage is because when using non-tagged
7802                  * IRQ status the mailbox/status_block protocol the chip
7803                  * uses with the cpu is race prone.
7804                  */
7805                 if (tp->hw_status->status & SD_STATUS_UPDATED) {
7806                         tw32(GRC_LOCAL_CTRL,
7807                              tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
7808                 } else {
7809                         tw32(HOSTCC_MODE, tp->coalesce_mode |
7810                              (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
7811                 }
7812
7813                 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
7814                         tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
7815                         spin_unlock(&tp->lock);
7816                         schedule_work(&tp->reset_task);
7817                         return;
7818                 }
7819         }
7820
7821         /* This part only runs once per second. */
7822         if (!--tp->timer_counter) {
7823                 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7824                         tg3_periodic_fetch_stats(tp);
7825
7826                 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
7827                         u32 mac_stat;
7828                         int phy_event;
7829
7830                         mac_stat = tr32(MAC_STATUS);
7831
7832                         phy_event = 0;
7833                         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
7834                                 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
7835                                         phy_event = 1;
7836                         } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
7837                                 phy_event = 1;
7838
7839                         if (phy_event)
7840                                 tg3_setup_phy(tp, 0);
7841                 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
7842                         u32 mac_stat = tr32(MAC_STATUS);
7843                         int need_setup = 0;
7844
7845                         if (netif_carrier_ok(tp->dev) &&
7846                             (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
7847                                 need_setup = 1;
7848                         }
7849                         if (! netif_carrier_ok(tp->dev) &&
7850                             (mac_stat & (MAC_STATUS_PCS_SYNCED |
7851                                          MAC_STATUS_SIGNAL_DET))) {
7852                                 need_setup = 1;
7853                         }
7854                         if (need_setup) {
7855                                 if (!tp->serdes_counter) {
7856                                         tw32_f(MAC_MODE,
7857                                              (tp->mac_mode &
7858                                               ~MAC_MODE_PORT_MODE_MASK));
7859                                         udelay(40);
7860                                         tw32_f(MAC_MODE, tp->mac_mode);
7861                                         udelay(40);
7862                                 }
7863                                 tg3_setup_phy(tp, 0);
7864                         }
7865                 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
7866                         tg3_serdes_parallel_detect(tp);
7867
7868                 tp->timer_counter = tp->timer_multiplier;
7869         }
7870
7871         /* Heartbeat is only sent once every 2 seconds.
7872          *
7873          * The heartbeat is to tell the ASF firmware that the host
7874          * driver is still alive.  In the event that the OS crashes,
7875          * ASF needs to reset the hardware to free up the FIFO space
7876          * that may be filled with rx packets destined for the host.
7877          * If the FIFO is full, ASF will no longer function properly.
7878          *
7879          * Unintended resets have been reported on real time kernels
7880          * where the timer doesn't run on time.  Netpoll will also have
7881          * same problem.
7882          *
7883          * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
7884          * to check the ring condition when the heartbeat is expiring
7885          * before doing the reset.  This will prevent most unintended
7886          * resets.
7887          */
7888         if (!--tp->asf_counter) {
7889                 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7890                     !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7891                         tg3_wait_for_event_ack(tp);
7892
7893                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
7894                                       FWCMD_NICDRV_ALIVE3);
7895                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
7896                         /* 5 seconds timeout */
7897                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
7898
7899                         tg3_generate_fw_event(tp);
7900                 }
7901                 tp->asf_counter = tp->asf_multiplier;
7902         }
7903
7904         spin_unlock(&tp->lock);
7905
7906 restart_timer:
7907         tp->timer.expires = jiffies + tp->timer_offset;
7908         add_timer(&tp->timer);
7909 }
7910
7911 static int tg3_request_irq(struct tg3 *tp)
7912 {
7913         irq_handler_t fn;
7914         unsigned long flags;
7915         struct net_device *dev = tp->dev;
7916
7917         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7918                 fn = tg3_msi;
7919                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
7920                         fn = tg3_msi_1shot;
7921                 flags = IRQF_SAMPLE_RANDOM;
7922         } else {
7923                 fn = tg3_interrupt;
7924                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7925                         fn = tg3_interrupt_tagged;
7926                 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
7927         }
7928         return (request_irq(tp->pdev->irq, fn, flags, dev->name, dev));
7929 }
7930
7931 static int tg3_test_interrupt(struct tg3 *tp)
7932 {
7933         struct net_device *dev = tp->dev;
7934         int err, i, intr_ok = 0;
7935
7936         if (!netif_running(dev))
7937                 return -ENODEV;
7938
7939         tg3_disable_ints(tp);
7940
7941         free_irq(tp->pdev->irq, dev);
7942
7943         err = request_irq(tp->pdev->irq, tg3_test_isr,
7944                           IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
7945         if (err)
7946                 return err;
7947
7948         tp->hw_status->status &= ~SD_STATUS_UPDATED;
7949         tg3_enable_ints(tp);
7950
7951         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
7952                HOSTCC_MODE_NOW);
7953
7954         for (i = 0; i < 5; i++) {
7955                 u32 int_mbox, misc_host_ctrl;
7956
7957                 int_mbox = tr32_mailbox(MAILBOX_INTERRUPT_0 +
7958                                         TG3_64BIT_REG_LOW);
7959                 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
7960
7961                 if ((int_mbox != 0) ||
7962                     (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
7963                         intr_ok = 1;
7964                         break;
7965                 }
7966
7967                 msleep(10);
7968         }
7969
7970         tg3_disable_ints(tp);
7971
7972         free_irq(tp->pdev->irq, dev);
7973
7974         err = tg3_request_irq(tp);
7975
7976         if (err)
7977                 return err;
7978
7979         if (intr_ok)
7980                 return 0;
7981
7982         return -EIO;
7983 }
7984
7985 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
7986  * successfully restored
7987  */
7988 static int tg3_test_msi(struct tg3 *tp)
7989 {
7990         struct net_device *dev = tp->dev;
7991         int err;
7992         u16 pci_cmd;
7993
7994         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
7995                 return 0;
7996
7997         /* Turn off SERR reporting in case MSI terminates with Master
7998          * Abort.
7999          */
8000         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8001         pci_write_config_word(tp->pdev, PCI_COMMAND,
8002                               pci_cmd & ~PCI_COMMAND_SERR);
8003
8004         err = tg3_test_interrupt(tp);
8005
8006         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8007
8008         if (!err)
8009                 return 0;
8010
8011         /* other failures */
8012         if (err != -EIO)
8013                 return err;
8014
8015         /* MSI test failed, go back to INTx mode */
8016         printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
8017                "switching to INTx mode. Please report this failure to "
8018                "the PCI maintainer and include system chipset information.\n",
8019                        tp->dev->name);
8020
8021         free_irq(tp->pdev->irq, dev);
8022         pci_disable_msi(tp->pdev);
8023
8024         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8025
8026         err = tg3_request_irq(tp);
8027         if (err)
8028                 return err;
8029
8030         /* Need to reset the chip because the MSI cycle may have terminated
8031          * with Master Abort.
8032          */
8033         tg3_full_lock(tp, 1);
8034
8035         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8036         err = tg3_init_hw(tp, 1);
8037
8038         tg3_full_unlock(tp);
8039
8040         if (err)
8041                 free_irq(tp->pdev->irq, dev);
8042
8043         return err;
8044 }
8045
8046 static int tg3_open(struct net_device *dev)
8047 {
8048         struct tg3 *tp = netdev_priv(dev);
8049         int err;
8050
8051         netif_carrier_off(tp->dev);
8052
8053         err = tg3_set_power_state(tp, PCI_D0);
8054         if (err)
8055                 return err;
8056
8057         tg3_full_lock(tp, 0);
8058
8059         tg3_disable_ints(tp);
8060         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8061
8062         tg3_full_unlock(tp);
8063
8064         /* The placement of this call is tied
8065          * to the setup and use of Host TX descriptors.
8066          */
8067         err = tg3_alloc_consistent(tp);
8068         if (err)
8069                 return err;
8070
8071         if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) {
8072                 /* All MSI supporting chips should support tagged
8073                  * status.  Assert that this is the case.
8074                  */
8075                 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8076                         printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
8077                                "Not using MSI.\n", tp->dev->name);
8078                 } else if (pci_enable_msi(tp->pdev) == 0) {
8079                         u32 msi_mode;
8080
8081                         msi_mode = tr32(MSGINT_MODE);
8082                         tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
8083                         tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
8084                 }
8085         }
8086         err = tg3_request_irq(tp);
8087
8088         if (err) {
8089                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8090                         pci_disable_msi(tp->pdev);
8091                         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8092                 }
8093                 tg3_free_consistent(tp);
8094                 return err;
8095         }
8096
8097         napi_enable(&tp->napi);
8098
8099         tg3_full_lock(tp, 0);
8100
8101         err = tg3_init_hw(tp, 1);
8102         if (err) {
8103                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8104                 tg3_free_rings(tp);
8105         } else {
8106                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8107                         tp->timer_offset = HZ;
8108                 else
8109                         tp->timer_offset = HZ / 10;
8110
8111                 BUG_ON(tp->timer_offset > HZ);
8112                 tp->timer_counter = tp->timer_multiplier =
8113                         (HZ / tp->timer_offset);
8114                 tp->asf_counter = tp->asf_multiplier =
8115                         ((HZ / tp->timer_offset) * 2);
8116
8117                 init_timer(&tp->timer);
8118                 tp->timer.expires = jiffies + tp->timer_offset;
8119                 tp->timer.data = (unsigned long) tp;
8120                 tp->timer.function = tg3_timer;
8121         }
8122
8123         tg3_full_unlock(tp);
8124
8125         if (err) {
8126                 napi_disable(&tp->napi);
8127                 free_irq(tp->pdev->irq, dev);
8128                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8129                         pci_disable_msi(tp->pdev);
8130                         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8131                 }
8132                 tg3_free_consistent(tp);
8133                 return err;
8134         }
8135
8136         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8137                 err = tg3_test_msi(tp);
8138
8139                 if (err) {
8140                         tg3_full_lock(tp, 0);
8141
8142                         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8143                                 pci_disable_msi(tp->pdev);
8144                                 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8145                         }
8146                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8147                         tg3_free_rings(tp);
8148                         tg3_free_consistent(tp);
8149
8150                         tg3_full_unlock(tp);
8151
8152                         napi_disable(&tp->napi);
8153
8154                         return err;
8155                 }
8156
8157                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8158                         if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) {
8159                                 u32 val = tr32(PCIE_TRANSACTION_CFG);
8160
8161                                 tw32(PCIE_TRANSACTION_CFG,
8162                                      val | PCIE_TRANS_CFG_1SHOT_MSI);
8163                         }
8164                 }
8165         }
8166
8167         tg3_phy_start(tp);
8168
8169         tg3_full_lock(tp, 0);
8170
8171         add_timer(&tp->timer);
8172         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
8173         tg3_enable_ints(tp);
8174
8175         tg3_full_unlock(tp);
8176
8177         netif_start_queue(dev);
8178
8179         return 0;
8180 }
8181
8182 #if 0
8183 /*static*/ void tg3_dump_state(struct tg3 *tp)
8184 {
8185         u32 val32, val32_2, val32_3, val32_4, val32_5;
8186         u16 val16;
8187         int i;
8188
8189         pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
8190         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
8191         printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
8192                val16, val32);
8193
8194         /* MAC block */
8195         printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
8196                tr32(MAC_MODE), tr32(MAC_STATUS));
8197         printk("       MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
8198                tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
8199         printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
8200                tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
8201         printk("       MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
8202                tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
8203
8204         /* Send data initiator control block */
8205         printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
8206                tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
8207         printk("       SNDDATAI_STATSCTRL[%08x]\n",
8208                tr32(SNDDATAI_STATSCTRL));
8209
8210         /* Send data completion control block */
8211         printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
8212
8213         /* Send BD ring selector block */
8214         printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
8215                tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
8216
8217         /* Send BD initiator control block */
8218         printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
8219                tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
8220
8221         /* Send BD completion control block */
8222         printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
8223
8224         /* Receive list placement control block */
8225         printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
8226                tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
8227         printk("       RCVLPC_STATSCTRL[%08x]\n",
8228                tr32(RCVLPC_STATSCTRL));
8229
8230         /* Receive data and receive BD initiator control block */
8231         printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
8232                tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
8233
8234         /* Receive data completion control block */
8235         printk("DEBUG: RCVDCC_MODE[%08x]\n",
8236                tr32(RCVDCC_MODE));
8237
8238         /* Receive BD initiator control block */
8239         printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
8240                tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
8241
8242         /* Receive BD completion control block */
8243         printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
8244                tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
8245
8246         /* Receive list selector control block */
8247         printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
8248                tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
8249
8250         /* Mbuf cluster free block */
8251         printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
8252                tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
8253
8254         /* Host coalescing control block */
8255         printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
8256                tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
8257         printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
8258                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8259                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8260         printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
8261                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8262                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8263         printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
8264                tr32(HOSTCC_STATS_BLK_NIC_ADDR));
8265         printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
8266                tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
8267
8268         /* Memory arbiter control block */
8269         printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
8270                tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
8271
8272         /* Buffer manager control block */
8273         printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
8274                tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
8275         printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
8276                tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
8277         printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
8278                "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
8279                tr32(BUFMGR_DMA_DESC_POOL_ADDR),
8280                tr32(BUFMGR_DMA_DESC_POOL_SIZE));
8281
8282         /* Read DMA control block */
8283         printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
8284                tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
8285
8286         /* Write DMA control block */
8287         printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
8288                tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
8289
8290         /* DMA completion block */
8291         printk("DEBUG: DMAC_MODE[%08x]\n",
8292                tr32(DMAC_MODE));
8293
8294         /* GRC block */
8295         printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
8296                tr32(GRC_MODE), tr32(GRC_MISC_CFG));
8297         printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
8298                tr32(GRC_LOCAL_CTRL));
8299
8300         /* TG3_BDINFOs */
8301         printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
8302                tr32(RCVDBDI_JUMBO_BD + 0x0),
8303                tr32(RCVDBDI_JUMBO_BD + 0x4),
8304                tr32(RCVDBDI_JUMBO_BD + 0x8),
8305                tr32(RCVDBDI_JUMBO_BD + 0xc));
8306         printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
8307                tr32(RCVDBDI_STD_BD + 0x0),
8308                tr32(RCVDBDI_STD_BD + 0x4),
8309                tr32(RCVDBDI_STD_BD + 0x8),
8310                tr32(RCVDBDI_STD_BD + 0xc));
8311         printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
8312                tr32(RCVDBDI_MINI_BD + 0x0),
8313                tr32(RCVDBDI_MINI_BD + 0x4),
8314                tr32(RCVDBDI_MINI_BD + 0x8),
8315                tr32(RCVDBDI_MINI_BD + 0xc));
8316
8317         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
8318         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
8319         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
8320         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
8321         printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
8322                val32, val32_2, val32_3, val32_4);
8323
8324         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
8325         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
8326         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
8327         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
8328         printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
8329                val32, val32_2, val32_3, val32_4);
8330
8331         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
8332         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
8333         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
8334         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
8335         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
8336         printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
8337                val32, val32_2, val32_3, val32_4, val32_5);
8338
8339         /* SW status block */
8340         printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
8341                tp->hw_status->status,
8342                tp->hw_status->status_tag,
8343                tp->hw_status->rx_jumbo_consumer,
8344                tp->hw_status->rx_consumer,
8345                tp->hw_status->rx_mini_consumer,
8346                tp->hw_status->idx[0].rx_producer,
8347                tp->hw_status->idx[0].tx_consumer);
8348
8349         /* SW statistics block */
8350         printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
8351                ((u32 *)tp->hw_stats)[0],
8352                ((u32 *)tp->hw_stats)[1],
8353                ((u32 *)tp->hw_stats)[2],
8354                ((u32 *)tp->hw_stats)[3]);
8355
8356         /* Mailboxes */
8357         printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
8358                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
8359                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
8360                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
8361                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
8362
8363         /* NIC side send descriptors. */
8364         for (i = 0; i < 6; i++) {
8365                 unsigned long txd;
8366
8367                 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
8368                         + (i * sizeof(struct tg3_tx_buffer_desc));
8369                 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
8370                        i,
8371                        readl(txd + 0x0), readl(txd + 0x4),
8372                        readl(txd + 0x8), readl(txd + 0xc));
8373         }
8374
8375         /* NIC side RX descriptors. */
8376         for (i = 0; i < 6; i++) {
8377                 unsigned long rxd;
8378
8379                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
8380                         + (i * sizeof(struct tg3_rx_buffer_desc));
8381                 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
8382                        i,
8383                        readl(rxd + 0x0), readl(rxd + 0x4),
8384                        readl(rxd + 0x8), readl(rxd + 0xc));
8385                 rxd += (4 * sizeof(u32));
8386                 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
8387                        i,
8388                        readl(rxd + 0x0), readl(rxd + 0x4),
8389                        readl(rxd + 0x8), readl(rxd + 0xc));
8390         }
8391
8392         for (i = 0; i < 6; i++) {
8393                 unsigned long rxd;
8394
8395                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
8396                         + (i * sizeof(struct tg3_rx_buffer_desc));
8397                 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
8398                        i,
8399                        readl(rxd + 0x0), readl(rxd + 0x4),
8400                        readl(rxd + 0x8), readl(rxd + 0xc));
8401                 rxd += (4 * sizeof(u32));
8402                 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
8403                        i,
8404                        readl(rxd + 0x0), readl(rxd + 0x4),
8405                        readl(rxd + 0x8), readl(rxd + 0xc));
8406         }
8407 }
8408 #endif
8409
8410 static struct net_device_stats *tg3_get_stats(struct net_device *);
8411 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
8412
8413 static int tg3_close(struct net_device *dev)
8414 {
8415         struct tg3 *tp = netdev_priv(dev);
8416
8417         napi_disable(&tp->napi);
8418         cancel_work_sync(&tp->reset_task);
8419
8420         netif_stop_queue(dev);
8421
8422         del_timer_sync(&tp->timer);
8423
8424         tg3_full_lock(tp, 1);
8425 #if 0
8426         tg3_dump_state(tp);
8427 #endif
8428
8429         tg3_disable_ints(tp);
8430
8431         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8432         tg3_free_rings(tp);
8433         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8434
8435         tg3_full_unlock(tp);
8436
8437         free_irq(tp->pdev->irq, dev);
8438         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8439                 pci_disable_msi(tp->pdev);
8440                 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8441         }
8442
8443         memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
8444                sizeof(tp->net_stats_prev));
8445         memcpy(&tp->estats_prev, tg3_get_estats(tp),
8446                sizeof(tp->estats_prev));
8447
8448         tg3_free_consistent(tp);
8449
8450         tg3_set_power_state(tp, PCI_D3hot);
8451
8452         netif_carrier_off(tp->dev);
8453
8454         return 0;
8455 }
8456
8457 static inline unsigned long get_stat64(tg3_stat64_t *val)
8458 {
8459         unsigned long ret;
8460
8461 #if (BITS_PER_LONG == 32)
8462         ret = val->low;
8463 #else
8464         ret = ((u64)val->high << 32) | ((u64)val->low);
8465 #endif
8466         return ret;
8467 }
8468
8469 static inline u64 get_estat64(tg3_stat64_t *val)
8470 {
8471        return ((u64)val->high << 32) | ((u64)val->low);
8472 }
8473
8474 static unsigned long calc_crc_errors(struct tg3 *tp)
8475 {
8476         struct tg3_hw_stats *hw_stats = tp->hw_stats;
8477
8478         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8479             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
8480              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
8481                 u32 val;
8482
8483                 spin_lock_bh(&tp->lock);
8484                 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
8485                         tg3_writephy(tp, MII_TG3_TEST1,
8486                                      val | MII_TG3_TEST1_CRC_EN);
8487                         tg3_readphy(tp, 0x14, &val);
8488                 } else
8489                         val = 0;
8490                 spin_unlock_bh(&tp->lock);
8491
8492                 tp->phy_crc_errors += val;
8493
8494                 return tp->phy_crc_errors;
8495         }
8496
8497         return get_stat64(&hw_stats->rx_fcs_errors);
8498 }
8499
8500 #define ESTAT_ADD(member) \
8501         estats->member =        old_estats->member + \
8502                                 get_estat64(&hw_stats->member)
8503
8504 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
8505 {
8506         struct tg3_ethtool_stats *estats = &tp->estats;
8507         struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
8508         struct tg3_hw_stats *hw_stats = tp->hw_stats;
8509
8510         if (!hw_stats)
8511                 return old_estats;
8512
8513         ESTAT_ADD(rx_octets);
8514         ESTAT_ADD(rx_fragments);
8515         ESTAT_ADD(rx_ucast_packets);
8516         ESTAT_ADD(rx_mcast_packets);
8517         ESTAT_ADD(rx_bcast_packets);
8518         ESTAT_ADD(rx_fcs_errors);
8519         ESTAT_ADD(rx_align_errors);
8520         ESTAT_ADD(rx_xon_pause_rcvd);
8521         ESTAT_ADD(rx_xoff_pause_rcvd);
8522         ESTAT_ADD(rx_mac_ctrl_rcvd);
8523         ESTAT_ADD(rx_xoff_entered);
8524         ESTAT_ADD(rx_frame_too_long_errors);
8525         ESTAT_ADD(rx_jabbers);
8526         ESTAT_ADD(rx_undersize_packets);
8527         ESTAT_ADD(rx_in_length_errors);
8528         ESTAT_ADD(rx_out_length_errors);
8529         ESTAT_ADD(rx_64_or_less_octet_packets);
8530         ESTAT_ADD(rx_65_to_127_octet_packets);
8531         ESTAT_ADD(rx_128_to_255_octet_packets);
8532         ESTAT_ADD(rx_256_to_511_octet_packets);
8533         ESTAT_ADD(rx_512_to_1023_octet_packets);
8534         ESTAT_ADD(rx_1024_to_1522_octet_packets);
8535         ESTAT_ADD(rx_1523_to_2047_octet_packets);
8536         ESTAT_ADD(rx_2048_to_4095_octet_packets);
8537         ESTAT_ADD(rx_4096_to_8191_octet_packets);
8538         ESTAT_ADD(rx_8192_to_9022_octet_packets);
8539
8540         ESTAT_ADD(tx_octets);
8541         ESTAT_ADD(tx_collisions);
8542         ESTAT_ADD(tx_xon_sent);
8543         ESTAT_ADD(tx_xoff_sent);
8544         ESTAT_ADD(tx_flow_control);
8545         ESTAT_ADD(tx_mac_errors);
8546         ESTAT_ADD(tx_single_collisions);
8547         ESTAT_ADD(tx_mult_collisions);
8548         ESTAT_ADD(tx_deferred);
8549         ESTAT_ADD(tx_excessive_collisions);
8550         ESTAT_ADD(tx_late_collisions);
8551         ESTAT_ADD(tx_collide_2times);
8552         ESTAT_ADD(tx_collide_3times);
8553         ESTAT_ADD(tx_collide_4times);
8554         ESTAT_ADD(tx_collide_5times);
8555         ESTAT_ADD(tx_collide_6times);
8556         ESTAT_ADD(tx_collide_7times);
8557         ESTAT_ADD(tx_collide_8times);
8558         ESTAT_ADD(tx_collide_9times);
8559         ESTAT_ADD(tx_collide_10times);
8560         ESTAT_ADD(tx_collide_11times);
8561         ESTAT_ADD(tx_collide_12times);
8562         ESTAT_ADD(tx_collide_13times);
8563         ESTAT_ADD(tx_collide_14times);
8564         ESTAT_ADD(tx_collide_15times);
8565         ESTAT_ADD(tx_ucast_packets);
8566         ESTAT_ADD(tx_mcast_packets);
8567         ESTAT_ADD(tx_bcast_packets);
8568         ESTAT_ADD(tx_carrier_sense_errors);
8569         ESTAT_ADD(tx_discards);
8570         ESTAT_ADD(tx_errors);
8571
8572         ESTAT_ADD(dma_writeq_full);
8573         ESTAT_ADD(dma_write_prioq_full);
8574         ESTAT_ADD(rxbds_empty);
8575         ESTAT_ADD(rx_discards);
8576         ESTAT_ADD(rx_errors);
8577         ESTAT_ADD(rx_threshold_hit);
8578
8579         ESTAT_ADD(dma_readq_full);
8580         ESTAT_ADD(dma_read_prioq_full);
8581         ESTAT_ADD(tx_comp_queue_full);
8582
8583         ESTAT_ADD(ring_set_send_prod_index);
8584         ESTAT_ADD(ring_status_update);
8585         ESTAT_ADD(nic_irqs);
8586         ESTAT_ADD(nic_avoided_irqs);
8587         ESTAT_ADD(nic_tx_threshold_hit);
8588
8589         return estats;
8590 }
8591
8592 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
8593 {
8594         struct tg3 *tp = netdev_priv(dev);
8595         struct net_device_stats *stats = &tp->net_stats;
8596         struct net_device_stats *old_stats = &tp->net_stats_prev;
8597         struct tg3_hw_stats *hw_stats = tp->hw_stats;
8598
8599         if (!hw_stats)
8600                 return old_stats;
8601
8602         stats->rx_packets = old_stats->rx_packets +
8603                 get_stat64(&hw_stats->rx_ucast_packets) +
8604                 get_stat64(&hw_stats->rx_mcast_packets) +
8605                 get_stat64(&hw_stats->rx_bcast_packets);
8606
8607         stats->tx_packets = old_stats->tx_packets +
8608                 get_stat64(&hw_stats->tx_ucast_packets) +
8609                 get_stat64(&hw_stats->tx_mcast_packets) +
8610                 get_stat64(&hw_stats->tx_bcast_packets);
8611
8612         stats->rx_bytes = old_stats->rx_bytes +
8613                 get_stat64(&hw_stats->rx_octets);
8614         stats->tx_bytes = old_stats->tx_bytes +
8615                 get_stat64(&hw_stats->tx_octets);
8616
8617         stats->rx_errors = old_stats->rx_errors +
8618                 get_stat64(&hw_stats->rx_errors);
8619         stats->tx_errors = old_stats->tx_errors +
8620                 get_stat64(&hw_stats->tx_errors) +
8621                 get_stat64(&hw_stats->tx_mac_errors) +
8622                 get_stat64(&hw_stats->tx_carrier_sense_errors) +
8623                 get_stat64(&hw_stats->tx_discards);
8624
8625         stats->multicast = old_stats->multicast +
8626                 get_stat64(&hw_stats->rx_mcast_packets);
8627         stats->collisions = old_stats->collisions +
8628                 get_stat64(&hw_stats->tx_collisions);
8629
8630         stats->rx_length_errors = old_stats->rx_length_errors +
8631                 get_stat64(&hw_stats->rx_frame_too_long_errors) +
8632                 get_stat64(&hw_stats->rx_undersize_packets);
8633
8634         stats->rx_over_errors = old_stats->rx_over_errors +
8635                 get_stat64(&hw_stats->rxbds_empty);
8636         stats->rx_frame_errors = old_stats->rx_frame_errors +
8637                 get_stat64(&hw_stats->rx_align_errors);
8638         stats->tx_aborted_errors = old_stats->tx_aborted_errors +
8639                 get_stat64(&hw_stats->tx_discards);
8640         stats->tx_carrier_errors = old_stats->tx_carrier_errors +
8641                 get_stat64(&hw_stats->tx_carrier_sense_errors);
8642
8643         stats->rx_crc_errors = old_stats->rx_crc_errors +
8644                 calc_crc_errors(tp);
8645
8646         stats->rx_missed_errors = old_stats->rx_missed_errors +
8647                 get_stat64(&hw_stats->rx_discards);
8648
8649         return stats;
8650 }
8651
8652 static inline u32 calc_crc(unsigned char *buf, int len)
8653 {
8654         u32 reg;
8655         u32 tmp;
8656         int j, k;
8657
8658         reg = 0xffffffff;
8659
8660         for (j = 0; j < len; j++) {
8661                 reg ^= buf[j];
8662
8663                 for (k = 0; k < 8; k++) {
8664                         tmp = reg & 0x01;
8665
8666                         reg >>= 1;
8667
8668                         if (tmp) {
8669                                 reg ^= 0xedb88320;
8670                         }
8671                 }
8672         }
8673
8674         return ~reg;
8675 }
8676
8677 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
8678 {
8679         /* accept or reject all multicast frames */
8680         tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
8681         tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
8682         tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
8683         tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
8684 }
8685
8686 static void __tg3_set_rx_mode(struct net_device *dev)
8687 {
8688         struct tg3 *tp = netdev_priv(dev);
8689         u32 rx_mode;
8690
8691         rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
8692                                   RX_MODE_KEEP_VLAN_TAG);
8693
8694         /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
8695          * flag clear.
8696          */
8697 #if TG3_VLAN_TAG_USED
8698         if (!tp->vlgrp &&
8699             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8700                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8701 #else
8702         /* By definition, VLAN is disabled always in this
8703          * case.
8704          */
8705         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8706                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8707 #endif
8708
8709         if (dev->flags & IFF_PROMISC) {
8710                 /* Promiscuous mode. */
8711                 rx_mode |= RX_MODE_PROMISC;
8712         } else if (dev->flags & IFF_ALLMULTI) {
8713                 /* Accept all multicast. */
8714                 tg3_set_multi (tp, 1);
8715         } else if (dev->mc_count < 1) {
8716                 /* Reject all multicast. */
8717                 tg3_set_multi (tp, 0);
8718         } else {
8719                 /* Accept one or more multicast(s). */
8720                 struct dev_mc_list *mclist;
8721                 unsigned int i;
8722                 u32 mc_filter[4] = { 0, };
8723                 u32 regidx;
8724                 u32 bit;
8725                 u32 crc;
8726
8727                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
8728                      i++, mclist = mclist->next) {
8729
8730                         crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
8731                         bit = ~crc & 0x7f;
8732                         regidx = (bit & 0x60) >> 5;
8733                         bit &= 0x1f;
8734                         mc_filter[regidx] |= (1 << bit);
8735                 }
8736
8737                 tw32(MAC_HASH_REG_0, mc_filter[0]);
8738                 tw32(MAC_HASH_REG_1, mc_filter[1]);
8739                 tw32(MAC_HASH_REG_2, mc_filter[2]);
8740                 tw32(MAC_HASH_REG_3, mc_filter[3]);
8741         }
8742
8743         if (rx_mode != tp->rx_mode) {
8744                 tp->rx_mode = rx_mode;
8745                 tw32_f(MAC_RX_MODE, rx_mode);
8746                 udelay(10);
8747         }
8748 }
8749
8750 static void tg3_set_rx_mode(struct net_device *dev)
8751 {
8752         struct tg3 *tp = netdev_priv(dev);
8753
8754         if (!netif_running(dev))
8755                 return;
8756
8757         tg3_full_lock(tp, 0);
8758         __tg3_set_rx_mode(dev);
8759         tg3_full_unlock(tp);
8760 }
8761
8762 #define TG3_REGDUMP_LEN         (32 * 1024)
8763
8764 static int tg3_get_regs_len(struct net_device *dev)
8765 {
8766         return TG3_REGDUMP_LEN;
8767 }
8768
8769 static void tg3_get_regs(struct net_device *dev,
8770                 struct ethtool_regs *regs, void *_p)
8771 {
8772         u32 *p = _p;
8773         struct tg3 *tp = netdev_priv(dev);
8774         u8 *orig_p = _p;
8775         int i;
8776
8777         regs->version = 0;
8778
8779         memset(p, 0, TG3_REGDUMP_LEN);
8780
8781         if (tp->link_config.phy_is_low_power)
8782                 return;
8783
8784         tg3_full_lock(tp, 0);
8785
8786 #define __GET_REG32(reg)        (*(p)++ = tr32(reg))
8787 #define GET_REG32_LOOP(base,len)                \
8788 do {    p = (u32 *)(orig_p + (base));           \
8789         for (i = 0; i < len; i += 4)            \
8790                 __GET_REG32((base) + i);        \
8791 } while (0)
8792 #define GET_REG32_1(reg)                        \
8793 do {    p = (u32 *)(orig_p + (reg));            \
8794         __GET_REG32((reg));                     \
8795 } while (0)
8796
8797         GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
8798         GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
8799         GET_REG32_LOOP(MAC_MODE, 0x4f0);
8800         GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
8801         GET_REG32_1(SNDDATAC_MODE);
8802         GET_REG32_LOOP(SNDBDS_MODE, 0x80);
8803         GET_REG32_LOOP(SNDBDI_MODE, 0x48);
8804         GET_REG32_1(SNDBDC_MODE);
8805         GET_REG32_LOOP(RCVLPC_MODE, 0x20);
8806         GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
8807         GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
8808         GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
8809         GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
8810         GET_REG32_1(RCVDCC_MODE);
8811         GET_REG32_LOOP(RCVBDI_MODE, 0x20);
8812         GET_REG32_LOOP(RCVCC_MODE, 0x14);
8813         GET_REG32_LOOP(RCVLSC_MODE, 0x08);
8814         GET_REG32_1(MBFREE_MODE);
8815         GET_REG32_LOOP(HOSTCC_MODE, 0x100);
8816         GET_REG32_LOOP(MEMARB_MODE, 0x10);
8817         GET_REG32_LOOP(BUFMGR_MODE, 0x58);
8818         GET_REG32_LOOP(RDMAC_MODE, 0x08);
8819         GET_REG32_LOOP(WDMAC_MODE, 0x08);
8820         GET_REG32_1(RX_CPU_MODE);
8821         GET_REG32_1(RX_CPU_STATE);
8822         GET_REG32_1(RX_CPU_PGMCTR);
8823         GET_REG32_1(RX_CPU_HWBKPT);
8824         GET_REG32_1(TX_CPU_MODE);
8825         GET_REG32_1(TX_CPU_STATE);
8826         GET_REG32_1(TX_CPU_PGMCTR);
8827         GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
8828         GET_REG32_LOOP(FTQ_RESET, 0x120);
8829         GET_REG32_LOOP(MSGINT_MODE, 0x0c);
8830         GET_REG32_1(DMAC_MODE);
8831         GET_REG32_LOOP(GRC_MODE, 0x4c);
8832         if (tp->tg3_flags & TG3_FLAG_NVRAM)
8833                 GET_REG32_LOOP(NVRAM_CMD, 0x24);
8834
8835 #undef __GET_REG32
8836 #undef GET_REG32_LOOP
8837 #undef GET_REG32_1
8838
8839         tg3_full_unlock(tp);
8840 }
8841
8842 static int tg3_get_eeprom_len(struct net_device *dev)
8843 {
8844         struct tg3 *tp = netdev_priv(dev);
8845
8846         return tp->nvram_size;
8847 }
8848
8849 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val);
8850 static int tg3_nvram_read_le(struct tg3 *tp, u32 offset, __le32 *val);
8851 static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val);
8852
8853 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
8854 {
8855         struct tg3 *tp = netdev_priv(dev);
8856         int ret;
8857         u8  *pd;
8858         u32 i, offset, len, b_offset, b_count;
8859         __le32 val;
8860
8861         if (tp->link_config.phy_is_low_power)
8862                 return -EAGAIN;
8863
8864         offset = eeprom->offset;
8865         len = eeprom->len;
8866         eeprom->len = 0;
8867
8868         eeprom->magic = TG3_EEPROM_MAGIC;
8869
8870         if (offset & 3) {
8871                 /* adjustments to start on required 4 byte boundary */
8872                 b_offset = offset & 3;
8873                 b_count = 4 - b_offset;
8874                 if (b_count > len) {
8875                         /* i.e. offset=1 len=2 */
8876                         b_count = len;
8877                 }
8878                 ret = tg3_nvram_read_le(tp, offset-b_offset, &val);
8879                 if (ret)
8880                         return ret;
8881                 memcpy(data, ((char*)&val) + b_offset, b_count);
8882                 len -= b_count;
8883                 offset += b_count;
8884                 eeprom->len += b_count;
8885         }
8886
8887         /* read bytes upto the last 4 byte boundary */
8888         pd = &data[eeprom->len];
8889         for (i = 0; i < (len - (len & 3)); i += 4) {
8890                 ret = tg3_nvram_read_le(tp, offset + i, &val);
8891                 if (ret) {
8892                         eeprom->len += i;
8893                         return ret;
8894                 }
8895                 memcpy(pd + i, &val, 4);
8896         }
8897         eeprom->len += i;
8898
8899         if (len & 3) {
8900                 /* read last bytes not ending on 4 byte boundary */
8901                 pd = &data[eeprom->len];
8902                 b_count = len & 3;
8903                 b_offset = offset + len - b_count;
8904                 ret = tg3_nvram_read_le(tp, b_offset, &val);
8905                 if (ret)
8906                         return ret;
8907                 memcpy(pd, &val, b_count);
8908                 eeprom->len += b_count;
8909         }
8910         return 0;
8911 }
8912
8913 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
8914
8915 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
8916 {
8917         struct tg3 *tp = netdev_priv(dev);
8918         int ret;
8919         u32 offset, len, b_offset, odd_len;
8920         u8 *buf;
8921         __le32 start, end;
8922
8923         if (tp->link_config.phy_is_low_power)
8924                 return -EAGAIN;
8925
8926         if (eeprom->magic != TG3_EEPROM_MAGIC)
8927                 return -EINVAL;
8928
8929         offset = eeprom->offset;
8930         len = eeprom->len;
8931
8932         if ((b_offset = (offset & 3))) {
8933                 /* adjustments to start on required 4 byte boundary */
8934                 ret = tg3_nvram_read_le(tp, offset-b_offset, &start);
8935                 if (ret)
8936                         return ret;
8937                 len += b_offset;
8938                 offset &= ~3;
8939                 if (len < 4)
8940                         len = 4;
8941         }
8942
8943         odd_len = 0;
8944         if (len & 3) {
8945                 /* adjustments to end on required 4 byte boundary */
8946                 odd_len = 1;
8947                 len = (len + 3) & ~3;
8948                 ret = tg3_nvram_read_le(tp, offset+len-4, &end);
8949                 if (ret)
8950                         return ret;
8951         }
8952
8953         buf = data;
8954         if (b_offset || odd_len) {
8955                 buf = kmalloc(len, GFP_KERNEL);
8956                 if (!buf)
8957                         return -ENOMEM;
8958                 if (b_offset)
8959                         memcpy(buf, &start, 4);
8960                 if (odd_len)
8961                         memcpy(buf+len-4, &end, 4);
8962                 memcpy(buf + b_offset, data, eeprom->len);
8963         }
8964
8965         ret = tg3_nvram_write_block(tp, offset, len, buf);
8966
8967         if (buf != data)
8968                 kfree(buf);
8969
8970         return ret;
8971 }
8972
8973 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8974 {
8975         struct tg3 *tp = netdev_priv(dev);
8976
8977         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8978                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8979                         return -EAGAIN;
8980                 return phy_ethtool_gset(tp->mdio_bus.phy_map[PHY_ADDR], cmd);
8981         }
8982
8983         cmd->supported = (SUPPORTED_Autoneg);
8984
8985         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
8986                 cmd->supported |= (SUPPORTED_1000baseT_Half |
8987                                    SUPPORTED_1000baseT_Full);
8988
8989         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
8990                 cmd->supported |= (SUPPORTED_100baseT_Half |
8991                                   SUPPORTED_100baseT_Full |
8992                                   SUPPORTED_10baseT_Half |
8993                                   SUPPORTED_10baseT_Full |
8994                                   SUPPORTED_TP);
8995                 cmd->port = PORT_TP;
8996         } else {
8997                 cmd->supported |= SUPPORTED_FIBRE;
8998                 cmd->port = PORT_FIBRE;
8999         }
9000
9001         cmd->advertising = tp->link_config.advertising;
9002         if (netif_running(dev)) {
9003                 cmd->speed = tp->link_config.active_speed;
9004                 cmd->duplex = tp->link_config.active_duplex;
9005         }
9006         cmd->phy_address = PHY_ADDR;
9007         cmd->transceiver = 0;
9008         cmd->autoneg = tp->link_config.autoneg;
9009         cmd->maxtxpkt = 0;
9010         cmd->maxrxpkt = 0;
9011         return 0;
9012 }
9013
9014 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9015 {
9016         struct tg3 *tp = netdev_priv(dev);
9017
9018         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9019                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9020                         return -EAGAIN;
9021                 return phy_ethtool_sset(tp->mdio_bus.phy_map[PHY_ADDR], cmd);
9022         }
9023
9024         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
9025                 /* These are the only valid advertisement bits allowed.  */
9026                 if (cmd->autoneg == AUTONEG_ENABLE &&
9027                     (cmd->advertising & ~(ADVERTISED_1000baseT_Half |
9028                                           ADVERTISED_1000baseT_Full |
9029                                           ADVERTISED_Autoneg |
9030                                           ADVERTISED_FIBRE)))
9031                         return -EINVAL;
9032                 /* Fiber can only do SPEED_1000.  */
9033                 else if ((cmd->autoneg != AUTONEG_ENABLE) &&
9034                          (cmd->speed != SPEED_1000))
9035                         return -EINVAL;
9036         /* Copper cannot force SPEED_1000.  */
9037         } else if ((cmd->autoneg != AUTONEG_ENABLE) &&
9038                    (cmd->speed == SPEED_1000))
9039                 return -EINVAL;
9040         else if ((cmd->speed == SPEED_1000) &&
9041                  (tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9042                 return -EINVAL;
9043
9044         tg3_full_lock(tp, 0);
9045
9046         tp->link_config.autoneg = cmd->autoneg;
9047         if (cmd->autoneg == AUTONEG_ENABLE) {
9048                 tp->link_config.advertising = (cmd->advertising |
9049                                               ADVERTISED_Autoneg);
9050                 tp->link_config.speed = SPEED_INVALID;
9051                 tp->link_config.duplex = DUPLEX_INVALID;
9052         } else {
9053                 tp->link_config.advertising = 0;
9054                 tp->link_config.speed = cmd->speed;
9055                 tp->link_config.duplex = cmd->duplex;
9056         }
9057
9058         tp->link_config.orig_speed = tp->link_config.speed;
9059         tp->link_config.orig_duplex = tp->link_config.duplex;
9060         tp->link_config.orig_autoneg = tp->link_config.autoneg;
9061
9062         if (netif_running(dev))
9063                 tg3_setup_phy(tp, 1);
9064
9065         tg3_full_unlock(tp);
9066
9067         return 0;
9068 }
9069
9070 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9071 {
9072         struct tg3 *tp = netdev_priv(dev);
9073
9074         strcpy(info->driver, DRV_MODULE_NAME);
9075         strcpy(info->version, DRV_MODULE_VERSION);
9076         strcpy(info->fw_version, tp->fw_ver);
9077         strcpy(info->bus_info, pci_name(tp->pdev));
9078 }
9079
9080 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9081 {
9082         struct tg3 *tp = netdev_priv(dev);
9083
9084         if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9085             device_can_wakeup(&tp->pdev->dev))
9086                 wol->supported = WAKE_MAGIC;
9087         else
9088                 wol->supported = 0;
9089         wol->wolopts = 0;
9090         if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)
9091                 wol->wolopts = WAKE_MAGIC;
9092         memset(&wol->sopass, 0, sizeof(wol->sopass));
9093 }
9094
9095 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9096 {
9097         struct tg3 *tp = netdev_priv(dev);
9098         struct device *dp = &tp->pdev->dev;
9099
9100         if (wol->wolopts & ~WAKE_MAGIC)
9101                 return -EINVAL;
9102         if ((wol->wolopts & WAKE_MAGIC) &&
9103             !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
9104                 return -EINVAL;
9105
9106         spin_lock_bh(&tp->lock);
9107         if (wol->wolopts & WAKE_MAGIC) {
9108                 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
9109                 device_set_wakeup_enable(dp, true);
9110         } else {
9111                 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
9112                 device_set_wakeup_enable(dp, false);
9113         }
9114         spin_unlock_bh(&tp->lock);
9115
9116         return 0;
9117 }
9118
9119 static u32 tg3_get_msglevel(struct net_device *dev)
9120 {
9121         struct tg3 *tp = netdev_priv(dev);
9122         return tp->msg_enable;
9123 }
9124
9125 static void tg3_set_msglevel(struct net_device *dev, u32 value)
9126 {
9127         struct tg3 *tp = netdev_priv(dev);
9128         tp->msg_enable = value;
9129 }
9130
9131 static int tg3_set_tso(struct net_device *dev, u32 value)
9132 {
9133         struct tg3 *tp = netdev_priv(dev);
9134
9135         if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9136                 if (value)
9137                         return -EINVAL;
9138                 return 0;
9139         }
9140         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
9141             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)) {
9142                 if (value) {
9143                         dev->features |= NETIF_F_TSO6;
9144                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9145                             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9146                              GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
9147                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
9148                                 dev->features |= NETIF_F_TSO_ECN;
9149                 } else
9150                         dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
9151         }
9152         return ethtool_op_set_tso(dev, value);
9153 }
9154
9155 static int tg3_nway_reset(struct net_device *dev)
9156 {
9157         struct tg3 *tp = netdev_priv(dev);
9158         int r;
9159
9160         if (!netif_running(dev))
9161                 return -EAGAIN;
9162
9163         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9164                 return -EINVAL;
9165
9166         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9167                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9168                         return -EAGAIN;
9169                 r = phy_start_aneg(tp->mdio_bus.phy_map[PHY_ADDR]);
9170         } else {
9171                 u32 bmcr;
9172
9173                 spin_lock_bh(&tp->lock);
9174                 r = -EINVAL;
9175                 tg3_readphy(tp, MII_BMCR, &bmcr);
9176                 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9177                     ((bmcr & BMCR_ANENABLE) ||
9178                      (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
9179                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9180                                                    BMCR_ANENABLE);
9181                         r = 0;
9182                 }
9183                 spin_unlock_bh(&tp->lock);
9184         }
9185
9186         return r;
9187 }
9188
9189 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9190 {
9191         struct tg3 *tp = netdev_priv(dev);
9192
9193         ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
9194         ering->rx_mini_max_pending = 0;
9195         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9196                 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9197         else
9198                 ering->rx_jumbo_max_pending = 0;
9199
9200         ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
9201
9202         ering->rx_pending = tp->rx_pending;
9203         ering->rx_mini_pending = 0;
9204         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9205                 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
9206         else
9207                 ering->rx_jumbo_pending = 0;
9208
9209         ering->tx_pending = tp->tx_pending;
9210 }
9211
9212 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9213 {
9214         struct tg3 *tp = netdev_priv(dev);
9215         int irq_sync = 0, err = 0;
9216
9217         if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
9218             (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
9219             (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
9220             (ering->tx_pending <= MAX_SKB_FRAGS) ||
9221             ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
9222              (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
9223                 return -EINVAL;
9224
9225         if (netif_running(dev)) {
9226                 tg3_phy_stop(tp);
9227                 tg3_netif_stop(tp);
9228                 irq_sync = 1;
9229         }
9230
9231         tg3_full_lock(tp, irq_sync);
9232
9233         tp->rx_pending = ering->rx_pending;
9234
9235         if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
9236             tp->rx_pending > 63)
9237                 tp->rx_pending = 63;
9238         tp->rx_jumbo_pending = ering->rx_jumbo_pending;
9239         tp->tx_pending = ering->tx_pending;
9240
9241         if (netif_running(dev)) {
9242                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9243                 err = tg3_restart_hw(tp, 1);
9244                 if (!err)
9245                         tg3_netif_start(tp);
9246         }
9247
9248         tg3_full_unlock(tp);
9249
9250         if (irq_sync && !err)
9251                 tg3_phy_start(tp);
9252
9253         return err;
9254 }
9255
9256 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9257 {
9258         struct tg3 *tp = netdev_priv(dev);
9259
9260         epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
9261
9262         if (tp->link_config.active_flowctrl & TG3_FLOW_CTRL_RX)
9263                 epause->rx_pause = 1;
9264         else
9265                 epause->rx_pause = 0;
9266
9267         if (tp->link_config.active_flowctrl & TG3_FLOW_CTRL_TX)
9268                 epause->tx_pause = 1;
9269         else
9270                 epause->tx_pause = 0;
9271 }
9272
9273 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9274 {
9275         struct tg3 *tp = netdev_priv(dev);
9276         int err = 0;
9277
9278         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9279                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9280                         return -EAGAIN;
9281
9282                 if (epause->autoneg) {
9283                         u32 newadv;
9284                         struct phy_device *phydev;
9285
9286                         phydev = tp->mdio_bus.phy_map[PHY_ADDR];
9287
9288                         if (epause->rx_pause) {
9289                                 if (epause->tx_pause)
9290                                         newadv = ADVERTISED_Pause;
9291                                 else
9292                                         newadv = ADVERTISED_Pause |
9293                                                  ADVERTISED_Asym_Pause;
9294                         } else if (epause->tx_pause) {
9295                                 newadv = ADVERTISED_Asym_Pause;
9296                         } else
9297                                 newadv = 0;
9298
9299                         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
9300                                 u32 oldadv = phydev->advertising &
9301                                              (ADVERTISED_Pause |
9302                                               ADVERTISED_Asym_Pause);
9303                                 if (oldadv != newadv) {
9304                                         phydev->advertising &=
9305                                                 ~(ADVERTISED_Pause |
9306                                                   ADVERTISED_Asym_Pause);
9307                                         phydev->advertising |= newadv;
9308                                         err = phy_start_aneg(phydev);
9309                                 }
9310                         } else {
9311                                 tp->link_config.advertising &=
9312                                                 ~(ADVERTISED_Pause |
9313                                                   ADVERTISED_Asym_Pause);
9314                                 tp->link_config.advertising |= newadv;
9315                         }
9316                 } else {
9317                         if (epause->rx_pause)
9318                                 tp->link_config.flowctrl |= TG3_FLOW_CTRL_RX;
9319                         else
9320                                 tp->link_config.flowctrl &= ~TG3_FLOW_CTRL_RX;
9321
9322                         if (epause->tx_pause)
9323                                 tp->link_config.flowctrl |= TG3_FLOW_CTRL_TX;
9324                         else
9325                                 tp->link_config.flowctrl &= ~TG3_FLOW_CTRL_TX;
9326
9327                         if (netif_running(dev))
9328                                 tg3_setup_flow_control(tp, 0, 0);
9329                 }
9330         } else {
9331                 int irq_sync = 0;
9332
9333                 if (netif_running(dev)) {
9334                         tg3_netif_stop(tp);
9335                         irq_sync = 1;
9336                 }
9337
9338                 tg3_full_lock(tp, irq_sync);
9339
9340                 if (epause->autoneg)
9341                         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9342                 else
9343                         tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9344                 if (epause->rx_pause)
9345                         tp->link_config.flowctrl |= TG3_FLOW_CTRL_RX;
9346                 else
9347                         tp->link_config.flowctrl &= ~TG3_FLOW_CTRL_RX;
9348                 if (epause->tx_pause)
9349                         tp->link_config.flowctrl |= TG3_FLOW_CTRL_TX;
9350                 else
9351                         tp->link_config.flowctrl &= ~TG3_FLOW_CTRL_TX;
9352
9353                 if (netif_running(dev)) {
9354                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9355                         err = tg3_restart_hw(tp, 1);
9356                         if (!err)
9357                                 tg3_netif_start(tp);
9358                 }
9359
9360                 tg3_full_unlock(tp);
9361         }
9362
9363         return err;
9364 }
9365
9366 static u32 tg3_get_rx_csum(struct net_device *dev)
9367 {
9368         struct tg3 *tp = netdev_priv(dev);
9369         return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
9370 }
9371
9372 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
9373 {
9374         struct tg3 *tp = netdev_priv(dev);
9375
9376         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9377                 if (data != 0)
9378                         return -EINVAL;
9379                 return 0;
9380         }
9381
9382         spin_lock_bh(&tp->lock);
9383         if (data)
9384                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
9385         else
9386                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
9387         spin_unlock_bh(&tp->lock);
9388
9389         return 0;
9390 }
9391
9392 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
9393 {
9394         struct tg3 *tp = netdev_priv(dev);
9395
9396         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9397                 if (data != 0)
9398                         return -EINVAL;
9399                 return 0;
9400         }
9401
9402         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
9403             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
9404             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
9405             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9406             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
9407                 ethtool_op_set_tx_ipv6_csum(dev, data);
9408         else
9409                 ethtool_op_set_tx_csum(dev, data);
9410
9411         return 0;
9412 }
9413
9414 static int tg3_get_sset_count (struct net_device *dev, int sset)
9415 {
9416         switch (sset) {
9417         case ETH_SS_TEST:
9418                 return TG3_NUM_TEST;
9419         case ETH_SS_STATS:
9420                 return TG3_NUM_STATS;
9421         default:
9422                 return -EOPNOTSUPP;
9423         }
9424 }
9425
9426 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
9427 {
9428         switch (stringset) {
9429         case ETH_SS_STATS:
9430                 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
9431                 break;
9432         case ETH_SS_TEST:
9433                 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
9434                 break;
9435         default:
9436                 WARN_ON(1);     /* we need a WARN() */
9437                 break;
9438         }
9439 }
9440
9441 static int tg3_phys_id(struct net_device *dev, u32 data)
9442 {
9443         struct tg3 *tp = netdev_priv(dev);
9444         int i;
9445
9446         if (!netif_running(tp->dev))
9447                 return -EAGAIN;
9448
9449         if (data == 0)
9450                 data = UINT_MAX / 2;
9451
9452         for (i = 0; i < (data * 2); i++) {
9453                 if ((i % 2) == 0)
9454                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9455                                            LED_CTRL_1000MBPS_ON |
9456                                            LED_CTRL_100MBPS_ON |
9457                                            LED_CTRL_10MBPS_ON |
9458                                            LED_CTRL_TRAFFIC_OVERRIDE |
9459                                            LED_CTRL_TRAFFIC_BLINK |
9460                                            LED_CTRL_TRAFFIC_LED);
9461
9462                 else
9463                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9464                                            LED_CTRL_TRAFFIC_OVERRIDE);
9465
9466                 if (msleep_interruptible(500))
9467                         break;
9468         }
9469         tw32(MAC_LED_CTRL, tp->led_ctrl);
9470         return 0;
9471 }
9472
9473 static void tg3_get_ethtool_stats (struct net_device *dev,
9474                                    struct ethtool_stats *estats, u64 *tmp_stats)
9475 {
9476         struct tg3 *tp = netdev_priv(dev);
9477         memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
9478 }
9479
9480 #define NVRAM_TEST_SIZE 0x100
9481 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE   0x14
9482 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE   0x18
9483 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE   0x1c
9484 #define NVRAM_SELFBOOT_HW_SIZE 0x20
9485 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
9486
9487 static int tg3_test_nvram(struct tg3 *tp)
9488 {
9489         u32 csum, magic;
9490         __le32 *buf;
9491         int i, j, k, err = 0, size;
9492
9493         if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
9494                 return -EIO;
9495
9496         if (magic == TG3_EEPROM_MAGIC)
9497                 size = NVRAM_TEST_SIZE;
9498         else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
9499                 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
9500                     TG3_EEPROM_SB_FORMAT_1) {
9501                         switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
9502                         case TG3_EEPROM_SB_REVISION_0:
9503                                 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
9504                                 break;
9505                         case TG3_EEPROM_SB_REVISION_2:
9506                                 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
9507                                 break;
9508                         case TG3_EEPROM_SB_REVISION_3:
9509                                 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
9510                                 break;
9511                         default:
9512                                 return 0;
9513                         }
9514                 } else
9515                         return 0;
9516         } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
9517                 size = NVRAM_SELFBOOT_HW_SIZE;
9518         else
9519                 return -EIO;
9520
9521         buf = kmalloc(size, GFP_KERNEL);
9522         if (buf == NULL)
9523                 return -ENOMEM;
9524
9525         err = -EIO;
9526         for (i = 0, j = 0; i < size; i += 4, j++) {
9527                 if ((err = tg3_nvram_read_le(tp, i, &buf[j])) != 0)
9528                         break;
9529         }
9530         if (i < size)
9531                 goto out;
9532
9533         /* Selfboot format */
9534         magic = swab32(le32_to_cpu(buf[0]));
9535         if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
9536             TG3_EEPROM_MAGIC_FW) {
9537                 u8 *buf8 = (u8 *) buf, csum8 = 0;
9538
9539                 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
9540                     TG3_EEPROM_SB_REVISION_2) {
9541                         /* For rev 2, the csum doesn't include the MBA. */
9542                         for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
9543                                 csum8 += buf8[i];
9544                         for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
9545                                 csum8 += buf8[i];
9546                 } else {
9547                         for (i = 0; i < size; i++)
9548                                 csum8 += buf8[i];
9549                 }
9550
9551                 if (csum8 == 0) {
9552                         err = 0;
9553                         goto out;
9554                 }
9555
9556                 err = -EIO;
9557                 goto out;
9558         }
9559
9560         if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
9561             TG3_EEPROM_MAGIC_HW) {
9562                 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
9563                 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
9564                 u8 *buf8 = (u8 *) buf;
9565
9566                 /* Separate the parity bits and the data bytes.  */
9567                 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
9568                         if ((i == 0) || (i == 8)) {
9569                                 int l;
9570                                 u8 msk;
9571
9572                                 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
9573                                         parity[k++] = buf8[i] & msk;
9574                                 i++;
9575                         }
9576                         else if (i == 16) {
9577                                 int l;
9578                                 u8 msk;
9579
9580                                 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
9581                                         parity[k++] = buf8[i] & msk;
9582                                 i++;
9583
9584                                 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
9585                                         parity[k++] = buf8[i] & msk;
9586                                 i++;
9587                         }
9588                         data[j++] = buf8[i];
9589                 }
9590
9591                 err = -EIO;
9592                 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
9593                         u8 hw8 = hweight8(data[i]);
9594
9595                         if ((hw8 & 0x1) && parity[i])
9596                                 goto out;
9597                         else if (!(hw8 & 0x1) && !parity[i])
9598                                 goto out;
9599                 }
9600                 err = 0;
9601                 goto out;
9602         }
9603
9604         /* Bootstrap checksum at offset 0x10 */
9605         csum = calc_crc((unsigned char *) buf, 0x10);
9606         if(csum != le32_to_cpu(buf[0x10/4]))
9607                 goto out;
9608
9609         /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
9610         csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
9611         if (csum != le32_to_cpu(buf[0xfc/4]))
9612                  goto out;
9613
9614         err = 0;
9615
9616 out:
9617         kfree(buf);
9618         return err;
9619 }
9620
9621 #define TG3_SERDES_TIMEOUT_SEC  2
9622 #define TG3_COPPER_TIMEOUT_SEC  6
9623
9624 static int tg3_test_link(struct tg3 *tp)
9625 {
9626         int i, max;
9627
9628         if (!netif_running(tp->dev))
9629                 return -ENODEV;
9630
9631         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
9632                 max = TG3_SERDES_TIMEOUT_SEC;
9633         else
9634                 max = TG3_COPPER_TIMEOUT_SEC;
9635
9636         for (i = 0; i < max; i++) {
9637                 if (netif_carrier_ok(tp->dev))
9638                         return 0;
9639
9640                 if (msleep_interruptible(1000))
9641                         break;
9642         }
9643
9644         return -EIO;
9645 }
9646
9647 /* Only test the commonly used registers */
9648 static int tg3_test_registers(struct tg3 *tp)
9649 {
9650         int i, is_5705, is_5750;
9651         u32 offset, read_mask, write_mask, val, save_val, read_val;
9652         static struct {
9653                 u16 offset;
9654                 u16 flags;
9655 #define TG3_FL_5705     0x1
9656 #define TG3_FL_NOT_5705 0x2
9657 #define TG3_FL_NOT_5788 0x4
9658 #define TG3_FL_NOT_5750 0x8
9659                 u32 read_mask;
9660                 u32 write_mask;
9661         } reg_tbl[] = {
9662                 /* MAC Control Registers */
9663                 { MAC_MODE, TG3_FL_NOT_5705,
9664                         0x00000000, 0x00ef6f8c },
9665                 { MAC_MODE, TG3_FL_5705,
9666                         0x00000000, 0x01ef6b8c },
9667                 { MAC_STATUS, TG3_FL_NOT_5705,
9668                         0x03800107, 0x00000000 },
9669                 { MAC_STATUS, TG3_FL_5705,
9670                         0x03800100, 0x00000000 },
9671                 { MAC_ADDR_0_HIGH, 0x0000,
9672                         0x00000000, 0x0000ffff },
9673                 { MAC_ADDR_0_LOW, 0x0000,
9674                         0x00000000, 0xffffffff },
9675                 { MAC_RX_MTU_SIZE, 0x0000,
9676                         0x00000000, 0x0000ffff },
9677                 { MAC_TX_MODE, 0x0000,
9678                         0x00000000, 0x00000070 },
9679                 { MAC_TX_LENGTHS, 0x0000,
9680                         0x00000000, 0x00003fff },
9681                 { MAC_RX_MODE, TG3_FL_NOT_5705,
9682                         0x00000000, 0x000007fc },
9683                 { MAC_RX_MODE, TG3_FL_5705,
9684                         0x00000000, 0x000007dc },
9685                 { MAC_HASH_REG_0, 0x0000,
9686                         0x00000000, 0xffffffff },
9687                 { MAC_HASH_REG_1, 0x0000,
9688                         0x00000000, 0xffffffff },
9689                 { MAC_HASH_REG_2, 0x0000,
9690                         0x00000000, 0xffffffff },
9691                 { MAC_HASH_REG_3, 0x0000,
9692                         0x00000000, 0xffffffff },
9693
9694                 /* Receive Data and Receive BD Initiator Control Registers. */
9695                 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
9696                         0x00000000, 0xffffffff },
9697                 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
9698                         0x00000000, 0xffffffff },
9699                 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
9700                         0x00000000, 0x00000003 },
9701                 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
9702                         0x00000000, 0xffffffff },
9703                 { RCVDBDI_STD_BD+0, 0x0000,
9704                         0x00000000, 0xffffffff },
9705                 { RCVDBDI_STD_BD+4, 0x0000,
9706                         0x00000000, 0xffffffff },
9707                 { RCVDBDI_STD_BD+8, 0x0000,
9708                         0x00000000, 0xffff0002 },
9709                 { RCVDBDI_STD_BD+0xc, 0x0000,
9710                         0x00000000, 0xffffffff },
9711
9712                 /* Receive BD Initiator Control Registers. */
9713                 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
9714                         0x00000000, 0xffffffff },
9715                 { RCVBDI_STD_THRESH, TG3_FL_5705,
9716                         0x00000000, 0x000003ff },
9717                 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
9718                         0x00000000, 0xffffffff },
9719
9720                 /* Host Coalescing Control Registers. */
9721                 { HOSTCC_MODE, TG3_FL_NOT_5705,
9722                         0x00000000, 0x00000004 },
9723                 { HOSTCC_MODE, TG3_FL_5705,
9724                         0x00000000, 0x000000f6 },
9725                 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
9726                         0x00000000, 0xffffffff },
9727                 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
9728                         0x00000000, 0x000003ff },
9729                 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
9730                         0x00000000, 0xffffffff },
9731                 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
9732                         0x00000000, 0x000003ff },
9733                 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
9734                         0x00000000, 0xffffffff },
9735                 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
9736                         0x00000000, 0x000000ff },
9737                 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
9738                         0x00000000, 0xffffffff },
9739                 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
9740                         0x00000000, 0x000000ff },
9741                 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
9742                         0x00000000, 0xffffffff },
9743                 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
9744                         0x00000000, 0xffffffff },
9745                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
9746                         0x00000000, 0xffffffff },
9747                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
9748                         0x00000000, 0x000000ff },
9749                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
9750                         0x00000000, 0xffffffff },
9751                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
9752                         0x00000000, 0x000000ff },
9753                 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
9754                         0x00000000, 0xffffffff },
9755                 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
9756                         0x00000000, 0xffffffff },
9757                 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
9758                         0x00000000, 0xffffffff },
9759                 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
9760                         0x00000000, 0xffffffff },
9761                 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
9762                         0x00000000, 0xffffffff },
9763                 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
9764                         0xffffffff, 0x00000000 },
9765                 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
9766                         0xffffffff, 0x00000000 },
9767
9768                 /* Buffer Manager Control Registers. */
9769                 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
9770                         0x00000000, 0x007fff80 },
9771                 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
9772                         0x00000000, 0x007fffff },
9773                 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
9774                         0x00000000, 0x0000003f },
9775                 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
9776                         0x00000000, 0x000001ff },
9777                 { BUFMGR_MB_HIGH_WATER, 0x0000,
9778                         0x00000000, 0x000001ff },
9779                 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
9780                         0xffffffff, 0x00000000 },
9781                 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
9782                         0xffffffff, 0x00000000 },
9783
9784                 /* Mailbox Registers */
9785                 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
9786                         0x00000000, 0x000001ff },
9787                 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
9788                         0x00000000, 0x000001ff },
9789                 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
9790                         0x00000000, 0x000007ff },
9791                 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
9792                         0x00000000, 0x000001ff },
9793
9794                 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
9795         };
9796
9797         is_5705 = is_5750 = 0;
9798         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
9799                 is_5705 = 1;
9800                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
9801                         is_5750 = 1;
9802         }
9803
9804         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
9805                 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
9806                         continue;
9807
9808                 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
9809                         continue;
9810
9811                 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
9812                     (reg_tbl[i].flags & TG3_FL_NOT_5788))
9813                         continue;
9814
9815                 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
9816                         continue;
9817
9818                 offset = (u32) reg_tbl[i].offset;
9819                 read_mask = reg_tbl[i].read_mask;
9820                 write_mask = reg_tbl[i].write_mask;
9821
9822                 /* Save the original register content */
9823                 save_val = tr32(offset);
9824
9825                 /* Determine the read-only value. */
9826                 read_val = save_val & read_mask;
9827
9828                 /* Write zero to the register, then make sure the read-only bits
9829                  * are not changed and the read/write bits are all zeros.
9830                  */
9831                 tw32(offset, 0);
9832
9833                 val = tr32(offset);
9834
9835                 /* Test the read-only and read/write bits. */
9836                 if (((val & read_mask) != read_val) || (val & write_mask))
9837                         goto out;
9838
9839                 /* Write ones to all the bits defined by RdMask and WrMask, then
9840                  * make sure the read-only bits are not changed and the
9841                  * read/write bits are all ones.
9842                  */
9843                 tw32(offset, read_mask | write_mask);
9844
9845                 val = tr32(offset);
9846
9847                 /* Test the read-only bits. */
9848                 if ((val & read_mask) != read_val)
9849                         goto out;
9850
9851                 /* Test the read/write bits. */
9852                 if ((val & write_mask) != write_mask)
9853                         goto out;
9854
9855                 tw32(offset, save_val);
9856         }
9857
9858         return 0;
9859
9860 out:
9861         if (netif_msg_hw(tp))
9862                 printk(KERN_ERR PFX "Register test failed at offset %x\n",
9863                        offset);
9864         tw32(offset, save_val);
9865         return -EIO;
9866 }
9867
9868 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
9869 {
9870         static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
9871         int i;
9872         u32 j;
9873
9874         for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
9875                 for (j = 0; j < len; j += 4) {
9876                         u32 val;
9877
9878                         tg3_write_mem(tp, offset + j, test_pattern[i]);
9879                         tg3_read_mem(tp, offset + j, &val);
9880                         if (val != test_pattern[i])
9881                                 return -EIO;
9882                 }
9883         }
9884         return 0;
9885 }
9886
9887 static int tg3_test_memory(struct tg3 *tp)
9888 {
9889         static struct mem_entry {
9890                 u32 offset;
9891                 u32 len;
9892         } mem_tbl_570x[] = {
9893                 { 0x00000000, 0x00b50},
9894                 { 0x00002000, 0x1c000},
9895                 { 0xffffffff, 0x00000}
9896         }, mem_tbl_5705[] = {
9897                 { 0x00000100, 0x0000c},
9898                 { 0x00000200, 0x00008},
9899                 { 0x00004000, 0x00800},
9900                 { 0x00006000, 0x01000},
9901                 { 0x00008000, 0x02000},
9902                 { 0x00010000, 0x0e000},
9903                 { 0xffffffff, 0x00000}
9904         }, mem_tbl_5755[] = {
9905                 { 0x00000200, 0x00008},
9906                 { 0x00004000, 0x00800},
9907                 { 0x00006000, 0x00800},
9908                 { 0x00008000, 0x02000},
9909                 { 0x00010000, 0x0c000},
9910                 { 0xffffffff, 0x00000}
9911         }, mem_tbl_5906[] = {
9912                 { 0x00000200, 0x00008},
9913                 { 0x00004000, 0x00400},
9914                 { 0x00006000, 0x00400},
9915                 { 0x00008000, 0x01000},
9916                 { 0x00010000, 0x01000},
9917                 { 0xffffffff, 0x00000}
9918         };
9919         struct mem_entry *mem_tbl;
9920         int err = 0;
9921         int i;
9922
9923         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
9924                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
9925                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
9926                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
9927                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9928                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
9929                         mem_tbl = mem_tbl_5755;
9930                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9931                         mem_tbl = mem_tbl_5906;
9932                 else
9933                         mem_tbl = mem_tbl_5705;
9934         } else
9935                 mem_tbl = mem_tbl_570x;
9936
9937         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
9938                 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
9939                     mem_tbl[i].len)) != 0)
9940                         break;
9941         }
9942
9943         return err;
9944 }
9945
9946 #define TG3_MAC_LOOPBACK        0
9947 #define TG3_PHY_LOOPBACK        1
9948
9949 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
9950 {
9951         u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
9952         u32 desc_idx;
9953         struct sk_buff *skb, *rx_skb;
9954         u8 *tx_data;
9955         dma_addr_t map;
9956         int num_pkts, tx_len, rx_len, i, err;
9957         struct tg3_rx_buffer_desc *desc;
9958
9959         if (loopback_mode == TG3_MAC_LOOPBACK) {
9960                 /* HW errata - mac loopback fails in some cases on 5780.
9961                  * Normal traffic and PHY loopback are not affected by
9962                  * errata.
9963                  */
9964                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
9965                         return 0;
9966
9967                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
9968                            MAC_MODE_PORT_INT_LPBACK;
9969                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
9970                         mac_mode |= MAC_MODE_LINK_POLARITY;
9971                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
9972                         mac_mode |= MAC_MODE_PORT_MODE_MII;
9973                 else
9974                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
9975                 tw32(MAC_MODE, mac_mode);
9976         } else if (loopback_mode == TG3_PHY_LOOPBACK) {
9977                 u32 val;
9978
9979                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9980                         u32 phytest;
9981
9982                         if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phytest)) {
9983                                 u32 phy;
9984
9985                                 tg3_writephy(tp, MII_TG3_EPHY_TEST,
9986                                              phytest | MII_TG3_EPHY_SHADOW_EN);
9987                                 if (!tg3_readphy(tp, 0x1b, &phy))
9988                                         tg3_writephy(tp, 0x1b, phy & ~0x20);
9989                                 tg3_writephy(tp, MII_TG3_EPHY_TEST, phytest);
9990                         }
9991                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
9992                 } else
9993                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
9994
9995                 tg3_phy_toggle_automdix(tp, 0);
9996
9997                 tg3_writephy(tp, MII_BMCR, val);
9998                 udelay(40);
9999
10000                 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
10001                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10002                         tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x1800);
10003                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10004                 } else
10005                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10006
10007                 /* reset to prevent losing 1st rx packet intermittently */
10008                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
10009                         tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10010                         udelay(10);
10011                         tw32_f(MAC_RX_MODE, tp->rx_mode);
10012                 }
10013                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
10014                         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
10015                                 mac_mode &= ~MAC_MODE_LINK_POLARITY;
10016                         else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
10017                                 mac_mode |= MAC_MODE_LINK_POLARITY;
10018                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
10019                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10020                 }
10021                 tw32(MAC_MODE, mac_mode);
10022         }
10023         else
10024                 return -EINVAL;
10025
10026         err = -EIO;
10027
10028         tx_len = 1514;
10029         skb = netdev_alloc_skb(tp->dev, tx_len);
10030         if (!skb)
10031                 return -ENOMEM;
10032
10033         tx_data = skb_put(skb, tx_len);
10034         memcpy(tx_data, tp->dev->dev_addr, 6);
10035         memset(tx_data + 6, 0x0, 8);
10036
10037         tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10038
10039         for (i = 14; i < tx_len; i++)
10040                 tx_data[i] = (u8) (i & 0xff);
10041
10042         map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
10043
10044         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10045              HOSTCC_MODE_NOW);
10046
10047         udelay(10);
10048
10049         rx_start_idx = tp->hw_status->idx[0].rx_producer;
10050
10051         num_pkts = 0;
10052
10053         tg3_set_txd(tp, tp->tx_prod, map, tx_len, 0, 1);
10054
10055         tp->tx_prod++;
10056         num_pkts++;
10057
10058         tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW,
10059                      tp->tx_prod);
10060         tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
10061
10062         udelay(10);
10063
10064         /* 250 usec to allow enough time on some 10/100 Mbps devices.  */
10065         for (i = 0; i < 25; i++) {
10066                 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10067                        HOSTCC_MODE_NOW);
10068
10069                 udelay(10);
10070
10071                 tx_idx = tp->hw_status->idx[0].tx_consumer;
10072                 rx_idx = tp->hw_status->idx[0].rx_producer;
10073                 if ((tx_idx == tp->tx_prod) &&
10074                     (rx_idx == (rx_start_idx + num_pkts)))
10075                         break;
10076         }
10077
10078         pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
10079         dev_kfree_skb(skb);
10080
10081         if (tx_idx != tp->tx_prod)
10082                 goto out;
10083
10084         if (rx_idx != rx_start_idx + num_pkts)
10085                 goto out;
10086
10087         desc = &tp->rx_rcb[rx_start_idx];
10088         desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
10089         opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
10090         if (opaque_key != RXD_OPAQUE_RING_STD)
10091                 goto out;
10092
10093         if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10094             (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10095                 goto out;
10096
10097         rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10098         if (rx_len != tx_len)
10099                 goto out;
10100
10101         rx_skb = tp->rx_std_buffers[desc_idx].skb;
10102
10103         map = pci_unmap_addr(&tp->rx_std_buffers[desc_idx], mapping);
10104         pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10105
10106         for (i = 14; i < tx_len; i++) {
10107                 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10108                         goto out;
10109         }
10110         err = 0;
10111
10112         /* tg3_free_rings will unmap and free the rx_skb */
10113 out:
10114         return err;
10115 }
10116
10117 #define TG3_MAC_LOOPBACK_FAILED         1
10118 #define TG3_PHY_LOOPBACK_FAILED         2
10119 #define TG3_LOOPBACK_FAILED             (TG3_MAC_LOOPBACK_FAILED |      \
10120                                          TG3_PHY_LOOPBACK_FAILED)
10121
10122 static int tg3_test_loopback(struct tg3 *tp)
10123 {
10124         int err = 0;
10125         u32 cpmuctrl = 0;
10126
10127         if (!netif_running(tp->dev))
10128                 return TG3_LOOPBACK_FAILED;
10129
10130         err = tg3_reset_hw(tp, 1);
10131         if (err)
10132                 return TG3_LOOPBACK_FAILED;
10133
10134         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
10135             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
10136             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
10137                 int i;
10138                 u32 status;
10139
10140                 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10141
10142                 /* Wait for up to 40 microseconds to acquire lock. */
10143                 for (i = 0; i < 4; i++) {
10144                         status = tr32(TG3_CPMU_MUTEX_GNT);
10145                         if (status == CPMU_MUTEX_GNT_DRIVER)
10146                                 break;
10147                         udelay(10);
10148                 }
10149
10150                 if (status != CPMU_MUTEX_GNT_DRIVER)
10151                         return TG3_LOOPBACK_FAILED;
10152
10153                 /* Turn off link-based power management. */
10154                 cpmuctrl = tr32(TG3_CPMU_CTRL);
10155                 tw32(TG3_CPMU_CTRL,
10156                      cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10157                                   CPMU_CTRL_LINK_AWARE_MODE));
10158         }
10159
10160         if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10161                 err |= TG3_MAC_LOOPBACK_FAILED;
10162
10163         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
10164             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
10165             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
10166                 tw32(TG3_CPMU_CTRL, cpmuctrl);
10167
10168                 /* Release the mutex */
10169                 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
10170         }
10171
10172         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
10173             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
10174                 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
10175                         err |= TG3_PHY_LOOPBACK_FAILED;
10176         }
10177
10178         return err;
10179 }
10180
10181 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
10182                           u64 *data)
10183 {
10184         struct tg3 *tp = netdev_priv(dev);
10185
10186         if (tp->link_config.phy_is_low_power)
10187                 tg3_set_power_state(tp, PCI_D0);
10188
10189         memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
10190
10191         if (tg3_test_nvram(tp) != 0) {
10192                 etest->flags |= ETH_TEST_FL_FAILED;
10193                 data[0] = 1;
10194         }
10195         if (tg3_test_link(tp) != 0) {
10196                 etest->flags |= ETH_TEST_FL_FAILED;
10197                 data[1] = 1;
10198         }
10199         if (etest->flags & ETH_TEST_FL_OFFLINE) {
10200                 int err, err2 = 0, irq_sync = 0;
10201
10202                 if (netif_running(dev)) {
10203                         tg3_phy_stop(tp);
10204                         tg3_netif_stop(tp);
10205                         irq_sync = 1;
10206                 }
10207
10208                 tg3_full_lock(tp, irq_sync);
10209
10210                 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
10211                 err = tg3_nvram_lock(tp);
10212                 tg3_halt_cpu(tp, RX_CPU_BASE);
10213                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10214                         tg3_halt_cpu(tp, TX_CPU_BASE);
10215                 if (!err)
10216                         tg3_nvram_unlock(tp);
10217
10218                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
10219                         tg3_phy_reset(tp);
10220
10221                 if (tg3_test_registers(tp) != 0) {
10222                         etest->flags |= ETH_TEST_FL_FAILED;
10223                         data[2] = 1;
10224                 }
10225                 if (tg3_test_memory(tp) != 0) {
10226                         etest->flags |= ETH_TEST_FL_FAILED;
10227                         data[3] = 1;
10228                 }
10229                 if ((data[4] = tg3_test_loopback(tp)) != 0)
10230                         etest->flags |= ETH_TEST_FL_FAILED;
10231
10232                 tg3_full_unlock(tp);
10233
10234                 if (tg3_test_interrupt(tp) != 0) {
10235                         etest->flags |= ETH_TEST_FL_FAILED;
10236                         data[5] = 1;
10237                 }
10238
10239                 tg3_full_lock(tp, 0);
10240
10241                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10242                 if (netif_running(dev)) {
10243                         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
10244                         err2 = tg3_restart_hw(tp, 1);
10245                         if (!err2)
10246                                 tg3_netif_start(tp);
10247                 }
10248
10249                 tg3_full_unlock(tp);
10250
10251                 if (irq_sync && !err2)
10252                         tg3_phy_start(tp);
10253         }
10254         if (tp->link_config.phy_is_low_power)
10255                 tg3_set_power_state(tp, PCI_D3hot);
10256
10257 }
10258
10259 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10260 {
10261         struct mii_ioctl_data *data = if_mii(ifr);
10262         struct tg3 *tp = netdev_priv(dev);
10263         int err;
10264
10265         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10266                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
10267                         return -EAGAIN;
10268                 return phy_mii_ioctl(tp->mdio_bus.phy_map[PHY_ADDR], data, cmd);
10269         }
10270
10271         switch(cmd) {
10272         case SIOCGMIIPHY:
10273                 data->phy_id = PHY_ADDR;
10274
10275                 /* fallthru */
10276         case SIOCGMIIREG: {
10277                 u32 mii_regval;
10278
10279                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10280                         break;                  /* We have no PHY */
10281
10282                 if (tp->link_config.phy_is_low_power)
10283                         return -EAGAIN;
10284
10285                 spin_lock_bh(&tp->lock);
10286                 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
10287                 spin_unlock_bh(&tp->lock);
10288
10289                 data->val_out = mii_regval;
10290
10291                 return err;
10292         }
10293
10294         case SIOCSMIIREG:
10295                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10296                         break;                  /* We have no PHY */
10297
10298                 if (!capable(CAP_NET_ADMIN))
10299                         return -EPERM;
10300
10301                 if (tp->link_config.phy_is_low_power)
10302                         return -EAGAIN;
10303
10304                 spin_lock_bh(&tp->lock);
10305                 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
10306                 spin_unlock_bh(&tp->lock);
10307
10308                 return err;
10309
10310         default:
10311                 /* do nothing */
10312                 break;
10313         }
10314         return -EOPNOTSUPP;
10315 }
10316
10317 #if TG3_VLAN_TAG_USED
10318 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
10319 {
10320         struct tg3 *tp = netdev_priv(dev);
10321
10322         if (netif_running(dev))
10323                 tg3_netif_stop(tp);
10324
10325         tg3_full_lock(tp, 0);
10326
10327         tp->vlgrp = grp;
10328
10329         /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
10330         __tg3_set_rx_mode(dev);
10331
10332         if (netif_running(dev))
10333                 tg3_netif_start(tp);
10334
10335         tg3_full_unlock(tp);
10336 }
10337 #endif
10338
10339 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10340 {
10341         struct tg3 *tp = netdev_priv(dev);
10342
10343         memcpy(ec, &tp->coal, sizeof(*ec));
10344         return 0;
10345 }
10346
10347 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10348 {
10349         struct tg3 *tp = netdev_priv(dev);
10350         u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
10351         u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
10352
10353         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
10354                 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
10355                 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
10356                 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
10357                 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
10358         }
10359
10360         if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
10361             (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
10362             (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
10363             (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
10364             (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
10365             (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
10366             (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
10367             (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
10368             (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
10369             (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
10370                 return -EINVAL;
10371
10372         /* No rx interrupts will be generated if both are zero */
10373         if ((ec->rx_coalesce_usecs == 0) &&
10374             (ec->rx_max_coalesced_frames == 0))
10375                 return -EINVAL;
10376
10377         /* No tx interrupts will be generated if both are zero */
10378         if ((ec->tx_coalesce_usecs == 0) &&
10379             (ec->tx_max_coalesced_frames == 0))
10380                 return -EINVAL;
10381
10382         /* Only copy relevant parameters, ignore all others. */
10383         tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
10384         tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
10385         tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
10386         tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
10387         tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
10388         tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
10389         tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
10390         tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
10391         tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
10392
10393         if (netif_running(dev)) {
10394                 tg3_full_lock(tp, 0);
10395                 __tg3_set_coalesce(tp, &tp->coal);
10396                 tg3_full_unlock(tp);
10397         }
10398         return 0;
10399 }
10400
10401 static const struct ethtool_ops tg3_ethtool_ops = {
10402         .get_settings           = tg3_get_settings,
10403         .set_settings           = tg3_set_settings,
10404         .get_drvinfo            = tg3_get_drvinfo,
10405         .get_regs_len           = tg3_get_regs_len,
10406         .get_regs               = tg3_get_regs,
10407         .get_wol                = tg3_get_wol,
10408         .set_wol                = tg3_set_wol,
10409         .get_msglevel           = tg3_get_msglevel,
10410         .set_msglevel           = tg3_set_msglevel,
10411         .nway_reset             = tg3_nway_reset,
10412         .get_link               = ethtool_op_get_link,
10413         .get_eeprom_len         = tg3_get_eeprom_len,
10414         .get_eeprom             = tg3_get_eeprom,
10415         .set_eeprom             = tg3_set_eeprom,
10416         .get_ringparam          = tg3_get_ringparam,
10417         .set_ringparam          = tg3_set_ringparam,
10418         .get_pauseparam         = tg3_get_pauseparam,
10419         .set_pauseparam         = tg3_set_pauseparam,
10420         .get_rx_csum            = tg3_get_rx_csum,
10421         .set_rx_csum            = tg3_set_rx_csum,
10422         .set_tx_csum            = tg3_set_tx_csum,
10423         .set_sg                 = ethtool_op_set_sg,
10424         .set_tso                = tg3_set_tso,
10425         .self_test              = tg3_self_test,
10426         .get_strings            = tg3_get_strings,
10427         .phys_id                = tg3_phys_id,
10428         .get_ethtool_stats      = tg3_get_ethtool_stats,
10429         .get_coalesce           = tg3_get_coalesce,
10430         .set_coalesce           = tg3_set_coalesce,
10431         .get_sset_count         = tg3_get_sset_count,
10432 };
10433
10434 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
10435 {
10436         u32 cursize, val, magic;
10437
10438         tp->nvram_size = EEPROM_CHIP_SIZE;
10439
10440         if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
10441                 return;
10442
10443         if ((magic != TG3_EEPROM_MAGIC) &&
10444             ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
10445             ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
10446                 return;
10447
10448         /*
10449          * Size the chip by reading offsets at increasing powers of two.
10450          * When we encounter our validation signature, we know the addressing
10451          * has wrapped around, and thus have our chip size.
10452          */
10453         cursize = 0x10;
10454
10455         while (cursize < tp->nvram_size) {
10456                 if (tg3_nvram_read_swab(tp, cursize, &val) != 0)
10457                         return;
10458
10459                 if (val == magic)
10460                         break;
10461
10462                 cursize <<= 1;
10463         }
10464
10465         tp->nvram_size = cursize;
10466 }
10467
10468 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
10469 {
10470         u32 val;
10471
10472         if (tg3_nvram_read_swab(tp, 0, &val) != 0)
10473                 return;
10474
10475         /* Selfboot format */
10476         if (val != TG3_EEPROM_MAGIC) {
10477                 tg3_get_eeprom_size(tp);
10478                 return;
10479         }
10480
10481         if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
10482                 if (val != 0) {
10483                         tp->nvram_size = (val >> 16) * 1024;
10484                         return;
10485                 }
10486         }
10487         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10488 }
10489
10490 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
10491 {
10492         u32 nvcfg1;
10493
10494         nvcfg1 = tr32(NVRAM_CFG1);
10495         if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
10496                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10497         }
10498         else {
10499                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10500                 tw32(NVRAM_CFG1, nvcfg1);
10501         }
10502
10503         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
10504             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
10505                 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
10506                         case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
10507                                 tp->nvram_jedecnum = JEDEC_ATMEL;
10508                                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10509                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10510                                 break;
10511                         case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
10512                                 tp->nvram_jedecnum = JEDEC_ATMEL;
10513                                 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
10514                                 break;
10515                         case FLASH_VENDOR_ATMEL_EEPROM:
10516                                 tp->nvram_jedecnum = JEDEC_ATMEL;
10517                                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10518                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10519                                 break;
10520                         case FLASH_VENDOR_ST:
10521                                 tp->nvram_jedecnum = JEDEC_ST;
10522                                 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
10523                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10524                                 break;
10525                         case FLASH_VENDOR_SAIFUN:
10526                                 tp->nvram_jedecnum = JEDEC_SAIFUN;
10527                                 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
10528                                 break;
10529                         case FLASH_VENDOR_SST_SMALL:
10530                         case FLASH_VENDOR_SST_LARGE:
10531                                 tp->nvram_jedecnum = JEDEC_SST;
10532                                 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
10533                                 break;
10534                 }
10535         }
10536         else {
10537                 tp->nvram_jedecnum = JEDEC_ATMEL;
10538                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10539                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10540         }
10541 }
10542
10543 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
10544 {
10545         u32 nvcfg1;
10546
10547         nvcfg1 = tr32(NVRAM_CFG1);
10548
10549         /* NVRAM protection for TPM */
10550         if (nvcfg1 & (1 << 27))
10551                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10552
10553         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10554                 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
10555                 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
10556                         tp->nvram_jedecnum = JEDEC_ATMEL;
10557                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10558                         break;
10559                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10560                         tp->nvram_jedecnum = JEDEC_ATMEL;
10561                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10562                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
10563                         break;
10564                 case FLASH_5752VENDOR_ST_M45PE10:
10565                 case FLASH_5752VENDOR_ST_M45PE20:
10566                 case FLASH_5752VENDOR_ST_M45PE40:
10567                         tp->nvram_jedecnum = JEDEC_ST;
10568                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10569                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
10570                         break;
10571         }
10572
10573         if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
10574                 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
10575                         case FLASH_5752PAGE_SIZE_256:
10576                                 tp->nvram_pagesize = 256;
10577                                 break;
10578                         case FLASH_5752PAGE_SIZE_512:
10579                                 tp->nvram_pagesize = 512;
10580                                 break;
10581                         case FLASH_5752PAGE_SIZE_1K:
10582                                 tp->nvram_pagesize = 1024;
10583                                 break;
10584                         case FLASH_5752PAGE_SIZE_2K:
10585                                 tp->nvram_pagesize = 2048;
10586                                 break;
10587                         case FLASH_5752PAGE_SIZE_4K:
10588                                 tp->nvram_pagesize = 4096;
10589                                 break;
10590                         case FLASH_5752PAGE_SIZE_264:
10591                                 tp->nvram_pagesize = 264;
10592                                 break;
10593                 }
10594         }
10595         else {
10596                 /* For eeprom, set pagesize to maximum eeprom size */
10597                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10598
10599                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10600                 tw32(NVRAM_CFG1, nvcfg1);
10601         }
10602 }
10603
10604 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
10605 {
10606         u32 nvcfg1, protect = 0;
10607
10608         nvcfg1 = tr32(NVRAM_CFG1);
10609
10610         /* NVRAM protection for TPM */
10611         if (nvcfg1 & (1 << 27)) {
10612                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10613                 protect = 1;
10614         }
10615
10616         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10617         switch (nvcfg1) {
10618                 case FLASH_5755VENDOR_ATMEL_FLASH_1:
10619                 case FLASH_5755VENDOR_ATMEL_FLASH_2:
10620                 case FLASH_5755VENDOR_ATMEL_FLASH_3:
10621                 case FLASH_5755VENDOR_ATMEL_FLASH_5:
10622                         tp->nvram_jedecnum = JEDEC_ATMEL;
10623                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10624                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
10625                         tp->nvram_pagesize = 264;
10626                         if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
10627                             nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
10628                                 tp->nvram_size = (protect ? 0x3e200 :
10629                                                   TG3_NVRAM_SIZE_512KB);
10630                         else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
10631                                 tp->nvram_size = (protect ? 0x1f200 :
10632                                                   TG3_NVRAM_SIZE_256KB);
10633                         else
10634                                 tp->nvram_size = (protect ? 0x1f200 :
10635                                                   TG3_NVRAM_SIZE_128KB);
10636                         break;
10637                 case FLASH_5752VENDOR_ST_M45PE10:
10638                 case FLASH_5752VENDOR_ST_M45PE20:
10639                 case FLASH_5752VENDOR_ST_M45PE40:
10640                         tp->nvram_jedecnum = JEDEC_ST;
10641                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10642                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
10643                         tp->nvram_pagesize = 256;
10644                         if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
10645                                 tp->nvram_size = (protect ?
10646                                                   TG3_NVRAM_SIZE_64KB :
10647                                                   TG3_NVRAM_SIZE_128KB);
10648                         else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
10649                                 tp->nvram_size = (protect ?
10650                                                   TG3_NVRAM_SIZE_64KB :
10651                                                   TG3_NVRAM_SIZE_256KB);
10652                         else
10653                                 tp->nvram_size = (protect ?
10654                                                   TG3_NVRAM_SIZE_128KB :
10655                                                   TG3_NVRAM_SIZE_512KB);
10656                         break;
10657         }
10658 }
10659
10660 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
10661 {
10662         u32 nvcfg1;
10663
10664         nvcfg1 = tr32(NVRAM_CFG1);
10665
10666         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10667                 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
10668                 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
10669                 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
10670                 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
10671                         tp->nvram_jedecnum = JEDEC_ATMEL;
10672                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10673                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10674
10675                         nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10676                         tw32(NVRAM_CFG1, nvcfg1);
10677                         break;
10678                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10679                 case FLASH_5755VENDOR_ATMEL_FLASH_1:
10680                 case FLASH_5755VENDOR_ATMEL_FLASH_2:
10681                 case FLASH_5755VENDOR_ATMEL_FLASH_3:
10682                         tp->nvram_jedecnum = JEDEC_ATMEL;
10683                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10684                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
10685                         tp->nvram_pagesize = 264;
10686                         break;
10687                 case FLASH_5752VENDOR_ST_M45PE10:
10688                 case FLASH_5752VENDOR_ST_M45PE20:
10689                 case FLASH_5752VENDOR_ST_M45PE40:
10690                         tp->nvram_jedecnum = JEDEC_ST;
10691                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10692                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
10693                         tp->nvram_pagesize = 256;
10694                         break;
10695         }
10696 }
10697
10698 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
10699 {
10700         u32 nvcfg1, protect = 0;
10701
10702         nvcfg1 = tr32(NVRAM_CFG1);
10703
10704         /* NVRAM protection for TPM */
10705         if (nvcfg1 & (1 << 27)) {
10706                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10707                 protect = 1;
10708         }
10709
10710         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10711         switch (nvcfg1) {
10712                 case FLASH_5761VENDOR_ATMEL_ADB021D:
10713                 case FLASH_5761VENDOR_ATMEL_ADB041D:
10714                 case FLASH_5761VENDOR_ATMEL_ADB081D:
10715                 case FLASH_5761VENDOR_ATMEL_ADB161D:
10716                 case FLASH_5761VENDOR_ATMEL_MDB021D:
10717                 case FLASH_5761VENDOR_ATMEL_MDB041D:
10718                 case FLASH_5761VENDOR_ATMEL_MDB081D:
10719                 case FLASH_5761VENDOR_ATMEL_MDB161D:
10720                         tp->nvram_jedecnum = JEDEC_ATMEL;
10721                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10722                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
10723                         tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10724                         tp->nvram_pagesize = 256;
10725                         break;
10726                 case FLASH_5761VENDOR_ST_A_M45PE20:
10727                 case FLASH_5761VENDOR_ST_A_M45PE40:
10728                 case FLASH_5761VENDOR_ST_A_M45PE80:
10729                 case FLASH_5761VENDOR_ST_A_M45PE16:
10730                 case FLASH_5761VENDOR_ST_M_M45PE20:
10731                 case FLASH_5761VENDOR_ST_M_M45PE40:
10732                 case FLASH_5761VENDOR_ST_M_M45PE80:
10733                 case FLASH_5761VENDOR_ST_M_M45PE16:
10734                         tp->nvram_jedecnum = JEDEC_ST;
10735                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10736                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
10737                         tp->nvram_pagesize = 256;
10738                         break;
10739         }
10740
10741         if (protect) {
10742                 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
10743         } else {
10744                 switch (nvcfg1) {
10745                         case FLASH_5761VENDOR_ATMEL_ADB161D:
10746                         case FLASH_5761VENDOR_ATMEL_MDB161D:
10747                         case FLASH_5761VENDOR_ST_A_M45PE16:
10748                         case FLASH_5761VENDOR_ST_M_M45PE16:
10749                                 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
10750                                 break;
10751                         case FLASH_5761VENDOR_ATMEL_ADB081D:
10752                         case FLASH_5761VENDOR_ATMEL_MDB081D:
10753                         case FLASH_5761VENDOR_ST_A_M45PE80:
10754                         case FLASH_5761VENDOR_ST_M_M45PE80:
10755                                 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
10756                                 break;
10757                         case FLASH_5761VENDOR_ATMEL_ADB041D:
10758                         case FLASH_5761VENDOR_ATMEL_MDB041D:
10759                         case FLASH_5761VENDOR_ST_A_M45PE40:
10760                         case FLASH_5761VENDOR_ST_M_M45PE40:
10761                                 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10762                                 break;
10763                         case FLASH_5761VENDOR_ATMEL_ADB021D:
10764                         case FLASH_5761VENDOR_ATMEL_MDB021D:
10765                         case FLASH_5761VENDOR_ST_A_M45PE20:
10766                         case FLASH_5761VENDOR_ST_M_M45PE20:
10767                                 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10768                                 break;
10769                 }
10770         }
10771 }
10772
10773 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
10774 {
10775         tp->nvram_jedecnum = JEDEC_ATMEL;
10776         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10777         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10778 }
10779
10780 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
10781 static void __devinit tg3_nvram_init(struct tg3 *tp)
10782 {
10783         tw32_f(GRC_EEPROM_ADDR,
10784              (EEPROM_ADDR_FSM_RESET |
10785               (EEPROM_DEFAULT_CLOCK_PERIOD <<
10786                EEPROM_ADDR_CLKPERD_SHIFT)));
10787
10788         msleep(1);
10789
10790         /* Enable seeprom accesses. */
10791         tw32_f(GRC_LOCAL_CTRL,
10792              tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
10793         udelay(100);
10794
10795         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
10796             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
10797                 tp->tg3_flags |= TG3_FLAG_NVRAM;
10798
10799                 if (tg3_nvram_lock(tp)) {
10800                         printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
10801                                "tg3_nvram_init failed.\n", tp->dev->name);
10802                         return;
10803                 }
10804                 tg3_enable_nvram_access(tp);
10805
10806                 tp->nvram_size = 0;
10807
10808                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
10809                         tg3_get_5752_nvram_info(tp);
10810                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10811                         tg3_get_5755_nvram_info(tp);
10812                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10813                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
10814                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
10815                         tg3_get_5787_nvram_info(tp);
10816                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
10817                         tg3_get_5761_nvram_info(tp);
10818                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10819                         tg3_get_5906_nvram_info(tp);
10820                 else
10821                         tg3_get_nvram_info(tp);
10822
10823                 if (tp->nvram_size == 0)
10824                         tg3_get_nvram_size(tp);
10825
10826                 tg3_disable_nvram_access(tp);
10827                 tg3_nvram_unlock(tp);
10828
10829         } else {
10830                 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
10831
10832                 tg3_get_eeprom_size(tp);
10833         }
10834 }
10835
10836 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
10837                                         u32 offset, u32 *val)
10838 {
10839         u32 tmp;
10840         int i;
10841
10842         if (offset > EEPROM_ADDR_ADDR_MASK ||
10843             (offset % 4) != 0)
10844                 return -EINVAL;
10845
10846         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
10847                                         EEPROM_ADDR_DEVID_MASK |
10848                                         EEPROM_ADDR_READ);
10849         tw32(GRC_EEPROM_ADDR,
10850              tmp |
10851              (0 << EEPROM_ADDR_DEVID_SHIFT) |
10852              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
10853               EEPROM_ADDR_ADDR_MASK) |
10854              EEPROM_ADDR_READ | EEPROM_ADDR_START);
10855
10856         for (i = 0; i < 1000; i++) {
10857                 tmp = tr32(GRC_EEPROM_ADDR);
10858
10859                 if (tmp & EEPROM_ADDR_COMPLETE)
10860                         break;
10861                 msleep(1);
10862         }
10863         if (!(tmp & EEPROM_ADDR_COMPLETE))
10864                 return -EBUSY;
10865
10866         *val = tr32(GRC_EEPROM_DATA);
10867         return 0;
10868 }
10869
10870 #define NVRAM_CMD_TIMEOUT 10000
10871
10872 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
10873 {
10874         int i;
10875
10876         tw32(NVRAM_CMD, nvram_cmd);
10877         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
10878                 udelay(10);
10879                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
10880                         udelay(10);
10881                         break;
10882                 }
10883         }
10884         if (i == NVRAM_CMD_TIMEOUT) {
10885                 return -EBUSY;
10886         }
10887         return 0;
10888 }
10889
10890 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
10891 {
10892         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
10893             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
10894             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
10895            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
10896             (tp->nvram_jedecnum == JEDEC_ATMEL))
10897
10898                 addr = ((addr / tp->nvram_pagesize) <<
10899                         ATMEL_AT45DB0X1B_PAGE_POS) +
10900                        (addr % tp->nvram_pagesize);
10901
10902         return addr;
10903 }
10904
10905 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
10906 {
10907         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
10908             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
10909             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
10910            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
10911             (tp->nvram_jedecnum == JEDEC_ATMEL))
10912
10913                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
10914                         tp->nvram_pagesize) +
10915                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
10916
10917         return addr;
10918 }
10919
10920 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
10921 {
10922         int ret;
10923
10924         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
10925                 return tg3_nvram_read_using_eeprom(tp, offset, val);
10926
10927         offset = tg3_nvram_phys_addr(tp, offset);
10928
10929         if (offset > NVRAM_ADDR_MSK)
10930                 return -EINVAL;
10931
10932         ret = tg3_nvram_lock(tp);
10933         if (ret)
10934                 return ret;
10935
10936         tg3_enable_nvram_access(tp);
10937
10938         tw32(NVRAM_ADDR, offset);
10939         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
10940                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
10941
10942         if (ret == 0)
10943                 *val = swab32(tr32(NVRAM_RDDATA));
10944
10945         tg3_disable_nvram_access(tp);
10946
10947         tg3_nvram_unlock(tp);
10948
10949         return ret;
10950 }
10951
10952 static int tg3_nvram_read_le(struct tg3 *tp, u32 offset, __le32 *val)
10953 {
10954         u32 v;
10955         int res = tg3_nvram_read(tp, offset, &v);
10956         if (!res)
10957                 *val = cpu_to_le32(v);
10958         return res;
10959 }
10960
10961 static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val)
10962 {
10963         int err;
10964         u32 tmp;
10965
10966         err = tg3_nvram_read(tp, offset, &tmp);
10967         *val = swab32(tmp);
10968         return err;
10969 }
10970
10971 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
10972                                     u32 offset, u32 len, u8 *buf)
10973 {
10974         int i, j, rc = 0;
10975         u32 val;
10976
10977         for (i = 0; i < len; i += 4) {
10978                 u32 addr;
10979                 __le32 data;
10980
10981                 addr = offset + i;
10982
10983                 memcpy(&data, buf + i, 4);
10984
10985                 tw32(GRC_EEPROM_DATA, le32_to_cpu(data));
10986
10987                 val = tr32(GRC_EEPROM_ADDR);
10988                 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
10989
10990                 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
10991                         EEPROM_ADDR_READ);
10992                 tw32(GRC_EEPROM_ADDR, val |
10993                         (0 << EEPROM_ADDR_DEVID_SHIFT) |
10994                         (addr & EEPROM_ADDR_ADDR_MASK) |
10995                         EEPROM_ADDR_START |
10996                         EEPROM_ADDR_WRITE);
10997
10998                 for (j = 0; j < 1000; j++) {
10999                         val = tr32(GRC_EEPROM_ADDR);
11000
11001                         if (val & EEPROM_ADDR_COMPLETE)
11002                                 break;
11003                         msleep(1);
11004                 }
11005                 if (!(val & EEPROM_ADDR_COMPLETE)) {
11006                         rc = -EBUSY;
11007                         break;
11008                 }
11009         }
11010
11011         return rc;
11012 }
11013
11014 /* offset and length are dword aligned */
11015 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11016                 u8 *buf)
11017 {
11018         int ret = 0;
11019         u32 pagesize = tp->nvram_pagesize;
11020         u32 pagemask = pagesize - 1;
11021         u32 nvram_cmd;
11022         u8 *tmp;
11023
11024         tmp = kmalloc(pagesize, GFP_KERNEL);
11025         if (tmp == NULL)
11026                 return -ENOMEM;
11027
11028         while (len) {
11029                 int j;
11030                 u32 phy_addr, page_off, size;
11031
11032                 phy_addr = offset & ~pagemask;
11033
11034                 for (j = 0; j < pagesize; j += 4) {
11035                         if ((ret = tg3_nvram_read_le(tp, phy_addr + j,
11036                                                 (__le32 *) (tmp + j))))
11037                                 break;
11038                 }
11039                 if (ret)
11040                         break;
11041
11042                 page_off = offset & pagemask;
11043                 size = pagesize;
11044                 if (len < size)
11045                         size = len;
11046
11047                 len -= size;
11048
11049                 memcpy(tmp + page_off, buf, size);
11050
11051                 offset = offset + (pagesize - page_off);
11052
11053                 tg3_enable_nvram_access(tp);
11054
11055                 /*
11056                  * Before we can erase the flash page, we need
11057                  * to issue a special "write enable" command.
11058                  */
11059                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11060
11061                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11062                         break;
11063
11064                 /* Erase the target page */
11065                 tw32(NVRAM_ADDR, phy_addr);
11066
11067                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
11068                         NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
11069
11070                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11071                         break;
11072
11073                 /* Issue another write enable to start the write. */
11074                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11075
11076                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11077                         break;
11078
11079                 for (j = 0; j < pagesize; j += 4) {
11080                         __be32 data;
11081
11082                         data = *((__be32 *) (tmp + j));
11083                         /* swab32(le32_to_cpu(data)), actually */
11084                         tw32(NVRAM_WRDATA, be32_to_cpu(data));
11085
11086                         tw32(NVRAM_ADDR, phy_addr + j);
11087
11088                         nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
11089                                 NVRAM_CMD_WR;
11090
11091                         if (j == 0)
11092                                 nvram_cmd |= NVRAM_CMD_FIRST;
11093                         else if (j == (pagesize - 4))
11094                                 nvram_cmd |= NVRAM_CMD_LAST;
11095
11096                         if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11097                                 break;
11098                 }
11099                 if (ret)
11100                         break;
11101         }
11102
11103         nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11104         tg3_nvram_exec_cmd(tp, nvram_cmd);
11105
11106         kfree(tmp);
11107
11108         return ret;
11109 }
11110
11111 /* offset and length are dword aligned */
11112 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
11113                 u8 *buf)
11114 {
11115         int i, ret = 0;
11116
11117         for (i = 0; i < len; i += 4, offset += 4) {
11118                 u32 page_off, phy_addr, nvram_cmd;
11119                 __be32 data;
11120
11121                 memcpy(&data, buf + i, 4);
11122                 tw32(NVRAM_WRDATA, be32_to_cpu(data));
11123
11124                 page_off = offset % tp->nvram_pagesize;
11125
11126                 phy_addr = tg3_nvram_phys_addr(tp, offset);
11127
11128                 tw32(NVRAM_ADDR, phy_addr);
11129
11130                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
11131
11132                 if ((page_off == 0) || (i == 0))
11133                         nvram_cmd |= NVRAM_CMD_FIRST;
11134                 if (page_off == (tp->nvram_pagesize - 4))
11135                         nvram_cmd |= NVRAM_CMD_LAST;
11136
11137                 if (i == (len - 4))
11138                         nvram_cmd |= NVRAM_CMD_LAST;
11139
11140                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752) &&
11141                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755) &&
11142                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787) &&
11143                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784) &&
11144                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) &&
11145                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) &&
11146                     (tp->nvram_jedecnum == JEDEC_ST) &&
11147                     (nvram_cmd & NVRAM_CMD_FIRST)) {
11148
11149                         if ((ret = tg3_nvram_exec_cmd(tp,
11150                                 NVRAM_CMD_WREN | NVRAM_CMD_GO |
11151                                 NVRAM_CMD_DONE)))
11152
11153                                 break;
11154                 }
11155                 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11156                         /* We always do complete word writes to eeprom. */
11157                         nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
11158                 }
11159
11160                 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11161                         break;
11162         }
11163         return ret;
11164 }
11165
11166 /* offset and length are dword aligned */
11167 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
11168 {
11169         int ret;
11170
11171         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11172                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
11173                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
11174                 udelay(40);
11175         }
11176
11177         if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
11178                 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
11179         }
11180         else {
11181                 u32 grc_mode;
11182
11183                 ret = tg3_nvram_lock(tp);
11184                 if (ret)
11185                         return ret;
11186
11187                 tg3_enable_nvram_access(tp);
11188                 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
11189                     !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
11190                         tw32(NVRAM_WRITE1, 0x406);
11191
11192                 grc_mode = tr32(GRC_MODE);
11193                 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
11194
11195                 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
11196                         !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11197
11198                         ret = tg3_nvram_write_block_buffered(tp, offset, len,
11199                                 buf);
11200                 }
11201                 else {
11202                         ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
11203                                 buf);
11204                 }
11205
11206                 grc_mode = tr32(GRC_MODE);
11207                 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
11208
11209                 tg3_disable_nvram_access(tp);
11210                 tg3_nvram_unlock(tp);
11211         }
11212
11213         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11214                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
11215                 udelay(40);
11216         }
11217
11218         return ret;
11219 }
11220
11221 struct subsys_tbl_ent {
11222         u16 subsys_vendor, subsys_devid;
11223         u32 phy_id;
11224 };
11225
11226 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
11227         /* Broadcom boards. */
11228         { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
11229         { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
11230         { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
11231         { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 },              /* BCM95700A9 */
11232         { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
11233         { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
11234         { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 },              /* BCM95701A7 */
11235         { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
11236         { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
11237         { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
11238         { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
11239
11240         /* 3com boards. */
11241         { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
11242         { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
11243         { PCI_VENDOR_ID_3COM, 0x1004, 0 },              /* 3C996SX */
11244         { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
11245         { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
11246
11247         /* DELL boards. */
11248         { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
11249         { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
11250         { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
11251         { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
11252
11253         /* Compaq boards. */
11254         { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
11255         { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
11256         { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 },              /* CHANGELING */
11257         { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
11258         { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
11259
11260         /* IBM boards. */
11261         { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
11262 };
11263
11264 static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
11265 {
11266         int i;
11267
11268         for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
11269                 if ((subsys_id_to_phy_id[i].subsys_vendor ==
11270                      tp->pdev->subsystem_vendor) &&
11271                     (subsys_id_to_phy_id[i].subsys_devid ==
11272                      tp->pdev->subsystem_device))
11273                         return &subsys_id_to_phy_id[i];
11274         }
11275         return NULL;
11276 }
11277
11278 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
11279 {
11280         u32 val;
11281         u16 pmcsr;
11282
11283         /* On some early chips the SRAM cannot be accessed in D3hot state,
11284          * so need make sure we're in D0.
11285          */
11286         pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
11287         pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
11288         pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
11289         msleep(1);
11290
11291         /* Make sure register accesses (indirect or otherwise)
11292          * will function correctly.
11293          */
11294         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11295                                tp->misc_host_ctrl);
11296
11297         /* The memory arbiter has to be enabled in order for SRAM accesses
11298          * to succeed.  Normally on powerup the tg3 chip firmware will make
11299          * sure it is enabled, but other entities such as system netboot
11300          * code might disable it.
11301          */
11302         val = tr32(MEMARB_MODE);
11303         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
11304
11305         tp->phy_id = PHY_ID_INVALID;
11306         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11307
11308         /* Assume an onboard device and WOL capable by default.  */
11309         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
11310
11311         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11312                 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
11313                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11314                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11315                 }
11316                 val = tr32(VCPU_CFGSHDW);
11317                 if (val & VCPU_CFGSHDW_ASPM_DBNC)
11318                         tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11319                 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
11320                     (val & VCPU_CFGSHDW_WOL_MAGPKT) &&
11321                     device_may_wakeup(&tp->pdev->dev))
11322                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11323                 return;
11324         }
11325
11326         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
11327         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
11328                 u32 nic_cfg, led_cfg;
11329                 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
11330                 int eeprom_phy_serdes = 0;
11331
11332                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
11333                 tp->nic_sram_data_cfg = nic_cfg;
11334
11335                 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
11336                 ver >>= NIC_SRAM_DATA_VER_SHIFT;
11337                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
11338                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
11339                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
11340                     (ver > 0) && (ver < 0x100))
11341                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
11342
11343                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11344                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
11345
11346                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
11347                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
11348                         eeprom_phy_serdes = 1;
11349
11350                 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
11351                 if (nic_phy_id != 0) {
11352                         u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
11353                         u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
11354
11355                         eeprom_phy_id  = (id1 >> 16) << 10;
11356                         eeprom_phy_id |= (id2 & 0xfc00) << 16;
11357                         eeprom_phy_id |= (id2 & 0x03ff) <<  0;
11358                 } else
11359                         eeprom_phy_id = 0;
11360
11361                 tp->phy_id = eeprom_phy_id;
11362                 if (eeprom_phy_serdes) {
11363                         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
11364                                 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
11365                         else
11366                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11367                 }
11368
11369                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
11370                         led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
11371                                     SHASTA_EXT_LED_MODE_MASK);
11372                 else
11373                         led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
11374
11375                 switch (led_cfg) {
11376                 default:
11377                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
11378                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11379                         break;
11380
11381                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
11382                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11383                         break;
11384
11385                 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
11386                         tp->led_ctrl = LED_CTRL_MODE_MAC;
11387
11388                         /* Default to PHY_1_MODE if 0 (MAC_MODE) is
11389                          * read on some older 5700/5701 bootcode.
11390                          */
11391                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
11392                             ASIC_REV_5700 ||
11393                             GET_ASIC_REV(tp->pci_chip_rev_id) ==
11394                             ASIC_REV_5701)
11395                                 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11396
11397                         break;
11398
11399                 case SHASTA_EXT_LED_SHARED:
11400                         tp->led_ctrl = LED_CTRL_MODE_SHARED;
11401                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
11402                             tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
11403                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11404                                                  LED_CTRL_MODE_PHY_2);
11405                         break;
11406
11407                 case SHASTA_EXT_LED_MAC:
11408                         tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
11409                         break;
11410
11411                 case SHASTA_EXT_LED_COMBO:
11412                         tp->led_ctrl = LED_CTRL_MODE_COMBO;
11413                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
11414                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11415                                                  LED_CTRL_MODE_PHY_2);
11416                         break;
11417
11418                 }
11419
11420                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11421                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
11422                     tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
11423                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11424
11425                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
11426                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11427
11428                 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
11429                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
11430                         if ((tp->pdev->subsystem_vendor ==
11431                              PCI_VENDOR_ID_ARIMA) &&
11432                             (tp->pdev->subsystem_device == 0x205a ||
11433                              tp->pdev->subsystem_device == 0x2063))
11434                                 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11435                 } else {
11436                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11437                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11438                 }
11439
11440                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
11441                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
11442                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
11443                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
11444                 }
11445                 if (nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE)
11446                         tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
11447                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
11448                     !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
11449                         tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
11450
11451                 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
11452                     (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE) &&
11453                     device_may_wakeup(&tp->pdev->dev))
11454                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11455
11456                 if (cfg2 & (1 << 17))
11457                         tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
11458
11459                 /* serdes signal pre-emphasis in register 0x590 set by */
11460                 /* bootcode if bit 18 is set */
11461                 if (cfg2 & (1 << 18))
11462                         tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
11463
11464                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11465                         u32 cfg3;
11466
11467                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
11468                         if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
11469                                 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11470                 }
11471
11472                 if (cfg4 & NIC_SRAM_RGMII_STD_IBND_DISABLE)
11473                         tp->tg3_flags3 |= TG3_FLG3_RGMII_STD_IBND_DISABLE;
11474                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
11475                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
11476                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
11477                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
11478         }
11479 }
11480
11481 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
11482 {
11483         int i;
11484         u32 val;
11485
11486         tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
11487         tw32(OTP_CTRL, cmd);
11488
11489         /* Wait for up to 1 ms for command to execute. */
11490         for (i = 0; i < 100; i++) {
11491                 val = tr32(OTP_STATUS);
11492                 if (val & OTP_STATUS_CMD_DONE)
11493                         break;
11494                 udelay(10);
11495         }
11496
11497         return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
11498 }
11499
11500 /* Read the gphy configuration from the OTP region of the chip.  The gphy
11501  * configuration is a 32-bit value that straddles the alignment boundary.
11502  * We do two 32-bit reads and then shift and merge the results.
11503  */
11504 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
11505 {
11506         u32 bhalf_otp, thalf_otp;
11507
11508         tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
11509
11510         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
11511                 return 0;
11512
11513         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
11514
11515         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11516                 return 0;
11517
11518         thalf_otp = tr32(OTP_READ_DATA);
11519
11520         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
11521
11522         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11523                 return 0;
11524
11525         bhalf_otp = tr32(OTP_READ_DATA);
11526
11527         return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
11528 }
11529
11530 static int __devinit tg3_phy_probe(struct tg3 *tp)
11531 {
11532         u32 hw_phy_id_1, hw_phy_id_2;
11533         u32 hw_phy_id, hw_phy_id_masked;
11534         int err;
11535
11536         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
11537                 return tg3_phy_init(tp);
11538
11539         /* Reading the PHY ID register can conflict with ASF
11540          * firwmare access to the PHY hardware.
11541          */
11542         err = 0;
11543         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
11544             (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
11545                 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
11546         } else {
11547                 /* Now read the physical PHY_ID from the chip and verify
11548                  * that it is sane.  If it doesn't look good, we fall back
11549                  * to either the hard-coded table based PHY_ID and failing
11550                  * that the value found in the eeprom area.
11551                  */
11552                 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
11553                 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
11554
11555                 hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
11556                 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
11557                 hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
11558
11559                 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
11560         }
11561
11562         if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
11563                 tp->phy_id = hw_phy_id;
11564                 if (hw_phy_id_masked == PHY_ID_BCM8002)
11565                         tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11566                 else
11567                         tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
11568         } else {
11569                 if (tp->phy_id != PHY_ID_INVALID) {
11570                         /* Do nothing, phy ID already set up in
11571                          * tg3_get_eeprom_hw_cfg().
11572                          */
11573                 } else {
11574                         struct subsys_tbl_ent *p;
11575
11576                         /* No eeprom signature?  Try the hardcoded
11577                          * subsys device table.
11578                          */
11579                         p = lookup_by_subsys(tp);
11580                         if (!p)
11581                                 return -ENODEV;
11582
11583                         tp->phy_id = p->phy_id;
11584                         if (!tp->phy_id ||
11585                             tp->phy_id == PHY_ID_BCM8002)
11586                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11587                 }
11588         }
11589
11590         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
11591             !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
11592             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
11593                 u32 bmsr, adv_reg, tg3_ctrl, mask;
11594
11595                 tg3_readphy(tp, MII_BMSR, &bmsr);
11596                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
11597                     (bmsr & BMSR_LSTATUS))
11598                         goto skip_phy_reset;
11599
11600                 err = tg3_phy_reset(tp);
11601                 if (err)
11602                         return err;
11603
11604                 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
11605                            ADVERTISE_100HALF | ADVERTISE_100FULL |
11606                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
11607                 tg3_ctrl = 0;
11608                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
11609                         tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
11610                                     MII_TG3_CTRL_ADV_1000_FULL);
11611                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
11612                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
11613                                 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
11614                                              MII_TG3_CTRL_ENABLE_AS_MASTER);
11615                 }
11616
11617                 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
11618                         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
11619                         ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
11620                 if (!tg3_copper_is_advertising_all(tp, mask)) {
11621                         tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11622
11623                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11624                                 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11625
11626                         tg3_writephy(tp, MII_BMCR,
11627                                      BMCR_ANENABLE | BMCR_ANRESTART);
11628                 }
11629                 tg3_phy_set_wirespeed(tp);
11630
11631                 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11632                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11633                         tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11634         }
11635
11636 skip_phy_reset:
11637         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
11638                 err = tg3_init_5401phy_dsp(tp);
11639                 if (err)
11640                         return err;
11641         }
11642
11643         if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
11644                 err = tg3_init_5401phy_dsp(tp);
11645         }
11646
11647         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
11648                 tp->link_config.advertising =
11649                         (ADVERTISED_1000baseT_Half |
11650                          ADVERTISED_1000baseT_Full |
11651                          ADVERTISED_Autoneg |
11652                          ADVERTISED_FIBRE);
11653         if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
11654                 tp->link_config.advertising &=
11655                         ~(ADVERTISED_1000baseT_Half |
11656                           ADVERTISED_1000baseT_Full);
11657
11658         return err;
11659 }
11660
11661 static void __devinit tg3_read_partno(struct tg3 *tp)
11662 {
11663         unsigned char vpd_data[256];
11664         unsigned int i;
11665         u32 magic;
11666
11667         if (tg3_nvram_read_swab(tp, 0x0, &magic))
11668                 goto out_not_found;
11669
11670         if (magic == TG3_EEPROM_MAGIC) {
11671                 for (i = 0; i < 256; i += 4) {
11672                         u32 tmp;
11673
11674                         if (tg3_nvram_read(tp, 0x100 + i, &tmp))
11675                                 goto out_not_found;
11676
11677                         vpd_data[i + 0] = ((tmp >>  0) & 0xff);
11678                         vpd_data[i + 1] = ((tmp >>  8) & 0xff);
11679                         vpd_data[i + 2] = ((tmp >> 16) & 0xff);
11680                         vpd_data[i + 3] = ((tmp >> 24) & 0xff);
11681                 }
11682         } else {
11683                 int vpd_cap;
11684
11685                 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
11686                 for (i = 0; i < 256; i += 4) {
11687                         u32 tmp, j = 0;
11688                         __le32 v;
11689                         u16 tmp16;
11690
11691                         pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
11692                                               i);
11693                         while (j++ < 100) {
11694                                 pci_read_config_word(tp->pdev, vpd_cap +
11695                                                      PCI_VPD_ADDR, &tmp16);
11696                                 if (tmp16 & 0x8000)
11697                                         break;
11698                                 msleep(1);
11699                         }
11700                         if (!(tmp16 & 0x8000))
11701                                 goto out_not_found;
11702
11703                         pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
11704                                               &tmp);
11705                         v = cpu_to_le32(tmp);
11706                         memcpy(&vpd_data[i], &v, 4);
11707                 }
11708         }
11709
11710         /* Now parse and find the part number. */
11711         for (i = 0; i < 254; ) {
11712                 unsigned char val = vpd_data[i];
11713                 unsigned int block_end;
11714
11715                 if (val == 0x82 || val == 0x91) {
11716                         i = (i + 3 +
11717                              (vpd_data[i + 1] +
11718                               (vpd_data[i + 2] << 8)));
11719                         continue;
11720                 }
11721
11722                 if (val != 0x90)
11723                         goto out_not_found;
11724
11725                 block_end = (i + 3 +
11726                              (vpd_data[i + 1] +
11727                               (vpd_data[i + 2] << 8)));
11728                 i += 3;
11729
11730                 if (block_end > 256)
11731                         goto out_not_found;
11732
11733                 while (i < (block_end - 2)) {
11734                         if (vpd_data[i + 0] == 'P' &&
11735                             vpd_data[i + 1] == 'N') {
11736                                 int partno_len = vpd_data[i + 2];
11737
11738                                 i += 3;
11739                                 if (partno_len > 24 || (partno_len + i) > 256)
11740                                         goto out_not_found;
11741
11742                                 memcpy(tp->board_part_number,
11743                                        &vpd_data[i], partno_len);
11744
11745                                 /* Success. */
11746                                 return;
11747                         }
11748                         i += 3 + vpd_data[i + 2];
11749                 }
11750
11751                 /* Part number not found. */
11752                 goto out_not_found;
11753         }
11754
11755 out_not_found:
11756         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11757                 strcpy(tp->board_part_number, "BCM95906");
11758         else
11759                 strcpy(tp->board_part_number, "none");
11760 }
11761
11762 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
11763 {
11764         u32 val;
11765
11766         if (tg3_nvram_read_swab(tp, offset, &val) ||
11767             (val & 0xfc000000) != 0x0c000000 ||
11768             tg3_nvram_read_swab(tp, offset + 4, &val) ||
11769             val != 0)
11770                 return 0;
11771
11772         return 1;
11773 }
11774
11775 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
11776 {
11777         u32 val, offset, start;
11778         u32 ver_offset;
11779         int i, bcnt;
11780
11781         if (tg3_nvram_read_swab(tp, 0, &val))
11782                 return;
11783
11784         if (val != TG3_EEPROM_MAGIC)
11785                 return;
11786
11787         if (tg3_nvram_read_swab(tp, 0xc, &offset) ||
11788             tg3_nvram_read_swab(tp, 0x4, &start))
11789                 return;
11790
11791         offset = tg3_nvram_logical_addr(tp, offset);
11792
11793         if (!tg3_fw_img_is_valid(tp, offset) ||
11794             tg3_nvram_read_swab(tp, offset + 8, &ver_offset))
11795                 return;
11796
11797         offset = offset + ver_offset - start;
11798         for (i = 0; i < 16; i += 4) {
11799                 __le32 v;
11800                 if (tg3_nvram_read_le(tp, offset + i, &v))
11801                         return;
11802
11803                 memcpy(tp->fw_ver + i, &v, 4);
11804         }
11805
11806         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
11807              (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
11808                 return;
11809
11810         for (offset = TG3_NVM_DIR_START;
11811              offset < TG3_NVM_DIR_END;
11812              offset += TG3_NVM_DIRENT_SIZE) {
11813                 if (tg3_nvram_read_swab(tp, offset, &val))
11814                         return;
11815
11816                 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
11817                         break;
11818         }
11819
11820         if (offset == TG3_NVM_DIR_END)
11821                 return;
11822
11823         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
11824                 start = 0x08000000;
11825         else if (tg3_nvram_read_swab(tp, offset - 4, &start))
11826                 return;
11827
11828         if (tg3_nvram_read_swab(tp, offset + 4, &offset) ||
11829             !tg3_fw_img_is_valid(tp, offset) ||
11830             tg3_nvram_read_swab(tp, offset + 8, &val))
11831                 return;
11832
11833         offset += val - start;
11834
11835         bcnt = strlen(tp->fw_ver);
11836
11837         tp->fw_ver[bcnt++] = ',';
11838         tp->fw_ver[bcnt++] = ' ';
11839
11840         for (i = 0; i < 4; i++) {
11841                 __le32 v;
11842                 if (tg3_nvram_read_le(tp, offset, &v))
11843                         return;
11844
11845                 offset += sizeof(v);
11846
11847                 if (bcnt > TG3_VER_SIZE - sizeof(v)) {
11848                         memcpy(&tp->fw_ver[bcnt], &v, TG3_VER_SIZE - bcnt);
11849                         break;
11850                 }
11851
11852                 memcpy(&tp->fw_ver[bcnt], &v, sizeof(v));
11853                 bcnt += sizeof(v);
11854         }
11855
11856         tp->fw_ver[TG3_VER_SIZE - 1] = 0;
11857 }
11858
11859 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
11860
11861 static int __devinit tg3_get_invariants(struct tg3 *tp)
11862 {
11863         static struct pci_device_id write_reorder_chipsets[] = {
11864                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
11865                              PCI_DEVICE_ID_AMD_FE_GATE_700C) },
11866                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
11867                              PCI_DEVICE_ID_AMD_8131_BRIDGE) },
11868                 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
11869                              PCI_DEVICE_ID_VIA_8385_0) },
11870                 { },
11871         };
11872         u32 misc_ctrl_reg;
11873         u32 cacheline_sz_reg;
11874         u32 pci_state_reg, grc_misc_cfg;
11875         u32 val;
11876         u16 pci_cmd;
11877         int err, pcie_cap;
11878
11879         /* Force memory write invalidate off.  If we leave it on,
11880          * then on 5700_BX chips we have to enable a workaround.
11881          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
11882          * to match the cacheline size.  The Broadcom driver have this
11883          * workaround but turns MWI off all the times so never uses
11884          * it.  This seems to suggest that the workaround is insufficient.
11885          */
11886         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
11887         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
11888         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
11889
11890         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
11891          * has the register indirect write enable bit set before
11892          * we try to access any of the MMIO registers.  It is also
11893          * critical that the PCI-X hw workaround situation is decided
11894          * before that as well.
11895          */
11896         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11897                               &misc_ctrl_reg);
11898
11899         tp->pci_chip_rev_id = (misc_ctrl_reg >>
11900                                MISC_HOST_CTRL_CHIPREV_SHIFT);
11901         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
11902                 u32 prod_id_asic_rev;
11903
11904                 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
11905                                       &prod_id_asic_rev);
11906                 tp->pci_chip_rev_id = prod_id_asic_rev & PROD_ID_ASIC_REV_MASK;
11907         }
11908
11909         /* Wrong chip ID in 5752 A0. This code can be removed later
11910          * as A0 is not in production.
11911          */
11912         if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
11913                 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
11914
11915         /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
11916          * we need to disable memory and use config. cycles
11917          * only to access all registers. The 5702/03 chips
11918          * can mistakenly decode the special cycles from the
11919          * ICH chipsets as memory write cycles, causing corruption
11920          * of register and memory space. Only certain ICH bridges
11921          * will drive special cycles with non-zero data during the
11922          * address phase which can fall within the 5703's address
11923          * range. This is not an ICH bug as the PCI spec allows
11924          * non-zero address during special cycles. However, only
11925          * these ICH bridges are known to drive non-zero addresses
11926          * during special cycles.
11927          *
11928          * Since special cycles do not cross PCI bridges, we only
11929          * enable this workaround if the 5703 is on the secondary
11930          * bus of these ICH bridges.
11931          */
11932         if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
11933             (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
11934                 static struct tg3_dev_id {
11935                         u32     vendor;
11936                         u32     device;
11937                         u32     rev;
11938                 } ich_chipsets[] = {
11939                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
11940                           PCI_ANY_ID },
11941                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
11942                           PCI_ANY_ID },
11943                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
11944                           0xa },
11945                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
11946                           PCI_ANY_ID },
11947                         { },
11948                 };
11949                 struct tg3_dev_id *pci_id = &ich_chipsets[0];
11950                 struct pci_dev *bridge = NULL;
11951
11952                 while (pci_id->vendor != 0) {
11953                         bridge = pci_get_device(pci_id->vendor, pci_id->device,
11954                                                 bridge);
11955                         if (!bridge) {
11956                                 pci_id++;
11957                                 continue;
11958                         }
11959                         if (pci_id->rev != PCI_ANY_ID) {
11960                                 if (bridge->revision > pci_id->rev)
11961                                         continue;
11962                         }
11963                         if (bridge->subordinate &&
11964                             (bridge->subordinate->number ==
11965                              tp->pdev->bus->number)) {
11966
11967                                 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
11968                                 pci_dev_put(bridge);
11969                                 break;
11970                         }
11971                 }
11972         }
11973
11974         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
11975                 static struct tg3_dev_id {
11976                         u32     vendor;
11977                         u32     device;
11978                 } bridge_chipsets[] = {
11979                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
11980                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
11981                         { },
11982                 };
11983                 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
11984                 struct pci_dev *bridge = NULL;
11985
11986                 while (pci_id->vendor != 0) {
11987                         bridge = pci_get_device(pci_id->vendor,
11988                                                 pci_id->device,
11989                                                 bridge);
11990                         if (!bridge) {
11991                                 pci_id++;
11992                                 continue;
11993                         }
11994                         if (bridge->subordinate &&
11995                             (bridge->subordinate->number <=
11996                              tp->pdev->bus->number) &&
11997                             (bridge->subordinate->subordinate >=
11998                              tp->pdev->bus->number)) {
11999                                 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
12000                                 pci_dev_put(bridge);
12001                                 break;
12002                         }
12003                 }
12004         }
12005
12006         /* The EPB bridge inside 5714, 5715, and 5780 cannot support
12007          * DMA addresses > 40-bit. This bridge may have other additional
12008          * 57xx devices behind it in some 4-port NIC designs for example.
12009          * Any tg3 device found behind the bridge will also need the 40-bit
12010          * DMA workaround.
12011          */
12012         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
12013             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12014                 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
12015                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12016                 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
12017         }
12018         else {
12019                 struct pci_dev *bridge = NULL;
12020
12021                 do {
12022                         bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
12023                                                 PCI_DEVICE_ID_SERVERWORKS_EPB,
12024                                                 bridge);
12025                         if (bridge && bridge->subordinate &&
12026                             (bridge->subordinate->number <=
12027                              tp->pdev->bus->number) &&
12028                             (bridge->subordinate->subordinate >=
12029                              tp->pdev->bus->number)) {
12030                                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12031                                 pci_dev_put(bridge);
12032                                 break;
12033                         }
12034                 } while (bridge);
12035         }
12036
12037         /* Initialize misc host control in PCI block. */
12038         tp->misc_host_ctrl |= (misc_ctrl_reg &
12039                                MISC_HOST_CTRL_CHIPREV);
12040         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12041                                tp->misc_host_ctrl);
12042
12043         pci_read_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
12044                               &cacheline_sz_reg);
12045
12046         tp->pci_cacheline_sz = (cacheline_sz_reg >>  0) & 0xff;
12047         tp->pci_lat_timer    = (cacheline_sz_reg >>  8) & 0xff;
12048         tp->pci_hdr_type     = (cacheline_sz_reg >> 16) & 0xff;
12049         tp->pci_bist         = (cacheline_sz_reg >> 24) & 0xff;
12050
12051         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
12052             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
12053                 tp->pdev_peer = tg3_find_peer(tp);
12054
12055         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12056             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
12057             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12058             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12059             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12060             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12061             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12062             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
12063             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
12064                 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
12065
12066         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
12067             (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12068                 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
12069
12070         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
12071                 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
12072                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
12073                     GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
12074                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
12075                      tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
12076                      tp->pdev_peer == tp->pdev))
12077                         tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
12078
12079                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12080                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12081                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12082                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12083                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12084                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12085                         tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
12086                         tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
12087                 } else {
12088                         tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
12089                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12090                                 ASIC_REV_5750 &&
12091                             tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
12092                                 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
12093                 }
12094         }
12095
12096         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12097              (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
12098                 tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
12099
12100         pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
12101         if (pcie_cap != 0) {
12102                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
12103
12104                 pcie_set_readrq(tp->pdev, 4096);
12105
12106                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12107                         u16 lnkctl;
12108
12109                         pci_read_config_word(tp->pdev,
12110                                              pcie_cap + PCI_EXP_LNKCTL,
12111                                              &lnkctl);
12112                         if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN)
12113                                 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
12114                 }
12115         }
12116
12117         /* If we have an AMD 762 or VIA K8T800 chipset, write
12118          * reordering to the mailbox registers done by the host
12119          * controller can cause major troubles.  We read back from
12120          * every mailbox register write to force the writes to be
12121          * posted to the chip in order.
12122          */
12123         if (pci_dev_present(write_reorder_chipsets) &&
12124             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12125                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
12126
12127         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12128             tp->pci_lat_timer < 64) {
12129                 tp->pci_lat_timer = 64;
12130
12131                 cacheline_sz_reg  = ((tp->pci_cacheline_sz & 0xff) <<  0);
12132                 cacheline_sz_reg |= ((tp->pci_lat_timer    & 0xff) <<  8);
12133                 cacheline_sz_reg |= ((tp->pci_hdr_type     & 0xff) << 16);
12134                 cacheline_sz_reg |= ((tp->pci_bist         & 0xff) << 24);
12135
12136                 pci_write_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
12137                                        cacheline_sz_reg);
12138         }
12139
12140         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12141             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
12142                 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
12143                 if (!tp->pcix_cap) {
12144                         printk(KERN_ERR PFX "Cannot find PCI-X "
12145                                             "capability, aborting.\n");
12146                         return -EIO;
12147                 }
12148         }
12149
12150         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12151                               &pci_state_reg);
12152
12153         if (tp->pcix_cap && (pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0) {
12154                 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
12155
12156                 /* If this is a 5700 BX chipset, and we are in PCI-X
12157                  * mode, enable register write workaround.
12158                  *
12159                  * The workaround is to use indirect register accesses
12160                  * for all chip writes not to mailbox registers.
12161                  */
12162                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
12163                         u32 pm_reg;
12164
12165                         tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12166
12167                         /* The chip can have it's power management PCI config
12168                          * space registers clobbered due to this bug.
12169                          * So explicitly force the chip into D0 here.
12170                          */
12171                         pci_read_config_dword(tp->pdev,
12172                                               tp->pm_cap + PCI_PM_CTRL,
12173                                               &pm_reg);
12174                         pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
12175                         pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
12176                         pci_write_config_dword(tp->pdev,
12177                                                tp->pm_cap + PCI_PM_CTRL,
12178                                                pm_reg);
12179
12180                         /* Also, force SERR#/PERR# in PCI command. */
12181                         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12182                         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
12183                         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12184                 }
12185         }
12186
12187         /* 5700 BX chips need to have their TX producer index mailboxes
12188          * written twice to workaround a bug.
12189          */
12190         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX)
12191                 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
12192
12193         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
12194                 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
12195         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
12196                 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
12197
12198         /* Chip-specific fixup from Broadcom driver */
12199         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
12200             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
12201                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
12202                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
12203         }
12204
12205         /* Default fast path register access methods */
12206         tp->read32 = tg3_read32;
12207         tp->write32 = tg3_write32;
12208         tp->read32_mbox = tg3_read32;
12209         tp->write32_mbox = tg3_write32;
12210         tp->write32_tx_mbox = tg3_write32;
12211         tp->write32_rx_mbox = tg3_write32;
12212
12213         /* Various workaround register access methods */
12214         if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
12215                 tp->write32 = tg3_write_indirect_reg32;
12216         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
12217                  ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
12218                   tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
12219                 /*
12220                  * Back to back register writes can cause problems on these
12221                  * chips, the workaround is to read back all reg writes
12222                  * except those to mailbox regs.
12223                  *
12224                  * See tg3_write_indirect_reg32().
12225                  */
12226                 tp->write32 = tg3_write_flush_reg32;
12227         }
12228
12229
12230         if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
12231             (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
12232                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
12233                 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
12234                         tp->write32_rx_mbox = tg3_write_flush_reg32;
12235         }
12236
12237         if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
12238                 tp->read32 = tg3_read_indirect_reg32;
12239                 tp->write32 = tg3_write_indirect_reg32;
12240                 tp->read32_mbox = tg3_read_indirect_mbox;
12241                 tp->write32_mbox = tg3_write_indirect_mbox;
12242                 tp->write32_tx_mbox = tg3_write_indirect_mbox;
12243                 tp->write32_rx_mbox = tg3_write_indirect_mbox;
12244
12245                 iounmap(tp->regs);
12246                 tp->regs = NULL;
12247
12248                 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12249                 pci_cmd &= ~PCI_COMMAND_MEMORY;
12250                 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12251         }
12252         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12253                 tp->read32_mbox = tg3_read32_mbox_5906;
12254                 tp->write32_mbox = tg3_write32_mbox_5906;
12255                 tp->write32_tx_mbox = tg3_write32_mbox_5906;
12256                 tp->write32_rx_mbox = tg3_write32_mbox_5906;
12257         }
12258
12259         if (tp->write32 == tg3_write_indirect_reg32 ||
12260             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12261              (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12262               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
12263                 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
12264
12265         /* Get eeprom hw config before calling tg3_set_power_state().
12266          * In particular, the TG3_FLG2_IS_NIC flag must be
12267          * determined before calling tg3_set_power_state() so that
12268          * we know whether or not to switch out of Vaux power.
12269          * When the flag is set, it means that GPIO1 is used for eeprom
12270          * write protect and also implies that it is a LOM where GPIOs
12271          * are not used to switch power.
12272          */
12273         tg3_get_eeprom_hw_cfg(tp);
12274
12275         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
12276                 /* Allow reads and writes to the
12277                  * APE register and memory space.
12278                  */
12279                 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
12280                                  PCISTATE_ALLOW_APE_SHMEM_WR;
12281                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
12282                                        pci_state_reg);
12283         }
12284
12285         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12286             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12287             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
12288                 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
12289
12290                 if (tp->pci_chip_rev_id == CHIPREV_ID_5784_A0 ||
12291                     tp->pci_chip_rev_id == CHIPREV_ID_5784_A1 ||
12292                     tp->pci_chip_rev_id == CHIPREV_ID_5761_A0 ||
12293                     tp->pci_chip_rev_id == CHIPREV_ID_5761_A1)
12294                         tp->tg3_flags3 |= TG3_FLG3_5761_5784_AX_FIXES;
12295         }
12296
12297         /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
12298          * GPIO1 driven high will bring 5700's external PHY out of reset.
12299          * It is also used as eeprom write protect on LOMs.
12300          */
12301         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
12302         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12303             (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
12304                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
12305                                        GRC_LCLCTRL_GPIO_OUTPUT1);
12306         /* Unused GPIO3 must be driven as output on 5752 because there
12307          * are no pull-up resistors on unused GPIO pins.
12308          */
12309         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
12310                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
12311
12312         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
12313                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12314
12315         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761) {
12316                 /* Turn off the debug UART. */
12317                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12318                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
12319                         /* Keep VMain power. */
12320                         tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
12321                                               GRC_LCLCTRL_GPIO_OUTPUT0;
12322         }
12323
12324         /* Force the chip into D0. */
12325         err = tg3_set_power_state(tp, PCI_D0);
12326         if (err) {
12327                 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
12328                        pci_name(tp->pdev));
12329                 return err;
12330         }
12331
12332         /* 5700 B0 chips do not support checksumming correctly due
12333          * to hardware bugs.
12334          */
12335         if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
12336                 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
12337
12338         /* Derive initial jumbo mode from MTU assigned in
12339          * ether_setup() via the alloc_etherdev() call
12340          */
12341         if (tp->dev->mtu > ETH_DATA_LEN &&
12342             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
12343                 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
12344
12345         /* Determine WakeOnLan speed to use. */
12346         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12347             tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12348             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
12349             tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
12350                 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
12351         } else {
12352                 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
12353         }
12354
12355         /* A few boards don't want Ethernet@WireSpeed phy feature */
12356         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12357             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
12358              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
12359              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
12360             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) ||
12361             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
12362                 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
12363
12364         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
12365             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
12366                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
12367         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
12368                 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
12369
12370         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
12371                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12372                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12373                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12374                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
12375                         if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
12376                             tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
12377                                 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
12378                         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
12379                                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
12380                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906 &&
12381                            GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
12382                         tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
12383         }
12384
12385         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12386             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
12387                 tp->phy_otp = tg3_read_otp_phycfg(tp);
12388                 if (tp->phy_otp == 0)
12389                         tp->phy_otp = TG3_OTP_DEFAULT;
12390         }
12391
12392         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
12393                 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
12394         else
12395                 tp->mi_mode = MAC_MI_MODE_BASE;
12396
12397         tp->coalesce_mode = 0;
12398         if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
12399             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
12400                 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
12401
12402         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12403                 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
12404
12405         err = tg3_mdio_init(tp);
12406         if (err)
12407                 return err;
12408
12409         /* Initialize data/descriptor byte/word swapping. */
12410         val = tr32(GRC_MODE);
12411         val &= GRC_MODE_HOST_STACKUP;
12412         tw32(GRC_MODE, val | tp->grc_mode);
12413
12414         tg3_switch_clocks(tp);
12415
12416         /* Clear this out for sanity. */
12417         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
12418
12419         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12420                               &pci_state_reg);
12421         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
12422             (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
12423                 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
12424
12425                 if (chiprevid == CHIPREV_ID_5701_A0 ||
12426                     chiprevid == CHIPREV_ID_5701_B0 ||
12427                     chiprevid == CHIPREV_ID_5701_B2 ||
12428                     chiprevid == CHIPREV_ID_5701_B5) {
12429                         void __iomem *sram_base;
12430
12431                         /* Write some dummy words into the SRAM status block
12432                          * area, see if it reads back correctly.  If the return
12433                          * value is bad, force enable the PCIX workaround.
12434                          */
12435                         sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
12436
12437                         writel(0x00000000, sram_base);
12438                         writel(0x00000000, sram_base + 4);
12439                         writel(0xffffffff, sram_base + 4);
12440                         if (readl(sram_base) != 0x00000000)
12441                                 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12442                 }
12443         }
12444
12445         udelay(50);
12446         tg3_nvram_init(tp);
12447
12448         grc_misc_cfg = tr32(GRC_MISC_CFG);
12449         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
12450
12451         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
12452             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
12453              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
12454                 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
12455
12456         if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
12457             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
12458                 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
12459         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
12460                 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
12461                                       HOSTCC_MODE_CLRTICK_TXBD);
12462
12463                 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
12464                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12465                                        tp->misc_host_ctrl);
12466         }
12467
12468         /* Preserve the APE MAC_MODE bits */
12469         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
12470                 tp->mac_mode = tr32(MAC_MODE) |
12471                                MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
12472         else
12473                 tp->mac_mode = TG3_DEF_MAC_MODE;
12474
12475         /* these are limited to 10/100 only */
12476         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12477              (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
12478             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
12479              tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
12480              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
12481               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
12482               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
12483             (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
12484              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
12485               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
12486               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
12487             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12488                 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
12489
12490         err = tg3_phy_probe(tp);
12491         if (err) {
12492                 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
12493                        pci_name(tp->pdev), err);
12494                 /* ... but do not return immediately ... */
12495                 tg3_mdio_fini(tp);
12496         }
12497
12498         tg3_read_partno(tp);
12499         tg3_read_fw_ver(tp);
12500
12501         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
12502                 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
12503         } else {
12504                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
12505                         tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
12506                 else
12507                         tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
12508         }
12509
12510         /* 5700 {AX,BX} chips have a broken status block link
12511          * change bit implementation, so we must use the
12512          * status register in those cases.
12513          */
12514         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
12515                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
12516         else
12517                 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
12518
12519         /* The led_ctrl is set during tg3_phy_probe, here we might
12520          * have to force the link status polling mechanism based
12521          * upon subsystem IDs.
12522          */
12523         if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
12524             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
12525             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
12526                 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
12527                                   TG3_FLAG_USE_LINKCHG_REG);
12528         }
12529
12530         /* For all SERDES we poll the MAC status register. */
12531         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
12532                 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
12533         else
12534                 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
12535
12536         /* All chips before 5787 can get confused if TX buffers
12537          * straddle the 4GB address boundary in some cases.
12538          */
12539         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12540             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12541             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12542             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12543             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12544             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12545                 tp->dev->hard_start_xmit = tg3_start_xmit;
12546         else
12547                 tp->dev->hard_start_xmit = tg3_start_xmit_dma_bug;
12548
12549         tp->rx_offset = 2;
12550         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
12551             (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
12552                 tp->rx_offset = 0;
12553
12554         tp->rx_std_max_post = TG3_RX_RING_SIZE;
12555
12556         /* Increment the rx prod index on the rx std ring by at most
12557          * 8 for these chips to workaround hw errata.
12558          */
12559         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12560             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
12561             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
12562                 tp->rx_std_max_post = 8;
12563
12564         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
12565                 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
12566                                      PCIE_PWR_MGMT_L1_THRESH_MSK;
12567
12568         return err;
12569 }
12570
12571 #ifdef CONFIG_SPARC
12572 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
12573 {
12574         struct net_device *dev = tp->dev;
12575         struct pci_dev *pdev = tp->pdev;
12576         struct device_node *dp = pci_device_to_OF_node(pdev);
12577         const unsigned char *addr;
12578         int len;
12579
12580         addr = of_get_property(dp, "local-mac-address", &len);
12581         if (addr && len == 6) {
12582                 memcpy(dev->dev_addr, addr, 6);
12583                 memcpy(dev->perm_addr, dev->dev_addr, 6);
12584                 return 0;
12585         }
12586         return -ENODEV;
12587 }
12588
12589 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
12590 {
12591         struct net_device *dev = tp->dev;
12592
12593         memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
12594         memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
12595         return 0;
12596 }
12597 #endif
12598
12599 static int __devinit tg3_get_device_address(struct tg3 *tp)
12600 {
12601         struct net_device *dev = tp->dev;
12602         u32 hi, lo, mac_offset;
12603         int addr_ok = 0;
12604
12605 #ifdef CONFIG_SPARC
12606         if (!tg3_get_macaddr_sparc(tp))
12607                 return 0;
12608 #endif
12609
12610         mac_offset = 0x7c;
12611         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
12612             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
12613                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
12614                         mac_offset = 0xcc;
12615                 if (tg3_nvram_lock(tp))
12616                         tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
12617                 else
12618                         tg3_nvram_unlock(tp);
12619         }
12620         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12621                 mac_offset = 0x10;
12622
12623         /* First try to get it from MAC address mailbox. */
12624         tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
12625         if ((hi >> 16) == 0x484b) {
12626                 dev->dev_addr[0] = (hi >>  8) & 0xff;
12627                 dev->dev_addr[1] = (hi >>  0) & 0xff;
12628
12629                 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
12630                 dev->dev_addr[2] = (lo >> 24) & 0xff;
12631                 dev->dev_addr[3] = (lo >> 16) & 0xff;
12632                 dev->dev_addr[4] = (lo >>  8) & 0xff;
12633                 dev->dev_addr[5] = (lo >>  0) & 0xff;
12634
12635                 /* Some old bootcode may report a 0 MAC address in SRAM */
12636                 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
12637         }
12638         if (!addr_ok) {
12639                 /* Next, try NVRAM. */
12640                 if (!tg3_nvram_read(tp, mac_offset + 0, &hi) &&
12641                     !tg3_nvram_read(tp, mac_offset + 4, &lo)) {
12642                         dev->dev_addr[0] = ((hi >> 16) & 0xff);
12643                         dev->dev_addr[1] = ((hi >> 24) & 0xff);
12644                         dev->dev_addr[2] = ((lo >>  0) & 0xff);
12645                         dev->dev_addr[3] = ((lo >>  8) & 0xff);
12646                         dev->dev_addr[4] = ((lo >> 16) & 0xff);
12647                         dev->dev_addr[5] = ((lo >> 24) & 0xff);
12648                 }
12649                 /* Finally just fetch it out of the MAC control regs. */
12650                 else {
12651                         hi = tr32(MAC_ADDR_0_HIGH);
12652                         lo = tr32(MAC_ADDR_0_LOW);
12653
12654                         dev->dev_addr[5] = lo & 0xff;
12655                         dev->dev_addr[4] = (lo >> 8) & 0xff;
12656                         dev->dev_addr[3] = (lo >> 16) & 0xff;
12657                         dev->dev_addr[2] = (lo >> 24) & 0xff;
12658                         dev->dev_addr[1] = hi & 0xff;
12659                         dev->dev_addr[0] = (hi >> 8) & 0xff;
12660                 }
12661         }
12662
12663         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
12664 #ifdef CONFIG_SPARC
12665                 if (!tg3_get_default_macaddr_sparc(tp))
12666                         return 0;
12667 #endif
12668                 return -EINVAL;
12669         }
12670         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
12671         return 0;
12672 }
12673
12674 #define BOUNDARY_SINGLE_CACHELINE       1
12675 #define BOUNDARY_MULTI_CACHELINE        2
12676
12677 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
12678 {
12679         int cacheline_size;
12680         u8 byte;
12681         int goal;
12682
12683         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
12684         if (byte == 0)
12685                 cacheline_size = 1024;
12686         else
12687                 cacheline_size = (int) byte * 4;
12688
12689         /* On 5703 and later chips, the boundary bits have no
12690          * effect.
12691          */
12692         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12693             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
12694             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12695                 goto out;
12696
12697 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
12698         goal = BOUNDARY_MULTI_CACHELINE;
12699 #else
12700 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
12701         goal = BOUNDARY_SINGLE_CACHELINE;
12702 #else
12703         goal = 0;
12704 #endif
12705 #endif
12706
12707         if (!goal)
12708                 goto out;
12709
12710         /* PCI controllers on most RISC systems tend to disconnect
12711          * when a device tries to burst across a cache-line boundary.
12712          * Therefore, letting tg3 do so just wastes PCI bandwidth.
12713          *
12714          * Unfortunately, for PCI-E there are only limited
12715          * write-side controls for this, and thus for reads
12716          * we will still get the disconnects.  We'll also waste
12717          * these PCI cycles for both read and write for chips
12718          * other than 5700 and 5701 which do not implement the
12719          * boundary bits.
12720          */
12721         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12722             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
12723                 switch (cacheline_size) {
12724                 case 16:
12725                 case 32:
12726                 case 64:
12727                 case 128:
12728                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
12729                                 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
12730                                         DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
12731                         } else {
12732                                 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
12733                                         DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
12734                         }
12735                         break;
12736
12737                 case 256:
12738                         val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
12739                                 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
12740                         break;
12741
12742                 default:
12743                         val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
12744                                 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
12745                         break;
12746                 }
12747         } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12748                 switch (cacheline_size) {
12749                 case 16:
12750                 case 32:
12751                 case 64:
12752                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
12753                                 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
12754                                 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
12755                                 break;
12756                         }
12757                         /* fallthrough */
12758                 case 128:
12759                 default:
12760                         val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
12761                         val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
12762                         break;
12763                 }
12764         } else {
12765                 switch (cacheline_size) {
12766                 case 16:
12767                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
12768                                 val |= (DMA_RWCTRL_READ_BNDRY_16 |
12769                                         DMA_RWCTRL_WRITE_BNDRY_16);
12770                                 break;
12771                         }
12772                         /* fallthrough */
12773                 case 32:
12774                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
12775                                 val |= (DMA_RWCTRL_READ_BNDRY_32 |
12776                                         DMA_RWCTRL_WRITE_BNDRY_32);
12777                                 break;
12778                         }
12779                         /* fallthrough */
12780                 case 64:
12781                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
12782                                 val |= (DMA_RWCTRL_READ_BNDRY_64 |
12783                                         DMA_RWCTRL_WRITE_BNDRY_64);
12784                                 break;
12785                         }
12786                         /* fallthrough */
12787                 case 128:
12788                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
12789                                 val |= (DMA_RWCTRL_READ_BNDRY_128 |
12790                                         DMA_RWCTRL_WRITE_BNDRY_128);
12791                                 break;
12792                         }
12793                         /* fallthrough */
12794                 case 256:
12795                         val |= (DMA_RWCTRL_READ_BNDRY_256 |
12796                                 DMA_RWCTRL_WRITE_BNDRY_256);
12797                         break;
12798                 case 512:
12799                         val |= (DMA_RWCTRL_READ_BNDRY_512 |
12800                                 DMA_RWCTRL_WRITE_BNDRY_512);
12801                         break;
12802                 case 1024:
12803                 default:
12804                         val |= (DMA_RWCTRL_READ_BNDRY_1024 |
12805                                 DMA_RWCTRL_WRITE_BNDRY_1024);
12806                         break;
12807                 }
12808         }
12809
12810 out:
12811         return val;
12812 }
12813
12814 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
12815 {
12816         struct tg3_internal_buffer_desc test_desc;
12817         u32 sram_dma_descs;
12818         int i, ret;
12819
12820         sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
12821
12822         tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
12823         tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
12824         tw32(RDMAC_STATUS, 0);
12825         tw32(WDMAC_STATUS, 0);
12826
12827         tw32(BUFMGR_MODE, 0);
12828         tw32(FTQ_RESET, 0);
12829
12830         test_desc.addr_hi = ((u64) buf_dma) >> 32;
12831         test_desc.addr_lo = buf_dma & 0xffffffff;
12832         test_desc.nic_mbuf = 0x00002100;
12833         test_desc.len = size;
12834
12835         /*
12836          * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
12837          * the *second* time the tg3 driver was getting loaded after an
12838          * initial scan.
12839          *
12840          * Broadcom tells me:
12841          *   ...the DMA engine is connected to the GRC block and a DMA
12842          *   reset may affect the GRC block in some unpredictable way...
12843          *   The behavior of resets to individual blocks has not been tested.
12844          *
12845          * Broadcom noted the GRC reset will also reset all sub-components.
12846          */
12847         if (to_device) {
12848                 test_desc.cqid_sqid = (13 << 8) | 2;
12849
12850                 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
12851                 udelay(40);
12852         } else {
12853                 test_desc.cqid_sqid = (16 << 8) | 7;
12854
12855                 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
12856                 udelay(40);
12857         }
12858         test_desc.flags = 0x00000005;
12859
12860         for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
12861                 u32 val;
12862
12863                 val = *(((u32 *)&test_desc) + i);
12864                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
12865                                        sram_dma_descs + (i * sizeof(u32)));
12866                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
12867         }
12868         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
12869
12870         if (to_device) {
12871                 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
12872         } else {
12873                 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
12874         }
12875
12876         ret = -ENODEV;
12877         for (i = 0; i < 40; i++) {
12878                 u32 val;
12879
12880                 if (to_device)
12881                         val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
12882                 else
12883                         val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
12884                 if ((val & 0xffff) == sram_dma_descs) {
12885                         ret = 0;
12886                         break;
12887                 }
12888
12889                 udelay(100);
12890         }
12891
12892         return ret;
12893 }
12894
12895 #define TEST_BUFFER_SIZE        0x2000
12896
12897 static int __devinit tg3_test_dma(struct tg3 *tp)
12898 {
12899         dma_addr_t buf_dma;
12900         u32 *buf, saved_dma_rwctrl;
12901         int ret;
12902
12903         buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
12904         if (!buf) {
12905                 ret = -ENOMEM;
12906                 goto out_nofree;
12907         }
12908
12909         tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
12910                           (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
12911
12912         tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
12913
12914         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12915                 /* DMA read watermark not used on PCIE */
12916                 tp->dma_rwctrl |= 0x00180000;
12917         } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
12918                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
12919                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
12920                         tp->dma_rwctrl |= 0x003f0000;
12921                 else
12922                         tp->dma_rwctrl |= 0x003f000f;
12923         } else {
12924                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
12925                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
12926                         u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
12927                         u32 read_water = 0x7;
12928
12929                         /* If the 5704 is behind the EPB bridge, we can
12930                          * do the less restrictive ONE_DMA workaround for
12931                          * better performance.
12932                          */
12933                         if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
12934                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
12935                                 tp->dma_rwctrl |= 0x8000;
12936                         else if (ccval == 0x6 || ccval == 0x7)
12937                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
12938
12939                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
12940                                 read_water = 4;
12941                         /* Set bit 23 to enable PCIX hw bug fix */
12942                         tp->dma_rwctrl |=
12943                                 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
12944                                 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
12945                                 (1 << 23);
12946                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
12947                         /* 5780 always in PCIX mode */
12948                         tp->dma_rwctrl |= 0x00144000;
12949                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12950                         /* 5714 always in PCIX mode */
12951                         tp->dma_rwctrl |= 0x00148000;
12952                 } else {
12953                         tp->dma_rwctrl |= 0x001b000f;
12954                 }
12955         }
12956
12957         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
12958             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
12959                 tp->dma_rwctrl &= 0xfffffff0;
12960
12961         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12962             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
12963                 /* Remove this if it causes problems for some boards. */
12964                 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
12965
12966                 /* On 5700/5701 chips, we need to set this bit.
12967                  * Otherwise the chip will issue cacheline transactions
12968                  * to streamable DMA memory with not all the byte
12969                  * enables turned on.  This is an error on several
12970                  * RISC PCI controllers, in particular sparc64.
12971                  *
12972                  * On 5703/5704 chips, this bit has been reassigned
12973                  * a different meaning.  In particular, it is used
12974                  * on those chips to enable a PCI-X workaround.
12975                  */
12976                 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
12977         }
12978
12979         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12980
12981 #if 0
12982         /* Unneeded, already done by tg3_get_invariants.  */
12983         tg3_switch_clocks(tp);
12984 #endif
12985
12986         ret = 0;
12987         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12988             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
12989                 goto out;
12990
12991         /* It is best to perform DMA test with maximum write burst size
12992          * to expose the 5700/5701 write DMA bug.
12993          */
12994         saved_dma_rwctrl = tp->dma_rwctrl;
12995         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
12996         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12997
12998         while (1) {
12999                 u32 *p = buf, i;
13000
13001                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
13002                         p[i] = i;
13003
13004                 /* Send the buffer to the chip. */
13005                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
13006                 if (ret) {
13007                         printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
13008                         break;
13009                 }
13010
13011 #if 0
13012                 /* validate data reached card RAM correctly. */
13013                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13014                         u32 val;
13015                         tg3_read_mem(tp, 0x2100 + (i*4), &val);
13016                         if (le32_to_cpu(val) != p[i]) {
13017                                 printk(KERN_ERR "  tg3_test_dma()  Card buffer corrupted on write! (%d != %d)\n", val, i);
13018                                 /* ret = -ENODEV here? */
13019                         }
13020                         p[i] = 0;
13021                 }
13022 #endif
13023                 /* Now read it back. */
13024                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
13025                 if (ret) {
13026                         printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
13027
13028                         break;
13029                 }
13030
13031                 /* Verify it. */
13032                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13033                         if (p[i] == i)
13034                                 continue;
13035
13036                         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13037                             DMA_RWCTRL_WRITE_BNDRY_16) {
13038                                 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13039                                 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13040                                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13041                                 break;
13042                         } else {
13043                                 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
13044                                 ret = -ENODEV;
13045                                 goto out;
13046                         }
13047                 }
13048
13049                 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
13050                         /* Success. */
13051                         ret = 0;
13052                         break;
13053                 }
13054         }
13055         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13056             DMA_RWCTRL_WRITE_BNDRY_16) {
13057                 static struct pci_device_id dma_wait_state_chipsets[] = {
13058                         { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
13059                                      PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
13060                         { },
13061                 };
13062
13063                 /* DMA test passed without adjusting DMA boundary,
13064                  * now look for chipsets that are known to expose the
13065                  * DMA bug without failing the test.
13066                  */
13067                 if (pci_dev_present(dma_wait_state_chipsets)) {
13068                         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13069                         tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13070                 }
13071                 else
13072                         /* Safe to use the calculated DMA boundary. */
13073                         tp->dma_rwctrl = saved_dma_rwctrl;
13074
13075                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13076         }
13077
13078 out:
13079         pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
13080 out_nofree:
13081         return ret;
13082 }
13083
13084 static void __devinit tg3_init_link_config(struct tg3 *tp)
13085 {
13086         tp->link_config.advertising =
13087                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
13088                  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
13089                  ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
13090                  ADVERTISED_Autoneg | ADVERTISED_MII);
13091         tp->link_config.speed = SPEED_INVALID;
13092         tp->link_config.duplex = DUPLEX_INVALID;
13093         tp->link_config.autoneg = AUTONEG_ENABLE;
13094         tp->link_config.active_speed = SPEED_INVALID;
13095         tp->link_config.active_duplex = DUPLEX_INVALID;
13096         tp->link_config.phy_is_low_power = 0;
13097         tp->link_config.orig_speed = SPEED_INVALID;
13098         tp->link_config.orig_duplex = DUPLEX_INVALID;
13099         tp->link_config.orig_autoneg = AUTONEG_INVALID;
13100 }
13101
13102 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
13103 {
13104         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
13105                 tp->bufmgr_config.mbuf_read_dma_low_water =
13106                         DEFAULT_MB_RDMA_LOW_WATER_5705;
13107                 tp->bufmgr_config.mbuf_mac_rx_low_water =
13108                         DEFAULT_MB_MACRX_LOW_WATER_5705;
13109                 tp->bufmgr_config.mbuf_high_water =
13110                         DEFAULT_MB_HIGH_WATER_5705;
13111                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13112                         tp->bufmgr_config.mbuf_mac_rx_low_water =
13113                                 DEFAULT_MB_MACRX_LOW_WATER_5906;
13114                         tp->bufmgr_config.mbuf_high_water =
13115                                 DEFAULT_MB_HIGH_WATER_5906;
13116                 }
13117
13118                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13119                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
13120                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13121                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
13122                 tp->bufmgr_config.mbuf_high_water_jumbo =
13123                         DEFAULT_MB_HIGH_WATER_JUMBO_5780;
13124         } else {
13125                 tp->bufmgr_config.mbuf_read_dma_low_water =
13126                         DEFAULT_MB_RDMA_LOW_WATER;
13127                 tp->bufmgr_config.mbuf_mac_rx_low_water =
13128                         DEFAULT_MB_MACRX_LOW_WATER;
13129                 tp->bufmgr_config.mbuf_high_water =
13130                         DEFAULT_MB_HIGH_WATER;
13131
13132                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13133                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
13134                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13135                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
13136                 tp->bufmgr_config.mbuf_high_water_jumbo =
13137                         DEFAULT_MB_HIGH_WATER_JUMBO;
13138         }
13139
13140         tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
13141         tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
13142 }
13143
13144 static char * __devinit tg3_phy_string(struct tg3 *tp)
13145 {
13146         switch (tp->phy_id & PHY_ID_MASK) {
13147         case PHY_ID_BCM5400:    return "5400";
13148         case PHY_ID_BCM5401:    return "5401";
13149         case PHY_ID_BCM5411:    return "5411";
13150         case PHY_ID_BCM5701:    return "5701";
13151         case PHY_ID_BCM5703:    return "5703";
13152         case PHY_ID_BCM5704:    return "5704";
13153         case PHY_ID_BCM5705:    return "5705";
13154         case PHY_ID_BCM5750:    return "5750";
13155         case PHY_ID_BCM5752:    return "5752";
13156         case PHY_ID_BCM5714:    return "5714";
13157         case PHY_ID_BCM5780:    return "5780";
13158         case PHY_ID_BCM5755:    return "5755";
13159         case PHY_ID_BCM5787:    return "5787";
13160         case PHY_ID_BCM5784:    return "5784";
13161         case PHY_ID_BCM5756:    return "5722/5756";
13162         case PHY_ID_BCM5906:    return "5906";
13163         case PHY_ID_BCM5761:    return "5761";
13164         case PHY_ID_BCM8002:    return "8002/serdes";
13165         case 0:                 return "serdes";
13166         default:                return "unknown";
13167         }
13168 }
13169
13170 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
13171 {
13172         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13173                 strcpy(str, "PCI Express");
13174                 return str;
13175         } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13176                 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
13177
13178                 strcpy(str, "PCIX:");
13179
13180                 if ((clock_ctrl == 7) ||
13181                     ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
13182                      GRC_MISC_CFG_BOARD_ID_5704CIOBE))
13183                         strcat(str, "133MHz");
13184                 else if (clock_ctrl == 0)
13185                         strcat(str, "33MHz");
13186                 else if (clock_ctrl == 2)
13187                         strcat(str, "50MHz");
13188                 else if (clock_ctrl == 4)
13189                         strcat(str, "66MHz");
13190                 else if (clock_ctrl == 6)
13191                         strcat(str, "100MHz");
13192         } else {
13193                 strcpy(str, "PCI:");
13194                 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
13195                         strcat(str, "66MHz");
13196                 else
13197                         strcat(str, "33MHz");
13198         }
13199         if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
13200                 strcat(str, ":32-bit");
13201         else
13202                 strcat(str, ":64-bit");
13203         return str;
13204 }
13205
13206 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
13207 {
13208         struct pci_dev *peer;
13209         unsigned int func, devnr = tp->pdev->devfn & ~7;
13210
13211         for (func = 0; func < 8; func++) {
13212                 peer = pci_get_slot(tp->pdev->bus, devnr | func);
13213                 if (peer && peer != tp->pdev)
13214                         break;
13215                 pci_dev_put(peer);
13216         }
13217         /* 5704 can be configured in single-port mode, set peer to
13218          * tp->pdev in that case.
13219          */
13220         if (!peer) {
13221                 peer = tp->pdev;
13222                 return peer;
13223         }
13224
13225         /*
13226          * We don't need to keep the refcount elevated; there's no way
13227          * to remove one half of this device without removing the other
13228          */
13229         pci_dev_put(peer);
13230
13231         return peer;
13232 }
13233
13234 static void __devinit tg3_init_coal(struct tg3 *tp)
13235 {
13236         struct ethtool_coalesce *ec = &tp->coal;
13237
13238         memset(ec, 0, sizeof(*ec));
13239         ec->cmd = ETHTOOL_GCOALESCE;
13240         ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
13241         ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
13242         ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
13243         ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
13244         ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
13245         ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
13246         ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
13247         ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
13248         ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
13249
13250         if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
13251                                  HOSTCC_MODE_CLRTICK_TXBD)) {
13252                 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
13253                 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
13254                 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
13255                 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
13256         }
13257
13258         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
13259                 ec->rx_coalesce_usecs_irq = 0;
13260                 ec->tx_coalesce_usecs_irq = 0;
13261                 ec->stats_block_coalesce_usecs = 0;
13262         }
13263 }
13264
13265 static int __devinit tg3_init_one(struct pci_dev *pdev,
13266                                   const struct pci_device_id *ent)
13267 {
13268         static int tg3_version_printed = 0;
13269         resource_size_t tg3reg_base;
13270         unsigned long tg3reg_len;
13271         struct net_device *dev;
13272         struct tg3 *tp;
13273         int err, pm_cap;
13274         char str[40];
13275         u64 dma_mask, persist_dma_mask;
13276         DECLARE_MAC_BUF(mac);
13277
13278         if (tg3_version_printed++ == 0)
13279                 printk(KERN_INFO "%s", version);
13280
13281         err = pci_enable_device(pdev);
13282         if (err) {
13283                 printk(KERN_ERR PFX "Cannot enable PCI device, "
13284                        "aborting.\n");
13285                 return err;
13286         }
13287
13288         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
13289                 printk(KERN_ERR PFX "Cannot find proper PCI device "
13290                        "base address, aborting.\n");
13291                 err = -ENODEV;
13292                 goto err_out_disable_pdev;
13293         }
13294
13295         err = pci_request_regions(pdev, DRV_MODULE_NAME);
13296         if (err) {
13297                 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
13298                        "aborting.\n");
13299                 goto err_out_disable_pdev;
13300         }
13301
13302         pci_set_master(pdev);
13303
13304         /* Find power-management capability. */
13305         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
13306         if (pm_cap == 0) {
13307                 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
13308                        "aborting.\n");
13309                 err = -EIO;
13310                 goto err_out_free_res;
13311         }
13312
13313         tg3reg_base = pci_resource_start(pdev, 0);
13314         tg3reg_len = pci_resource_len(pdev, 0);
13315
13316         dev = alloc_etherdev(sizeof(*tp));
13317         if (!dev) {
13318                 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
13319                 err = -ENOMEM;
13320                 goto err_out_free_res;
13321         }
13322
13323         SET_NETDEV_DEV(dev, &pdev->dev);
13324
13325 #if TG3_VLAN_TAG_USED
13326         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
13327         dev->vlan_rx_register = tg3_vlan_rx_register;
13328 #endif
13329
13330         tp = netdev_priv(dev);
13331         tp->pdev = pdev;
13332         tp->dev = dev;
13333         tp->pm_cap = pm_cap;
13334         tp->rx_mode = TG3_DEF_RX_MODE;
13335         tp->tx_mode = TG3_DEF_TX_MODE;
13336
13337         if (tg3_debug > 0)
13338                 tp->msg_enable = tg3_debug;
13339         else
13340                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
13341
13342         /* The word/byte swap controls here control register access byte
13343          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
13344          * setting below.
13345          */
13346         tp->misc_host_ctrl =
13347                 MISC_HOST_CTRL_MASK_PCI_INT |
13348                 MISC_HOST_CTRL_WORD_SWAP |
13349                 MISC_HOST_CTRL_INDIR_ACCESS |
13350                 MISC_HOST_CTRL_PCISTATE_RW;
13351
13352         /* The NONFRM (non-frame) byte/word swap controls take effect
13353          * on descriptor entries, anything which isn't packet data.
13354          *
13355          * The StrongARM chips on the board (one for tx, one for rx)
13356          * are running in big-endian mode.
13357          */
13358         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
13359                         GRC_MODE_WSWAP_NONFRM_DATA);
13360 #ifdef __BIG_ENDIAN
13361         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
13362 #endif
13363         spin_lock_init(&tp->lock);
13364         spin_lock_init(&tp->indirect_lock);
13365         INIT_WORK(&tp->reset_task, tg3_reset_task);
13366
13367         tp->regs = ioremap_nocache(tg3reg_base, tg3reg_len);
13368         if (!tp->regs) {
13369                 printk(KERN_ERR PFX "Cannot map device registers, "
13370                        "aborting.\n");
13371                 err = -ENOMEM;
13372                 goto err_out_free_dev;
13373         }
13374
13375         tg3_init_link_config(tp);
13376
13377         tp->rx_pending = TG3_DEF_RX_RING_PENDING;
13378         tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
13379         tp->tx_pending = TG3_DEF_TX_RING_PENDING;
13380
13381         dev->open = tg3_open;
13382         dev->stop = tg3_close;
13383         dev->get_stats = tg3_get_stats;
13384         dev->set_multicast_list = tg3_set_rx_mode;
13385         dev->set_mac_address = tg3_set_mac_addr;
13386         dev->do_ioctl = tg3_ioctl;
13387         dev->tx_timeout = tg3_tx_timeout;
13388         netif_napi_add(dev, &tp->napi, tg3_poll, 64);
13389         dev->ethtool_ops = &tg3_ethtool_ops;
13390         dev->watchdog_timeo = TG3_TX_TIMEOUT;
13391         dev->change_mtu = tg3_change_mtu;
13392         dev->irq = pdev->irq;
13393 #ifdef CONFIG_NET_POLL_CONTROLLER
13394         dev->poll_controller = tg3_poll_controller;
13395 #endif
13396
13397         err = tg3_get_invariants(tp);
13398         if (err) {
13399                 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
13400                        "aborting.\n");
13401                 goto err_out_iounmap;
13402         }
13403
13404         /* The EPB bridge inside 5714, 5715, and 5780 and any
13405          * device behind the EPB cannot support DMA addresses > 40-bit.
13406          * On 64-bit systems with IOMMU, use 40-bit dma_mask.
13407          * On 64-bit systems without IOMMU, use 64-bit dma_mask and
13408          * do DMA address check in tg3_start_xmit().
13409          */
13410         if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
13411                 persist_dma_mask = dma_mask = DMA_32BIT_MASK;
13412         else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
13413                 persist_dma_mask = dma_mask = DMA_40BIT_MASK;
13414 #ifdef CONFIG_HIGHMEM
13415                 dma_mask = DMA_64BIT_MASK;
13416 #endif
13417         } else
13418                 persist_dma_mask = dma_mask = DMA_64BIT_MASK;
13419
13420         /* Configure DMA attributes. */
13421         if (dma_mask > DMA_32BIT_MASK) {
13422                 err = pci_set_dma_mask(pdev, dma_mask);
13423                 if (!err) {
13424                         dev->features |= NETIF_F_HIGHDMA;
13425                         err = pci_set_consistent_dma_mask(pdev,
13426                                                           persist_dma_mask);
13427                         if (err < 0) {
13428                                 printk(KERN_ERR PFX "Unable to obtain 64 bit "
13429                                        "DMA for consistent allocations\n");
13430                                 goto err_out_iounmap;
13431                         }
13432                 }
13433         }
13434         if (err || dma_mask == DMA_32BIT_MASK) {
13435                 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
13436                 if (err) {
13437                         printk(KERN_ERR PFX "No usable DMA configuration, "
13438                                "aborting.\n");
13439                         goto err_out_iounmap;
13440                 }
13441         }
13442
13443         tg3_init_bufmgr_config(tp);
13444
13445         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
13446                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
13447         }
13448         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13449             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13450             tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
13451             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
13452             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
13453                 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
13454         } else {
13455                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG;
13456         }
13457
13458         /* TSO is on by default on chips that support hardware TSO.
13459          * Firmware TSO on older chips gives lower performance, so it
13460          * is off by default, but can be enabled using ethtool.
13461          */
13462         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
13463                 dev->features |= NETIF_F_TSO;
13464                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
13465                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906))
13466                         dev->features |= NETIF_F_TSO6;
13467                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13468                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13469                      GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
13470                         GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
13471                         dev->features |= NETIF_F_TSO_ECN;
13472         }
13473
13474
13475         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
13476             !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
13477             !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
13478                 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
13479                 tp->rx_pending = 63;
13480         }
13481
13482         err = tg3_get_device_address(tp);
13483         if (err) {
13484                 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
13485                        "aborting.\n");
13486                 goto err_out_iounmap;
13487         }
13488
13489         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13490                 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
13491                         printk(KERN_ERR PFX "Cannot find proper PCI device "
13492                                "base address for APE, aborting.\n");
13493                         err = -ENODEV;
13494                         goto err_out_iounmap;
13495                 }
13496
13497                 tg3reg_base = pci_resource_start(pdev, 2);
13498                 tg3reg_len = pci_resource_len(pdev, 2);
13499
13500                 tp->aperegs = ioremap_nocache(tg3reg_base, tg3reg_len);
13501                 if (!tp->aperegs) {
13502                         printk(KERN_ERR PFX "Cannot map APE registers, "
13503                                "aborting.\n");
13504                         err = -ENOMEM;
13505                         goto err_out_iounmap;
13506                 }
13507
13508                 tg3_ape_lock_init(tp);
13509         }
13510
13511         /*
13512          * Reset chip in case UNDI or EFI driver did not shutdown
13513          * DMA self test will enable WDMAC and we'll see (spurious)
13514          * pending DMA on the PCI bus at that point.
13515          */
13516         if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
13517             (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
13518                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
13519                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
13520         }
13521
13522         err = tg3_test_dma(tp);
13523         if (err) {
13524                 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
13525                 goto err_out_apeunmap;
13526         }
13527
13528         /* Tigon3 can do ipv4 only... and some chips have buggy
13529          * checksumming.
13530          */
13531         if ((tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) == 0) {
13532                 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
13533                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13534                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13535                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13536                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13537                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
13538                         dev->features |= NETIF_F_IPV6_CSUM;
13539
13540                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
13541         } else
13542                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
13543
13544         /* flow control autonegotiation is default behavior */
13545         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
13546         tp->link_config.flowctrl = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
13547
13548         tg3_init_coal(tp);
13549
13550         pci_set_drvdata(pdev, dev);
13551
13552         err = register_netdev(dev);
13553         if (err) {
13554                 printk(KERN_ERR PFX "Cannot register net device, "
13555                        "aborting.\n");
13556                 goto err_out_apeunmap;
13557         }
13558
13559         printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x PHY(%s)] "
13560                "(%s) %s Ethernet %s\n",
13561                dev->name,
13562                tp->board_part_number,
13563                tp->pci_chip_rev_id,
13564                tg3_phy_string(tp),
13565                tg3_bus_string(tp, str),
13566                ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
13567                 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
13568                  "10/100/1000Base-T")),
13569                print_mac(mac, dev->dev_addr));
13570
13571         printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] "
13572                "MIirq[%d] ASF[%d] WireSpeed[%d] TSOcap[%d]\n",
13573                dev->name,
13574                (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
13575                (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
13576                (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
13577                (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
13578                (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0,
13579                (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
13580         printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
13581                dev->name, tp->dma_rwctrl,
13582                (pdev->dma_mask == DMA_32BIT_MASK) ? 32 :
13583                 (((u64) pdev->dma_mask == DMA_40BIT_MASK) ? 40 : 64));
13584
13585         return 0;
13586
13587 err_out_apeunmap:
13588         if (tp->aperegs) {
13589                 iounmap(tp->aperegs);
13590                 tp->aperegs = NULL;
13591         }
13592
13593 err_out_iounmap:
13594         if (tp->regs) {
13595                 iounmap(tp->regs);
13596                 tp->regs = NULL;
13597         }
13598
13599 err_out_free_dev:
13600         free_netdev(dev);
13601
13602 err_out_free_res:
13603         pci_release_regions(pdev);
13604
13605 err_out_disable_pdev:
13606         pci_disable_device(pdev);
13607         pci_set_drvdata(pdev, NULL);
13608         return err;
13609 }
13610
13611 static void __devexit tg3_remove_one(struct pci_dev *pdev)
13612 {
13613         struct net_device *dev = pci_get_drvdata(pdev);
13614
13615         if (dev) {
13616                 struct tg3 *tp = netdev_priv(dev);
13617
13618                 flush_scheduled_work();
13619
13620                 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
13621                         tg3_phy_fini(tp);
13622                         tg3_mdio_fini(tp);
13623                 }
13624
13625                 unregister_netdev(dev);
13626                 if (tp->aperegs) {
13627                         iounmap(tp->aperegs);
13628                         tp->aperegs = NULL;
13629                 }
13630                 if (tp->regs) {
13631                         iounmap(tp->regs);
13632                         tp->regs = NULL;
13633                 }
13634                 free_netdev(dev);
13635                 pci_release_regions(pdev);
13636                 pci_disable_device(pdev);
13637                 pci_set_drvdata(pdev, NULL);
13638         }
13639 }
13640
13641 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
13642 {
13643         struct net_device *dev = pci_get_drvdata(pdev);
13644         struct tg3 *tp = netdev_priv(dev);
13645         pci_power_t target_state;
13646         int err;
13647
13648         /* PCI register 4 needs to be saved whether netif_running() or not.
13649          * MSI address and data need to be saved if using MSI and
13650          * netif_running().
13651          */
13652         pci_save_state(pdev);
13653
13654         if (!netif_running(dev))
13655                 return 0;
13656
13657         flush_scheduled_work();
13658         tg3_phy_stop(tp);
13659         tg3_netif_stop(tp);
13660
13661         del_timer_sync(&tp->timer);
13662
13663         tg3_full_lock(tp, 1);
13664         tg3_disable_ints(tp);
13665         tg3_full_unlock(tp);
13666
13667         netif_device_detach(dev);
13668
13669         tg3_full_lock(tp, 0);
13670         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
13671         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
13672         tg3_full_unlock(tp);
13673
13674         target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
13675
13676         err = tg3_set_power_state(tp, target_state);
13677         if (err) {
13678                 int err2;
13679
13680                 tg3_full_lock(tp, 0);
13681
13682                 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
13683                 err2 = tg3_restart_hw(tp, 1);
13684                 if (err2)
13685                         goto out;
13686
13687                 tp->timer.expires = jiffies + tp->timer_offset;
13688                 add_timer(&tp->timer);
13689
13690                 netif_device_attach(dev);
13691                 tg3_netif_start(tp);
13692
13693 out:
13694                 tg3_full_unlock(tp);
13695
13696                 if (!err2)
13697                         tg3_phy_start(tp);
13698         }
13699
13700         return err;
13701 }
13702
13703 static int tg3_resume(struct pci_dev *pdev)
13704 {
13705         struct net_device *dev = pci_get_drvdata(pdev);
13706         struct tg3 *tp = netdev_priv(dev);
13707         int err;
13708
13709         pci_restore_state(tp->pdev);
13710
13711         if (!netif_running(dev))
13712                 return 0;
13713
13714         err = tg3_set_power_state(tp, PCI_D0);
13715         if (err)
13716                 return err;
13717
13718         netif_device_attach(dev);
13719
13720         tg3_full_lock(tp, 0);
13721
13722         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
13723         err = tg3_restart_hw(tp, 1);
13724         if (err)
13725                 goto out;
13726
13727         tp->timer.expires = jiffies + tp->timer_offset;
13728         add_timer(&tp->timer);
13729
13730         tg3_netif_start(tp);
13731
13732 out:
13733         tg3_full_unlock(tp);
13734
13735         if (!err)
13736                 tg3_phy_start(tp);
13737
13738         return err;
13739 }
13740
13741 static struct pci_driver tg3_driver = {
13742         .name           = DRV_MODULE_NAME,
13743         .id_table       = tg3_pci_tbl,
13744         .probe          = tg3_init_one,
13745         .remove         = __devexit_p(tg3_remove_one),
13746         .suspend        = tg3_suspend,
13747         .resume         = tg3_resume
13748 };
13749
13750 static int __init tg3_init(void)
13751 {
13752         return pci_register_driver(&tg3_driver);
13753 }
13754
13755 static void __exit tg3_cleanup(void)
13756 {
13757         pci_unregister_driver(&tg3_driver);
13758 }
13759
13760 module_init(tg3_init);
13761 module_exit(tg3_cleanup);