Merge branch 'bugzilla-9761' into release
[linux-2.6] / arch / powerpc / boot / dts / mpc8572ds.dts
1 /*
2  * MPC8572 DS Device Tree Source
3  *
4  * Copyright 2007, 2008 Freescale Semiconductor Inc.
5  *
6  * This program is free software; you can redistribute  it and/or modify it
7  * under  the terms of  the GNU General  Public License as published by the
8  * Free Software Foundation;  either version 2 of the  License, or (at your
9  * option) any later version.
10  */
11
12 /dts-v1/;
13 / {
14         model = "fsl,MPC8572DS";
15         compatible = "fsl,MPC8572DS";
16         #address-cells = <1>;
17         #size-cells = <1>;
18
19         aliases {
20                 ethernet0 = &enet0;
21                 ethernet1 = &enet1;
22                 ethernet2 = &enet2;
23                 ethernet3 = &enet3;
24                 serial0 = &serial0;
25                 serial1 = &serial1;
26                 pci0 = &pci0;
27                 pci1 = &pci1;
28                 pci2 = &pci2;
29         };
30
31         cpus {
32                 #address-cells = <1>;
33                 #size-cells = <0>;
34
35                 PowerPC,8572@0 {
36                         device_type = "cpu";
37                         reg = <0x0>;
38                         d-cache-line-size = <32>;       // 32 bytes
39                         i-cache-line-size = <32>;       // 32 bytes
40                         d-cache-size = <0x8000>;                // L1, 32K
41                         i-cache-size = <0x8000>;                // L1, 32K
42                         timebase-frequency = <0>;
43                         bus-frequency = <0>;
44                         clock-frequency = <0>;
45                 };
46
47                 PowerPC,8572@1 {
48                         device_type = "cpu";
49                         reg = <0x1>;
50                         d-cache-line-size = <32>;       // 32 bytes
51                         i-cache-line-size = <32>;       // 32 bytes
52                         d-cache-size = <0x8000>;                // L1, 32K
53                         i-cache-size = <0x8000>;                // L1, 32K
54                         timebase-frequency = <0>;
55                         bus-frequency = <0>;
56                         clock-frequency = <0>;
57                 };
58         };
59
60         memory {
61                 device_type = "memory";
62                 reg = <0x0 0x0>;        // Filled by U-Boot
63         };
64
65         soc8572@ffe00000 {
66                 #address-cells = <1>;
67                 #size-cells = <1>;
68                 device_type = "soc";
69                 ranges = <0x0 0xffe00000 0x100000>;
70                 reg = <0xffe00000 0x1000>;      // CCSRBAR & soc regs, remove once parse code for immrbase fixed
71                 bus-frequency = <0>;            // Filled out by uboot.
72
73                 memory-controller@2000 {
74                         compatible = "fsl,mpc8572-memory-controller";
75                         reg = <0x2000 0x1000>;
76                         interrupt-parent = <&mpic>;
77                         interrupts = <18 2>;
78                 };
79
80                 memory-controller@6000 {
81                         compatible = "fsl,mpc8572-memory-controller";
82                         reg = <0x6000 0x1000>;
83                         interrupt-parent = <&mpic>;
84                         interrupts = <18 2>;
85                 };
86
87                 l2-cache-controller@20000 {
88                         compatible = "fsl,mpc8572-l2-cache-controller";
89                         reg = <0x20000 0x1000>;
90                         cache-line-size = <32>; // 32 bytes
91                         cache-size = <0x80000>; // L2, 512K
92                         interrupt-parent = <&mpic>;
93                         interrupts = <16 2>;
94                 };
95
96                 i2c@3000 {
97                         #address-cells = <1>;
98                         #size-cells = <0>;
99                         cell-index = <0>;
100                         compatible = "fsl-i2c";
101                         reg = <0x3000 0x100>;
102                         interrupts = <43 2>;
103                         interrupt-parent = <&mpic>;
104                         dfsrr;
105                 };
106
107                 i2c@3100 {
108                         #address-cells = <1>;
109                         #size-cells = <0>;
110                         cell-index = <1>;
111                         compatible = "fsl-i2c";
112                         reg = <0x3100 0x100>;
113                         interrupts = <43 2>;
114                         interrupt-parent = <&mpic>;
115                         dfsrr;
116                 };
117
118                 mdio@24520 {
119                         #address-cells = <1>;
120                         #size-cells = <0>;
121                         compatible = "fsl,gianfar-mdio";
122                         reg = <0x24520 0x20>;
123
124                         phy0: ethernet-phy@0 {
125                                 interrupt-parent = <&mpic>;
126                                 interrupts = <10 1>;
127                                 reg = <0x0>;
128                         };
129                         phy1: ethernet-phy@1 {
130                                 interrupt-parent = <&mpic>;
131                                 interrupts = <10 1>;
132                                 reg = <0x1>;
133                         };
134                         phy2: ethernet-phy@2 {
135                                 interrupt-parent = <&mpic>;
136                                 interrupts = <10 1>;
137                                 reg = <0x2>;
138                         };
139                         phy3: ethernet-phy@3 {
140                                 interrupt-parent = <&mpic>;
141                                 interrupts = <10 1>;
142                                 reg = <0x3>;
143                         };
144                 };
145
146                 enet0: ethernet@24000 {
147                         cell-index = <0>;
148                         device_type = "network";
149                         model = "eTSEC";
150                         compatible = "gianfar";
151                         reg = <0x24000 0x1000>;
152                         local-mac-address = [ 00 00 00 00 00 00 ];
153                         interrupts = <29 2 30 2 34 2>;
154                         interrupt-parent = <&mpic>;
155                         phy-handle = <&phy0>;
156                         phy-connection-type = "rgmii-id";
157                 };
158
159                 enet1: ethernet@25000 {
160                         cell-index = <1>;
161                         device_type = "network";
162                         model = "eTSEC";
163                         compatible = "gianfar";
164                         reg = <0x25000 0x1000>;
165                         local-mac-address = [ 00 00 00 00 00 00 ];
166                         interrupts = <35 2 36 2 40 2>;
167                         interrupt-parent = <&mpic>;
168                         phy-handle = <&phy1>;
169                         phy-connection-type = "rgmii-id";
170                 };
171
172                 enet2: ethernet@26000 {
173                         cell-index = <2>;
174                         device_type = "network";
175                         model = "eTSEC";
176                         compatible = "gianfar";
177                         reg = <0x26000 0x1000>;
178                         local-mac-address = [ 00 00 00 00 00 00 ];
179                         interrupts = <31 2 32 2 33 2>;
180                         interrupt-parent = <&mpic>;
181                         phy-handle = <&phy2>;
182                         phy-connection-type = "rgmii-id";
183                 };
184
185                 enet3: ethernet@27000 {
186                         cell-index = <3>;
187                         device_type = "network";
188                         model = "eTSEC";
189                         compatible = "gianfar";
190                         reg = <0x27000 0x1000>;
191                         local-mac-address = [ 00 00 00 00 00 00 ];
192                         interrupts = <37 2 38 2 39 2>;
193                         interrupt-parent = <&mpic>;
194                         phy-handle = <&phy3>;
195                         phy-connection-type = "rgmii-id";
196                 };
197
198                 serial0: serial@4500 {
199                         cell-index = <0>;
200                         device_type = "serial";
201                         compatible = "ns16550";
202                         reg = <0x4500 0x100>;
203                         clock-frequency = <0>;
204                         interrupts = <42 2>;
205                         interrupt-parent = <&mpic>;
206                 };
207
208                 serial1: serial@4600 {
209                         cell-index = <1>;
210                         device_type = "serial";
211                         compatible = "ns16550";
212                         reg = <0x4600 0x100>;
213                         clock-frequency = <0>;
214                         interrupts = <42 2>;
215                         interrupt-parent = <&mpic>;
216                 };
217
218                 global-utilities@e0000 {        //global utilities block
219                         compatible = "fsl,mpc8572-guts";
220                         reg = <0xe0000 0x1000>;
221                         fsl,has-rstcr;
222                 };
223
224                 mpic: pic@40000 {
225                         clock-frequency = <0>;
226                         interrupt-controller;
227                         #address-cells = <0>;
228                         #interrupt-cells = <2>;
229                         reg = <0x40000 0x40000>;
230                         compatible = "chrp,open-pic";
231                         device_type = "open-pic";
232                         big-endian;
233                 };
234         };
235
236         pci0: pcie@ffe08000 {
237                 cell-index = <0>;
238                 compatible = "fsl,mpc8548-pcie";
239                 device_type = "pci";
240                 #interrupt-cells = <1>;
241                 #size-cells = <2>;
242                 #address-cells = <3>;
243                 reg = <0xffe08000 0x1000>;
244                 bus-range = <0 255>;
245                 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
246                           0x1000000 0x0 0x0 0xffc00000 0x0 0x10000>;
247                 clock-frequency = <33333333>;
248                 interrupt-parent = <&mpic>;
249                 interrupts = <24 2>;
250                 interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
251                 interrupt-map = <
252                         /* IDSEL 0x11 func 0 - PCI slot 1 */
253                         0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
254                         0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
255                         0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
256                         0x8800 0x0 0x0 0x4 &mpic 0x1 0x1
257
258                         /* IDSEL 0x11 func 1 - PCI slot 1 */
259                         0x8900 0x0 0x0 0x1 &mpic 0x2 0x1
260                         0x8900 0x0 0x0 0x2 &mpic 0x3 0x1
261                         0x8900 0x0 0x0 0x3 &mpic 0x4 0x1
262                         0x8900 0x0 0x0 0x4 &mpic 0x1 0x1
263
264                         /* IDSEL 0x11 func 2 - PCI slot 1 */
265                         0x8a00 0x0 0x0 0x1 &mpic 0x2 0x1
266                         0x8a00 0x0 0x0 0x2 &mpic 0x3 0x1
267                         0x8a00 0x0 0x0 0x3 &mpic 0x4 0x1
268                         0x8a00 0x0 0x0 0x4 &mpic 0x1 0x1
269
270                         /* IDSEL 0x11 func 3 - PCI slot 1 */
271                         0x8b00 0x0 0x0 0x1 &mpic 0x2 0x1
272                         0x8b00 0x0 0x0 0x2 &mpic 0x3 0x1
273                         0x8b00 0x0 0x0 0x3 &mpic 0x4 0x1
274                         0x8b00 0x0 0x0 0x4 &mpic 0x1 0x1
275
276                         /* IDSEL 0x11 func 4 - PCI slot 1 */
277                         0x8c00 0x0 0x0 0x1 &mpic 0x2 0x1
278                         0x8c00 0x0 0x0 0x2 &mpic 0x3 0x1
279                         0x8c00 0x0 0x0 0x3 &mpic 0x4 0x1
280                         0x8c00 0x0 0x0 0x4 &mpic 0x1 0x1
281
282                         /* IDSEL 0x11 func 5 - PCI slot 1 */
283                         0x8d00 0x0 0x0 0x1 &mpic 0x2 0x1
284                         0x8d00 0x0 0x0 0x2 &mpic 0x3 0x1
285                         0x8d00 0x0 0x0 0x3 &mpic 0x4 0x1
286                         0x8d00 0x0 0x0 0x4 &mpic 0x1 0x1
287
288                         /* IDSEL 0x11 func 6 - PCI slot 1 */
289                         0x8e00 0x0 0x0 0x1 &mpic 0x2 0x1
290                         0x8e00 0x0 0x0 0x2 &mpic 0x3 0x1
291                         0x8e00 0x0 0x0 0x3 &mpic 0x4 0x1
292                         0x8e00 0x0 0x0 0x4 &mpic 0x1 0x1
293
294                         /* IDSEL 0x11 func 7 - PCI slot 1 */
295                         0x8f00 0x0 0x0 0x1 &mpic 0x2 0x1
296                         0x8f00 0x0 0x0 0x2 &mpic 0x3 0x1
297                         0x8f00 0x0 0x0 0x3 &mpic 0x4 0x1
298                         0x8f00 0x0 0x0 0x4 &mpic 0x1 0x1
299
300                         /* IDSEL 0x12 func 0 - PCI slot 2 */
301                         0x9000 0x0 0x0 0x1 &mpic 0x3 0x1
302                         0x9000 0x0 0x0 0x2 &mpic 0x4 0x1
303                         0x9000 0x0 0x0 0x3 &mpic 0x1 0x1
304                         0x9000 0x0 0x0 0x4 &mpic 0x2 0x1
305
306                         /* IDSEL 0x12 func 1 - PCI slot 2 */
307                         0x9100 0x0 0x0 0x1 &mpic 0x3 0x1
308                         0x9100 0x0 0x0 0x2 &mpic 0x4 0x1
309                         0x9100 0x0 0x0 0x3 &mpic 0x1 0x1
310                         0x9100 0x0 0x0 0x4 &mpic 0x2 0x1
311
312                         /* IDSEL 0x12 func 2 - PCI slot 2 */
313                         0x9200 0x0 0x0 0x1 &mpic 0x3 0x1
314                         0x9200 0x0 0x0 0x2 &mpic 0x4 0x1
315                         0x9200 0x0 0x0 0x3 &mpic 0x1 0x1
316                         0x9200 0x0 0x0 0x4 &mpic 0x2 0x1
317
318                         /* IDSEL 0x12 func 3 - PCI slot 2 */
319                         0x9300 0x0 0x0 0x1 &mpic 0x3 0x1
320                         0x9300 0x0 0x0 0x2 &mpic 0x4 0x1
321                         0x9300 0x0 0x0 0x3 &mpic 0x1 0x1
322                         0x9300 0x0 0x0 0x4 &mpic 0x2 0x1
323
324                         /* IDSEL 0x12 func 4 - PCI slot 2 */
325                         0x9400 0x0 0x0 0x1 &mpic 0x3 0x1
326                         0x9400 0x0 0x0 0x2 &mpic 0x4 0x1
327                         0x9400 0x0 0x0 0x3 &mpic 0x1 0x1
328                         0x9400 0x0 0x0 0x4 &mpic 0x2 0x1
329
330                         /* IDSEL 0x12 func 5 - PCI slot 2 */
331                         0x9500 0x0 0x0 0x1 &mpic 0x3 0x1
332                         0x9500 0x0 0x0 0x2 &mpic 0x4 0x1
333                         0x9500 0x0 0x0 0x3 &mpic 0x1 0x1
334                         0x9500 0x0 0x0 0x4 &mpic 0x2 0x1
335
336                         /* IDSEL 0x12 func 6 - PCI slot 2 */
337                         0x9600 0x0 0x0 0x1 &mpic 0x3 0x1
338                         0x9600 0x0 0x0 0x2 &mpic 0x4 0x1
339                         0x9600 0x0 0x0 0x3 &mpic 0x1 0x1
340                         0x9600 0x0 0x0 0x4 &mpic 0x2 0x1
341
342                         /* IDSEL 0x12 func 7 - PCI slot 2 */
343                         0x9700 0x0 0x0 0x1 &mpic 0x3 0x1
344                         0x9700 0x0 0x0 0x2 &mpic 0x4 0x1
345                         0x9700 0x0 0x0 0x3 &mpic 0x1 0x1
346                         0x9700 0x0 0x0 0x4 &mpic 0x2 0x1
347
348                         // IDSEL 0x1c  USB
349                         0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
350                         0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
351                         0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
352                         0xe300 0x0 0x0 0x4 &i8259 0xb 0x2
353
354                         // IDSEL 0x1d  Audio
355                         0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
356
357                         // IDSEL 0x1e Legacy
358                         0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
359                         0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
360
361                         // IDSEL 0x1f IDE/SATA
362                         0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
363                         0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
364
365                         >;
366
367                 pcie@0 {
368                         reg = <0x0 0x0 0x0 0x0 0x0>;
369                         #size-cells = <2>;
370                         #address-cells = <3>;
371                         device_type = "pci";
372                         ranges = <0x2000000 0x0 0x80000000
373                                   0x2000000 0x0 0x80000000
374                                   0x0 0x20000000
375
376                                   0x1000000 0x0 0x0
377                                   0x1000000 0x0 0x0
378                                   0x0 0x100000>;
379                         uli1575@0 {
380                                 reg = <0x0 0x0 0x0 0x0 0x0>;
381                                 #size-cells = <2>;
382                                 #address-cells = <3>;
383                                 ranges = <0x2000000 0x0 0x80000000
384                                           0x2000000 0x0 0x80000000
385                                           0x0 0x20000000
386
387                                           0x1000000 0x0 0x0
388                                           0x1000000 0x0 0x0
389                                           0x0 0x100000>;
390                                 isa@1e {
391                                         device_type = "isa";
392                                         #interrupt-cells = <2>;
393                                         #size-cells = <1>;
394                                         #address-cells = <2>;
395                                         reg = <0xf000 0x0 0x0 0x0 0x0>;
396                                         ranges = <0x1 0x0 0x1000000 0x0 0x0
397                                                   0x1000>;
398                                         interrupt-parent = <&i8259>;
399
400                                         i8259: interrupt-controller@20 {
401                                                 reg = <0x1 0x20 0x2
402                                                        0x1 0xa0 0x2
403                                                        0x1 0x4d0 0x2>;
404                                                 interrupt-controller;
405                                                 device_type = "interrupt-controller";
406                                                 #address-cells = <0>;
407                                                 #interrupt-cells = <2>;
408                                                 compatible = "chrp,iic";
409                                                 interrupts = <9 2>;
410                                                 interrupt-parent = <&mpic>;
411                                         };
412
413                                         i8042@60 {
414                                                 #size-cells = <0>;
415                                                 #address-cells = <1>;
416                                                 reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
417                                                 interrupts = <1 3 12 3>;
418                                                 interrupt-parent =
419                                                         <&i8259>;
420
421                                                 keyboard@0 {
422                                                         reg = <0x0>;
423                                                         compatible = "pnpPNP,303";
424                                                 };
425
426                                                 mouse@1 {
427                                                         reg = <0x1>;
428                                                         compatible = "pnpPNP,f03";
429                                                 };
430                                         };
431
432                                         rtc@70 {
433                                                 compatible = "pnpPNP,b00";
434                                                 reg = <0x1 0x70 0x2>;
435                                         };
436
437                                         gpio@400 {
438                                                 reg = <0x1 0x400 0x80>;
439                                         };
440                                 };
441                         };
442                 };
443
444         };
445
446         pci1: pcie@ffe09000 {
447                 cell-index = <1>;
448                 compatible = "fsl,mpc8548-pcie";
449                 device_type = "pci";
450                 #interrupt-cells = <1>;
451                 #size-cells = <2>;
452                 #address-cells = <3>;
453                 reg = <0xffe09000 0x1000>;
454                 bus-range = <0 255>;
455                 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
456                           0x1000000 0x0 0x0 0xffc10000 0x0 0x10000>;
457                 clock-frequency = <33333333>;
458                 interrupt-parent = <&mpic>;
459                 interrupts = <26 2>;
460                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
461                 interrupt-map = <
462                         /* IDSEL 0x0 */
463                         0000 0x0 0x0 0x1 &mpic 0x4 0x1
464                         0000 0x0 0x0 0x2 &mpic 0x5 0x1
465                         0000 0x0 0x0 0x3 &mpic 0x6 0x1
466                         0000 0x0 0x0 0x4 &mpic 0x7 0x1
467                         >;
468                 pcie@0 {
469                         reg = <0x0 0x0 0x0 0x0 0x0>;
470                         #size-cells = <2>;
471                         #address-cells = <3>;
472                         device_type = "pci";
473                         ranges = <0x2000000 0x0 0xa0000000
474                                   0x2000000 0x0 0xa0000000
475                                   0x0 0x20000000
476
477                                   0x1000000 0x0 0x0
478                                   0x1000000 0x0 0x0
479                                   0x0 0x100000>;
480                 };
481         };
482
483         pci2: pcie@ffe0a000 {
484                 cell-index = <2>;
485                 compatible = "fsl,mpc8548-pcie";
486                 device_type = "pci";
487                 #interrupt-cells = <1>;
488                 #size-cells = <2>;
489                 #address-cells = <3>;
490                 reg = <0xffe0a000 0x1000>;
491                 bus-range = <0 255>;
492                 ranges = <0x2000000 0x0 0xc0000000 0xc0000000 0x0 0x20000000
493                           0x1000000 0x0 0x0 0xffc20000 0x0 0x10000>;
494                 clock-frequency = <33333333>;
495                 interrupt-parent = <&mpic>;
496                 interrupts = <27 2>;
497                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
498                 interrupt-map = <
499                         /* IDSEL 0x0 */
500                         0000 0x0 0x0 0x1 &mpic 0x0 0x1
501                         0000 0x0 0x0 0x2 &mpic 0x1 0x1
502                         0000 0x0 0x0 0x3 &mpic 0x2 0x1
503                         0000 0x0 0x0 0x4 &mpic 0x3 0x1
504                         >;
505                 pcie@0 {
506                         reg = <0x0 0x0 0x0 0x0 0x0>;
507                         #size-cells = <2>;
508                         #address-cells = <3>;
509                         device_type = "pci";
510                         ranges = <0x2000000 0x0 0xc0000000
511                                   0x2000000 0x0 0xc0000000
512                                   0x0 0x20000000
513
514                                   0x1000000 0x0 0x0
515                                   0x1000000 0x0 0x0
516                                   0x0 0x100000>;
517                 };
518         };
519 };