3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
5 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
6 * Adapted for Power Macintosh by Paul Mackerras.
7 * Low-level exception handlers and MMU support
8 * rewritten by Paul Mackerras.
9 * Copyright (C) 1996 Paul Mackerras.
10 * MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
12 * This file contains the system call entry code, context switch
13 * code, and exception/interrupt return code for PowerPC.
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
21 #include <linux/errno.h>
22 #include <asm/unistd.h>
23 #include <asm/processor.h>
26 #include <asm/thread_info.h>
27 #include <asm/ppc_asm.h>
28 #include <asm/asm-offsets.h>
29 #include <asm/cputable.h>
30 #include <asm/firmware.h>
32 #include <asm/ptrace.h>
33 #include <asm/irqflags.h>
34 #include <asm/ftrace.h>
41 .tc .sys_call_table[TC],.sys_call_table
43 /* This value is used to mark exception frames on the stack. */
45 .tc ID_EXC_MARKER[TC],STACK_FRAME_REGS_MARKER
52 .globl system_call_common
56 addi r1,r1,-INT_FRAME_SIZE
65 ACCOUNT_CPU_USER_ENTRY(r10, r11)
91 addi r9,r1,STACK_FRAME_OVERHEAD
92 ld r11,exception_marker@toc(r2)
93 std r11,-16(r9) /* "regshere" marker */
94 #ifdef CONFIG_TRACE_IRQFLAGS
99 addi r9,r1,STACK_FRAME_OVERHEAD
101 #endif /* CONFIG_TRACE_IRQFLAGS */
103 stb r10,PACASOFTIRQEN(r13)
104 stb r10,PACAHARDIRQEN(r13)
106 #ifdef CONFIG_PPC_ISERIES
108 /* Hack for handling interrupts when soft-enabling on iSeries */
109 cmpdi cr1,r0,0x5555 /* syscall 0x5555 */
110 andi. r10,r12,MSR_PR /* from kernel */
111 crand 4*cr0+eq,4*cr1+eq,4*cr0+eq
113 b hardware_interrupt_entry
115 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
116 #endif /* CONFIG_PPC_ISERIES */
126 addi r9,r1,STACK_FRAME_OVERHEAD
128 clrrdi r11,r1,THREAD_SHIFT
130 andi. r11,r10,_TIF_SYSCALL_T_OR_A
132 syscall_dotrace_cont:
133 cmpldi 0,r0,NR_syscalls
136 system_call: /* label this so stack traces look sane */
138 * Need to vector to 32 Bit or default sys_call_table here,
139 * based on caller's run-mode / personality.
141 ld r11,.SYS_CALL_TABLE@toc(2)
142 andi. r10,r10,_TIF_32BIT
144 addi r11,r11,8 /* use 32-bit syscall entries */
153 ldx r10,r11,r0 /* Fetch system call handler [ptr] */
155 bctrl /* Call handler */
160 bl .do_show_syscall_exit
163 clrrdi r12,r1,THREAD_SHIFT
165 /* disable interrupts so current_thread_info()->flags can't change,
166 and so that we don't get interrupted after loading SRR0/1. */
176 andi. r0,r9,(_TIF_SYSCALL_T_OR_A|_TIF_SINGLESTEP|_TIF_USER_WORK_MASK|_TIF_PERSYSCALL_MASK)
177 bne- syscall_exit_work
183 stdcx. r0,0,r1 /* to clear the reservation */
187 * Clear RI before restoring r13. If we are returning to
188 * userspace and we take an exception after restoring r13,
189 * we end up corrupting the userspace r13 value.
193 mtmsrd r11,1 /* clear MSR.RI */
195 ACCOUNT_CPU_USER_EXIT(r11, r12)
196 ld r13,GPR13(r1) /* only restore r13 if returning to usermode */
204 b . /* prevent speculative execution */
207 oris r5,r5,0x1000 /* Set SO bit in CR */
212 /* Traced system call support */
215 addi r3,r1,STACK_FRAME_OVERHEAD
216 bl .do_syscall_trace_enter
218 * Restore argument registers possibly just changed.
219 * We use the return value of do_syscall_trace_enter
220 * for the call number to look up in the table (r0).
229 addi r9,r1,STACK_FRAME_OVERHEAD
230 clrrdi r10,r1,THREAD_SHIFT
232 b syscall_dotrace_cont
239 /* If TIF_RESTOREALL is set, don't scribble on either r3 or ccr.
240 If TIF_NOERROR is set, just save r3 as it is. */
242 andi. r0,r9,_TIF_RESTOREALL
246 0: cmpld r3,r11 /* r10 is -LAST_ERRNO */
248 andi. r0,r9,_TIF_NOERROR
252 oris r5,r5,0x1000 /* Set SO bit in CR */
255 2: andi. r0,r9,(_TIF_PERSYSCALL_MASK)
258 /* Clear per-syscall TIF flags if any are set. */
260 li r11,_TIF_PERSYSCALL_MASK
261 addi r12,r12,TI_FLAGS
266 subi r12,r12,TI_FLAGS
268 4: /* Anything else left to do? */
269 andi. r0,r9,(_TIF_SYSCALL_T_OR_A|_TIF_SINGLESTEP)
270 beq .ret_from_except_lite
272 /* Re-enable interrupts */
278 addi r3,r1,STACK_FRAME_OVERHEAD
279 bl .do_syscall_trace_leave
282 /* Save non-volatile GPRs, if not already saved. */
294 * The sigsuspend and rt_sigsuspend system calls can call do_signal
295 * and thus put the process into the stopped state where we might
296 * want to examine its user state with ptrace. Therefore we need
297 * to save all the nonvolatile registers (r14 - r31) before calling
298 * the C code. Similarly, fork, vfork and clone need the full
299 * register state on the stack so that it can be copied to the child.
317 _GLOBAL(ppc32_swapcontext)
319 bl .compat_sys_swapcontext
322 _GLOBAL(ppc64_swapcontext)
327 _GLOBAL(ret_from_fork)
334 * This routine switches between two different tasks. The process
335 * state of one is saved on its kernel stack. Then the state
336 * of the other is restored from its kernel stack. The memory
337 * management hardware is updated to the second process's state.
338 * Finally, we can return to the second process, via ret_from_except.
339 * On entry, r3 points to the THREAD for the current task, r4
340 * points to the THREAD for the new task.
342 * Note: there are two ways to get to the "going out" portion
343 * of this code; either by coming in via the entry (_switch)
344 * or via "fork" which must set up an environment equivalent
345 * to the "_switch" path. If you change this you'll have to change
346 * the fork code also.
348 * The code which creates the new task context is in 'copy_thread'
349 * in arch/powerpc/kernel/process.c
355 stdu r1,-SWITCH_FRAME_SIZE(r1)
356 /* r3-r13 are caller saved -- Cort */
359 mflr r20 /* Return to switch caller */
364 oris r0,r0,MSR_VSX@h /* Disable VSX */
365 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
366 #endif /* CONFIG_VSX */
367 #ifdef CONFIG_ALTIVEC
369 oris r0,r0,MSR_VEC@h /* Disable altivec */
370 mfspr r24,SPRN_VRSAVE /* save vrsave register value */
371 std r24,THREAD_VRSAVE(r3)
372 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
373 #endif /* CONFIG_ALTIVEC */
382 std r1,KSP(r3) /* Set old stack pointer */
385 /* We need a sync somewhere here to make sure that if the
386 * previous task gets rescheduled on another CPU, it sees all
387 * stores it has performed on this one.
390 #endif /* CONFIG_SMP */
392 addi r6,r4,-THREAD /* Convert THREAD to 'current' */
393 std r6,PACACURRENT(r13) /* Set new 'current' */
395 ld r8,KSP(r4) /* new stack pointer */
397 BEGIN_FTR_SECTION_NESTED(95)
398 clrrdi r6,r8,28 /* get its ESID */
399 clrrdi r9,r1,28 /* get current sp ESID */
400 FTR_SECTION_ELSE_NESTED(95)
401 clrrdi r6,r8,40 /* get its 1T ESID */
402 clrrdi r9,r1,40 /* get current sp 1T ESID */
403 ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_1T_SEGMENT, 95)
406 ALT_FTR_SECTION_END_IFSET(CPU_FTR_SLB)
407 clrldi. r0,r6,2 /* is new ESID c00000000? */
408 cmpd cr1,r6,r9 /* or is new ESID the same as current ESID? */
410 beq 2f /* if yes, don't slbie it */
412 /* Bolt in the new stack SLB entry */
413 ld r7,KSP_VSID(r4) /* Get new stack's VSID */
414 oris r0,r6,(SLB_ESID_V)@h
415 ori r0,r0,(SLB_NUM_BOLTED-1)@l
417 li r9,MMU_SEGSIZE_1T /* insert B field */
418 oris r6,r6,(MMU_SEGSIZE_1T << SLBIE_SSIZE_SHIFT)@h
419 rldimi r7,r9,SLB_VSID_SSIZE_SHIFT,0
420 END_FTR_SECTION_IFSET(CPU_FTR_1T_SEGMENT)
422 /* Update the last bolted SLB. No write barriers are needed
423 * here, provided we only update the current CPU's SLB shadow
426 ld r9,PACA_SLBSHADOWPTR(r13)
428 std r12,SLBSHADOW_STACKESID(r9) /* Clear ESID */
429 std r7,SLBSHADOW_STACKVSID(r9) /* Save VSID */
430 std r0,SLBSHADOW_STACKESID(r9) /* Save ESID */
432 /* No need to check for CPU_FTR_NO_SLBIE_B here, since when
433 * we have 1TB segments, the only CPUs known to have the errata
434 * only support less than 1TB of system memory and we'll never
435 * actually hit this code path.
439 slbie r6 /* Workaround POWER5 < DD2.1 issue */
444 clrrdi r7,r8,THREAD_SHIFT /* base of new stack */
445 /* Note: this uses SWITCH_FRAME_SIZE rather than INT_FRAME_SIZE
446 because we don't need to leave the 288-byte ABI gap at the
447 top of the kernel stack. */
448 addi r7,r7,THREAD_SIZE-SWITCH_FRAME_SIZE
450 mr r1,r8 /* start using new stack pointer */
451 std r7,PACAKSAVE(r13)
456 #ifdef CONFIG_ALTIVEC
458 ld r0,THREAD_VRSAVE(r4)
459 mtspr SPRN_VRSAVE,r0 /* if G4, restore VRSAVE reg */
460 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
461 #endif /* CONFIG_ALTIVEC */
463 /* r3-r13 are destroyed -- Cort */
467 /* convert old thread to its task_struct for return value */
469 ld r7,_NIP(r1) /* Return to _switch caller in new task */
471 addi r1,r1,SWITCH_FRAME_SIZE
475 _GLOBAL(ret_from_except)
478 bne .ret_from_except_lite
481 _GLOBAL(ret_from_except_lite)
483 * Disable interrupts so that current_thread_info()->flags
484 * can't change between when we test it and when we return
485 * from the interrupt.
487 mfmsr r10 /* Get current interrupt state */
488 rldicl r9,r10,48,1 /* clear MSR_EE */
490 mtmsrd r9,1 /* Update machine state */
492 #ifdef CONFIG_PREEMPT
493 clrrdi r9,r1,THREAD_SHIFT /* current_thread_info() */
494 li r0,_TIF_NEED_RESCHED /* bits to check */
497 /* Move MSR_PR bit in r3 to _TIF_SIGPENDING position in r0 */
498 rlwimi r0,r3,32+TIF_SIGPENDING-MSR_PR_LG,_TIF_SIGPENDING
499 and. r0,r4,r0 /* check NEED_RESCHED and maybe SIGPENDING */
502 #else /* !CONFIG_PREEMPT */
503 ld r3,_MSR(r1) /* Returning to user mode? */
505 beq restore /* if not, just restore regs and return */
507 /* Check current_thread_info()->flags */
508 clrrdi r9,r1,THREAD_SHIFT
510 andi. r0,r4,_TIF_USER_WORK_MASK
516 #ifdef CONFIG_PPC_ISERIES
520 /* Check for pending interrupts (iSeries) */
521 ld r3,PACALPPACAPTR(r13)
522 ld r3,LPPACAANYINT(r3)
524 beq+ 4f /* skip do_IRQ if no interrupts */
527 stb r3,PACASOFTIRQEN(r13) /* ensure we are soft-disabled */
528 #ifdef CONFIG_TRACE_IRQFLAGS
529 bl .trace_hardirqs_off
533 mtmsrd r10 /* hard-enable again */
534 addi r3,r1,STACK_FRAME_OVERHEAD
536 b .ret_from_except_lite /* loop back and handle more */
538 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
540 TRACE_AND_RESTORE_IRQ(r5);
542 /* extract EE bit and use it to restore paca->hard_enabled */
544 rldicl r4,r3,49,63 /* r0 = (r3 >> 15) & 1 */
545 stb r4,PACAHARDIRQEN(r13)
559 stdcx. r0,0,r1 /* to clear the reservation */
562 * Clear RI before restoring r13. If we are returning to
563 * userspace and we take an exception after restoring r13,
564 * we end up corrupting the userspace r13 value.
567 andc r4,r4,r0 /* r0 contains MSR_RI here */
571 * r13 is our per cpu area, only restore it if we are returning to
576 ACCOUNT_CPU_USER_EXIT(r2, r4)
593 b . /* prevent speculative execution */
596 #ifdef CONFIG_PREEMPT
597 andi. r0,r3,MSR_PR /* Returning to user mode? */
599 /* Check that preempt_count() == 0 and interrupts are enabled */
600 lwz r8,TI_PREEMPT(r9)
604 crandc eq,cr1*4+eq,eq
606 /* here we are preempting the current task */
608 #ifdef CONFIG_TRACE_IRQFLAGS
609 bl .trace_hardirqs_on
610 /* Note: we just clobbered r10 which used to contain the previous
611 * MSR before the hard-disabling done by the caller of do_work.
612 * We don't have that value anymore, but it doesn't matter as
613 * we will hard-enable unconditionally, we can just reload the
614 * current MSR into r10
617 #endif /* CONFIG_TRACE_IRQFLAGS */
619 stb r0,PACASOFTIRQEN(r13)
620 stb r0,PACAHARDIRQEN(r13)
622 mtmsrd r10,1 /* reenable interrupts */
625 clrrdi r9,r1,THREAD_SHIFT
626 rldicl r10,r10,48,1 /* disable interrupts again */
630 andi. r0,r4,_TIF_NEED_RESCHED
636 /* Enable interrupts */
640 andi. r0,r4,_TIF_NEED_RESCHED
643 b .ret_from_except_lite
646 addi r3,r1,STACK_FRAME_OVERHEAD
651 addi r3,r1,STACK_FRAME_OVERHEAD
652 bl .unrecoverable_exception
655 #ifdef CONFIG_PPC_RTAS
657 * On CHRP, the Run-Time Abstraction Services (RTAS) have to be
658 * called with the MMU off.
660 * In addition, we need to be in 32b mode, at least for now.
662 * Note: r3 is an input parameter to rtas, so don't trash it...
667 stdu r1,-RTAS_FRAME_SIZE(r1) /* Save SP and create stack space. */
669 /* Because RTAS is running in 32b mode, it clobbers the high order half
670 * of all registers that it saves. We therefore save those registers
671 * RTAS might touch to the stack. (r0, r3-r13 are caller saved)
673 SAVE_GPR(2, r1) /* Save the TOC */
674 SAVE_GPR(13, r1) /* Save paca */
675 SAVE_8GPRS(14, r1) /* Save the non-volatiles */
676 SAVE_10GPRS(22, r1) /* ditto */
693 /* Temporary workaround to clear CR until RTAS can be modified to
700 /* There is no way it is acceptable to get here with interrupts enabled,
701 * check it with the asm equivalent of WARN_ON
703 lbz r0,PACASOFTIRQEN(r13)
705 EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,BUGFLAG_WARNING
708 /* Hard-disable interrupts */
714 /* Unfortunately, the stack pointer and the MSR are also clobbered,
715 * so they are saved in the PACA which allows us to restore
716 * our original state after RTAS returns.
719 std r6,PACASAVEDMSR(r13)
721 /* Setup our real return addr */
722 LOAD_REG_ADDR(r4,.rtas_return_loc)
723 clrldi r4,r4,2 /* convert to realmode address */
727 ori r0,r0,MSR_EE|MSR_SE|MSR_BE|MSR_RI
731 rldicr r9,r9,MSR_SF_LG,(63-MSR_SF_LG)
732 ori r9,r9,MSR_IR|MSR_DR|MSR_FE0|MSR_FE1|MSR_FP
735 sync /* disable interrupts so SRR0/1 */
736 mtmsrd r0 /* don't get trashed */
738 LOAD_REG_ADDR(r4, rtas)
739 ld r5,RTASENTRY(r4) /* get the rtas->entry value */
740 ld r4,RTASBASE(r4) /* get the rtas->base value */
745 b . /* prevent speculative execution */
747 _STATIC(rtas_return_loc)
748 /* relocation is off at this point */
749 mfspr r4,SPRN_SPRG3 /* Get PACA */
750 clrldi r4,r4,2 /* convert to realmode address */
758 ld r1,PACAR1(r4) /* Restore our SP */
759 LOAD_REG_IMMEDIATE(r3,.rtas_restore_regs)
760 ld r4,PACASAVEDMSR(r4) /* Restore our MSR */
765 b . /* prevent speculative execution */
767 _STATIC(rtas_restore_regs)
768 /* relocation is on at this point */
769 REST_GPR(2, r1) /* Restore the TOC */
770 REST_GPR(13, r1) /* Restore paca */
771 REST_8GPRS(14, r1) /* Restore the non-volatiles */
772 REST_10GPRS(22, r1) /* ditto */
791 addi r1,r1,RTAS_FRAME_SIZE /* Unstack our frame */
792 ld r0,16(r1) /* get return address */
795 blr /* return to caller */
797 #endif /* CONFIG_PPC_RTAS */
802 stdu r1,-PROM_FRAME_SIZE(r1) /* Save SP and create stack space */
804 /* Because PROM is running in 32b mode, it clobbers the high order half
805 * of all registers that it saves. We therefore save those registers
806 * PROM might touch to the stack. (r0, r3-r13 are caller saved)
829 /* Get the PROM entrypoint */
833 /* Switch MSR to 32 bits mode
837 rldicr r12,r12,MSR_SF_LG,(63-MSR_SF_LG)
840 rldicr r12,r12,MSR_ISF_LG,(63-MSR_ISF_LG)
845 /* Restore arguments & enter PROM here... */
849 /* Just make sure that r1 top 32 bits didn't get
854 /* Restore the MSR (back to 64 bits) */
859 /* Restore other registers */
879 addi r1,r1,PROM_FRAME_SIZE
885 #ifdef CONFIG_DYNAMIC_FTRACE
888 /* Taken from output of objdump from lib64/glibc */
892 subi r3, r3, MCOUNT_INSN_SIZE
902 _GLOBAL(ftrace_caller)
903 /* Taken from output of objdump from lib64/glibc */
909 subi r3, r3, MCOUNT_INSN_SIZE
924 /* Taken from output of objdump from lib64/glibc */
931 subi r3, r3, MCOUNT_INSN_SIZE
932 LOAD_REG_ADDR(r5,ftrace_trace_function)