2 * Port for PPC64 David Engebretsen, IBM Corp.
3 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
5 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
6 * Rework, based on alpha PCI code.
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
16 #include <linux/config.h>
17 #include <linux/kernel.h>
18 #include <linux/pci.h>
19 #include <linux/string.h>
20 #include <linux/init.h>
21 #include <linux/bootmem.h>
23 #include <linux/list.h>
25 #include <asm/processor.h>
28 #include <asm/pci-bridge.h>
29 #include <asm/byteorder.h>
31 #include <asm/machdep.h>
37 #define DBG(fmt...) udbg_printf(fmt)
42 unsigned long pci_probe_only = 1;
43 unsigned long pci_assign_all_buses = 0;
46 * legal IO pages under MAX_ISA_PORT. This is to ensure we don't touch
47 * devices we don't have access to.
49 unsigned long io_page_mask;
51 EXPORT_SYMBOL(io_page_mask);
54 unsigned int pcibios_assign_all_busses(void)
56 return pci_assign_all_buses;
59 /* pci_io_base -- the base address from which io bars are offsets.
60 * This is the lowest I/O base address (so bar values are always positive),
61 * and it *must* be the start of ISA space if an ISA bus exists because
62 * ISA drivers use hard coded offsets. If no ISA bus exists a dummy
63 * page is mapped and isa_io_limit prevents access to it.
65 unsigned long isa_io_base; /* NULL if no ISA bus */
66 EXPORT_SYMBOL(isa_io_base);
67 unsigned long pci_io_base;
68 EXPORT_SYMBOL(pci_io_base);
70 void iSeries_pcibios_init(void);
74 struct dma_mapping_ops pci_dma_ops;
75 EXPORT_SYMBOL(pci_dma_ops);
77 int global_phb_number; /* Global phb counter */
79 /* Cached ISA bridge dev. */
80 struct pci_dev *ppc64_isabridge_dev = NULL;
82 static void fixup_broken_pcnet32(struct pci_dev* dev)
84 if ((dev->class>>8 == PCI_CLASS_NETWORK_ETHERNET)) {
85 dev->vendor = PCI_VENDOR_ID_AMD;
86 pci_write_config_word(dev, PCI_VENDOR_ID, PCI_VENDOR_ID_AMD);
90 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TRIDENT, PCI_ANY_ID, fixup_broken_pcnet32);
92 void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
95 unsigned long offset = 0;
96 struct pci_controller *hose = pci_bus_to_host(dev->bus);
101 if (res->flags & IORESOURCE_IO)
102 offset = (unsigned long)hose->io_base_virt - pci_io_base;
104 if (res->flags & IORESOURCE_MEM)
105 offset = hose->pci_mem_offset;
107 region->start = res->start - offset;
108 region->end = res->end - offset;
111 #ifdef CONFIG_HOTPLUG
112 EXPORT_SYMBOL(pcibios_resource_to_bus);
116 * We need to avoid collisions with `mirrored' VGA ports
117 * and other strange ISA hardware, so we always want the
118 * addresses to be allocated in the 0x000-0x0ff region
121 * Why? Because some silly external IO cards only decode
122 * the low 10 bits of the IO address. The 0x00-0xff region
123 * is reserved for motherboard devices that decode all 16
124 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
125 * but we want to try to avoid allocating at 0x2900-0x2bff
126 * which might have be mirrored at 0x0100-0x03ff..
128 void pcibios_align_resource(void *data, struct resource *res,
129 unsigned long size, unsigned long align)
131 struct pci_dev *dev = data;
132 struct pci_controller *hose = pci_bus_to_host(dev->bus);
133 unsigned long start = res->start;
134 unsigned long alignto;
136 if (res->flags & IORESOURCE_IO) {
137 unsigned long offset = (unsigned long)hose->io_base_virt -
139 /* Make sure we start at our min on all hoses */
140 if (start - offset < PCIBIOS_MIN_IO)
141 start = PCIBIOS_MIN_IO + offset;
144 * Put everything into 0x00-0xff region modulo 0x400
147 start = (start + 0x3ff) & ~0x3ff;
149 } else if (res->flags & IORESOURCE_MEM) {
150 /* Make sure we start at our min on all hoses */
151 if (start - hose->pci_mem_offset < PCIBIOS_MIN_MEM)
152 start = PCIBIOS_MIN_MEM + hose->pci_mem_offset;
154 /* Align to multiple of size of minimum base. */
155 alignto = max(0x1000UL, align);
156 start = ALIGN(start, alignto);
162 static DEFINE_SPINLOCK(hose_spinlock);
165 * pci_controller(phb) initialized common variables.
167 void __devinit pci_setup_pci_controller(struct pci_controller *hose)
169 memset(hose, 0, sizeof(struct pci_controller));
171 spin_lock(&hose_spinlock);
172 hose->global_number = global_phb_number++;
173 list_add_tail(&hose->list_node, &hose_list);
174 spin_unlock(&hose_spinlock);
177 static void __init pcibios_claim_one_bus(struct pci_bus *b)
180 struct pci_bus *child_bus;
182 list_for_each_entry(dev, &b->devices, bus_list) {
185 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
186 struct resource *r = &dev->resource[i];
188 if (r->parent || !r->start || !r->flags)
190 pci_claim_resource(dev, i);
194 list_for_each_entry(child_bus, &b->children, node)
195 pcibios_claim_one_bus(child_bus);
198 #ifndef CONFIG_PPC_ISERIES
199 static void __init pcibios_claim_of_setup(void)
203 list_for_each_entry(b, &pci_root_buses, node)
204 pcibios_claim_one_bus(b);
208 static int __init pcibios_init(void)
210 struct pci_controller *hose, *tmp;
213 /* For now, override phys_mem_access_prot. If we need it,
214 * later, we may move that initialization to each ppc_md
216 ppc_md.phys_mem_access_prot = pci_phys_mem_access_prot;
218 #ifdef CONFIG_PPC_ISERIES
219 iSeries_pcibios_init();
222 printk("PCI: Probing PCI hardware\n");
224 /* Scan all of the recorded PCI controllers. */
225 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
226 hose->last_busno = 0xff;
227 bus = pci_scan_bus(hose->first_busno, hose->ops,
230 hose->last_busno = bus->subordinate;
233 #ifndef CONFIG_PPC_ISERIES
235 pcibios_claim_of_setup();
237 /* FIXME: `else' will be removed when
238 pci_assign_unassigned_resources() is able to work
239 correctly with [partially] allocated PCI tree. */
240 pci_assign_unassigned_resources();
241 #endif /* !CONFIG_PPC_ISERIES */
243 /* Call machine dependent final fixup */
244 if (ppc_md.pcibios_fixup)
245 ppc_md.pcibios_fixup();
247 /* Cache the location of the ISA bridge (if we have one) */
248 ppc64_isabridge_dev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
249 if (ppc64_isabridge_dev != NULL)
250 printk("ISA bridge at %s\n", pci_name(ppc64_isabridge_dev));
252 printk("PCI: Probing PCI hardware done\n");
257 subsys_initcall(pcibios_init);
259 char __init *pcibios_setup(char *str)
264 int pcibios_enable_device(struct pci_dev *dev, int mask)
269 pci_read_config_word(dev, PCI_COMMAND, &cmd);
272 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
273 struct resource *res = &dev->resource[i];
275 /* Only set up the requested stuff */
276 if (!(mask & (1<<i)))
279 if (res->flags & IORESOURCE_IO)
280 cmd |= PCI_COMMAND_IO;
281 if (res->flags & IORESOURCE_MEM)
282 cmd |= PCI_COMMAND_MEMORY;
286 printk(KERN_DEBUG "PCI: Enabling device: (%s), cmd %x\n",
288 /* Enable the appropriate bits in the PCI command register. */
289 pci_write_config_word(dev, PCI_COMMAND, cmd);
295 * Return the domain number for this bus.
297 int pci_domain_nr(struct pci_bus *bus)
299 #ifdef CONFIG_PPC_ISERIES
302 struct pci_controller *hose = pci_bus_to_host(bus);
304 return hose->global_number;
308 EXPORT_SYMBOL(pci_domain_nr);
310 /* Decide whether to display the domain number in /proc */
311 int pci_proc_domain(struct pci_bus *bus)
313 #ifdef CONFIG_PPC_ISERIES
316 struct pci_controller *hose = pci_bus_to_host(bus);
322 * Platform support for /proc/bus/pci/X/Y mmap()s,
323 * modelled on the sparc64 implementation by Dave Miller.
328 * Adjust vm_pgoff of VMA such that it is the physical page offset
329 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
331 * Basically, the user finds the base address for his device which he wishes
332 * to mmap. They read the 32-bit value from the config space base register,
333 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
334 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
336 * Returns negative error code on failure, zero on success.
338 static struct resource *__pci_mmap_make_offset(struct pci_dev *dev,
339 unsigned long *offset,
340 enum pci_mmap_state mmap_state)
342 struct pci_controller *hose = pci_bus_to_host(dev->bus);
343 unsigned long io_offset = 0;
347 return NULL; /* should never happen */
349 /* If memory, add on the PCI bridge address offset */
350 if (mmap_state == pci_mmap_mem) {
351 *offset += hose->pci_mem_offset;
352 res_bit = IORESOURCE_MEM;
354 io_offset = (unsigned long)hose->io_base_virt - pci_io_base;
355 *offset += io_offset;
356 res_bit = IORESOURCE_IO;
360 * Check that the offset requested corresponds to one of the
361 * resources of the device.
363 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
364 struct resource *rp = &dev->resource[i];
365 int flags = rp->flags;
367 /* treat ROM as memory (should be already) */
368 if (i == PCI_ROM_RESOURCE)
369 flags |= IORESOURCE_MEM;
371 /* Active and same type? */
372 if ((flags & res_bit) == 0)
375 /* In the range of this resource? */
376 if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end)
379 /* found it! construct the final physical address */
380 if (mmap_state == pci_mmap_io)
381 *offset += hose->io_base_phys - io_offset;
389 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
392 static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp,
394 enum pci_mmap_state mmap_state,
397 unsigned long prot = pgprot_val(protection);
399 /* Write combine is always 0 on non-memory space mappings. On
400 * memory space, if the user didn't pass 1, we check for a
401 * "prefetchable" resource. This is a bit hackish, but we use
402 * this to workaround the inability of /sysfs to provide a write
405 if (mmap_state != pci_mmap_mem)
407 else if (write_combine == 0) {
408 if (rp->flags & IORESOURCE_PREFETCH)
412 /* XXX would be nice to have a way to ask for write-through */
413 prot |= _PAGE_NO_CACHE;
415 prot &= ~_PAGE_GUARDED;
417 prot |= _PAGE_GUARDED;
419 printk("PCI map for %s:%lx, prot: %lx\n", pci_name(dev), rp->start,
422 return __pgprot(prot);
426 * This one is used by /dev/mem and fbdev who have no clue about the
427 * PCI device, it tries to find the PCI device first and calls the
430 pgprot_t pci_phys_mem_access_prot(struct file *file,
431 unsigned long offset,
435 struct pci_dev *pdev = NULL;
436 struct resource *found = NULL;
437 unsigned long prot = pgprot_val(protection);
440 if (page_is_ram(offset >> PAGE_SHIFT))
441 return __pgprot(prot);
443 prot |= _PAGE_NO_CACHE | _PAGE_GUARDED;
445 for_each_pci_dev(pdev) {
446 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
447 struct resource *rp = &pdev->resource[i];
448 int flags = rp->flags;
450 /* Active and same type? */
451 if ((flags & IORESOURCE_MEM) == 0)
453 /* In the range of this resource? */
454 if (offset < (rp->start & PAGE_MASK) ||
464 if (found->flags & IORESOURCE_PREFETCH)
465 prot &= ~_PAGE_GUARDED;
469 DBG("non-PCI map for %lx, prot: %lx\n", offset, prot);
471 return __pgprot(prot);
476 * Perform the actual remap of the pages for a PCI device mapping, as
477 * appropriate for this architecture. The region in the process to map
478 * is described by vm_start and vm_end members of VMA, the base physical
479 * address is found in vm_pgoff.
480 * The pci device structure is provided so that architectures may make mapping
481 * decisions on a per-device or per-bus basis.
483 * Returns a negative error code on failure, zero on success.
485 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
486 enum pci_mmap_state mmap_state,
489 unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
493 rp = __pci_mmap_make_offset(dev, &offset, mmap_state);
497 vma->vm_pgoff = offset >> PAGE_SHIFT;
498 vma->vm_flags |= VM_SHM | VM_LOCKED | VM_IO;
499 vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp,
501 mmap_state, write_combine);
503 ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
504 vma->vm_end - vma->vm_start, vma->vm_page_prot);
509 #ifdef CONFIG_PPC_MULTIPLATFORM
510 static ssize_t pci_show_devspec(struct device *dev, struct device_attribute *attr, char *buf)
512 struct pci_dev *pdev;
513 struct device_node *np;
515 pdev = to_pci_dev (dev);
516 np = pci_device_to_OF_node(pdev);
517 if (np == NULL || np->full_name == NULL)
519 return sprintf(buf, "%s", np->full_name);
521 static DEVICE_ATTR(devspec, S_IRUGO, pci_show_devspec, NULL);
522 #endif /* CONFIG_PPC_MULTIPLATFORM */
524 void pcibios_add_platform_entries(struct pci_dev *pdev)
526 #ifdef CONFIG_PPC_MULTIPLATFORM
527 device_create_file(&pdev->dev, &dev_attr_devspec);
528 #endif /* CONFIG_PPC_MULTIPLATFORM */
531 #ifdef CONFIG_PPC_MULTIPLATFORM
533 #define ISA_SPACE_MASK 0x1
534 #define ISA_SPACE_IO 0x1
536 static void __devinit pci_process_ISA_OF_ranges(struct device_node *isa_node,
537 unsigned long phb_io_base_phys,
538 void __iomem * phb_io_base_virt)
540 struct isa_range *range;
541 unsigned long pci_addr;
542 unsigned int isa_addr;
546 range = (struct isa_range *) get_property(isa_node, "ranges", &rlen);
547 if (range == NULL || (rlen < sizeof(struct isa_range))) {
548 printk(KERN_ERR "no ISA ranges or unexpected isa range size,"
550 __ioremap_explicit(phb_io_base_phys,
551 (unsigned long)phb_io_base_virt,
552 0x10000, _PAGE_NO_CACHE | _PAGE_GUARDED);
556 /* From "ISA Binding to 1275"
557 * The ranges property is laid out as an array of elements,
558 * each of which comprises:
559 * cells 0 - 1: an ISA address
560 * cells 2 - 4: a PCI address
561 * (size depending on dev->n_addr_cells)
562 * cell 5: the size of the range
564 if ((range->isa_addr.a_hi && ISA_SPACE_MASK) == ISA_SPACE_IO) {
565 isa_addr = range->isa_addr.a_lo;
566 pci_addr = (unsigned long) range->pci_addr.a_mid << 32 |
567 range->pci_addr.a_lo;
569 /* Assume these are both zero */
570 if ((pci_addr != 0) || (isa_addr != 0)) {
571 printk(KERN_ERR "unexpected isa to pci mapping: %s\n",
576 size = PAGE_ALIGN(range->size);
578 __ioremap_explicit(phb_io_base_phys,
579 (unsigned long) phb_io_base_virt,
580 size, _PAGE_NO_CACHE | _PAGE_GUARDED);
584 void __devinit pci_process_bridge_OF_ranges(struct pci_controller *hose,
585 struct device_node *dev)
587 unsigned int *ranges;
591 struct resource *res;
592 int np, na = prom_n_addr_cells(dev);
593 unsigned long pci_addr, cpu_phys_addr;
597 /* From "PCI Binding to 1275"
598 * The ranges property is laid out as an array of elements,
599 * each of which comprises:
600 * cells 0 - 2: a PCI address
601 * cells 3 or 3+4: a CPU physical address
602 * (size depending on dev->n_addr_cells)
603 * cells 4+5 or 5+6: the size of the range
606 hose->io_base_phys = 0;
607 ranges = (unsigned int *) get_property(dev, "ranges", &rlen);
608 while ((rlen -= np * sizeof(unsigned int)) >= 0) {
610 pci_addr = (unsigned long)ranges[1] << 32 | ranges[2];
612 cpu_phys_addr = ranges[3];
614 cpu_phys_addr = cpu_phys_addr << 32 | ranges[4];
616 size = (unsigned long)ranges[na+3] << 32 | ranges[na+4];
619 switch ((ranges[0] >> 24) & 0x3) {
620 case 1: /* I/O space */
621 hose->io_base_phys = cpu_phys_addr;
622 hose->pci_io_size = size;
624 res = &hose->io_resource;
625 res->flags = IORESOURCE_IO;
626 res->start = pci_addr;
627 DBG("phb%d: IO 0x%lx -> 0x%lx\n", hose->global_number,
628 res->start, res->start + size - 1);
630 case 2: /* memory space */
632 while (memno < 3 && hose->mem_resources[memno].flags)
636 hose->pci_mem_offset = cpu_phys_addr - pci_addr;
638 res = &hose->mem_resources[memno];
639 res->flags = IORESOURCE_MEM;
640 res->start = cpu_phys_addr;
641 DBG("phb%d: MEM 0x%lx -> 0x%lx\n", hose->global_number,
642 res->start, res->start + size - 1);
647 res->name = dev->full_name;
648 res->end = res->start + size - 1;
657 void __init pci_setup_phb_io(struct pci_controller *hose, int primary)
659 unsigned long size = hose->pci_io_size;
660 unsigned long io_virt_offset;
661 struct resource *res;
662 struct device_node *isa_dn;
664 hose->io_base_virt = reserve_phb_iospace(size);
665 DBG("phb%d io_base_phys 0x%lx io_base_virt 0x%lx\n",
666 hose->global_number, hose->io_base_phys,
667 (unsigned long) hose->io_base_virt);
670 pci_io_base = (unsigned long)hose->io_base_virt;
671 isa_dn = of_find_node_by_type(NULL, "isa");
673 isa_io_base = pci_io_base;
674 pci_process_ISA_OF_ranges(isa_dn, hose->io_base_phys,
682 io_virt_offset = (unsigned long)hose->io_base_virt - pci_io_base;
683 res = &hose->io_resource;
684 res->start += io_virt_offset;
685 res->end += io_virt_offset;
688 void __devinit pci_setup_phb_io_dynamic(struct pci_controller *hose,
691 unsigned long size = hose->pci_io_size;
692 unsigned long io_virt_offset;
693 struct resource *res;
695 hose->io_base_virt = __ioremap(hose->io_base_phys, size,
696 _PAGE_NO_CACHE | _PAGE_GUARDED);
697 DBG("phb%d io_base_phys 0x%lx io_base_virt 0x%lx\n",
698 hose->global_number, hose->io_base_phys,
699 (unsigned long) hose->io_base_virt);
702 pci_io_base = (unsigned long)hose->io_base_virt;
704 io_virt_offset = (unsigned long)hose->io_base_virt - pci_io_base;
705 res = &hose->io_resource;
706 res->start += io_virt_offset;
707 res->end += io_virt_offset;
711 static int get_bus_io_range(struct pci_bus *bus, unsigned long *start_phys,
712 unsigned long *start_virt, unsigned long *size)
714 struct pci_controller *hose = pci_bus_to_host(bus);
715 struct pci_bus_region region;
716 struct resource *res;
719 res = bus->resource[0];
720 pcibios_resource_to_bus(bus->self, ®ion, res);
721 *start_phys = hose->io_base_phys + region.start;
722 *start_virt = (unsigned long) hose->io_base_virt +
724 if (region.end > region.start)
725 *size = region.end - region.start + 1;
727 printk("%s(): unexpected region 0x%lx->0x%lx\n",
728 __FUNCTION__, region.start, region.end);
734 res = &hose->io_resource;
735 *start_phys = hose->io_base_phys;
736 *start_virt = (unsigned long) hose->io_base_virt;
737 if (res->end > res->start)
738 *size = res->end - res->start + 1;
740 printk("%s(): unexpected region 0x%lx->0x%lx\n",
741 __FUNCTION__, res->start, res->end);
749 int unmap_bus_range(struct pci_bus *bus)
751 unsigned long start_phys;
752 unsigned long start_virt;
756 printk(KERN_ERR "%s() expected bus\n", __FUNCTION__);
760 if (get_bus_io_range(bus, &start_phys, &start_virt, &size))
762 if (iounmap_explicit((void __iomem *) start_virt, size))
767 EXPORT_SYMBOL(unmap_bus_range);
769 int remap_bus_range(struct pci_bus *bus)
771 unsigned long start_phys;
772 unsigned long start_virt;
776 printk(KERN_ERR "%s() expected bus\n", __FUNCTION__);
781 if (get_bus_io_range(bus, &start_phys, &start_virt, &size))
783 printk("mapping IO %lx -> %lx, size: %lx\n", start_phys, start_virt, size);
784 if (__ioremap_explicit(start_phys, start_virt, size,
785 _PAGE_NO_CACHE | _PAGE_GUARDED))
790 EXPORT_SYMBOL(remap_bus_range);
792 void phbs_remap_io(void)
794 struct pci_controller *hose, *tmp;
796 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
797 remap_bus_range(hose->bus);
801 * ppc64 can have multifunction devices that do not respond to function 0.
802 * In this case we must scan all functions.
804 int pcibios_scan_all_fns(struct pci_bus *bus, int devfn)
806 struct device_node *busdn, *dn;
809 busdn = pci_device_to_OF_node(bus->self);
811 busdn = bus->sysdata; /* must be a phb */
817 * Check to see if there is any of the 8 functions are in the
818 * device tree. If they are then we need to scan all the
819 * functions of this slot.
821 for (dn = busdn->child; dn; dn = dn->sibling)
822 if ((dn->devfn >> 3) == (devfn >> 3))
829 void __devinit pcibios_fixup_device_resources(struct pci_dev *dev,
832 /* Update device resources. */
833 struct pci_controller *hose = pci_bus_to_host(bus);
836 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
837 if (dev->resource[i].flags & IORESOURCE_IO) {
838 unsigned long offset = (unsigned long)hose->io_base_virt
840 unsigned long start, end, mask;
842 start = dev->resource[i].start += offset;
843 end = dev->resource[i].end += offset;
845 /* Need to allow IO access to pages that are in the
847 if (start < MAX_ISA_PORT) {
848 if (end > MAX_ISA_PORT)
851 start >>= PAGE_SHIFT;
854 /* get the range of pages for the map */
855 mask = ((1 << (end+1))-1) ^ ((1 << start)-1);
856 io_page_mask |= mask;
859 else if (dev->resource[i].flags & IORESOURCE_MEM) {
860 dev->resource[i].start += hose->pci_mem_offset;
861 dev->resource[i].end += hose->pci_mem_offset;
865 EXPORT_SYMBOL(pcibios_fixup_device_resources);
867 void __devinit pcibios_fixup_bus(struct pci_bus *bus)
869 struct pci_controller *hose = pci_bus_to_host(bus);
870 struct pci_dev *dev = bus->self;
871 struct resource *res;
878 bus->resource[0] = res = &hose->io_resource;
880 if (res->flags && request_resource(&ioport_resource, res))
881 printk(KERN_ERR "Failed to request IO on "
882 "PCI domain %d\n", pci_domain_nr(bus));
884 for (i = 0; i < 3; ++i) {
885 res = &hose->mem_resources[i];
886 bus->resource[i+1] = res;
887 if (res->flags && request_resource(&iomem_resource, res))
888 printk(KERN_ERR "Failed to request MEM on "
892 } else if (pci_probe_only &&
893 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
894 /* This is a subordinate bridge */
896 pci_read_bridge_bases(bus);
897 pcibios_fixup_device_resources(dev, bus);
900 ppc_md.iommu_bus_setup(bus);
902 list_for_each_entry(dev, &bus->devices, bus_list)
903 ppc_md.iommu_dev_setup(dev);
905 if (ppc_md.irq_bus_setup)
906 ppc_md.irq_bus_setup(bus);
911 list_for_each_entry(dev, &bus->devices, bus_list) {
912 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
913 pcibios_fixup_device_resources(dev, bus);
916 EXPORT_SYMBOL(pcibios_fixup_bus);
919 * Reads the interrupt pin to determine if interrupt is use by card.
920 * If the interrupt is used, then gets the interrupt line from the
921 * openfirmware and sets it in the pci_dev and pci_config line.
923 int pci_read_irq_line(struct pci_dev *pci_dev)
926 struct device_node *node;
928 pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &intpin);
932 node = pci_device_to_OF_node(pci_dev);
936 if (node->n_intrs == 0)
939 pci_dev->irq = node->intrs[0].line;
941 pci_write_config_byte(pci_dev, PCI_INTERRUPT_LINE, pci_dev->irq);
945 EXPORT_SYMBOL(pci_read_irq_line);
947 void pci_resource_to_user(const struct pci_dev *dev, int bar,
948 const struct resource *rsrc,
949 u64 *start, u64 *end)
951 struct pci_controller *hose = pci_bus_to_host(dev->bus);
952 unsigned long offset = 0;
957 if (rsrc->flags & IORESOURCE_IO)
958 offset = pci_io_base - (unsigned long)hose->io_base_virt +
961 *start = rsrc->start + offset;
962 *end = rsrc->end + offset;
965 #endif /* CONFIG_PPC_MULTIPLATFORM */