2 * PowerPC64 SLB support.
4 * Copyright (C) 2004 David Gibson <dwg@au.ibm.com>, IBM
5 * Based on earlier code writteh by:
6 * Dave Engebretsen and Mike Corrigan {engebret|mikejc}@us.ibm.com
7 * Copyright (c) 2001 Dave Engebretsen
8 * Copyright (C) 2002 Anton Blanchard <anton@au.ibm.com>, IBM
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version
14 * 2 of the License, or (at your option) any later version.
19 #include <asm/pgtable.h>
21 #include <asm/mmu_context.h>
23 #include <asm/cputable.h>
24 #include <asm/cacheflush.h>
26 #include <asm/firmware.h>
27 #include <linux/compiler.h>
30 #define DBG(fmt...) udbg_printf(fmt)
35 extern void slb_allocate_realmode(unsigned long ea);
36 extern void slb_allocate_user(unsigned long ea);
38 static void slb_allocate(unsigned long ea)
40 /* Currently, we do real mode for all SLBs including user, but
41 * that will change if we bring back dynamic VSIDs
43 slb_allocate_realmode(ea);
46 static inline unsigned long mk_esid_data(unsigned long ea, unsigned long slot)
48 return (ea & ESID_MASK) | SLB_ESID_V | slot;
51 static inline unsigned long mk_vsid_data(unsigned long ea, unsigned long flags)
53 return (get_kernel_vsid(ea) << SLB_VSID_SHIFT) | flags;
56 static inline void slb_shadow_update(unsigned long ea,
61 * Clear the ESID first so the entry is not valid while we are
64 get_slb_shadow()->save_area[entry].esid = 0;
66 get_slb_shadow()->save_area[entry].vsid = mk_vsid_data(ea, flags);
68 get_slb_shadow()->save_area[entry].esid = mk_esid_data(ea, entry);
72 static inline void slb_shadow_clear(unsigned long entry)
74 get_slb_shadow()->save_area[entry].esid = 0;
77 static inline void create_shadowed_slbe(unsigned long ea, unsigned long flags,
81 * Updating the shadow buffer before writing the SLB ensures
82 * we don't get a stale entry here if we get preempted by PHYP
83 * between these two statements.
85 slb_shadow_update(ea, flags, entry);
87 asm volatile("slbmte %0,%1" :
88 : "r" (mk_vsid_data(ea, flags)),
89 "r" (mk_esid_data(ea, entry))
93 void slb_flush_and_rebolt(void)
95 /* If you change this make sure you change SLB_NUM_BOLTED
96 * appropriately too. */
97 unsigned long linear_llp, vmalloc_llp, lflags, vflags;
98 unsigned long ksp_esid_data;
100 WARN_ON(!irqs_disabled());
102 linear_llp = mmu_psize_defs[mmu_linear_psize].sllp;
103 vmalloc_llp = mmu_psize_defs[mmu_vmalloc_psize].sllp;
104 lflags = SLB_VSID_KERNEL | linear_llp;
105 vflags = SLB_VSID_KERNEL | vmalloc_llp;
107 ksp_esid_data = mk_esid_data(get_paca()->kstack, 2);
108 if ((ksp_esid_data & ESID_MASK) == PAGE_OFFSET) {
109 ksp_esid_data &= ~SLB_ESID_V;
112 /* Update stack entry; others don't change */
113 slb_shadow_update(get_paca()->kstack, lflags, 2);
116 /* We need to do this all in asm, so we're sure we don't touch
117 * the stack between the slbia and rebolting it. */
118 asm volatile("isync\n"
120 /* Slot 1 - first VMALLOC segment */
122 /* Slot 2 - kernel stack */
125 :: "r"(mk_vsid_data(VMALLOC_START, vflags)),
126 "r"(mk_esid_data(VMALLOC_START, 1)),
127 "r"(mk_vsid_data(ksp_esid_data, lflags)),
132 void slb_vmalloc_update(void)
134 unsigned long vflags;
136 vflags = SLB_VSID_KERNEL | mmu_psize_defs[mmu_vmalloc_psize].sllp;
137 slb_shadow_update(VMALLOC_START, vflags, 1);
138 slb_flush_and_rebolt();
141 /* Flush all user entries from the segment table of the current processor. */
142 void switch_slb(struct task_struct *tsk, struct mm_struct *mm)
144 unsigned long offset = get_paca()->slb_cache_ptr;
145 unsigned long esid_data = 0;
146 unsigned long pc = KSTK_EIP(tsk);
147 unsigned long stack = KSTK_ESP(tsk);
148 unsigned long unmapped_base;
150 if (offset <= SLB_CACHE_ENTRIES) {
152 asm volatile("isync" : : : "memory");
153 for (i = 0; i < offset; i++) {
154 esid_data = ((unsigned long)get_paca()->slb_cache[i]
155 << SID_SHIFT) | SLBIE_C;
156 asm volatile("slbie %0" : : "r" (esid_data));
158 asm volatile("isync" : : : "memory");
160 slb_flush_and_rebolt();
163 /* Workaround POWER5 < DD2.1 issue */
164 if (offset == 1 || offset > SLB_CACHE_ENTRIES)
165 asm volatile("slbie %0" : : "r" (esid_data));
167 get_paca()->slb_cache_ptr = 0;
168 get_paca()->context = mm->context;
171 * preload some userspace segments into the SLB.
173 if (test_tsk_thread_flag(tsk, TIF_32BIT))
174 unmapped_base = TASK_UNMAPPED_BASE_USER32;
176 unmapped_base = TASK_UNMAPPED_BASE_USER64;
178 if (is_kernel_addr(pc))
182 if (GET_ESID(pc) == GET_ESID(stack))
185 if (is_kernel_addr(stack))
189 if ((GET_ESID(pc) == GET_ESID(unmapped_base))
190 || (GET_ESID(stack) == GET_ESID(unmapped_base)))
193 if (is_kernel_addr(unmapped_base))
195 slb_allocate(unmapped_base);
198 static inline void patch_slb_encoding(unsigned int *insn_addr,
201 /* Assume the instruction had a "0" immediate value, just
202 * "or" in the new value
205 flush_icache_range((unsigned long)insn_addr, 4+
206 (unsigned long)insn_addr);
209 void slb_initialize(void)
211 unsigned long linear_llp, vmalloc_llp, io_llp;
212 unsigned long lflags, vflags;
213 static int slb_encoding_inited;
214 extern unsigned int *slb_miss_kernel_load_linear;
215 extern unsigned int *slb_miss_kernel_load_io;
217 /* Prepare our SLB miss handler based on our page size */
218 linear_llp = mmu_psize_defs[mmu_linear_psize].sllp;
219 io_llp = mmu_psize_defs[mmu_io_psize].sllp;
220 vmalloc_llp = mmu_psize_defs[mmu_vmalloc_psize].sllp;
221 get_paca()->vmalloc_sllp = SLB_VSID_KERNEL | vmalloc_llp;
223 if (!slb_encoding_inited) {
224 slb_encoding_inited = 1;
225 patch_slb_encoding(slb_miss_kernel_load_linear,
226 SLB_VSID_KERNEL | linear_llp);
227 patch_slb_encoding(slb_miss_kernel_load_io,
228 SLB_VSID_KERNEL | io_llp);
230 DBG("SLB: linear LLP = %04x\n", linear_llp);
231 DBG("SLB: io LLP = %04x\n", io_llp);
234 get_paca()->stab_rr = SLB_NUM_BOLTED;
236 /* On iSeries the bolted entries have already been set up by
237 * the hypervisor from the lparMap data in head.S */
238 if (firmware_has_feature(FW_FEATURE_ISERIES))
241 lflags = SLB_VSID_KERNEL | linear_llp;
242 vflags = SLB_VSID_KERNEL | vmalloc_llp;
244 /* Invalidate the entire SLB (even slot 0) & all the ERATS */
245 asm volatile("isync":::"memory");
246 asm volatile("slbmte %0,%0"::"r" (0) : "memory");
247 asm volatile("isync; slbia; isync":::"memory");
248 create_shadowed_slbe(PAGE_OFFSET, lflags, 0);
250 create_shadowed_slbe(VMALLOC_START, vflags, 1);
252 /* We don't bolt the stack for the time being - we're in boot,
253 * so the stack is in the bolted segment. By the time it goes
254 * elsewhere, we'll call _switch() which will bolt in the new
256 asm volatile("isync":::"memory");