Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/bart/ide-2.6
[linux-2.6] / arch / arm / mach-davinci / dm644x.c
1 /*
2  * TI DaVinci DM644x chip specific setup
3  *
4  * Author: Kevin Hilman, Deep Root Systems, LLC
5  *
6  * 2007 (c) Deep Root Systems, LLC. This file is licensed under
7  * the terms of the GNU General Public License version 2. This program
8  * is licensed "as is" without any warranty of any kind, whether express
9  * or implied.
10  */
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/clk.h>
14 #include <linux/platform_device.h>
15
16 #include <mach/dm644x.h>
17 #include <mach/clock.h>
18 #include <mach/cputype.h>
19 #include <mach/edma.h>
20 #include <mach/irqs.h>
21 #include <mach/psc.h>
22 #include <mach/mux.h>
23
24 #include "clock.h"
25 #include "mux.h"
26
27 /*
28  * Device specific clocks
29  */
30 #define DM644X_REF_FREQ         27000000
31
32 static struct pll_data pll1_data = {
33         .num       = 1,
34         .phys_base = DAVINCI_PLL1_BASE,
35 };
36
37 static struct pll_data pll2_data = {
38         .num       = 2,
39         .phys_base = DAVINCI_PLL2_BASE,
40 };
41
42 static struct clk ref_clk = {
43         .name = "ref_clk",
44         .rate = DM644X_REF_FREQ,
45 };
46
47 static struct clk pll1_clk = {
48         .name = "pll1",
49         .parent = &ref_clk,
50         .pll_data = &pll1_data,
51         .flags = CLK_PLL,
52 };
53
54 static struct clk pll1_sysclk1 = {
55         .name = "pll1_sysclk1",
56         .parent = &pll1_clk,
57         .flags = CLK_PLL,
58         .div_reg = PLLDIV1,
59 };
60
61 static struct clk pll1_sysclk2 = {
62         .name = "pll1_sysclk2",
63         .parent = &pll1_clk,
64         .flags = CLK_PLL,
65         .div_reg = PLLDIV2,
66 };
67
68 static struct clk pll1_sysclk3 = {
69         .name = "pll1_sysclk3",
70         .parent = &pll1_clk,
71         .flags = CLK_PLL,
72         .div_reg = PLLDIV3,
73 };
74
75 static struct clk pll1_sysclk5 = {
76         .name = "pll1_sysclk5",
77         .parent = &pll1_clk,
78         .flags = CLK_PLL,
79         .div_reg = PLLDIV5,
80 };
81
82 static struct clk pll1_aux_clk = {
83         .name = "pll1_aux_clk",
84         .parent = &pll1_clk,
85         .flags = CLK_PLL | PRE_PLL,
86 };
87
88 static struct clk pll1_sysclkbp = {
89         .name = "pll1_sysclkbp",
90         .parent = &pll1_clk,
91         .flags = CLK_PLL | PRE_PLL,
92         .div_reg = BPDIV
93 };
94
95 static struct clk pll2_clk = {
96         .name = "pll2",
97         .parent = &ref_clk,
98         .pll_data = &pll2_data,
99         .flags = CLK_PLL,
100 };
101
102 static struct clk pll2_sysclk1 = {
103         .name = "pll2_sysclk1",
104         .parent = &pll2_clk,
105         .flags = CLK_PLL,
106         .div_reg = PLLDIV1,
107 };
108
109 static struct clk pll2_sysclk2 = {
110         .name = "pll2_sysclk2",
111         .parent = &pll2_clk,
112         .flags = CLK_PLL,
113         .div_reg = PLLDIV2,
114 };
115
116 static struct clk pll2_sysclkbp = {
117         .name = "pll2_sysclkbp",
118         .parent = &pll2_clk,
119         .flags = CLK_PLL | PRE_PLL,
120         .div_reg = BPDIV
121 };
122
123 static struct clk dsp_clk = {
124         .name = "dsp",
125         .parent = &pll1_sysclk1,
126         .lpsc = DAVINCI_LPSC_GEM,
127         .flags = PSC_DSP,
128         .usecount = 1,                  /* REVISIT how to disable? */
129 };
130
131 static struct clk arm_clk = {
132         .name = "arm",
133         .parent = &pll1_sysclk2,
134         .lpsc = DAVINCI_LPSC_ARM,
135         .flags = ALWAYS_ENABLED,
136 };
137
138 static struct clk vicp_clk = {
139         .name = "vicp",
140         .parent = &pll1_sysclk2,
141         .lpsc = DAVINCI_LPSC_IMCOP,
142         .flags = PSC_DSP,
143         .usecount = 1,                  /* REVISIT how to disable? */
144 };
145
146 static struct clk vpss_master_clk = {
147         .name = "vpss_master",
148         .parent = &pll1_sysclk3,
149         .lpsc = DAVINCI_LPSC_VPSSMSTR,
150         .flags = CLK_PSC,
151 };
152
153 static struct clk vpss_slave_clk = {
154         .name = "vpss_slave",
155         .parent = &pll1_sysclk3,
156         .lpsc = DAVINCI_LPSC_VPSSSLV,
157 };
158
159 static struct clk uart0_clk = {
160         .name = "uart0",
161         .parent = &pll1_aux_clk,
162         .lpsc = DAVINCI_LPSC_UART0,
163 };
164
165 static struct clk uart1_clk = {
166         .name = "uart1",
167         .parent = &pll1_aux_clk,
168         .lpsc = DAVINCI_LPSC_UART1,
169 };
170
171 static struct clk uart2_clk = {
172         .name = "uart2",
173         .parent = &pll1_aux_clk,
174         .lpsc = DAVINCI_LPSC_UART2,
175 };
176
177 static struct clk emac_clk = {
178         .name = "emac",
179         .parent = &pll1_sysclk5,
180         .lpsc = DAVINCI_LPSC_EMAC_WRAPPER,
181 };
182
183 static struct clk i2c_clk = {
184         .name = "i2c",
185         .parent = &pll1_aux_clk,
186         .lpsc = DAVINCI_LPSC_I2C,
187 };
188
189 static struct clk ide_clk = {
190         .name = "ide",
191         .parent = &pll1_sysclk5,
192         .lpsc = DAVINCI_LPSC_ATA,
193 };
194
195 static struct clk asp_clk = {
196         .name = "asp0",
197         .parent = &pll1_sysclk5,
198         .lpsc = DAVINCI_LPSC_McBSP,
199 };
200
201 static struct clk mmcsd_clk = {
202         .name = "mmcsd",
203         .parent = &pll1_sysclk5,
204         .lpsc = DAVINCI_LPSC_MMC_SD,
205 };
206
207 static struct clk spi_clk = {
208         .name = "spi",
209         .parent = &pll1_sysclk5,
210         .lpsc = DAVINCI_LPSC_SPI,
211 };
212
213 static struct clk gpio_clk = {
214         .name = "gpio",
215         .parent = &pll1_sysclk5,
216         .lpsc = DAVINCI_LPSC_GPIO,
217 };
218
219 static struct clk usb_clk = {
220         .name = "usb",
221         .parent = &pll1_sysclk5,
222         .lpsc = DAVINCI_LPSC_USB,
223 };
224
225 static struct clk vlynq_clk = {
226         .name = "vlynq",
227         .parent = &pll1_sysclk5,
228         .lpsc = DAVINCI_LPSC_VLYNQ,
229 };
230
231 static struct clk aemif_clk = {
232         .name = "aemif",
233         .parent = &pll1_sysclk5,
234         .lpsc = DAVINCI_LPSC_AEMIF,
235 };
236
237 static struct clk pwm0_clk = {
238         .name = "pwm0",
239         .parent = &pll1_aux_clk,
240         .lpsc = DAVINCI_LPSC_PWM0,
241 };
242
243 static struct clk pwm1_clk = {
244         .name = "pwm1",
245         .parent = &pll1_aux_clk,
246         .lpsc = DAVINCI_LPSC_PWM1,
247 };
248
249 static struct clk pwm2_clk = {
250         .name = "pwm2",
251         .parent = &pll1_aux_clk,
252         .lpsc = DAVINCI_LPSC_PWM2,
253 };
254
255 static struct clk timer0_clk = {
256         .name = "timer0",
257         .parent = &pll1_aux_clk,
258         .lpsc = DAVINCI_LPSC_TIMER0,
259 };
260
261 static struct clk timer1_clk = {
262         .name = "timer1",
263         .parent = &pll1_aux_clk,
264         .lpsc = DAVINCI_LPSC_TIMER1,
265 };
266
267 static struct clk timer2_clk = {
268         .name = "timer2",
269         .parent = &pll1_aux_clk,
270         .lpsc = DAVINCI_LPSC_TIMER2,
271         .usecount = 1,              /* REVISIT: why cant' this be disabled? */
272 };
273
274 struct davinci_clk dm644x_clks[] = {
275         CLK(NULL, "ref", &ref_clk),
276         CLK(NULL, "pll1", &pll1_clk),
277         CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
278         CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
279         CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
280         CLK(NULL, "pll1_sysclk5", &pll1_sysclk5),
281         CLK(NULL, "pll1_aux", &pll1_aux_clk),
282         CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp),
283         CLK(NULL, "pll2", &pll2_clk),
284         CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
285         CLK(NULL, "pll2_sysclk2", &pll2_sysclk2),
286         CLK(NULL, "pll2_sysclkbp", &pll2_sysclkbp),
287         CLK(NULL, "dsp", &dsp_clk),
288         CLK(NULL, "arm", &arm_clk),
289         CLK(NULL, "vicp", &vicp_clk),
290         CLK(NULL, "vpss_master", &vpss_master_clk),
291         CLK(NULL, "vpss_slave", &vpss_slave_clk),
292         CLK(NULL, "arm", &arm_clk),
293         CLK(NULL, "uart0", &uart0_clk),
294         CLK(NULL, "uart1", &uart1_clk),
295         CLK(NULL, "uart2", &uart2_clk),
296         CLK("davinci_emac.1", NULL, &emac_clk),
297         CLK("i2c_davinci.1", NULL, &i2c_clk),
298         CLK("palm_bk3710", NULL, &ide_clk),
299         CLK("soc-audio.0", NULL, &asp_clk),
300         CLK("davinci_mmc.0", NULL, &mmcsd_clk),
301         CLK(NULL, "spi", &spi_clk),
302         CLK(NULL, "gpio", &gpio_clk),
303         CLK(NULL, "usb", &usb_clk),
304         CLK(NULL, "vlynq", &vlynq_clk),
305         CLK(NULL, "aemif", &aemif_clk),
306         CLK(NULL, "pwm0", &pwm0_clk),
307         CLK(NULL, "pwm1", &pwm1_clk),
308         CLK(NULL, "pwm2", &pwm2_clk),
309         CLK(NULL, "timer0", &timer0_clk),
310         CLK(NULL, "timer1", &timer1_clk),
311         CLK("watchdog", NULL, &timer2_clk),
312         CLK(NULL, NULL, NULL),
313 };
314
315 #if defined(CONFIG_TI_DAVINCI_EMAC) || defined(CONFIG_TI_DAVINCI_EMAC_MODULE)
316
317 static struct resource dm644x_emac_resources[] = {
318         {
319                 .start  = DM644X_EMAC_BASE,
320                 .end    = DM644X_EMAC_BASE + 0x47ff,
321                 .flags  = IORESOURCE_MEM,
322         },
323         {
324                 .start = IRQ_EMACINT,
325                 .end   = IRQ_EMACINT,
326                 .flags = IORESOURCE_IRQ,
327         },
328 };
329
330 static struct platform_device dm644x_emac_device = {
331        .name            = "davinci_emac",
332        .id              = 1,
333        .num_resources   = ARRAY_SIZE(dm644x_emac_resources),
334        .resource        = dm644x_emac_resources,
335 };
336
337 #endif
338
339 /*
340  * Device specific mux setup
341  *
342  *      soc     description     mux  mode   mode  mux    dbg
343  *                              reg  offset mask  mode
344  */
345 static const struct mux_config dm644x_pins[] = {
346 MUX_CFG(DM644X, HDIREN,         0,   16,    1,    1,     true)
347 MUX_CFG(DM644X, ATAEN,          0,   17,    1,    1,     true)
348 MUX_CFG(DM644X, ATAEN_DISABLE,  0,   17,    1,    0,     true)
349
350 MUX_CFG(DM644X, HPIEN_DISABLE,  0,   29,    1,    0,     true)
351
352 MUX_CFG(DM644X, AEAW,           0,   0,     31,   31,    true)
353
354 MUX_CFG(DM644X, MSTK,           1,   9,     1,    0,     false)
355
356 MUX_CFG(DM644X, I2C,            1,   7,     1,    1,     false)
357
358 MUX_CFG(DM644X, MCBSP,          1,   10,    1,    1,     false)
359
360 MUX_CFG(DM644X, UART1,          1,   1,     1,    1,     true)
361 MUX_CFG(DM644X, UART2,          1,   2,     1,    1,     true)
362
363 MUX_CFG(DM644X, PWM0,           1,   4,     1,    1,     false)
364
365 MUX_CFG(DM644X, PWM1,           1,   5,     1,    1,     false)
366
367 MUX_CFG(DM644X, PWM2,           1,   6,     1,    1,     false)
368
369 MUX_CFG(DM644X, VLYNQEN,        0,   15,    1,    1,     false)
370 MUX_CFG(DM644X, VLSCREN,        0,   14,    1,    1,     false)
371 MUX_CFG(DM644X, VLYNQWD,        0,   12,    3,    3,     false)
372
373 MUX_CFG(DM644X, EMACEN,         0,   31,    1,    1,     true)
374
375 MUX_CFG(DM644X, GPIO3V,         0,   31,    1,    0,     true)
376
377 MUX_CFG(DM644X, GPIO0,          0,   24,    1,    0,     true)
378 MUX_CFG(DM644X, GPIO3,          0,   25,    1,    0,     false)
379 MUX_CFG(DM644X, GPIO43_44,      1,   7,     1,    0,     false)
380 MUX_CFG(DM644X, GPIO46_47,      0,   22,    1,    0,     true)
381
382 MUX_CFG(DM644X, RGB666,         0,   22,    1,    1,     true)
383
384 MUX_CFG(DM644X, LOEEN,          0,   24,    1,    1,     true)
385 MUX_CFG(DM644X, LFLDEN,         0,   25,    1,    1,     false)
386 };
387
388
389 /*----------------------------------------------------------------------*/
390
391 static const s8 dma_chan_dm644x_no_event[] = {
392          0,  1, 12, 13, 14,
393         15, 25, 30, 31, 45,
394         46, 47, 55, 56, 57,
395         58, 59, 60, 61, 62,
396         63,
397         -1
398 };
399
400 static struct edma_soc_info dm644x_edma_info = {
401         .n_channel      = 64,
402         .n_region       = 4,
403         .n_slot         = 128,
404         .n_tc           = 2,
405         .noevent        = dma_chan_dm644x_no_event,
406 };
407
408 static struct resource edma_resources[] = {
409         {
410                 .name   = "edma_cc",
411                 .start  = 0x01c00000,
412                 .end    = 0x01c00000 + SZ_64K - 1,
413                 .flags  = IORESOURCE_MEM,
414         },
415         {
416                 .name   = "edma_tc0",
417                 .start  = 0x01c10000,
418                 .end    = 0x01c10000 + SZ_1K - 1,
419                 .flags  = IORESOURCE_MEM,
420         },
421         {
422                 .name   = "edma_tc1",
423                 .start  = 0x01c10400,
424                 .end    = 0x01c10400 + SZ_1K - 1,
425                 .flags  = IORESOURCE_MEM,
426         },
427         {
428                 .start  = IRQ_CCINT0,
429                 .flags  = IORESOURCE_IRQ,
430         },
431         {
432                 .start  = IRQ_CCERRINT,
433                 .flags  = IORESOURCE_IRQ,
434         },
435         /* not using TC*_ERR */
436 };
437
438 static struct platform_device dm644x_edma_device = {
439         .name                   = "edma",
440         .id                     = -1,
441         .dev.platform_data      = &dm644x_edma_info,
442         .num_resources          = ARRAY_SIZE(edma_resources),
443         .resource               = edma_resources,
444 };
445
446 /*----------------------------------------------------------------------*/
447 void __init dm644x_init(void)
448 {
449         davinci_clk_init(dm644x_clks);
450         davinci_mux_register(dm644x_pins, ARRAY_SIZE(dm644x_pins));
451 }
452
453 static int __init dm644x_init_devices(void)
454 {
455         if (!cpu_is_davinci_dm644x())
456                 return 0;
457
458         platform_device_register(&dm644x_edma_device);
459         return 0;
460 }
461 postcore_initcall(dm644x_init_devices);