git.oblomov.eu Git - linux-2.6/blob - drivers/net/wireless/ath9k/main.c

   1 /*
   2  * Copyright (c) 2008-2009 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/nl80211.h>
  18 #include "ath9k.h"
  19
  20 #define ATH_PCI_VERSION "0.1"
  21
  22 static char *dev_info = "ath9k";
  23
  24 MODULE_AUTHOR("Atheros Communications");
  25 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
  26 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
  27 MODULE_LICENSE("Dual BSD/GPL");
  28
  29 static int modparam_nohwcrypt;
  30 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
  31 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
  32
  33 /* We use the hw_value as an index into our private channel structure */
  34
  35 #define CHAN2G(_freq, _idx)  { \
  36         .center_freq = (_freq), \
  37         .hw_value = (_idx), \
  38         .max_power = 30, \
  39 }
  40
  41 #define CHAN5G(_freq, _idx) { \
  42         .band = IEEE80211_BAND_5GHZ, \
  43         .center_freq = (_freq), \
  44         .hw_value = (_idx), \
  45         .max_power = 30, \
  46 }
  47
  48 /* Some 2 GHz radios are actually tunable on 2312-2732
  49  * on 5 MHz steps, we support the channels which we know
  50  * we have calibration data for all cards though to make
  51  * this static */
  52 static struct ieee80211_channel ath9k_2ghz_chantable[] = {
  53         CHAN2G(2412, 0), /* Channel 1 */
  54         CHAN2G(2417, 1), /* Channel 2 */
  55         CHAN2G(2422, 2), /* Channel 3 */
  56         CHAN2G(2427, 3), /* Channel 4 */
  57         CHAN2G(2432, 4), /* Channel 5 */
  58         CHAN2G(2437, 5), /* Channel 6 */
  59         CHAN2G(2442, 6), /* Channel 7 */
  60         CHAN2G(2447, 7), /* Channel 8 */
  61         CHAN2G(2452, 8), /* Channel 9 */
  62         CHAN2G(2457, 9), /* Channel 10 */
  63         CHAN2G(2462, 10), /* Channel 11 */
  64         CHAN2G(2467, 11), /* Channel 12 */
  65         CHAN2G(2472, 12), /* Channel 13 */
  66         CHAN2G(2484, 13), /* Channel 14 */
  67 };
  68
  69 /* Some 5 GHz radios are actually tunable on XXXX-YYYY
  70  * on 5 MHz steps, we support the channels which we know
  71  * we have calibration data for all cards though to make
  72  * this static */
  73 static struct ieee80211_channel ath9k_5ghz_chantable[] = {
  74         /* _We_ call this UNII 1 */
  75         CHAN5G(5180, 14), /* Channel 36 */
  76         CHAN5G(5200, 15), /* Channel 40 */
  77         CHAN5G(5220, 16), /* Channel 44 */
  78         CHAN5G(5240, 17), /* Channel 48 */
  79         /* _We_ call this UNII 2 */
  80         CHAN5G(5260, 18), /* Channel 52 */
  81         CHAN5G(5280, 19), /* Channel 56 */
  82         CHAN5G(5300, 20), /* Channel 60 */
  83         CHAN5G(5320, 21), /* Channel 64 */
  84         /* _We_ call this "Middle band" */
  85         CHAN5G(5500, 22), /* Channel 100 */
  86         CHAN5G(5520, 23), /* Channel 104 */
  87         CHAN5G(5540, 24), /* Channel 108 */
  88         CHAN5G(5560, 25), /* Channel 112 */
  89         CHAN5G(5580, 26), /* Channel 116 */
  90         CHAN5G(5600, 27), /* Channel 120 */
  91         CHAN5G(5620, 28), /* Channel 124 */
  92         CHAN5G(5640, 29), /* Channel 128 */
  93         CHAN5G(5660, 30), /* Channel 132 */
  94         CHAN5G(5680, 31), /* Channel 136 */
  95         CHAN5G(5700, 32), /* Channel 140 */
  96         /* _We_ call this UNII 3 */
  97         CHAN5G(5745, 33), /* Channel 149 */
  98         CHAN5G(5765, 34), /* Channel 153 */
  99         CHAN5G(5785, 35), /* Channel 157 */
 100         CHAN5G(5805, 36), /* Channel 161 */
 101         CHAN5G(5825, 37), /* Channel 165 */
 102 };
 103
 104 static void ath_cache_conf_rate(struct ath_softc *sc,
 105                                 struct ieee80211_conf *conf)
 106 {
 107         switch (conf->channel->band) {
 108         case IEEE80211_BAND_2GHZ:
 109                 if (conf_is_ht20(conf))
 110                         sc->cur_rate_table =
 111                           sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
 112                 else if (conf_is_ht40_minus(conf))
 113                         sc->cur_rate_table =
 114                           sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
 115                 else if (conf_is_ht40_plus(conf))
 116                         sc->cur_rate_table =
 117                           sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
 118                 else
 119                         sc->cur_rate_table =
 120                           sc->hw_rate_table[ATH9K_MODE_11G];
 121                 break;
 122         case IEEE80211_BAND_5GHZ:
 123                 if (conf_is_ht20(conf))
 124                         sc->cur_rate_table =
 125                           sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
 126                 else if (conf_is_ht40_minus(conf))
 127                         sc->cur_rate_table =
 128                           sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
 129                 else if (conf_is_ht40_plus(conf))
 130                         sc->cur_rate_table =
 131                           sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
 132                 else
 133                         sc->cur_rate_table =
 134                           sc->hw_rate_table[ATH9K_MODE_11A];
 135                 break;
 136         default:
 137                 BUG_ON(1);
 138                 break;
 139         }
 140 }
 141
 142 static void ath_update_txpow(struct ath_softc *sc)
 143 {
 144         struct ath_hw *ah = sc->sc_ah;
 145         u32 txpow;
 146
 147         if (sc->curtxpow != sc->config.txpowlimit) {
 148                 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
 149                 /* read back in case value is clamped */
 150                 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
 151                 sc->curtxpow = txpow;
 152         }
 153 }
 154
 155 static u8 parse_mpdudensity(u8 mpdudensity)
 156 {
 157         /*
 158          * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
 159          *   0 for no restriction
 160          *   1 for 1/4 us
 161          *   2 for 1/2 us
 162          *   3 for 1 us
 163          *   4 for 2 us
 164          *   5 for 4 us
 165          *   6 for 8 us
 166          *   7 for 16 us
 167          */
 168         switch (mpdudensity) {
 169         case 0:
 170                 return 0;
 171         case 1:
 172         case 2:
 173         case 3:
 174                 /* Our lower layer calculations limit our precision to
 175                    1 microsecond */
 176                 return 1;
 177         case 4:
 178                 return 2;
 179         case 5:
 180                 return 4;
 181         case 6:
 182                 return 8;
 183         case 7:
 184                 return 16;
 185         default:
 186                 return 0;
 187         }
 188 }
 189
 190 static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
 191 {
 192         struct ath_rate_table *rate_table = NULL;
 193         struct ieee80211_supported_band *sband;
 194         struct ieee80211_rate *rate;
 195         int i, maxrates;
 196
 197         switch (band) {
 198         case IEEE80211_BAND_2GHZ:
 199                 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
 200                 break;
 201         case IEEE80211_BAND_5GHZ:
 202                 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
 203                 break;
 204         default:
 205                 break;
 206         }
 207
 208         if (rate_table == NULL)
 209                 return;
 210
 211         sband = &sc->sbands[band];
 212         rate = sc->rates[band];
 213
 214         if (rate_table->rate_cnt > ATH_RATE_MAX)
 215                 maxrates = ATH_RATE_MAX;
 216         else
 217                 maxrates = rate_table->rate_cnt;
 218
 219         for (i = 0; i < maxrates; i++) {
 220                 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
 221                 rate[i].hw_value = rate_table->info[i].ratecode;
 222                 if (rate_table->info[i].short_preamble) {
 223                         rate[i].hw_value_short = rate_table->info[i].ratecode |
 224                                 rate_table->info[i].short_preamble;
 225                         rate[i].flags = IEEE80211_RATE_SHORT_PREAMBLE;
 226                 }
 227                 sband->n_bitrates++;
 228
 229                 DPRINTF(sc, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
 230                         rate[i].bitrate / 10, rate[i].hw_value);
 231         }
 232 }
 233
 234 /*
 235  * Set/change channels.  If the channel is really being changed, it's done
 236  * by reseting the chip.  To accomplish this we must first cleanup any pending
 237  * DMA, then restart stuff.
 238 */
 239 int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
 240                     struct ath9k_channel *hchan)
 241 {
 242         struct ath_hw *ah = sc->sc_ah;
 243         bool fastcc = true, stopped;
 244         struct ieee80211_channel *channel = hw->conf.channel;
 245         int r;
 246
 247         if (sc->sc_flags & SC_OP_INVALID)
 248                 return -EIO;
 249
 250         ath9k_ps_wakeup(sc);
 251
 252         /*
 253          * This is only performed if the channel settings have
 254          * actually changed.
 255          *
 256          * To switch channels clear any pending DMA operations;
 257          * wait long enough for the RX fifo to drain, reset the
 258          * hardware at the new frequency, and then re-enable
 259          * the relevant bits of the h/w.
 260          */
 261         ath9k_hw_set_interrupts(ah, 0);
 262         ath_drain_all_txq(sc, false);
 263         stopped = ath_stoprecv(sc);
 264
 265         /* XXX: do not flush receive queue here. We don't want
 266          * to flush data frames already in queue because of
 267          * changing channel. */
 268
 269         if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
 270                 fastcc = false;
 271
 272         DPRINTF(sc, ATH_DBG_CONFIG,
 273                 "(%u MHz) -> (%u MHz), chanwidth: %d\n",
 274                 sc->sc_ah->curchan->channel,
 275                 channel->center_freq, sc->tx_chan_width);
 276
 277         spin_lock_bh(&sc->sc_resetlock);
 278
 279         r = ath9k_hw_reset(ah, hchan, fastcc);
 280         if (r) {
 281                 DPRINTF(sc, ATH_DBG_FATAL,
 282                         "Unable to reset channel (%u Mhz) "
 283                         "reset status %u\n",
 284                         channel->center_freq, r);
 285                 spin_unlock_bh(&sc->sc_resetlock);
 286                 return r;
 287         }
 288         spin_unlock_bh(&sc->sc_resetlock);
 289
 290         sc->sc_flags &= ~SC_OP_CHAINMASK_UPDATE;
 291         sc->sc_flags &= ~SC_OP_FULL_RESET;
 292
 293         if (ath_startrecv(sc) != 0) {
 294                 DPRINTF(sc, ATH_DBG_FATAL,
 295                         "Unable to restart recv logic\n");
 296                 return -EIO;
 297         }
 298
 299         ath_cache_conf_rate(sc, &hw->conf);
 300         ath_update_txpow(sc);
 301         ath9k_hw_set_interrupts(ah, sc->imask);
 302         ath9k_ps_restore(sc);
 303         return 0;
 304 }
 305
 306 /*
 307  *  This routine performs the periodic noise floor calibration function
 308  *  that is used to adjust and optimize the chip performance.  This
 309  *  takes environmental changes (location, temperature) into account.
 310  *  When the task is complete, it reschedules itself depending on the
 311  *  appropriate interval that was calculated.
 312  */
 313 static void ath_ani_calibrate(unsigned long data)
 314 {
 315         struct ath_softc *sc = (struct ath_softc *)data;
 316         struct ath_hw *ah = sc->sc_ah;
 317         bool longcal = false;
 318         bool shortcal = false;
 319         bool aniflag = false;
 320         unsigned int timestamp = jiffies_to_msecs(jiffies);
 321         u32 cal_interval, short_cal_interval;
 322
 323         short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
 324                 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
 325
 326         /*
 327         * don't calibrate when we're scanning.
 328         * we are most likely not on our home channel.
 329         */
 330         if (sc->sc_flags & SC_OP_SCANNING)
 331                 goto set_timer;
 332
 333         /* Long calibration runs independently of short calibration. */
 334         if ((timestamp - sc->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
 335                 longcal = true;
 336                 DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
 337                 sc->ani.longcal_timer = timestamp;
 338         }
 339
 340         /* Short calibration applies only while caldone is false */
 341         if (!sc->ani.caldone) {
 342                 if ((timestamp - sc->ani.shortcal_timer) >= short_cal_interval) {
 343                         shortcal = true;
 344                         DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
 345                         sc->ani.shortcal_timer = timestamp;
 346                         sc->ani.resetcal_timer = timestamp;
 347                 }
 348         } else {
 349                 if ((timestamp - sc->ani.resetcal_timer) >=
 350                     ATH_RESTART_CALINTERVAL) {
 351                         sc->ani.caldone = ath9k_hw_reset_calvalid(ah);
 352                         if (sc->ani.caldone)
 353                                 sc->ani.resetcal_timer = timestamp;
 354                 }
 355         }
 356
 357         /* Verify whether we must check ANI */
 358         if ((timestamp - sc->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) {
 359                 aniflag = true;
 360                 sc->ani.checkani_timer = timestamp;
 361         }
 362
 363         /* Skip all processing if there's nothing to do. */
 364         if (longcal || shortcal || aniflag) {
 365                 /* Call ANI routine if necessary */
 366                 if (aniflag)
 367                         ath9k_hw_ani_monitor(ah, &sc->nodestats, ah->curchan);
 368
 369                 /* Perform calibration if necessary */
 370                 if (longcal || shortcal) {
 371                         bool iscaldone = false;
 372
 373                         if (ath9k_hw_calibrate(ah, ah->curchan,
 374                                                sc->rx_chainmask, longcal,
 375                                                &iscaldone)) {
 376                                 if (longcal)
 377                                         sc->ani.noise_floor =
 378                                                 ath9k_hw_getchan_noise(ah,
 379                                                                ah->curchan);
 380
 381                                 DPRINTF(sc, ATH_DBG_ANI,
 382                                         "calibrate chan %u/%x nf: %d\n",
 383                                         ah->curchan->channel,
 384                                         ah->curchan->channelFlags,
 385                                         sc->ani.noise_floor);
 386                         } else {
 387                                 DPRINTF(sc, ATH_DBG_ANY,
 388                                         "calibrate chan %u/%x failed\n",
 389                                         ah->curchan->channel,
 390                                         ah->curchan->channelFlags);
 391                         }
 392                         sc->ani.caldone = iscaldone;
 393                 }
 394         }
 395
 396 set_timer:
 397         /*
 398         * Set timer interval based on previous results.
 399         * The interval must be the shortest necessary to satisfy ANI,
 400         * short calibration and long calibration.
 401         */
 402         cal_interval = ATH_LONG_CALINTERVAL;
 403         if (sc->sc_ah->config.enable_ani)
 404                 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
 405         if (!sc->ani.caldone)
 406                 cal_interval = min(cal_interval, (u32)short_cal_interval);
 407
 408         mod_timer(&sc->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
 409 }
 410
 411 /*
 412  * Update tx/rx chainmask. For legacy association,
 413  * hard code chainmask to 1x1, for 11n association, use
 414  * the chainmask configuration, for bt coexistence, use
 415  * the chainmask configuration even in legacy mode.
 416  */
 417 void ath_update_chainmask(struct ath_softc *sc, int is_ht)
 418 {
 419         sc->sc_flags |= SC_OP_CHAINMASK_UPDATE;
 420         if (is_ht ||
 421             (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)) {
 422                 sc->tx_chainmask = sc->sc_ah->caps.tx_chainmask;
 423                 sc->rx_chainmask = sc->sc_ah->caps.rx_chainmask;
 424         } else {
 425                 sc->tx_chainmask = 1;
 426                 sc->rx_chainmask = 1;
 427         }
 428
 429         DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
 430                 sc->tx_chainmask, sc->rx_chainmask);
 431 }
 432
 433 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
 434 {
 435         struct ath_node *an;
 436
 437         an = (struct ath_node *)sta->drv_priv;
 438
 439         if (sc->sc_flags & SC_OP_TXAGGR)
 440                 ath_tx_node_init(sc, an);
 441
 442         an->maxampdu = 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR +
 443                              sta->ht_cap.ampdu_factor);
 444         an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
 445 }
 446
 447 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
 448 {
 449         struct ath_node *an = (struct ath_node *)sta->drv_priv;
 450
 451         if (sc->sc_flags & SC_OP_TXAGGR)
 452                 ath_tx_node_cleanup(sc, an);
 453 }
 454
 455 static void ath9k_tasklet(unsigned long data)
 456 {
 457         struct ath_softc *sc = (struct ath_softc *)data;
 458         u32 status = sc->intrstatus;
 459
 460         if (status & ATH9K_INT_FATAL) {
 461                 /* need a chip reset */
 462                 ath_reset(sc, false);
 463                 return;
 464         } else {
 465
 466                 if (status &
 467                     (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
 468                         spin_lock_bh(&sc->rx.rxflushlock);
 469                         ath_rx_tasklet(sc, 0);
 470                         spin_unlock_bh(&sc->rx.rxflushlock);
 471                 }
 472                 /* XXX: optimize this */
 473                 if (status & ATH9K_INT_TX)
 474                         ath_tx_tasklet(sc);
 475         }
 476
 477         /* re-enable hardware interrupt */
 478         ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
 479 }
 480
 481 irqreturn_t ath_isr(int irq, void *dev)
 482 {
 483         struct ath_softc *sc = dev;
 484         struct ath_hw *ah = sc->sc_ah;
 485         enum ath9k_int status;
 486         bool sched = false;
 487
 488         do {
 489                 if (sc->sc_flags & SC_OP_INVALID) {
 490                         /*
 491                          * The hardware is not ready/present, don't
 492                          * touch anything. Note this can happen early
 493                          * on if the IRQ is shared.
 494                          */
 495                         return IRQ_NONE;
 496                 }
 497                 if (!ath9k_hw_intrpend(ah)) {   /* shared irq, not for us */
 498                         return IRQ_NONE;
 499                 }
 500
 501                 /*
 502                  * Figure out the reason(s) for the interrupt.  Note
 503                  * that the hal returns a pseudo-ISR that may include
 504                  * bits we haven't explicitly enabled so we mask the
 505                  * value to insure we only process bits we requested.
 506                  */
 507                 ath9k_hw_getisr(ah, &status);   /* NB: clears ISR too */
 508
 509                 status &= sc->imask;    /* discard unasked-for bits */
 510
 511                 /*
 512                  * If there are no status bits set, then this interrupt was not
 513                  * for me (should have been caught above).
 514                  */
 515                 if (!status)
 516                         return IRQ_NONE;
 517
 518                 sc->intrstatus = status;
 519                 ath9k_ps_wakeup(sc);
 520
 521                 if (status & ATH9K_INT_FATAL) {
 522                         /* need a chip reset */
 523                         sched = true;
 524                 } else if (status & ATH9K_INT_RXORN) {
 525                         /* need a chip reset */
 526                         sched = true;
 527                 } else {
 528                         if (status & ATH9K_INT_SWBA) {
 529                                 /* schedule a tasklet for beacon handling */
 530                                 tasklet_schedule(&sc->bcon_tasklet);
 531                         }
 532                         if (status & ATH9K_INT_RXEOL) {
 533                                 /*
 534                                  * NB: the hardware should re-read the link when
 535                                  *     RXE bit is written, but it doesn't work
 536                                  *     at least on older hardware revs.
 537                                  */
 538                                 sched = true;
 539                         }
 540
 541                         if (status & ATH9K_INT_TXURN)
 542                                 /* bump tx trigger level */
 543                                 ath9k_hw_updatetxtriglevel(ah, true);
 544                         /* XXX: optimize this */
 545                         if (status & ATH9K_INT_RX)
 546                                 sched = true;
 547                         if (status & ATH9K_INT_TX)
 548                                 sched = true;
 549                         if (status & ATH9K_INT_BMISS)
 550                                 sched = true;
 551                         /* carrier sense timeout */
 552                         if (status & ATH9K_INT_CST)
 553                                 sched = true;
 554                         if (status & ATH9K_INT_MIB) {
 555                                 /*
 556                                  * Disable interrupts until we service the MIB
 557                                  * interrupt; otherwise it will continue to
 558                                  * fire.
 559                                  */
 560                                 ath9k_hw_set_interrupts(ah, 0);
 561                                 /*
 562                                  * Let the hal handle the event. We assume
 563                                  * it will clear whatever condition caused
 564                                  * the interrupt.
 565                                  */
 566                                 ath9k_hw_procmibevent(ah, &sc->nodestats);
 567                                 ath9k_hw_set_interrupts(ah, sc->imask);
 568                         }
 569                         if (status & ATH9K_INT_TIM_TIMER) {
 570                                 if (!(ah->caps.hw_caps &
 571                                       ATH9K_HW_CAP_AUTOSLEEP)) {
 572                                         /* Clear RxAbort bit so that we can
 573                                          * receive frames */
 574                                         ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
 575                                         ath9k_hw_setrxabort(ah, 0);
 576                                         sched = true;
 577                                         sc->sc_flags |= SC_OP_WAIT_FOR_BEACON;
 578                                 }
 579                         }
 580                         if (status & ATH9K_INT_TSFOOR) {
 581                                 /* FIXME: Handle this interrupt for power save */
 582                                 sched = true;
 583                         }
 584                 }
 585                 ath9k_ps_restore(sc);
 586         } while (0);
 587
 588         ath_debug_stat_interrupt(sc, status);
 589
 590         if (sched) {
 591                 /* turn off every interrupt except SWBA */
 592                 ath9k_hw_set_interrupts(ah, (sc->imask & ATH9K_INT_SWBA));
 593                 tasklet_schedule(&sc->intr_tq);
 594         }
 595
 596         return IRQ_HANDLED;
 597 }
 598
 599 static u32 ath_get_extchanmode(struct ath_softc *sc,
 600                                struct ieee80211_channel *chan,
 601                                enum nl80211_channel_type channel_type)
 602 {
 603         u32 chanmode = 0;
 604
 605         switch (chan->band) {
 606         case IEEE80211_BAND_2GHZ:
 607                 switch(channel_type) {
 608                 case NL80211_CHAN_NO_HT:
 609                 case NL80211_CHAN_HT20:
 610                         chanmode = CHANNEL_G_HT20;
 611                         break;
 612                 case NL80211_CHAN_HT40PLUS:
 613                         chanmode = CHANNEL_G_HT40PLUS;
 614                         break;
 615                 case NL80211_CHAN_HT40MINUS:
 616                         chanmode = CHANNEL_G_HT40MINUS;
 617                         break;
 618                 }
 619                 break;
 620         case IEEE80211_BAND_5GHZ:
 621                 switch(channel_type) {
 622                 case NL80211_CHAN_NO_HT:
 623                 case NL80211_CHAN_HT20:
 624                         chanmode = CHANNEL_A_HT20;
 625                         break;
 626                 case NL80211_CHAN_HT40PLUS:
 627                         chanmode = CHANNEL_A_HT40PLUS;
 628                         break;
 629                 case NL80211_CHAN_HT40MINUS:
 630                         chanmode = CHANNEL_A_HT40MINUS;
 631                         break;
 632                 }
 633                 break;
 634         default:
 635                 break;
 636         }
 637
 638         return chanmode;
 639 }
 640
 641 static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
 642                            struct ath9k_keyval *hk, const u8 *addr,
 643                            bool authenticator)
 644 {
 645         const u8 *key_rxmic;
 646         const u8 *key_txmic;
 647
 648         key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
 649         key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
 650
 651         if (addr == NULL) {
 652                 /*
 653                  * Group key installation - only two key cache entries are used
 654                  * regardless of splitmic capability since group key is only
 655                  * used either for TX or RX.
 656                  */
 657                 if (authenticator) {
 658                         memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
 659                         memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_mic));
 660                 } else {
 661                         memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
 662                         memcpy(hk->kv_txmic, key_rxmic, sizeof(hk->kv_mic));
 663                 }
 664                 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
 665         }
 666         if (!sc->splitmic) {
 667                 /* TX and RX keys share the same key cache entry. */
 668                 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
 669                 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
 670                 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
 671         }
 672
 673         /* Separate key cache entries for TX and RX */
 674
 675         /* TX key goes at first index, RX key at +32. */
 676         memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
 677         if (!ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, NULL)) {
 678                 /* TX MIC entry failed. No need to proceed further */
 679                 DPRINTF(sc, ATH_DBG_KEYCACHE,
 680                         "Setting TX MIC Key Failed\n");
 681                 return 0;
 682         }
 683
 684         memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
 685         /* XXX delete tx key on failure? */
 686         return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix + 32, hk, addr);
 687 }
 688
 689 static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
 690 {
 691         int i;
 692
 693         for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
 694                 if (test_bit(i, sc->keymap) ||
 695                     test_bit(i + 64, sc->keymap))
 696                         continue; /* At least one part of TKIP key allocated */
 697                 if (sc->splitmic &&
 698                     (test_bit(i + 32, sc->keymap) ||
 699                      test_bit(i + 64 + 32, sc->keymap)))
 700                         continue; /* At least one part of TKIP key allocated */
 701
 702                 /* Found a free slot for a TKIP key */
 703                 return i;
 704         }
 705         return -1;
 706 }
 707
 708 static int ath_reserve_key_cache_slot(struct ath_softc *sc)
 709 {
 710         int i;
 711
 712         /* First, try to find slots that would not be available for TKIP. */
 713         if (sc->splitmic) {
 714                 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 4; i++) {
 715                         if (!test_bit(i, sc->keymap) &&
 716                             (test_bit(i + 32, sc->keymap) ||
 717                              test_bit(i + 64, sc->keymap) ||
 718                              test_bit(i + 64 + 32, sc->keymap)))
 719                                 return i;
 720                         if (!test_bit(i + 32, sc->keymap) &&
 721                             (test_bit(i, sc->keymap) ||
 722                              test_bit(i + 64, sc->keymap) ||
 723                              test_bit(i + 64 + 32, sc->keymap)))
 724                                 return i + 32;
 725                         if (!test_bit(i + 64, sc->keymap) &&
 726                             (test_bit(i , sc->keymap) ||
 727                              test_bit(i + 32, sc->keymap) ||
 728                              test_bit(i + 64 + 32, sc->keymap)))
 729                                 return i + 64;
 730                         if (!test_bit(i + 64 + 32, sc->keymap) &&
 731                             (test_bit(i, sc->keymap) ||
 732                              test_bit(i + 32, sc->keymap) ||
 733                              test_bit(i + 64, sc->keymap)))
 734                                 return i + 64 + 32;
 735                 }
 736         } else {
 737                 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
 738                         if (!test_bit(i, sc->keymap) &&
 739                             test_bit(i + 64, sc->keymap))
 740                                 return i;
 741                         if (test_bit(i, sc->keymap) &&
 742                             !test_bit(i + 64, sc->keymap))
 743                                 return i + 64;
 744                 }
 745         }
 746
 747         /* No partially used TKIP slots, pick any available slot */
 748         for (i = IEEE80211_WEP_NKID; i < sc->keymax; i++) {
 749                 /* Do not allow slots that could be needed for TKIP group keys
 750                  * to be used. This limitation could be removed if we know that
 751                  * TKIP will not be used. */
 752                 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
 753                         continue;
 754                 if (sc->splitmic) {
 755                         if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
 756                                 continue;
 757                         if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
 758                                 continue;
 759                 }
 760
 761                 if (!test_bit(i, sc->keymap))
 762                         return i; /* Found a free slot for a key */
 763         }
 764
 765         /* No free slot found */
 766         return -1;
 767 }
 768
 769 static int ath_key_config(struct ath_softc *sc,
 770                           struct ieee80211_vif *vif,
 771                           struct ieee80211_sta *sta,
 772                           struct ieee80211_key_conf *key)
 773 {
 774         struct ath9k_keyval hk;
 775         const u8 *mac = NULL;
 776         int ret = 0;
 777         int idx;
 778
 779         memset(&hk, 0, sizeof(hk));
 780
 781         switch (key->alg) {
 782         case ALG_WEP:
 783                 hk.kv_type = ATH9K_CIPHER_WEP;
 784                 break;
 785         case ALG_TKIP:
 786                 hk.kv_type = ATH9K_CIPHER_TKIP;
 787                 break;
 788         case ALG_CCMP:
 789                 hk.kv_type = ATH9K_CIPHER_AES_CCM;
 790                 break;
 791         default:
 792                 return -EOPNOTSUPP;
 793         }
 794
 795         hk.kv_len = key->keylen;
 796         memcpy(hk.kv_val, key->key, key->keylen);
 797
 798         if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
 799                 /* For now, use the default keys for broadcast keys. This may
 800                  * need to change with virtual interfaces. */
 801                 idx = key->keyidx;
 802         } else if (key->keyidx) {
 803                 if (WARN_ON(!sta))
 804                         return -EOPNOTSUPP;
 805                 mac = sta->addr;
 806
 807                 if (vif->type != NL80211_IFTYPE_AP) {
 808                         /* Only keyidx 0 should be used with unicast key, but
 809                          * allow this for client mode for now. */
 810                         idx = key->keyidx;
 811                 } else
 812                         return -EIO;
 813         } else {
 814                 if (WARN_ON(!sta))
 815                         return -EOPNOTSUPP;
 816                 mac = sta->addr;
 817
 818                 if (key->alg == ALG_TKIP)
 819                         idx = ath_reserve_key_cache_slot_tkip(sc);
 820                 else
 821                         idx = ath_reserve_key_cache_slot(sc);
 822                 if (idx < 0)
 823                         return -ENOSPC; /* no free key cache entries */
 824         }
 825
 826         if (key->alg == ALG_TKIP)
 827                 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac,
 828                                       vif->type == NL80211_IFTYPE_AP);
 829         else
 830                 ret = ath9k_hw_set_keycache_entry(sc->sc_ah, idx, &hk, mac);
 831
 832         if (!ret)
 833                 return -EIO;
 834
 835         set_bit(idx, sc->keymap);
 836         if (key->alg == ALG_TKIP) {
 837                 set_bit(idx + 64, sc->keymap);
 838                 if (sc->splitmic) {
 839                         set_bit(idx + 32, sc->keymap);
 840                         set_bit(idx + 64 + 32, sc->keymap);
 841                 }
 842         }
 843
 844         return idx;
 845 }
 846
 847 static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
 848 {
 849         ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
 850         if (key->hw_key_idx < IEEE80211_WEP_NKID)
 851                 return;
 852
 853         clear_bit(key->hw_key_idx, sc->keymap);
 854         if (key->alg != ALG_TKIP)
 855                 return;
 856
 857         clear_bit(key->hw_key_idx + 64, sc->keymap);
 858         if (sc->splitmic) {
 859                 clear_bit(key->hw_key_idx + 32, sc->keymap);
 860                 clear_bit(key->hw_key_idx + 64 + 32, sc->keymap);
 861         }
 862 }
 863
 864 static void setup_ht_cap(struct ath_softc *sc,
 865                          struct ieee80211_sta_ht_cap *ht_info)
 866 {
 867 #define ATH9K_HT_CAP_MAXRXAMPDU_65536 0x3       /* 2 ^ 16 */
 868 #define ATH9K_HT_CAP_MPDUDENSITY_8 0x6          /* 8 usec */
 869
 870         ht_info->ht_supported = true;
 871         ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
 872                        IEEE80211_HT_CAP_SM_PS |
 873                        IEEE80211_HT_CAP_SGI_40 |
 874                        IEEE80211_HT_CAP_DSSSCCK40;
 875
 876         ht_info->ampdu_factor = ATH9K_HT_CAP_MAXRXAMPDU_65536;
 877         ht_info->ampdu_density = ATH9K_HT_CAP_MPDUDENSITY_8;
 878
 879         /* set up supported mcs set */
 880         memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
 881
 882         switch(sc->rx_chainmask) {
 883         case 1:
 884                 ht_info->mcs.rx_mask[0] = 0xff;
 885                 break;
 886         case 3:
 887         case 5:
 888         case 7:
 889         default:
 890                 ht_info->mcs.rx_mask[0] = 0xff;
 891                 ht_info->mcs.rx_mask[1] = 0xff;
 892                 break;
 893         }
 894
 895         ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
 896 }
 897
 898 static void ath9k_bss_assoc_info(struct ath_softc *sc,
 899                                  struct ieee80211_vif *vif,
 900                                  struct ieee80211_bss_conf *bss_conf)
 901 {
 902         struct ath_vif *avp = (void *)vif->drv_priv;
 903
 904         if (bss_conf->assoc) {
 905                 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
 906                         bss_conf->aid, sc->curbssid);
 907
 908                 /* New association, store aid */
 909                 if (avp->av_opmode == NL80211_IFTYPE_STATION) {
 910                         sc->curaid = bss_conf->aid;
 911                         ath9k_hw_write_associd(sc);
 912                 }
 913
 914                 /* Configure the beacon */
 915                 ath_beacon_config(sc, vif);
 916
 917                 /* Reset rssi stats */
 918                 sc->nodestats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
 919                 sc->nodestats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
 920                 sc->nodestats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
 921                 sc->nodestats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
 922
 923                 /* Start ANI */
 924                 mod_timer(&sc->ani.timer,
 925                           jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
 926         } else {
 927                 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISSOC\n");
 928                 sc->curaid = 0;
 929         }
 930 }
 931
 932 /********************************/
 933 /*       LED functions          */
 934 /********************************/
 935
 936 static void ath_led_blink_work(struct work_struct *work)
 937 {
 938         struct ath_softc *sc = container_of(work, struct ath_softc,
 939                                             ath_led_blink_work.work);
 940
 941         if (!(sc->sc_flags & SC_OP_LED_ASSOCIATED))
 942                 return;
 943
 944         if ((sc->led_on_duration == ATH_LED_ON_DURATION_IDLE) ||
 945             (sc->led_off_duration == ATH_LED_OFF_DURATION_IDLE))
 946                 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
 947         else
 948                 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
 949                                   (sc->sc_flags & SC_OP_LED_ON) ? 1 : 0);
 950
 951         queue_delayed_work(sc->hw->workqueue, &sc->ath_led_blink_work,
 952                            (sc->sc_flags & SC_OP_LED_ON) ?
 953                            msecs_to_jiffies(sc->led_off_duration) :
 954                            msecs_to_jiffies(sc->led_on_duration));
 955
 956         sc->led_on_duration = sc->led_on_cnt ?
 957                         max((ATH_LED_ON_DURATION_IDLE - sc->led_on_cnt), 25) :
 958                         ATH_LED_ON_DURATION_IDLE;
 959         sc->led_off_duration = sc->led_off_cnt ?
 960                         max((ATH_LED_OFF_DURATION_IDLE - sc->led_off_cnt), 10) :
 961                         ATH_LED_OFF_DURATION_IDLE;
 962         sc->led_on_cnt = sc->led_off_cnt = 0;
 963         if (sc->sc_flags & SC_OP_LED_ON)
 964                 sc->sc_flags &= ~SC_OP_LED_ON;
 965         else
 966                 sc->sc_flags |= SC_OP_LED_ON;
 967 }
 968
 969 static void ath_led_brightness(struct led_classdev *led_cdev,
 970                                enum led_brightness brightness)
 971 {
 972         struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
 973         struct ath_softc *sc = led->sc;
 974
 975         switch (brightness) {
 976         case LED_OFF:
 977                 if (led->led_type == ATH_LED_ASSOC ||
 978                     led->led_type == ATH_LED_RADIO) {
 979                         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
 980                                 (led->led_type == ATH_LED_RADIO));
 981                         sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
 982                         if (led->led_type == ATH_LED_RADIO)
 983                                 sc->sc_flags &= ~SC_OP_LED_ON;
 984                 } else {
 985                         sc->led_off_cnt++;
 986                 }
 987                 break;
 988         case LED_FULL:
 989                 if (led->led_type == ATH_LED_ASSOC) {
 990                         sc->sc_flags |= SC_OP_LED_ASSOCIATED;
 991                         queue_delayed_work(sc->hw->workqueue,
 992                                            &sc->ath_led_blink_work, 0);
 993                 } else if (led->led_type == ATH_LED_RADIO) {
 994                         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
 995                         sc->sc_flags |= SC_OP_LED_ON;
 996                 } else {
 997                         sc->led_on_cnt++;
 998                 }
 999                 break;
1000         default:
1001                 break;
1002         }
1003 }
1004
1005 static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
1006                             char *trigger)
1007 {
1008         int ret;
1009
1010         led->sc = sc;
1011         led->led_cdev.name = led->name;
1012         led->led_cdev.default_trigger = trigger;
1013         led->led_cdev.brightness_set = ath_led_brightness;
1014
1015         ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
1016         if (ret)
1017                 DPRINTF(sc, ATH_DBG_FATAL,
1018                         "Failed to register led:%s", led->name);
1019         else
1020                 led->registered = 1;
1021         return ret;
1022 }
1023
1024 static void ath_unregister_led(struct ath_led *led)
1025 {
1026         if (led->registered) {
1027                 led_classdev_unregister(&led->led_cdev);
1028                 led->registered = 0;
1029         }
1030 }
1031
1032 static void ath_deinit_leds(struct ath_softc *sc)
1033 {
1034         cancel_delayed_work_sync(&sc->ath_led_blink_work);
1035         ath_unregister_led(&sc->assoc_led);
1036         sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1037         ath_unregister_led(&sc->tx_led);
1038         ath_unregister_led(&sc->rx_led);
1039         ath_unregister_led(&sc->radio_led);
1040         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1041 }
1042
1043 static void ath_init_leds(struct ath_softc *sc)
1044 {
1045         char *trigger;
1046         int ret;
1047
1048         /* Configure gpio 1 for output */
1049         ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
1050                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1051         /* LED off, active low */
1052         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1053
1054         INIT_DELAYED_WORK(&sc->ath_led_blink_work, ath_led_blink_work);
1055
1056         trigger = ieee80211_get_radio_led_name(sc->hw);
1057         snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
1058                 "ath9k-%s::radio", wiphy_name(sc->hw->wiphy));
1059         ret = ath_register_led(sc, &sc->radio_led, trigger);
1060         sc->radio_led.led_type = ATH_LED_RADIO;
1061         if (ret)
1062                 goto fail;
1063
1064         trigger = ieee80211_get_assoc_led_name(sc->hw);
1065         snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
1066                 "ath9k-%s::assoc", wiphy_name(sc->hw->wiphy));
1067         ret = ath_register_led(sc, &sc->assoc_led, trigger);
1068         sc->assoc_led.led_type = ATH_LED_ASSOC;
1069         if (ret)
1070                 goto fail;
1071
1072         trigger = ieee80211_get_tx_led_name(sc->hw);
1073         snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
1074                 "ath9k-%s::tx", wiphy_name(sc->hw->wiphy));
1075         ret = ath_register_led(sc, &sc->tx_led, trigger);
1076         sc->tx_led.led_type = ATH_LED_TX;
1077         if (ret)
1078                 goto fail;
1079
1080         trigger = ieee80211_get_rx_led_name(sc->hw);
1081         snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
1082                 "ath9k-%s::rx", wiphy_name(sc->hw->wiphy));
1083         ret = ath_register_led(sc, &sc->rx_led, trigger);
1084         sc->rx_led.led_type = ATH_LED_RX;
1085         if (ret)
1086                 goto fail;
1087
1088         return;
1089
1090 fail:
1091         ath_deinit_leds(sc);
1092 }
1093
1094 void ath_radio_enable(struct ath_softc *sc)
1095 {
1096         struct ath_hw *ah = sc->sc_ah;
1097         struct ieee80211_channel *channel = sc->hw->conf.channel;
1098         int r;
1099
1100         ath9k_ps_wakeup(sc);
1101         spin_lock_bh(&sc->sc_resetlock);
1102
1103         r = ath9k_hw_reset(ah, ah->curchan, false);
1104
1105         if (r) {
1106                 DPRINTF(sc, ATH_DBG_FATAL,
1107                         "Unable to reset channel %u (%uMhz) ",
1108                         "reset status %u\n",
1109                         channel->center_freq, r);
1110         }
1111         spin_unlock_bh(&sc->sc_resetlock);
1112
1113         ath_update_txpow(sc);
1114         if (ath_startrecv(sc) != 0) {
1115                 DPRINTF(sc, ATH_DBG_FATAL,
1116                         "Unable to restart recv logic\n");
1117                 return;
1118         }
1119
1120         if (sc->sc_flags & SC_OP_BEACONS)
1121                 ath_beacon_config(sc, NULL);    /* restart beacons */
1122
1123         /* Re-Enable  interrupts */
1124         ath9k_hw_set_interrupts(ah, sc->imask);
1125
1126         /* Enable LED */
1127         ath9k_hw_cfg_output(ah, ATH_LED_PIN,
1128                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1129         ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0);
1130
1131         ieee80211_wake_queues(sc->hw);
1132         ath9k_ps_restore(sc);
1133 }
1134
1135 void ath_radio_disable(struct ath_softc *sc)
1136 {
1137         struct ath_hw *ah = sc->sc_ah;
1138         struct ieee80211_channel *channel = sc->hw->conf.channel;
1139         int r;
1140
1141         ath9k_ps_wakeup(sc);
1142         ieee80211_stop_queues(sc->hw);
1143
1144         /* Disable LED */
1145         ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1);
1146         ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN);
1147
1148         /* Disable interrupts */
1149         ath9k_hw_set_interrupts(ah, 0);
1150
1151         ath_drain_all_txq(sc, false);   /* clear pending tx frames */
1152         ath_stoprecv(sc);               /* turn off frame recv */
1153         ath_flushrecv(sc);              /* flush recv queue */
1154
1155         spin_lock_bh(&sc->sc_resetlock);
1156         r = ath9k_hw_reset(ah, ah->curchan, false);
1157         if (r) {
1158                 DPRINTF(sc, ATH_DBG_FATAL,
1159                         "Unable to reset channel %u (%uMhz) "
1160                         "reset status %u\n",
1161                         channel->center_freq, r);
1162         }
1163         spin_unlock_bh(&sc->sc_resetlock);
1164
1165         ath9k_hw_phy_disable(ah);
1166         ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1167         ath9k_ps_restore(sc);
1168 }
1169
1170 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1171
1172 /*******************/
1173 /*      Rfkill     */
1174 /*******************/
1175
1176 static bool ath_is_rfkill_set(struct ath_softc *sc)
1177 {
1178         struct ath_hw *ah = sc->sc_ah;
1179
1180         return ath9k_hw_gpio_get(ah, ah->rfkill_gpio) ==
1181                                   ah->rfkill_polarity;
1182 }
1183
1184 /* h/w rfkill poll function */
1185 static void ath_rfkill_poll(struct work_struct *work)
1186 {
1187         struct ath_softc *sc = container_of(work, struct ath_softc,
1188                                             rf_kill.rfkill_poll.work);
1189         bool radio_on;
1190
1191         if (sc->sc_flags & SC_OP_INVALID)
1192                 return;
1193
1194         radio_on = !ath_is_rfkill_set(sc);
1195
1196         /*
1197          * enable/disable radio only when there is a
1198          * state change in RF switch
1199          */
1200         if (radio_on == !!(sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED)) {
1201                 enum rfkill_state state;
1202
1203                 if (sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED) {
1204                         state = radio_on ? RFKILL_STATE_SOFT_BLOCKED
1205                                 : RFKILL_STATE_HARD_BLOCKED;
1206                 } else if (radio_on) {
1207                         ath_radio_enable(sc);
1208                         state = RFKILL_STATE_UNBLOCKED;
1209                 } else {
1210                         ath_radio_disable(sc);
1211                         state = RFKILL_STATE_HARD_BLOCKED;
1212                 }
1213
1214                 if (state == RFKILL_STATE_HARD_BLOCKED)
1215                         sc->sc_flags |= SC_OP_RFKILL_HW_BLOCKED;
1216                 else
1217                         sc->sc_flags &= ~SC_OP_RFKILL_HW_BLOCKED;
1218
1219                 rfkill_force_state(sc->rf_kill.rfkill, state);
1220         }
1221
1222         queue_delayed_work(sc->hw->workqueue, &sc->rf_kill.rfkill_poll,
1223                            msecs_to_jiffies(ATH_RFKILL_POLL_INTERVAL));
1224 }
1225
1226 /* s/w rfkill handler */
1227 static int ath_sw_toggle_radio(void *data, enum rfkill_state state)
1228 {
1229         struct ath_softc *sc = data;
1230
1231         switch (state) {
1232         case RFKILL_STATE_SOFT_BLOCKED:
1233                 if (!(sc->sc_flags & (SC_OP_RFKILL_HW_BLOCKED |
1234                     SC_OP_RFKILL_SW_BLOCKED)))
1235                         ath_radio_disable(sc);
1236                 sc->sc_flags |= SC_OP_RFKILL_SW_BLOCKED;
1237                 return 0;
1238         case RFKILL_STATE_UNBLOCKED:
1239                 if ((sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED)) {
1240                         sc->sc_flags &= ~SC_OP_RFKILL_SW_BLOCKED;
1241                         if (sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED) {
1242                                 DPRINTF(sc, ATH_DBG_FATAL, "Can't turn on the"
1243                                         "radio as it is disabled by h/w\n");
1244                                 return -EPERM;
1245                         }
1246                         ath_radio_enable(sc);
1247                 }
1248                 return 0;
1249         default:
1250                 return -EINVAL;
1251         }
1252 }
1253
1254 /* Init s/w rfkill */
1255 static int ath_init_sw_rfkill(struct ath_softc *sc)
1256 {
1257         sc->rf_kill.rfkill = rfkill_allocate(wiphy_dev(sc->hw->wiphy),
1258                                              RFKILL_TYPE_WLAN);
1259         if (!sc->rf_kill.rfkill) {
1260                 DPRINTF(sc, ATH_DBG_FATAL, "Failed to allocate rfkill\n");
1261                 return -ENOMEM;
1262         }
1263
1264         snprintf(sc->rf_kill.rfkill_name, sizeof(sc->rf_kill.rfkill_name),
1265                 "ath9k-%s::rfkill", wiphy_name(sc->hw->wiphy));
1266         sc->rf_kill.rfkill->name = sc->rf_kill.rfkill_name;
1267         sc->rf_kill.rfkill->data = sc;
1268         sc->rf_kill.rfkill->toggle_radio = ath_sw_toggle_radio;
1269         sc->rf_kill.rfkill->state = RFKILL_STATE_UNBLOCKED;
1270         sc->rf_kill.rfkill->user_claim_unsupported = 1;
1271
1272         return 0;
1273 }
1274
1275 /* Deinitialize rfkill */
1276 static void ath_deinit_rfkill(struct ath_softc *sc)
1277 {
1278         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1279                 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
1280
1281         if (sc->sc_flags & SC_OP_RFKILL_REGISTERED) {
1282                 rfkill_unregister(sc->rf_kill.rfkill);
1283                 sc->sc_flags &= ~SC_OP_RFKILL_REGISTERED;
1284                 sc->rf_kill.rfkill = NULL;
1285         }
1286 }
1287
1288 static int ath_start_rfkill_poll(struct ath_softc *sc)
1289 {
1290         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1291                 queue_delayed_work(sc->hw->workqueue,
1292                                    &sc->rf_kill.rfkill_poll, 0);
1293
1294         if (!(sc->sc_flags & SC_OP_RFKILL_REGISTERED)) {
1295                 if (rfkill_register(sc->rf_kill.rfkill)) {
1296                         DPRINTF(sc, ATH_DBG_FATAL,
1297                                 "Unable to register rfkill\n");
1298                         rfkill_free(sc->rf_kill.rfkill);
1299
1300                         /* Deinitialize the device */
1301                         ath_cleanup(sc);
1302                         return -EIO;
1303                 } else {
1304                         sc->sc_flags |= SC_OP_RFKILL_REGISTERED;
1305                 }
1306         }
1307
1308         return 0;
1309 }
1310 #endif /* CONFIG_RFKILL */
1311
1312 void ath_cleanup(struct ath_softc *sc)
1313 {
1314         ath_detach(sc);
1315         free_irq(sc->irq, sc);
1316         ath_bus_cleanup(sc);
1317         kfree(sc->sec_wiphy);
1318         ieee80211_free_hw(sc->hw);
1319 }
1320
1321 void ath_detach(struct ath_softc *sc)
1322 {
1323         struct ieee80211_hw *hw = sc->hw;
1324         int i = 0;
1325
1326         ath9k_ps_wakeup(sc);
1327
1328         DPRINTF(sc, ATH_DBG_CONFIG, "Detach ATH hw\n");
1329
1330 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1331         ath_deinit_rfkill(sc);
1332 #endif
1333         ath_deinit_leds(sc);
1334         cancel_work_sync(&sc->chan_work);
1335         cancel_delayed_work_sync(&sc->wiphy_work);
1336
1337         for (i = 0; i < sc->num_sec_wiphy; i++) {
1338                 struct ath_wiphy *aphy = sc->sec_wiphy[i];
1339                 if (aphy == NULL)
1340                         continue;
1341                 sc->sec_wiphy[i] = NULL;
1342                 ieee80211_unregister_hw(aphy->hw);
1343                 ieee80211_free_hw(aphy->hw);
1344         }
1345         ieee80211_unregister_hw(hw);
1346         ath_rx_cleanup(sc);
1347         ath_tx_cleanup(sc);
1348
1349         tasklet_kill(&sc->intr_tq);
1350         tasklet_kill(&sc->bcon_tasklet);
1351
1352         if (!(sc->sc_flags & SC_OP_INVALID))
1353                 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
1354
1355         /* cleanup tx queues */
1356         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1357                 if (ATH_TXQ_SETUP(sc, i))
1358                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1359
1360         ath9k_hw_detach(sc->sc_ah);
1361         ath9k_exit_debug(sc);
1362         ath9k_ps_restore(sc);
1363 }
1364
1365 static int ath_init(u16 devid, struct ath_softc *sc)
1366 {
1367         struct ath_hw *ah = NULL;
1368         int status;
1369         int error = 0, i;
1370         int csz = 0;
1371
1372         /* XXX: hardware will not be ready until ath_open() being called */
1373         sc->sc_flags |= SC_OP_INVALID;
1374
1375         if (ath9k_init_debug(sc) < 0)
1376                 printk(KERN_ERR "Unable to create debugfs files\n");
1377
1378         spin_lock_init(&sc->wiphy_lock);
1379         spin_lock_init(&sc->sc_resetlock);
1380         spin_lock_init(&sc->sc_serial_rw);
1381         mutex_init(&sc->mutex);
1382         tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
1383         tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet,
1384                      (unsigned long)sc);
1385
1386         /*
1387          * Cache line size is used to size and align various
1388          * structures used to communicate with the hardware.
1389          */
1390         ath_read_cachesize(sc, &csz);
1391         /* XXX assert csz is non-zero */
1392         sc->cachelsz = csz << 2;        /* convert to bytes */
1393
1394         ah = ath9k_hw_attach(devid, sc, &status);
1395         if (ah == NULL) {
1396                 DPRINTF(sc, ATH_DBG_FATAL,
1397                         "Unable to attach hardware; HAL status %d\n", status);
1398                 error = -ENXIO;
1399                 goto bad;
1400         }
1401         sc->sc_ah = ah;
1402
1403         /* Get the hardware key cache size. */
1404         sc->keymax = ah->caps.keycache_size;
1405         if (sc->keymax > ATH_KEYMAX) {
1406                 DPRINTF(sc, ATH_DBG_KEYCACHE,
1407                         "Warning, using only %u entries in %u key cache\n",
1408                         ATH_KEYMAX, sc->keymax);
1409                 sc->keymax = ATH_KEYMAX;
1410         }
1411
1412         /*
1413          * Reset the key cache since some parts do not
1414          * reset the contents on initial power up.
1415          */
1416         for (i = 0; i < sc->keymax; i++)
1417                 ath9k_hw_keyreset(ah, (u16) i);
1418
1419         if (ath9k_regd_init(sc->sc_ah))
1420                 goto bad;
1421
1422         /* default to MONITOR mode */
1423         sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
1424
1425         /* Setup rate tables */
1426
1427         ath_rate_attach(sc);
1428         ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1429         ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1430
1431         /*
1432          * Allocate hardware transmit queues: one queue for
1433          * beacon frames and one data queue for each QoS
1434          * priority.  Note that the hal handles reseting
1435          * these queues at the needed time.
1436          */
1437         sc->beacon.beaconq = ath_beaconq_setup(ah);
1438         if (sc->beacon.beaconq == -1) {
1439                 DPRINTF(sc, ATH_DBG_FATAL,
1440                         "Unable to setup a beacon xmit queue\n");
1441                 error = -EIO;
1442                 goto bad2;
1443         }
1444         sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1445         if (sc->beacon.cabq == NULL) {
1446                 DPRINTF(sc, ATH_DBG_FATAL,
1447                         "Unable to setup CAB xmit queue\n");
1448                 error = -EIO;
1449                 goto bad2;
1450         }
1451
1452         sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
1453         ath_cabq_update(sc);
1454
1455         for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1456                 sc->tx.hwq_map[i] = -1;
1457
1458         /* Setup data queues */
1459         /* NB: ensure BK queue is the lowest priority h/w queue */
1460         if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1461                 DPRINTF(sc, ATH_DBG_FATAL,
1462                         "Unable to setup xmit queue for BK traffic\n");
1463                 error = -EIO;
1464                 goto bad2;
1465         }
1466
1467         if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1468                 DPRINTF(sc, ATH_DBG_FATAL,
1469                         "Unable to setup xmit queue for BE traffic\n");
1470                 error = -EIO;
1471                 goto bad2;
1472         }
1473         if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1474                 DPRINTF(sc, ATH_DBG_FATAL,
1475                         "Unable to setup xmit queue for VI traffic\n");
1476                 error = -EIO;
1477                 goto bad2;
1478         }
1479         if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1480                 DPRINTF(sc, ATH_DBG_FATAL,
1481                         "Unable to setup xmit queue for VO traffic\n");
1482                 error = -EIO;
1483                 goto bad2;
1484         }
1485
1486         /* Initializes the noise floor to a reasonable default value.
1487          * Later on this will be updated during ANI processing. */
1488
1489         sc->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1490         setup_timer(&sc->ani.timer, ath_ani_calibrate, (unsigned long)sc);
1491
1492         if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1493                                    ATH9K_CIPHER_TKIP, NULL)) {
1494                 /*
1495                  * Whether we should enable h/w TKIP MIC.
1496                  * XXX: if we don't support WME TKIP MIC, then we wouldn't
1497                  * report WMM capable, so it's always safe to turn on
1498                  * TKIP MIC in this case.
1499                  */
1500                 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1501                                        0, 1, NULL);
1502         }
1503
1504         /*
1505          * Check whether the separate key cache entries
1506          * are required to handle both tx+rx MIC keys.
1507          * With split mic keys the number of stations is limited
1508          * to 27 otherwise 59.
1509          */
1510         if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1511                                    ATH9K_CIPHER_TKIP, NULL)
1512             && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1513                                       ATH9K_CIPHER_MIC, NULL)
1514             && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1515                                       0, NULL))
1516                 sc->splitmic = 1;
1517
1518         /* turn on mcast key search if possible */
1519         if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1520                 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1521                                              1, NULL);
1522
1523         sc->config.txpowlimit = ATH_TXPOWER_MAX;
1524
1525         /* 11n Capabilities */
1526         if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1527                 sc->sc_flags |= SC_OP_TXAGGR;
1528                 sc->sc_flags |= SC_OP_RXAGGR;
1529         }
1530
1531         sc->tx_chainmask = ah->caps.tx_chainmask;
1532         sc->rx_chainmask = ah->caps.rx_chainmask;
1533
1534         ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
1535         sc->rx.defant = ath9k_hw_getdefantenna(ah);
1536
1537         if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
1538                 memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN);
1539
1540         sc->beacon.slottime = ATH9K_SLOT_TIME_9;        /* default to short slot time */
1541
1542         /* initialize beacon slots */
1543         for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
1544                 sc->beacon.bslot[i] = NULL;
1545                 sc->beacon.bslot_aphy[i] = NULL;
1546         }
1547
1548         /* save MISC configurations */
1549         sc->config.swBeaconProcess = 1;
1550
1551         /* setup channels and rates */
1552
1553         sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
1554         sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1555                 sc->rates[IEEE80211_BAND_2GHZ];
1556         sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
1557         sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
1558                 ARRAY_SIZE(ath9k_2ghz_chantable);
1559
1560         if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) {
1561                 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
1562                 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1563                         sc->rates[IEEE80211_BAND_5GHZ];
1564                 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
1565                 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
1566                         ARRAY_SIZE(ath9k_5ghz_chantable);
1567         }
1568
1569         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)
1570                 ath9k_hw_btcoex_enable(sc->sc_ah);
1571
1572         return 0;
1573 bad2:
1574         /* cleanup tx queues */
1575         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1576                 if (ATH_TXQ_SETUP(sc, i))
1577                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1578 bad:
1579         if (ah)
1580                 ath9k_hw_detach(ah);
1581         ath9k_exit_debug(sc);
1582
1583         return error;
1584 }
1585
1586 void ath_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
1587 {
1588         hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1589                 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1590                 IEEE80211_HW_SIGNAL_DBM |
1591                 IEEE80211_HW_AMPDU_AGGREGATION |
1592                 IEEE80211_HW_SUPPORTS_PS |
1593                 IEEE80211_HW_PS_NULLFUNC_STACK |
1594                 IEEE80211_HW_SPECTRUM_MGMT;
1595
1596         if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || modparam_nohwcrypt)
1597                 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
1598
1599         hw->wiphy->interface_modes =
1600                 BIT(NL80211_IFTYPE_AP) |
1601                 BIT(NL80211_IFTYPE_STATION) |
1602                 BIT(NL80211_IFTYPE_ADHOC) |
1603                 BIT(NL80211_IFTYPE_MESH_POINT);
1604
1605         hw->wiphy->reg_notifier = ath9k_reg_notifier;
1606         hw->wiphy->strict_regulatory = true;
1607
1608         hw->queues = 4;
1609         hw->max_rates = 4;
1610         hw->channel_change_time = 5000;
1611         hw->max_listen_interval = 10;
1612         hw->max_rate_tries = ATH_11N_TXMAXTRY;
1613         hw->sta_data_size = sizeof(struct ath_node);
1614         hw->vif_data_size = sizeof(struct ath_vif);
1615
1616         hw->rate_control_algorithm = "ath9k_rate_control";
1617
1618         hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
1619                 &sc->sbands[IEEE80211_BAND_2GHZ];
1620         if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1621                 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1622                         &sc->sbands[IEEE80211_BAND_5GHZ];
1623 }
1624
1625 int ath_attach(u16 devid, struct ath_softc *sc)
1626 {
1627         struct ieee80211_hw *hw = sc->hw;
1628         const struct ieee80211_regdomain *regd;
1629         int error = 0, i;
1630
1631         DPRINTF(sc, ATH_DBG_CONFIG, "Attach ATH hw\n");
1632
1633         error = ath_init(devid, sc);
1634         if (error != 0)
1635                 return error;
1636
1637         /* get mac address from hardware and set in mac80211 */
1638
1639         SET_IEEE80211_PERM_ADDR(hw, sc->sc_ah->macaddr);
1640
1641         ath_set_hw_capab(sc, hw);
1642
1643         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1644                 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
1645                 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1646                         setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
1647         }
1648
1649         /* initialize tx/rx engine */
1650         error = ath_tx_init(sc, ATH_TXBUF);
1651         if (error != 0)
1652                 goto error_attach;
1653
1654         error = ath_rx_init(sc, ATH_RXBUF);
1655         if (error != 0)
1656                 goto error_attach;
1657
1658 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1659         /* Initialze h/w Rfkill */
1660         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1661                 INIT_DELAYED_WORK(&sc->rf_kill.rfkill_poll, ath_rfkill_poll);
1662
1663         /* Initialize s/w rfkill */
1664         error = ath_init_sw_rfkill(sc);
1665         if (error)
1666                 goto error_attach;
1667 #endif
1668
1669         if (ath9k_is_world_regd(sc->sc_ah)) {
1670                 /* Anything applied here (prior to wiphy registration) gets
1671                  * saved on the wiphy orig_* parameters */
1672                 regd = ath9k_world_regdomain(sc->sc_ah);
1673                 hw->wiphy->custom_regulatory = true;
1674                 hw->wiphy->strict_regulatory = false;
1675         } else {
1676                 /* This gets applied in the case of the absense of CRDA,
1677                  * it's our own custom world regulatory domain, similar to
1678                  * cfg80211's but we enable passive scanning */
1679                 regd = ath9k_default_world_regdomain();
1680         }
1681         wiphy_apply_custom_regulatory(hw->wiphy, regd);
1682         ath9k_reg_apply_radar_flags(hw->wiphy);
1683         ath9k_reg_apply_world_flags(hw->wiphy, NL80211_REGDOM_SET_BY_DRIVER);
1684
1685         INIT_WORK(&sc->chan_work, ath9k_wiphy_chan_work);
1686         INIT_DELAYED_WORK(&sc->wiphy_work, ath9k_wiphy_work);
1687         sc->wiphy_scheduler_int = msecs_to_jiffies(500);
1688
1689         error = ieee80211_register_hw(hw);
1690
1691         if (!ath9k_is_world_regd(sc->sc_ah)) {
1692                 error = regulatory_hint(hw->wiphy,
1693                         sc->sc_ah->regulatory.alpha2);
1694                 if (error)
1695                         goto error_attach;
1696         }
1697
1698         /* Initialize LED control */
1699         ath_init_leds(sc);
1700
1701
1702         return 0;
1703
1704 error_attach:
1705         /* cleanup tx queues */
1706         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1707                 if (ATH_TXQ_SETUP(sc, i))
1708                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1709
1710         ath9k_hw_detach(sc->sc_ah);
1711         ath9k_exit_debug(sc);
1712
1713         return error;
1714 }
1715
1716 int ath_reset(struct ath_softc *sc, bool retry_tx)
1717 {
1718         struct ath_hw *ah = sc->sc_ah;
1719         struct ieee80211_hw *hw = sc->hw;
1720         int r;
1721
1722         ath9k_hw_set_interrupts(ah, 0);
1723         ath_drain_all_txq(sc, retry_tx);
1724         ath_stoprecv(sc);
1725         ath_flushrecv(sc);
1726
1727         spin_lock_bh(&sc->sc_resetlock);
1728         r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
1729         if (r)
1730                 DPRINTF(sc, ATH_DBG_FATAL,
1731                         "Unable to reset hardware; reset status %u\n", r);
1732         spin_unlock_bh(&sc->sc_resetlock);
1733
1734         if (ath_startrecv(sc) != 0)
1735                 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
1736
1737         /*
1738          * We may be doing a reset in response to a request
1739          * that changes the channel so update any state that
1740          * might change as a result.
1741          */
1742         ath_cache_conf_rate(sc, &hw->conf);
1743
1744         ath_update_txpow(sc);
1745
1746         if (sc->sc_flags & SC_OP_BEACONS)
1747                 ath_beacon_config(sc, NULL);    /* restart beacons */
1748
1749         ath9k_hw_set_interrupts(ah, sc->imask);
1750
1751         if (retry_tx) {
1752                 int i;
1753                 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1754                         if (ATH_TXQ_SETUP(sc, i)) {
1755                                 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1756                                 ath_txq_schedule(sc, &sc->tx.txq[i]);
1757                                 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
1758                         }
1759                 }
1760         }
1761
1762         return r;
1763 }
1764
1765 /*
1766  *  This function will allocate both the DMA descriptor structure, and the
1767  *  buffers it contains.  These are used to contain the descriptors used
1768  *  by the system.
1769 */
1770 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1771                       struct list_head *head, const char *name,
1772                       int nbuf, int ndesc)
1773 {
1774 #define DS2PHYS(_dd, _ds)                                               \
1775         ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1776 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1777 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1778
1779         struct ath_desc *ds;
1780         struct ath_buf *bf;
1781         int i, bsize, error;
1782
1783         DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
1784                 name, nbuf, ndesc);
1785
1786         INIT_LIST_HEAD(head);
1787         /* ath_desc must be a multiple of DWORDs */
1788         if ((sizeof(struct ath_desc) % 4) != 0) {
1789                 DPRINTF(sc, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
1790                 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1791                 error = -ENOMEM;
1792                 goto fail;
1793         }
1794
1795         dd->dd_name = name;
1796         dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1797
1798         /*
1799          * Need additional DMA memory because we can't use
1800          * descriptors that cross the 4K page boundary. Assume
1801          * one skipped descriptor per 4K page.
1802          */
1803         if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1804                 u32 ndesc_skipped =
1805                         ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1806                 u32 dma_len;
1807
1808                 while (ndesc_skipped) {
1809                         dma_len = ndesc_skipped * sizeof(struct ath_desc);
1810                         dd->dd_desc_len += dma_len;
1811
1812                         ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1813                 };
1814         }
1815
1816         /* allocate descriptors */
1817         dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
1818                                          &dd->dd_desc_paddr, GFP_KERNEL);
1819         if (dd->dd_desc == NULL) {
1820                 error = -ENOMEM;
1821                 goto fail;
1822         }
1823         ds = dd->dd_desc;
1824         DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
1825                 dd->dd_name, ds, (u32) dd->dd_desc_len,
1826                 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1827
1828         /* allocate buffers */
1829         bsize = sizeof(struct ath_buf) * nbuf;
1830         bf = kzalloc(bsize, GFP_KERNEL);
1831         if (bf == NULL) {
1832                 error = -ENOMEM;
1833                 goto fail2;
1834         }
1835         dd->dd_bufptr = bf;
1836
1837         for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1838                 bf->bf_desc = ds;
1839                 bf->bf_daddr = DS2PHYS(dd, ds);
1840
1841                 if (!(sc->sc_ah->caps.hw_caps &
1842                       ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1843                         /*
1844                          * Skip descriptor addresses which can cause 4KB
1845                          * boundary crossing (addr + length) with a 32 dword
1846                          * descriptor fetch.
1847                          */
1848                         while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1849                                 ASSERT((caddr_t) bf->bf_desc <
1850                                        ((caddr_t) dd->dd_desc +
1851                                         dd->dd_desc_len));
1852
1853                                 ds += ndesc;
1854                                 bf->bf_desc = ds;
1855                                 bf->bf_daddr = DS2PHYS(dd, ds);
1856                         }
1857                 }
1858                 list_add_tail(&bf->list, head);
1859         }
1860         return 0;
1861 fail2:
1862         dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1863                           dd->dd_desc_paddr);
1864 fail:
1865         memset(dd, 0, sizeof(*dd));
1866         return error;
1867 #undef ATH_DESC_4KB_BOUND_CHECK
1868 #undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1869 #undef DS2PHYS
1870 }
1871
1872 void ath_descdma_cleanup(struct ath_softc *sc,
1873                          struct ath_descdma *dd,
1874                          struct list_head *head)
1875 {
1876         dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1877                           dd->dd_desc_paddr);
1878
1879         INIT_LIST_HEAD(head);
1880         kfree(dd->dd_bufptr);
1881         memset(dd, 0, sizeof(*dd));
1882 }
1883
1884 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1885 {
1886         int qnum;
1887
1888         switch (queue) {
1889         case 0:
1890                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
1891                 break;
1892         case 1:
1893                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
1894                 break;
1895         case 2:
1896                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1897                 break;
1898         case 3:
1899                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
1900                 break;
1901         default:
1902                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1903                 break;
1904         }
1905
1906         return qnum;
1907 }
1908
1909 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1910 {
1911         int qnum;
1912
1913         switch (queue) {
1914         case ATH9K_WME_AC_VO:
1915                 qnum = 0;
1916                 break;
1917         case ATH9K_WME_AC_VI:
1918                 qnum = 1;
1919                 break;
1920         case ATH9K_WME_AC_BE:
1921                 qnum = 2;
1922                 break;
1923         case ATH9K_WME_AC_BK:
1924                 qnum = 3;
1925                 break;
1926         default:
1927                 qnum = -1;
1928                 break;
1929         }
1930
1931         return qnum;
1932 }
1933
1934 /* XXX: Remove me once we don't depend on ath9k_channel for all
1935  * this redundant data */
1936 void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
1937                            struct ath9k_channel *ichan)
1938 {
1939         struct ieee80211_channel *chan = hw->conf.channel;
1940         struct ieee80211_conf *conf = &hw->conf;
1941
1942         ichan->channel = chan->center_freq;
1943         ichan->chan = chan;
1944
1945         if (chan->band == IEEE80211_BAND_2GHZ) {
1946                 ichan->chanmode = CHANNEL_G;
1947                 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM;
1948         } else {
1949                 ichan->chanmode = CHANNEL_A;
1950                 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
1951         }
1952
1953         sc->tx_chan_width = ATH9K_HT_MACMODE_20;
1954
1955         if (conf_is_ht(conf)) {
1956                 if (conf_is_ht40(conf))
1957                         sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
1958
1959                 ichan->chanmode = ath_get_extchanmode(sc, chan,
1960                                             conf->channel_type);
1961         }
1962 }
1963
1964 /**********************/
1965 /* mac80211 callbacks */
1966 /**********************/
1967
1968 static int ath9k_start(struct ieee80211_hw *hw)
1969 {
1970         struct ath_wiphy *aphy = hw->priv;
1971         struct ath_softc *sc = aphy->sc;
1972         struct ieee80211_channel *curchan = hw->conf.channel;
1973         struct ath9k_channel *init_channel;
1974         int r, pos;
1975
1976         DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with "
1977                 "initial channel: %d MHz\n", curchan->center_freq);
1978
1979         mutex_lock(&sc->mutex);
1980
1981         if (ath9k_wiphy_started(sc)) {
1982                 if (sc->chan_idx == curchan->hw_value) {
1983                         /*
1984                          * Already on the operational channel, the new wiphy
1985                          * can be marked active.
1986                          */
1987                         aphy->state = ATH_WIPHY_ACTIVE;
1988                         ieee80211_wake_queues(hw);
1989                 } else {
1990                         /*
1991                          * Another wiphy is on another channel, start the new
1992                          * wiphy in paused state.
1993                          */
1994                         aphy->state = ATH_WIPHY_PAUSED;
1995                         ieee80211_stop_queues(hw);
1996                 }
1997                 mutex_unlock(&sc->mutex);
1998                 return 0;
1999         }
2000         aphy->state = ATH_WIPHY_ACTIVE;
2001
2002         /* setup initial channel */
2003
2004         pos = curchan->hw_value;
2005
2006         sc->chan_idx = pos;
2007         init_channel = &sc->sc_ah->channels[pos];
2008         ath9k_update_ichannel(sc, hw, init_channel);
2009
2010         /* Reset SERDES registers */
2011         ath9k_hw_configpcipowersave(sc->sc_ah, 0);
2012
2013         /*
2014          * The basic interface to setting the hardware in a good
2015          * state is ``reset''.  On return the hardware is known to
2016          * be powered up and with interrupts disabled.  This must
2017          * be followed by initialization of the appropriate bits
2018          * and then setup of the interrupt mask.
2019          */
2020         spin_lock_bh(&sc->sc_resetlock);
2021         r = ath9k_hw_reset(sc->sc_ah, init_channel, false);
2022         if (r) {
2023                 DPRINTF(sc, ATH_DBG_FATAL,
2024                         "Unable to reset hardware; reset status %u "
2025                         "(freq %u MHz)\n", r,
2026                         curchan->center_freq);
2027                 spin_unlock_bh(&sc->sc_resetlock);
2028                 goto mutex_unlock;
2029         }
2030         spin_unlock_bh(&sc->sc_resetlock);
2031
2032         /*
2033          * This is needed only to setup initial state
2034          * but it's best done after a reset.
2035          */
2036         ath_update_txpow(sc);
2037
2038         /*
2039          * Setup the hardware after reset:
2040          * The receive engine is set going.
2041          * Frame transmit is handled entirely
2042          * in the frame output path; there's nothing to do
2043          * here except setup the interrupt mask.
2044          */
2045         if (ath_startrecv(sc) != 0) {
2046                 DPRINTF(sc, ATH_DBG_FATAL,
2047                         "Unable to start recv logic\n");
2048                 r = -EIO;
2049                 goto mutex_unlock;
2050         }
2051
2052         /* Setup our intr mask. */
2053         sc->imask = ATH9K_INT_RX | ATH9K_INT_TX
2054                 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
2055                 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
2056
2057         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
2058                 sc->imask |= ATH9K_INT_GTT;
2059
2060         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
2061                 sc->imask |= ATH9K_INT_CST;
2062
2063         ath_cache_conf_rate(sc, &hw->conf);
2064
2065         sc->sc_flags &= ~SC_OP_INVALID;
2066
2067         /* Disable BMISS interrupt when we're not associated */
2068         sc->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
2069         ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
2070
2071         ieee80211_wake_queues(hw);
2072
2073 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2074         r = ath_start_rfkill_poll(sc);
2075 #endif
2076
2077 mutex_unlock:
2078         mutex_unlock(&sc->mutex);
2079
2080         return r;
2081 }
2082
2083 static int ath9k_tx(struct ieee80211_hw *hw,
2084                     struct sk_buff *skb)
2085 {
2086         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2087         struct ath_wiphy *aphy = hw->priv;
2088         struct ath_softc *sc = aphy->sc;
2089         struct ath_tx_control txctl;
2090         int hdrlen, padsize;
2091
2092         if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
2093                 printk(KERN_DEBUG "ath9k: %s: TX in unexpected wiphy state "
2094                        "%d\n", wiphy_name(hw->wiphy), aphy->state);
2095                 goto exit;
2096         }
2097
2098         memset(&txctl, 0, sizeof(struct ath_tx_control));
2099
2100         /*
2101          * As a temporary workaround, assign seq# here; this will likely need
2102          * to be cleaned up to work better with Beacon transmission and virtual
2103          * BSSes.
2104          */
2105         if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2106                 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2107                 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
2108                         sc->tx.seq_no += 0x10;
2109                 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
2110                 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
2111         }
2112
2113         /* Add the padding after the header if this is not already done */
2114         hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2115         if (hdrlen & 3) {
2116                 padsize = hdrlen % 4;
2117                 if (skb_headroom(skb) < padsize)
2118                         return -1;
2119                 skb_push(skb, padsize);
2120                 memmove(skb->data, skb->data + padsize, hdrlen);
2121         }
2122
2123         /* Check if a tx queue is available */
2124
2125         txctl.txq = ath_test_get_txq(sc, skb);
2126         if (!txctl.txq)
2127                 goto exit;
2128
2129         DPRINTF(sc, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
2130
2131         if (ath_tx_start(hw, skb, &txctl) != 0) {
2132                 DPRINTF(sc, ATH_DBG_XMIT, "TX failed\n");
2133                 goto exit;
2134         }
2135
2136         return 0;
2137 exit:
2138         dev_kfree_skb_any(skb);
2139         return 0;
2140 }
2141
2142 static void ath9k_stop(struct ieee80211_hw *hw)
2143 {
2144         struct ath_wiphy *aphy = hw->priv;
2145         struct ath_softc *sc = aphy->sc;
2146
2147         aphy->state = ATH_WIPHY_INACTIVE;
2148
2149         if (sc->sc_flags & SC_OP_INVALID) {
2150                 DPRINTF(sc, ATH_DBG_ANY, "Device not present\n");
2151                 return;
2152         }
2153
2154         mutex_lock(&sc->mutex);
2155
2156         ieee80211_stop_queues(hw);
2157
2158         if (ath9k_wiphy_started(sc)) {
2159                 mutex_unlock(&sc->mutex);
2160                 return; /* another wiphy still in use */
2161         }
2162
2163         /* make sure h/w will not generate any interrupt
2164          * before setting the invalid flag. */
2165         ath9k_hw_set_interrupts(sc->sc_ah, 0);
2166
2167         if (!(sc->sc_flags & SC_OP_INVALID)) {
2168                 ath_drain_all_txq(sc, false);
2169                 ath_stoprecv(sc);
2170                 ath9k_hw_phy_disable(sc->sc_ah);
2171         } else
2172                 sc->rx.rxlink = NULL;
2173
2174 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2175         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2176                 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
2177 #endif
2178         /* disable HAL and put h/w to sleep */
2179         ath9k_hw_disable(sc->sc_ah);
2180         ath9k_hw_configpcipowersave(sc->sc_ah, 1);
2181
2182         sc->sc_flags |= SC_OP_INVALID;
2183
2184         mutex_unlock(&sc->mutex);
2185
2186         DPRINTF(sc, ATH_DBG_CONFIG, "Driver halt\n");
2187 }
2188
2189 static int ath9k_add_interface(struct ieee80211_hw *hw,
2190                                struct ieee80211_if_init_conf *conf)
2191 {
2192         struct ath_wiphy *aphy = hw->priv;
2193         struct ath_softc *sc = aphy->sc;
2194         struct ath_vif *avp = (void *)conf->vif->drv_priv;
2195         enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2196         int ret = 0;
2197
2198         mutex_lock(&sc->mutex);
2199
2200         if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) &&
2201             sc->nvifs > 0) {
2202                 ret = -ENOBUFS;
2203                 goto out;
2204         }
2205
2206         switch (conf->type) {
2207         case NL80211_IFTYPE_STATION:
2208                 ic_opmode = NL80211_IFTYPE_STATION;
2209                 break;
2210         case NL80211_IFTYPE_ADHOC:
2211         case NL80211_IFTYPE_AP:
2212         case NL80211_IFTYPE_MESH_POINT:
2213                 if (sc->nbcnvifs >= ATH_BCBUF) {
2214                         ret = -ENOBUFS;
2215                         goto out;
2216                 }
2217                 ic_opmode = conf->type;
2218                 break;
2219         default:
2220                 DPRINTF(sc, ATH_DBG_FATAL,
2221                         "Interface type %d not yet supported\n", conf->type);
2222                 ret = -EOPNOTSUPP;
2223                 goto out;
2224         }
2225
2226         DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VIF of type: %d\n", ic_opmode);
2227
2228         /* Set the VIF opmode */
2229         avp->av_opmode = ic_opmode;
2230         avp->av_bslot = -1;
2231
2232         sc->nvifs++;
2233
2234         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
2235                 ath9k_set_bssid_mask(hw);
2236
2237         if (sc->nvifs > 1)
2238                 goto out; /* skip global settings for secondary vif */
2239
2240         if (ic_opmode == NL80211_IFTYPE_AP) {
2241                 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
2242                 sc->sc_flags |= SC_OP_TSF_RESET;
2243         }
2244
2245         /* Set the device opmode */
2246         sc->sc_ah->opmode = ic_opmode;
2247
2248         /*
2249          * Enable MIB interrupts when there are hardware phy counters.
2250          * Note we only do this (at the moment) for station mode.
2251          */
2252         if ((conf->type == NL80211_IFTYPE_STATION) ||
2253             (conf->type == NL80211_IFTYPE_ADHOC) ||
2254             (conf->type == NL80211_IFTYPE_MESH_POINT)) {
2255                 if (ath9k_hw_phycounters(sc->sc_ah))
2256                         sc->imask |= ATH9K_INT_MIB;
2257                 sc->imask |= ATH9K_INT_TSFOOR;
2258         }
2259
2260         /*
2261          * Some hardware processes the TIM IE and fires an
2262          * interrupt when the TIM bit is set.  For hardware
2263          * that does, if not overridden by configuration,
2264          * enable the TIM interrupt when operating as station.
2265          */
2266         if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_ENHANCEDPM) &&
2267             (conf->type == NL80211_IFTYPE_STATION) &&
2268             !sc->config.swBeaconProcess)
2269                 sc->imask |= ATH9K_INT_TIM;
2270
2271         ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
2272
2273         if (conf->type == NL80211_IFTYPE_AP) {
2274                 /* TODO: is this a suitable place to start ANI for AP mode? */
2275                 /* Start ANI */
2276                 mod_timer(&sc->ani.timer,
2277                           jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
2278         }
2279
2280 out:
2281         mutex_unlock(&sc->mutex);
2282         return ret;
2283 }
2284
2285 static void ath9k_remove_interface(struct ieee80211_hw *hw,
2286                                    struct ieee80211_if_init_conf *conf)
2287 {
2288         struct ath_wiphy *aphy = hw->priv;
2289         struct ath_softc *sc = aphy->sc;
2290         struct ath_vif *avp = (void *)conf->vif->drv_priv;
2291         int i;
2292
2293         DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n");
2294
2295         mutex_lock(&sc->mutex);
2296
2297         /* Stop ANI */
2298         del_timer_sync(&sc->ani.timer);
2299
2300         /* Reclaim beacon resources */
2301         if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
2302             (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) ||
2303             (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) {
2304                 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2305                 ath_beacon_return(sc, avp);
2306         }
2307
2308         sc->sc_flags &= ~SC_OP_BEACONS;
2309
2310         for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
2311                 if (sc->beacon.bslot[i] == conf->vif) {
2312                         printk(KERN_DEBUG "%s: vif had allocated beacon "
2313                                "slot\n", __func__);
2314                         sc->beacon.bslot[i] = NULL;
2315                         sc->beacon.bslot_aphy[i] = NULL;
2316                 }
2317         }
2318
2319         sc->nvifs--;
2320
2321         mutex_unlock(&sc->mutex);
2322 }
2323
2324 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
2325 {
2326         struct ath_wiphy *aphy = hw->priv;
2327         struct ath_softc *sc = aphy->sc;
2328         struct ieee80211_conf *conf = &hw->conf;
2329
2330         mutex_lock(&sc->mutex);
2331
2332         if (changed & IEEE80211_CONF_CHANGE_PS) {
2333                 if (conf->flags & IEEE80211_CONF_PS) {
2334                         if ((sc->imask & ATH9K_INT_TIM_TIMER) == 0) {
2335                                 sc->imask |= ATH9K_INT_TIM_TIMER;
2336                                 ath9k_hw_set_interrupts(sc->sc_ah,
2337                                                 sc->imask);
2338                         }
2339                         ath9k_hw_setrxabort(sc->sc_ah, 1);
2340                         ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
2341                 } else {
2342                         ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
2343                         ath9k_hw_setrxabort(sc->sc_ah, 0);
2344                         sc->sc_flags &= ~SC_OP_WAIT_FOR_BEACON;
2345                         if (sc->imask & ATH9K_INT_TIM_TIMER) {
2346                                 sc->imask &= ~ATH9K_INT_TIM_TIMER;
2347                                 ath9k_hw_set_interrupts(sc->sc_ah,
2348                                                 sc->imask);
2349                         }
2350                 }
2351         }
2352
2353         if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
2354                 struct ieee80211_channel *curchan = hw->conf.channel;
2355                 int pos = curchan->hw_value;
2356
2357                 aphy->chan_idx = pos;
2358                 aphy->chan_is_ht = conf_is_ht(conf);
2359
2360                 if (aphy->state == ATH_WIPHY_SCAN ||
2361                     aphy->state == ATH_WIPHY_ACTIVE)
2362                         ath9k_wiphy_pause_all_forced(sc, aphy);
2363                 else {
2364                         /*
2365                          * Do not change operational channel based on a paused
2366                          * wiphy changes.
2367                          */
2368                         goto skip_chan_change;
2369                 }
2370
2371                 DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2372                         curchan->center_freq);
2373
2374                 /* XXX: remove me eventualy */
2375                 ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
2376
2377                 ath_update_chainmask(sc, conf_is_ht(conf));
2378
2379                 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
2380                         DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n");
2381                         mutex_unlock(&sc->mutex);
2382                         return -EINVAL;
2383                 }
2384         }
2385
2386 skip_chan_change:
2387         if (changed & IEEE80211_CONF_CHANGE_POWER)
2388                 sc->config.txpowlimit = 2 * conf->power_level;
2389
2390         /*
2391          * The HW TSF has to be reset when the beacon interval changes.
2392          * We set the flag here, and ath_beacon_config_ap() would take this
2393          * into account when it gets called through the subsequent
2394          * config_interface() call - with IFCC_BEACON in the changed field.
2395          */
2396
2397         if (changed & IEEE80211_CONF_CHANGE_BEACON_INTERVAL)
2398                 sc->sc_flags |= SC_OP_TSF_RESET;
2399
2400         mutex_unlock(&sc->mutex);
2401
2402         return 0;
2403 }
2404
2405 static int ath9k_config_interface(struct ieee80211_hw *hw,
2406                                   struct ieee80211_vif *vif,
2407                                   struct ieee80211_if_conf *conf)
2408 {
2409         struct ath_wiphy *aphy = hw->priv;
2410         struct ath_softc *sc = aphy->sc;
2411         struct ath_hw *ah = sc->sc_ah;
2412         struct ath_vif *avp = (void *)vif->drv_priv;
2413         u32 rfilt = 0;
2414         int error, i;
2415
2416         mutex_lock(&sc->mutex);
2417
2418         /* TODO: Need to decide which hw opmode to use for multi-interface
2419          * cases */
2420         if (vif->type == NL80211_IFTYPE_AP &&
2421             ah->opmode != NL80211_IFTYPE_AP) {
2422                 ah->opmode = NL80211_IFTYPE_STATION;
2423                 ath9k_hw_setopmode(ah);
2424                 memcpy(sc->curbssid, sc->sc_ah->macaddr, ETH_ALEN);
2425                 sc->curaid = 0;
2426                 ath9k_hw_write_associd(sc);
2427                 /* Request full reset to get hw opmode changed properly */
2428                 sc->sc_flags |= SC_OP_FULL_RESET;
2429         }
2430
2431         if ((conf->changed & IEEE80211_IFCC_BSSID) &&
2432             !is_zero_ether_addr(conf->bssid)) {
2433                 switch (vif->type) {
2434                 case NL80211_IFTYPE_STATION:
2435                 case NL80211_IFTYPE_ADHOC:
2436                 case NL80211_IFTYPE_MESH_POINT:
2437                         /* Set BSSID */
2438                         memcpy(sc->curbssid, conf->bssid, ETH_ALEN);
2439                         memcpy(avp->bssid, conf->bssid, ETH_ALEN);
2440                         sc->curaid = 0;
2441                         ath9k_hw_write_associd(sc);
2442
2443                         /* Set aggregation protection mode parameters */
2444                         sc->config.ath_aggr_prot = 0;
2445
2446                         DPRINTF(sc, ATH_DBG_CONFIG,
2447                                 "RX filter 0x%x bssid %pM aid 0x%x\n",
2448                                 rfilt, sc->curbssid, sc->curaid);
2449
2450                         /* need to reconfigure the beacon */
2451                         sc->sc_flags &= ~SC_OP_BEACONS ;
2452
2453                         break;
2454                 default:
2455                         break;
2456                 }
2457         }
2458
2459         if ((vif->type == NL80211_IFTYPE_ADHOC) ||
2460             (vif->type == NL80211_IFTYPE_AP) ||
2461             (vif->type == NL80211_IFTYPE_MESH_POINT)) {
2462                 if ((conf->changed & IEEE80211_IFCC_BEACON) ||
2463                     (conf->changed & IEEE80211_IFCC_BEACON_ENABLED &&
2464                      conf->enable_beacon)) {
2465                         /*
2466                          * Allocate and setup the beacon frame.
2467                          *
2468                          * Stop any previous beacon DMA.  This may be
2469                          * necessary, for example, when an ibss merge
2470                          * causes reconfiguration; we may be called
2471                          * with beacon transmission active.
2472                          */
2473                         ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2474
2475                         error = ath_beacon_alloc(aphy, vif);
2476                         if (error != 0) {
2477                                 mutex_unlock(&sc->mutex);
2478                                 return error;
2479                         }
2480
2481                         ath_beacon_config(sc, vif);
2482                 }
2483         }
2484
2485         /* Check for WLAN_CAPABILITY_PRIVACY ? */
2486         if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
2487                 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2488                         if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2489                                 ath9k_hw_keysetmac(sc->sc_ah,
2490                                                    (u16)i,
2491                                                    sc->curbssid);
2492         }
2493
2494         /* Only legacy IBSS for now */
2495         if (vif->type == NL80211_IFTYPE_ADHOC)
2496                 ath_update_chainmask(sc, 0);
2497
2498         mutex_unlock(&sc->mutex);
2499
2500         return 0;
2501 }
2502
2503 #define SUPPORTED_FILTERS                       \
2504         (FIF_PROMISC_IN_BSS |                   \
2505         FIF_ALLMULTI |                          \
2506         FIF_CONTROL |                           \
2507         FIF_OTHER_BSS |                         \
2508         FIF_BCN_PRBRESP_PROMISC |               \
2509         FIF_FCSFAIL)
2510
2511 /* FIXME: sc->sc_full_reset ? */
2512 static void ath9k_configure_filter(struct ieee80211_hw *hw,
2513                                    unsigned int changed_flags,
2514                                    unsigned int *total_flags,
2515                                    int mc_count,
2516                                    struct dev_mc_list *mclist)
2517 {
2518         struct ath_wiphy *aphy = hw->priv;
2519         struct ath_softc *sc = aphy->sc;
2520         u32 rfilt;
2521
2522         changed_flags &= SUPPORTED_FILTERS;
2523         *total_flags &= SUPPORTED_FILTERS;
2524
2525         sc->rx.rxfilter = *total_flags;
2526         rfilt = ath_calcrxfilter(sc);
2527         ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
2528
2529         DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", sc->rx.rxfilter);
2530 }
2531
2532 static void ath9k_sta_notify(struct ieee80211_hw *hw,
2533                              struct ieee80211_vif *vif,
2534                              enum sta_notify_cmd cmd,
2535                              struct ieee80211_sta *sta)
2536 {
2537         struct ath_wiphy *aphy = hw->priv;
2538         struct ath_softc *sc = aphy->sc;
2539
2540         switch (cmd) {
2541         case STA_NOTIFY_ADD:
2542                 ath_node_attach(sc, sta);
2543                 break;
2544         case STA_NOTIFY_REMOVE:
2545                 ath_node_detach(sc, sta);
2546                 break;
2547         default:
2548                 break;
2549         }
2550 }
2551
2552 static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
2553                          const struct ieee80211_tx_queue_params *params)
2554 {
2555         struct ath_wiphy *aphy = hw->priv;
2556         struct ath_softc *sc = aphy->sc;
2557         struct ath9k_tx_queue_info qi;
2558         int ret = 0, qnum;
2559
2560         if (queue >= WME_NUM_AC)
2561                 return 0;
2562
2563         mutex_lock(&sc->mutex);
2564
2565         qi.tqi_aifs = params->aifs;
2566         qi.tqi_cwmin = params->cw_min;
2567         qi.tqi_cwmax = params->cw_max;
2568         qi.tqi_burstTime = params->txop;
2569         qnum = ath_get_hal_qnum(queue, sc);
2570
2571         DPRINTF(sc, ATH_DBG_CONFIG,
2572                 "Configure tx [queue/halq] [%d/%d],  "
2573                 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
2574                 queue, qnum, params->aifs, params->cw_min,
2575                 params->cw_max, params->txop);
2576
2577         ret = ath_txq_update(sc, qnum, &qi);
2578         if (ret)
2579                 DPRINTF(sc, ATH_DBG_FATAL, "TXQ Update failed\n");
2580
2581         mutex_unlock(&sc->mutex);
2582
2583         return ret;
2584 }
2585
2586 static int ath9k_set_key(struct ieee80211_hw *hw,
2587                          enum set_key_cmd cmd,
2588                          struct ieee80211_vif *vif,
2589                          struct ieee80211_sta *sta,
2590                          struct ieee80211_key_conf *key)
2591 {
2592         struct ath_wiphy *aphy = hw->priv;
2593         struct ath_softc *sc = aphy->sc;
2594         int ret = 0;
2595
2596         if (modparam_nohwcrypt)
2597                 return -ENOSPC;
2598
2599         mutex_lock(&sc->mutex);
2600         ath9k_ps_wakeup(sc);
2601         DPRINTF(sc, ATH_DBG_KEYCACHE, "Set HW Key\n");
2602
2603         switch (cmd) {
2604         case SET_KEY:
2605                 ret = ath_key_config(sc, vif, sta, key);
2606                 if (ret >= 0) {
2607                         key->hw_key_idx = ret;
2608                         /* push IV and Michael MIC generation to stack */
2609                         key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2610                         if (key->alg == ALG_TKIP)
2611                                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
2612                         if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
2613                                 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
2614                         ret = 0;
2615                 }
2616                 break;
2617         case DISABLE_KEY:
2618                 ath_key_delete(sc, key);
2619                 break;
2620         default:
2621                 ret = -EINVAL;
2622         }
2623
2624         ath9k_ps_restore(sc);
2625         mutex_unlock(&sc->mutex);
2626
2627         return ret;
2628 }
2629
2630 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2631                                    struct ieee80211_vif *vif,
2632                                    struct ieee80211_bss_conf *bss_conf,
2633                                    u32 changed)
2634 {
2635         struct ath_wiphy *aphy = hw->priv;
2636         struct ath_softc *sc = aphy->sc;
2637
2638         mutex_lock(&sc->mutex);
2639
2640         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
2641                 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
2642                         bss_conf->use_short_preamble);
2643                 if (bss_conf->use_short_preamble)
2644                         sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2645                 else
2646                         sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2647         }
2648
2649         if (changed & BSS_CHANGED_ERP_CTS_PROT) {
2650                 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
2651                         bss_conf->use_cts_prot);
2652                 if (bss_conf->use_cts_prot &&
2653                     hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2654                         sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2655                 else
2656                         sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2657         }
2658
2659         if (changed & BSS_CHANGED_ASSOC) {
2660                 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
2661                         bss_conf->assoc);
2662                 ath9k_bss_assoc_info(sc, vif, bss_conf);
2663         }
2664
2665         mutex_unlock(&sc->mutex);
2666 }
2667
2668 static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2669 {
2670         u64 tsf;
2671         struct ath_wiphy *aphy = hw->priv;
2672         struct ath_softc *sc = aphy->sc;
2673
2674         mutex_lock(&sc->mutex);
2675         tsf = ath9k_hw_gettsf64(sc->sc_ah);
2676         mutex_unlock(&sc->mutex);
2677
2678         return tsf;
2679 }
2680
2681 static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
2682 {
2683         struct ath_wiphy *aphy = hw->priv;
2684         struct ath_softc *sc = aphy->sc;
2685
2686         mutex_lock(&sc->mutex);
2687         ath9k_hw_settsf64(sc->sc_ah, tsf);
2688         mutex_unlock(&sc->mutex);
2689 }
2690
2691 static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2692 {
2693         struct ath_wiphy *aphy = hw->priv;
2694         struct ath_softc *sc = aphy->sc;
2695
2696         mutex_lock(&sc->mutex);
2697         ath9k_hw_reset_tsf(sc->sc_ah);
2698         mutex_unlock(&sc->mutex);
2699 }
2700
2701 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
2702                               enum ieee80211_ampdu_mlme_action action,
2703                               struct ieee80211_sta *sta,
2704                               u16 tid, u16 *ssn)
2705 {
2706         struct ath_wiphy *aphy = hw->priv;
2707         struct ath_softc *sc = aphy->sc;
2708         int ret = 0;
2709
2710         switch (action) {
2711         case IEEE80211_AMPDU_RX_START:
2712                 if (!(sc->sc_flags & SC_OP_RXAGGR))
2713                         ret = -ENOTSUPP;
2714                 break;
2715         case IEEE80211_AMPDU_RX_STOP:
2716                 break;
2717         case IEEE80211_AMPDU_TX_START:
2718                 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
2719                 if (ret < 0)
2720                         DPRINTF(sc, ATH_DBG_FATAL,
2721                                 "Unable to start TX aggregation\n");
2722                 else
2723                         ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2724                 break;
2725         case IEEE80211_AMPDU_TX_STOP:
2726                 ret = ath_tx_aggr_stop(sc, sta, tid);
2727                 if (ret < 0)
2728                         DPRINTF(sc, ATH_DBG_FATAL,
2729                                 "Unable to stop TX aggregation\n");
2730
2731                 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2732                 break;
2733         case IEEE80211_AMPDU_TX_OPERATIONAL:
2734                 ath_tx_aggr_resume(sc, sta, tid);
2735                 break;
2736         default:
2737                 DPRINTF(sc, ATH_DBG_FATAL, "Unknown AMPDU action\n");
2738         }
2739
2740         return ret;
2741 }
2742
2743 static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
2744 {
2745         struct ath_wiphy *aphy = hw->priv;
2746         struct ath_softc *sc = aphy->sc;
2747
2748         if (ath9k_wiphy_scanning(sc)) {
2749                 printk(KERN_DEBUG "ath9k: Two wiphys trying to scan at the "
2750                        "same time\n");
2751                 /*
2752                  * Do not allow the concurrent scanning state for now. This
2753                  * could be improved with scanning control moved into ath9k.
2754                  */
2755                 return;
2756         }
2757
2758         aphy->state = ATH_WIPHY_SCAN;
2759         ath9k_wiphy_pause_all_forced(sc, aphy);
2760
2761         mutex_lock(&sc->mutex);
2762         sc->sc_flags |= SC_OP_SCANNING;
2763         mutex_unlock(&sc->mutex);
2764 }
2765
2766 static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
2767 {
2768         struct ath_wiphy *aphy = hw->priv;
2769         struct ath_softc *sc = aphy->sc;
2770
2771         mutex_lock(&sc->mutex);
2772         aphy->state = ATH_WIPHY_ACTIVE;
2773         sc->sc_flags &= ~SC_OP_SCANNING;
2774         mutex_unlock(&sc->mutex);
2775 }
2776
2777 struct ieee80211_ops ath9k_ops = {
2778         .tx                 = ath9k_tx,
2779         .start              = ath9k_start,
2780         .stop               = ath9k_stop,
2781         .add_interface      = ath9k_add_interface,
2782         .remove_interface   = ath9k_remove_interface,
2783         .config             = ath9k_config,
2784         .config_interface   = ath9k_config_interface,
2785         .configure_filter   = ath9k_configure_filter,
2786         .sta_notify         = ath9k_sta_notify,
2787         .conf_tx            = ath9k_conf_tx,
2788         .bss_info_changed   = ath9k_bss_info_changed,
2789         .set_key            = ath9k_set_key,
2790         .get_tsf            = ath9k_get_tsf,
2791         .set_tsf            = ath9k_set_tsf,
2792         .reset_tsf          = ath9k_reset_tsf,
2793         .ampdu_action       = ath9k_ampdu_action,
2794         .sw_scan_start      = ath9k_sw_scan_start,
2795         .sw_scan_complete   = ath9k_sw_scan_complete,
2796 };
2797
2798 static struct {
2799         u32 version;
2800         const char * name;
2801 } ath_mac_bb_names[] = {
2802         { AR_SREV_VERSION_5416_PCI,     "5416" },
2803         { AR_SREV_VERSION_5416_PCIE,    "5418" },
2804         { AR_SREV_VERSION_9100,         "9100" },
2805         { AR_SREV_VERSION_9160,         "9160" },
2806         { AR_SREV_VERSION_9280,         "9280" },
2807         { AR_SREV_VERSION_9285,         "9285" }
2808 };
2809
2810 static struct {
2811         u16 version;
2812         const char * name;
2813 } ath_rf_names[] = {
2814         { 0,                            "5133" },
2815         { AR_RAD5133_SREV_MAJOR,        "5133" },
2816         { AR_RAD5122_SREV_MAJOR,        "5122" },
2817         { AR_RAD2133_SREV_MAJOR,        "2133" },
2818         { AR_RAD2122_SREV_MAJOR,        "2122" }
2819 };
2820
2821 /*
2822  * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2823  */
2824 const char *
2825 ath_mac_bb_name(u32 mac_bb_version)
2826 {
2827         int i;
2828
2829         for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2830                 if (ath_mac_bb_names[i].version == mac_bb_version) {
2831                         return ath_mac_bb_names[i].name;
2832                 }
2833         }
2834
2835         return "????";
2836 }
2837
2838 /*
2839  * Return the RF name. "????" is returned if the RF is unknown.
2840  */
2841 const char *
2842 ath_rf_name(u16 rf_version)
2843 {
2844         int i;
2845
2846         for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2847                 if (ath_rf_names[i].version == rf_version) {
2848                         return ath_rf_names[i].name;
2849                 }
2850         }
2851
2852         return "????";
2853 }
2854
2855 static int __init ath9k_init(void)
2856 {
2857         int error;
2858
2859         /* Register rate control algorithm */
2860         error = ath_rate_control_register();
2861         if (error != 0) {
2862                 printk(KERN_ERR
2863                         "ath9k: Unable to register rate control "
2864                         "algorithm: %d\n",
2865                         error);
2866                 goto err_out;
2867         }
2868
2869         error = ath9k_debug_create_root();
2870         if (error) {
2871                 printk(KERN_ERR
2872                         "ath9k: Unable to create debugfs root: %d\n",
2873                         error);
2874                 goto err_rate_unregister;
2875         }
2876
2877         error = ath_pci_init();
2878         if (error < 0) {
2879                 printk(KERN_ERR
2880                         "ath9k: No PCI devices found, driver not installed.\n");
2881                 error = -ENODEV;
2882                 goto err_remove_root;
2883         }
2884
2885         error = ath_ahb_init();
2886         if (error < 0) {
2887                 error = -ENODEV;
2888                 goto err_pci_exit;
2889         }
2890
2891         return 0;
2892
2893  err_pci_exit:
2894         ath_pci_exit();
2895
2896  err_remove_root:
2897         ath9k_debug_remove_root();
2898  err_rate_unregister:
2899         ath_rate_control_unregister();
2900  err_out:
2901         return error;
2902 }
2903 module_init(ath9k_init);
2904
2905 static void __exit ath9k_exit(void)
2906 {
2907         ath_ahb_exit();
2908         ath_pci_exit();
2909         ath9k_debug_remove_root();
2910         ath_rate_control_unregister();
2911         printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
2912 }
2913 module_exit(ath9k_exit);