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   1 /*
   2  * arch/sh/kernel/cpu/sh4/probe.c
   3  *
   4  * CPU Subtype Probing for SH-4.
   5  *
   6  * Copyright (C) 2001, 2002, 2003, 2004  Paul Mundt
   7  * Copyright (C) 2003  Richard Curnow
   8  *
   9  * This file is subject to the terms and conditions of the GNU General Public
  10  * License.  See the file "COPYING" in the main directory of this archive
  11  * for more details.
  12  */
  13
  14 #include <linux/init.h>
  15 #include <asm/processor.h>
  16 #include <asm/cache.h>
  17 #include <asm/io.h>
  18
  19 int __init detect_cpu_and_cache_system(void)
  20 {
  21         unsigned long pvr, prr, cvr;
  22         unsigned long size;
  23
  24         static unsigned long sizes[16] = {
  25                 [1] = (1 << 12),
  26                 [2] = (1 << 13),
  27                 [4] = (1 << 14),
  28                 [8] = (1 << 15),
  29                 [9] = (1 << 16)
  30         };
  31
  32         pvr = (ctrl_inl(CCN_PVR) >> 8) & 0xffff;
  33         prr = (ctrl_inl(CCN_PRR) >> 4) & 0xff;
  34         cvr = (ctrl_inl(CCN_CVR));
  35
  36         /*
  37          * Setup some sane SH-4 defaults for the icache
  38          */
  39         cpu_data->icache.way_incr       = (1 << 13);
  40         cpu_data->icache.entry_shift    = 5;
  41         cpu_data->icache.entry_mask     = 0x1fe0;
  42         cpu_data->icache.sets           = 256;
  43         cpu_data->icache.ways           = 1;
  44         cpu_data->icache.linesz         = L1_CACHE_BYTES;
  45
  46         /*
  47          * And again for the dcache ..
  48          */
  49         cpu_data->dcache.way_incr       = (1 << 14);
  50         cpu_data->dcache.entry_shift    = 5;
  51         cpu_data->dcache.entry_mask     = 0x3fe0;
  52         cpu_data->dcache.sets           = 512;
  53         cpu_data->dcache.ways           = 1;
  54         cpu_data->dcache.linesz         = L1_CACHE_BYTES;
  55
  56         /* Set the FPU flag, virtually all SH-4's have one */
  57         cpu_data->flags |= CPU_HAS_FPU;
  58
  59         /*
  60          * Probe the underlying processor version/revision and
  61          * adjust cpu_data setup accordingly.
  62          */
  63         switch (pvr) {
  64         case 0x205:
  65                 cpu_data->type = CPU_SH7750;
  66                 cpu_data->flags |= CPU_HAS_P2_FLUSH_BUG | CPU_HAS_PERF_COUNTER;
  67                 break;
  68         case 0x206:
  69                 cpu_data->type = CPU_SH7750S;
  70                 cpu_data->flags |= CPU_HAS_P2_FLUSH_BUG | CPU_HAS_PERF_COUNTER;
  71                 break;
  72         case 0x1100:
  73                 cpu_data->type = CPU_SH7751;
  74                 break;
  75         case 0x2000:
  76                 cpu_data->type = CPU_SH73180;
  77                 cpu_data->icache.ways = 4;
  78                 cpu_data->dcache.ways = 4;
  79                 cpu_data->flags &= ~CPU_HAS_FPU;
  80                 break;
  81         case 0x2001:
  82         case 0x2004:
  83                 cpu_data->type = CPU_SH7770;
  84                 cpu_data->icache.ways = 4;
  85                 cpu_data->dcache.ways = 4;
  86                 break;
  87         case 0x2006:
  88         case 0x200A:
  89                 if (prr == 0x61)
  90                         cpu_data->type = CPU_SH7781;
  91                 else
  92                         cpu_data->type = CPU_SH7780;
  93                 cpu_data->icache.ways = 4;
  94                 cpu_data->dcache.ways = 4;
  95                 break;
  96         case 0x8000:
  97                 cpu_data->type = CPU_ST40RA;
  98                 break;
  99         case 0x8100:
 100                 cpu_data->type = CPU_ST40GX1;
 101                 break;
 102         case 0x700:
 103                 cpu_data->type = CPU_SH4_501;
 104                 cpu_data->icache.ways = 2;
 105                 cpu_data->dcache.ways = 2;
 106
 107                 /* No FPU on the SH4-500 series.. */
 108                 cpu_data->flags &= ~CPU_HAS_FPU;
 109                 break;
 110         case 0x600:
 111                 cpu_data->type = CPU_SH4_202;
 112                 cpu_data->icache.ways = 2;
 113                 cpu_data->dcache.ways = 2;
 114                 break;
 115         case 0x500 ... 0x501:
 116                 switch (prr) {
 117                 case 0x10:
 118                         cpu_data->type = CPU_SH7750R;
 119                         break;
 120                 case 0x11:
 121                         cpu_data->type = CPU_SH7751R;
 122                         break;
 123                 case 0x50 ... 0x5f:
 124                         cpu_data->type = CPU_SH7760;
 125                         break;
 126                 }
 127
 128                 cpu_data->icache.ways = 2;
 129                 cpu_data->dcache.ways = 2;
 130
 131                 break;
 132         default:
 133                 cpu_data->type = CPU_SH_NONE;
 134                 break;
 135         }
 136
 137 #ifdef CONFIG_SH_DIRECT_MAPPED
 138         cpu_data->icache.ways = 1;
 139         cpu_data->dcache.ways = 1;
 140 #endif
 141
 142         /*
 143          * On anything that's not a direct-mapped cache, look to the CVR
 144          * for I/D-cache specifics.
 145          */
 146         if (cpu_data->icache.ways > 1) {
 147                 size = sizes[(cvr >> 20) & 0xf];
 148                 cpu_data->icache.way_incr       = (size >> 1);
 149                 cpu_data->icache.sets           = (size >> 6);
 150                 cpu_data->icache.entry_mask     =
 151                         (cpu_data->icache.way_incr - (1 << 5));
 152         }
 153
 154         cpu_data->icache.way_size = cpu_data->icache.sets *
 155                                     cpu_data->icache.linesz;
 156
 157         if (cpu_data->dcache.ways > 1) {
 158                 size = sizes[(cvr >> 16) & 0xf];
 159                 cpu_data->dcache.way_incr       = (size >> 1);
 160                 cpu_data->dcache.sets           = (size >> 6);
 161                 cpu_data->dcache.entry_mask     =
 162                         (cpu_data->dcache.way_incr - (1 << 5));
 163         }
 164
 165         cpu_data->dcache.way_size = cpu_data->dcache.sets *
 166                                     cpu_data->dcache.linesz;
 167
 168         return 0;
 169 }
 170