2 * arch/ppc/platforms/85xx/mpc85xx_devices.c
4 * MPC85xx Device descriptions
6 * Maintainer: Kumar Gala <kumar.gala@freescale.com>
8 * Copyright 2005 Freescale Semiconductor Inc.
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
16 #include <linux/init.h>
17 #include <linux/module.h>
18 #include <linux/device.h>
19 #include <linux/serial_8250.h>
20 #include <linux/fsl_devices.h>
21 #include <asm/mpc85xx.h>
23 #include <asm/ppc_sys.h>
25 /* We use offsets for IORESOURCE_MEM since we do not know at compile time
26 * what CCSRBAR is, will get fixed up by mach_mpc85xx_fixup
29 static struct gianfar_platform_data mpc85xx_tsec1_pdata = {
30 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
31 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
32 FSL_GIANFAR_DEV_HAS_MULTI_INTR,
33 .phy_reg_addr = MPC85xx_ENET1_OFFSET,
36 static struct gianfar_platform_data mpc85xx_tsec2_pdata = {
37 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
38 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
39 FSL_GIANFAR_DEV_HAS_MULTI_INTR,
40 .phy_reg_addr = MPC85xx_ENET1_OFFSET,
43 static struct gianfar_platform_data mpc85xx_etsec1_pdata = {
44 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
45 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
46 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
47 FSL_GIANFAR_DEV_HAS_CSUM | FSL_GIANFAR_DEV_HAS_VLAN |
48 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH,
49 .phy_reg_addr = MPC85xx_ENET1_OFFSET,
52 static struct gianfar_platform_data mpc85xx_etsec2_pdata = {
53 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
54 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
55 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
56 FSL_GIANFAR_DEV_HAS_CSUM | FSL_GIANFAR_DEV_HAS_VLAN |
57 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH,
58 .phy_reg_addr = MPC85xx_ENET1_OFFSET,
61 static struct gianfar_platform_data mpc85xx_etsec3_pdata = {
62 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
63 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
64 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
65 FSL_GIANFAR_DEV_HAS_CSUM | FSL_GIANFAR_DEV_HAS_VLAN |
66 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH,
67 .phy_reg_addr = MPC85xx_ENET1_OFFSET,
70 static struct gianfar_platform_data mpc85xx_etsec4_pdata = {
71 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
72 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
73 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
74 FSL_GIANFAR_DEV_HAS_CSUM | FSL_GIANFAR_DEV_HAS_VLAN |
75 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH,
76 .phy_reg_addr = MPC85xx_ENET1_OFFSET,
79 static struct gianfar_platform_data mpc85xx_fec_pdata = {
80 .phy_reg_addr = MPC85xx_ENET1_OFFSET,
83 static struct fsl_i2c_platform_data mpc85xx_fsl_i2c_pdata = {
84 .device_flags = FSL_I2C_DEV_SEPARATE_DFSRR,
87 static struct fsl_i2c_platform_data mpc85xx_fsl_i2c2_pdata = {
88 .device_flags = FSL_I2C_DEV_SEPARATE_DFSRR,
91 static struct plat_serial8250_port serial_platform_data[] = {
94 .irq = MPC85xx_IRQ_DUART,
96 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_SHARE_IRQ,
100 .irq = MPC85xx_IRQ_DUART,
102 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_SHARE_IRQ,
107 struct platform_device ppc_sys_platform_devices[] = {
109 .name = "fsl-gianfar",
111 .dev.platform_data = &mpc85xx_tsec1_pdata,
113 .resource = (struct resource[]) {
115 .start = MPC85xx_ENET1_OFFSET,
116 .end = MPC85xx_ENET1_OFFSET +
117 MPC85xx_ENET1_SIZE - 1,
118 .flags = IORESOURCE_MEM,
122 .start = MPC85xx_IRQ_TSEC1_TX,
123 .end = MPC85xx_IRQ_TSEC1_TX,
124 .flags = IORESOURCE_IRQ,
128 .start = MPC85xx_IRQ_TSEC1_RX,
129 .end = MPC85xx_IRQ_TSEC1_RX,
130 .flags = IORESOURCE_IRQ,
134 .start = MPC85xx_IRQ_TSEC1_ERROR,
135 .end = MPC85xx_IRQ_TSEC1_ERROR,
136 .flags = IORESOURCE_IRQ,
141 .name = "fsl-gianfar",
143 .dev.platform_data = &mpc85xx_tsec2_pdata,
145 .resource = (struct resource[]) {
147 .start = MPC85xx_ENET2_OFFSET,
148 .end = MPC85xx_ENET2_OFFSET +
149 MPC85xx_ENET2_SIZE - 1,
150 .flags = IORESOURCE_MEM,
154 .start = MPC85xx_IRQ_TSEC2_TX,
155 .end = MPC85xx_IRQ_TSEC2_TX,
156 .flags = IORESOURCE_IRQ,
160 .start = MPC85xx_IRQ_TSEC2_RX,
161 .end = MPC85xx_IRQ_TSEC2_RX,
162 .flags = IORESOURCE_IRQ,
166 .start = MPC85xx_IRQ_TSEC2_ERROR,
167 .end = MPC85xx_IRQ_TSEC2_ERROR,
168 .flags = IORESOURCE_IRQ,
173 .name = "fsl-gianfar",
175 .dev.platform_data = &mpc85xx_fec_pdata,
177 .resource = (struct resource[]) {
179 .start = MPC85xx_ENET3_OFFSET,
180 .end = MPC85xx_ENET3_OFFSET +
181 MPC85xx_ENET3_SIZE - 1,
182 .flags = IORESOURCE_MEM,
186 .start = MPC85xx_IRQ_FEC,
187 .end = MPC85xx_IRQ_FEC,
188 .flags = IORESOURCE_IRQ,
195 .dev.platform_data = &mpc85xx_fsl_i2c_pdata,
197 .resource = (struct resource[]) {
199 .start = MPC85xx_IIC1_OFFSET,
200 .end = MPC85xx_IIC1_OFFSET +
201 MPC85xx_IIC1_SIZE - 1,
202 .flags = IORESOURCE_MEM,
205 .start = MPC85xx_IRQ_IIC1,
206 .end = MPC85xx_IRQ_IIC1,
207 .flags = IORESOURCE_IRQ,
215 .resource = (struct resource[]) {
217 .start = MPC85xx_DMA0_OFFSET,
218 .end = MPC85xx_DMA0_OFFSET +
219 MPC85xx_DMA0_SIZE - 1,
220 .flags = IORESOURCE_MEM,
223 .start = MPC85xx_IRQ_DMA0,
224 .end = MPC85xx_IRQ_DMA0,
225 .flags = IORESOURCE_IRQ,
233 .resource = (struct resource[]) {
235 .start = MPC85xx_DMA1_OFFSET,
236 .end = MPC85xx_DMA1_OFFSET +
237 MPC85xx_DMA1_SIZE - 1,
238 .flags = IORESOURCE_MEM,
241 .start = MPC85xx_IRQ_DMA1,
242 .end = MPC85xx_IRQ_DMA1,
243 .flags = IORESOURCE_IRQ,
251 .resource = (struct resource[]) {
253 .start = MPC85xx_DMA2_OFFSET,
254 .end = MPC85xx_DMA2_OFFSET +
255 MPC85xx_DMA2_SIZE - 1,
256 .flags = IORESOURCE_MEM,
259 .start = MPC85xx_IRQ_DMA2,
260 .end = MPC85xx_IRQ_DMA2,
261 .flags = IORESOURCE_IRQ,
269 .resource = (struct resource[]) {
271 .start = MPC85xx_DMA3_OFFSET,
272 .end = MPC85xx_DMA3_OFFSET +
273 MPC85xx_DMA3_SIZE - 1,
274 .flags = IORESOURCE_MEM,
277 .start = MPC85xx_IRQ_DMA3,
278 .end = MPC85xx_IRQ_DMA3,
279 .flags = IORESOURCE_IRQ,
284 .name = "serial8250",
286 .dev.platform_data = serial_platform_data,
288 [MPC85xx_PERFMON] = {
289 .name = "fsl-perfmon",
292 .resource = (struct resource[]) {
294 .start = MPC85xx_PERFMON_OFFSET,
295 .end = MPC85xx_PERFMON_OFFSET +
296 MPC85xx_PERFMON_SIZE - 1,
297 .flags = IORESOURCE_MEM,
300 .start = MPC85xx_IRQ_PERFMON,
301 .end = MPC85xx_IRQ_PERFMON,
302 .flags = IORESOURCE_IRQ,
310 .resource = (struct resource[]) {
312 .start = MPC85xx_SEC2_OFFSET,
313 .end = MPC85xx_SEC2_OFFSET +
314 MPC85xx_SEC2_SIZE - 1,
315 .flags = IORESOURCE_MEM,
318 .start = MPC85xx_IRQ_SEC2,
319 .end = MPC85xx_IRQ_SEC2,
320 .flags = IORESOURCE_IRQ,
325 [MPC85xx_CPM_FCC1] = {
326 .name = "fsl-cpm-fcc",
329 .resource = (struct resource[]) {
333 .flags = IORESOURCE_MEM,
338 .flags = IORESOURCE_MEM,
341 .start = SIU_INT_FCC1,
343 .flags = IORESOURCE_IRQ,
347 [MPC85xx_CPM_FCC2] = {
348 .name = "fsl-cpm-fcc",
351 .resource = (struct resource[]) {
355 .flags = IORESOURCE_MEM,
360 .flags = IORESOURCE_MEM,
363 .start = SIU_INT_FCC2,
365 .flags = IORESOURCE_IRQ,
369 [MPC85xx_CPM_FCC3] = {
370 .name = "fsl-cpm-fcc",
373 .resource = (struct resource[]) {
377 .flags = IORESOURCE_MEM,
382 .flags = IORESOURCE_MEM,
385 .start = SIU_INT_FCC3,
387 .flags = IORESOURCE_IRQ,
391 [MPC85xx_CPM_I2C] = {
392 .name = "fsl-cpm-i2c",
395 .resource = (struct resource[]) {
399 .flags = IORESOURCE_MEM,
402 .start = SIU_INT_I2C,
404 .flags = IORESOURCE_IRQ,
408 [MPC85xx_CPM_SCC1] = {
409 .name = "fsl-cpm-scc",
412 .resource = (struct resource[]) {
416 .flags = IORESOURCE_MEM,
419 .start = SIU_INT_SCC1,
421 .flags = IORESOURCE_IRQ,
425 [MPC85xx_CPM_SCC2] = {
426 .name = "fsl-cpm-scc",
429 .resource = (struct resource[]) {
433 .flags = IORESOURCE_MEM,
436 .start = SIU_INT_SCC2,
438 .flags = IORESOURCE_IRQ,
442 [MPC85xx_CPM_SCC3] = {
443 .name = "fsl-cpm-scc",
446 .resource = (struct resource[]) {
450 .flags = IORESOURCE_MEM,
453 .start = SIU_INT_SCC3,
455 .flags = IORESOURCE_IRQ,
459 [MPC85xx_CPM_SCC4] = {
460 .name = "fsl-cpm-scc",
463 .resource = (struct resource[]) {
467 .flags = IORESOURCE_MEM,
470 .start = SIU_INT_SCC4,
472 .flags = IORESOURCE_IRQ,
476 [MPC85xx_CPM_SPI] = {
477 .name = "fsl-cpm-spi",
480 .resource = (struct resource[]) {
484 .flags = IORESOURCE_MEM,
487 .start = SIU_INT_SPI,
489 .flags = IORESOURCE_IRQ,
493 [MPC85xx_CPM_MCC1] = {
494 .name = "fsl-cpm-mcc",
497 .resource = (struct resource[]) {
501 .flags = IORESOURCE_MEM,
504 .start = SIU_INT_MCC1,
506 .flags = IORESOURCE_IRQ,
510 [MPC85xx_CPM_MCC2] = {
511 .name = "fsl-cpm-mcc",
514 .resource = (struct resource[]) {
518 .flags = IORESOURCE_MEM,
521 .start = SIU_INT_MCC2,
523 .flags = IORESOURCE_IRQ,
527 [MPC85xx_CPM_SMC1] = {
528 .name = "fsl-cpm-smc",
531 .resource = (struct resource[]) {
535 .flags = IORESOURCE_MEM,
538 .start = SIU_INT_SMC1,
540 .flags = IORESOURCE_IRQ,
544 [MPC85xx_CPM_SMC2] = {
545 .name = "fsl-cpm-smc",
548 .resource = (struct resource[]) {
552 .flags = IORESOURCE_MEM,
555 .start = SIU_INT_SMC2,
557 .flags = IORESOURCE_IRQ,
561 [MPC85xx_CPM_USB] = {
562 .name = "fsl-cpm-usb",
565 .resource = (struct resource[]) {
569 .flags = IORESOURCE_MEM,
572 .start = SIU_INT_USB,
574 .flags = IORESOURCE_IRQ,
578 #endif /* CONFIG_CPM2 */
580 .name = "fsl-gianfar",
582 .dev.platform_data = &mpc85xx_etsec1_pdata,
584 .resource = (struct resource[]) {
586 .start = MPC85xx_ENET1_OFFSET,
587 .end = MPC85xx_ENET1_OFFSET +
588 MPC85xx_ENET1_SIZE - 1,
589 .flags = IORESOURCE_MEM,
593 .start = MPC85xx_IRQ_TSEC1_TX,
594 .end = MPC85xx_IRQ_TSEC1_TX,
595 .flags = IORESOURCE_IRQ,
599 .start = MPC85xx_IRQ_TSEC1_RX,
600 .end = MPC85xx_IRQ_TSEC1_RX,
601 .flags = IORESOURCE_IRQ,
605 .start = MPC85xx_IRQ_TSEC1_ERROR,
606 .end = MPC85xx_IRQ_TSEC1_ERROR,
607 .flags = IORESOURCE_IRQ,
612 .name = "fsl-gianfar",
614 .dev.platform_data = &mpc85xx_etsec2_pdata,
616 .resource = (struct resource[]) {
618 .start = MPC85xx_ENET2_OFFSET,
619 .end = MPC85xx_ENET2_OFFSET +
620 MPC85xx_ENET2_SIZE - 1,
621 .flags = IORESOURCE_MEM,
625 .start = MPC85xx_IRQ_TSEC2_TX,
626 .end = MPC85xx_IRQ_TSEC2_TX,
627 .flags = IORESOURCE_IRQ,
631 .start = MPC85xx_IRQ_TSEC2_RX,
632 .end = MPC85xx_IRQ_TSEC2_RX,
633 .flags = IORESOURCE_IRQ,
637 .start = MPC85xx_IRQ_TSEC2_ERROR,
638 .end = MPC85xx_IRQ_TSEC2_ERROR,
639 .flags = IORESOURCE_IRQ,
644 .name = "fsl-gianfar",
646 .dev.platform_data = &mpc85xx_etsec3_pdata,
648 .resource = (struct resource[]) {
650 .start = MPC85xx_ENET3_OFFSET,
651 .end = MPC85xx_ENET3_OFFSET +
652 MPC85xx_ENET3_SIZE - 1,
653 .flags = IORESOURCE_MEM,
657 .start = MPC85xx_IRQ_TSEC3_TX,
658 .end = MPC85xx_IRQ_TSEC3_TX,
659 .flags = IORESOURCE_IRQ,
663 .start = MPC85xx_IRQ_TSEC3_RX,
664 .end = MPC85xx_IRQ_TSEC3_RX,
665 .flags = IORESOURCE_IRQ,
669 .start = MPC85xx_IRQ_TSEC3_ERROR,
670 .end = MPC85xx_IRQ_TSEC3_ERROR,
671 .flags = IORESOURCE_IRQ,
676 .name = "fsl-gianfar",
678 .dev.platform_data = &mpc85xx_etsec4_pdata,
680 .resource = (struct resource[]) {
684 .flags = IORESOURCE_MEM,
688 .start = MPC85xx_IRQ_TSEC4_TX,
689 .end = MPC85xx_IRQ_TSEC4_TX,
690 .flags = IORESOURCE_IRQ,
694 .start = MPC85xx_IRQ_TSEC4_RX,
695 .end = MPC85xx_IRQ_TSEC4_RX,
696 .flags = IORESOURCE_IRQ,
700 .start = MPC85xx_IRQ_TSEC4_ERROR,
701 .end = MPC85xx_IRQ_TSEC4_ERROR,
702 .flags = IORESOURCE_IRQ,
709 .dev.platform_data = &mpc85xx_fsl_i2c2_pdata,
711 .resource = (struct resource[]) {
715 .flags = IORESOURCE_MEM,
718 .start = MPC85xx_IRQ_IIC1,
719 .end = MPC85xx_IRQ_IIC1,
720 .flags = IORESOURCE_IRQ,
726 static int __init mach_mpc85xx_fixup(struct platform_device *pdev)
728 ppc_sys_fixup_mem_resource(pdev, CCSRBAR);
732 static int __init mach_mpc85xx_init(void)
734 ppc_sys_device_fixup = mach_mpc85xx_fixup;
738 postcore_initcall(mach_mpc85xx_init);