Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6
[linux-2.6] / drivers / net / wireless / ath5k / eeprom.c
1 /*
2  * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
3  * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
4  * Copyright (c) 2008 Felix Fietkau <nbd@openwrt.org>
5  *
6  * Permission to use, copy, modify, and distribute this software for any
7  * purpose with or without fee is hereby granted, provided that the above
8  * copyright notice and this permission notice appear in all copies.
9  *
10  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17  *
18  */
19
20 /*************************************\
21 * EEPROM access functions and helpers *
22 \*************************************/
23
24 #include "ath5k.h"
25 #include "reg.h"
26 #include "debug.h"
27 #include "base.h"
28
29 /*
30  * Read from eeprom
31  */
32 static int ath5k_hw_eeprom_read(struct ath5k_hw *ah, u32 offset, u16 *data)
33 {
34         u32 status, timeout;
35
36         ATH5K_TRACE(ah->ah_sc);
37         /*
38          * Initialize EEPROM access
39          */
40         if (ah->ah_version == AR5K_AR5210) {
41                 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, AR5K_PCICFG_EEAE);
42                 (void)ath5k_hw_reg_read(ah, AR5K_EEPROM_BASE + (4 * offset));
43         } else {
44                 ath5k_hw_reg_write(ah, offset, AR5K_EEPROM_BASE);
45                 AR5K_REG_ENABLE_BITS(ah, AR5K_EEPROM_CMD,
46                                 AR5K_EEPROM_CMD_READ);
47         }
48
49         for (timeout = AR5K_TUNE_REGISTER_TIMEOUT; timeout > 0; timeout--) {
50                 status = ath5k_hw_reg_read(ah, AR5K_EEPROM_STATUS);
51                 if (status & AR5K_EEPROM_STAT_RDDONE) {
52                         if (status & AR5K_EEPROM_STAT_RDERR)
53                                 return -EIO;
54                         *data = (u16)(ath5k_hw_reg_read(ah, AR5K_EEPROM_DATA) &
55                                         0xffff);
56                         return 0;
57                 }
58                 udelay(15);
59         }
60
61         return -ETIMEDOUT;
62 }
63
64 /*
65  * Translate binary channel representation in EEPROM to frequency
66  */
67 static u16 ath5k_eeprom_bin2freq(struct ath5k_eeprom_info *ee, u16 bin,
68                                  unsigned int mode)
69 {
70         u16 val;
71
72         if (bin == AR5K_EEPROM_CHANNEL_DIS)
73                 return bin;
74
75         if (mode == AR5K_EEPROM_MODE_11A) {
76                 if (ee->ee_version > AR5K_EEPROM_VERSION_3_2)
77                         val = (5 * bin) + 4800;
78                 else
79                         val = bin > 62 ? (10 * 62) + (5 * (bin - 62)) + 5100 :
80                                 (bin * 10) + 5100;
81         } else {
82                 if (ee->ee_version > AR5K_EEPROM_VERSION_3_2)
83                         val = bin + 2300;
84                 else
85                         val = bin + 2400;
86         }
87
88         return val;
89 }
90
91 /*
92  * Initialize eeprom & capabilities structs
93  */
94 static int
95 ath5k_eeprom_init_header(struct ath5k_hw *ah)
96 {
97         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
98         int ret;
99         u16 val;
100
101         /* Initial TX thermal adjustment values */
102         ee->ee_tx_clip = 4;
103         ee->ee_pwd_84 = ee->ee_pwd_90 = 1;
104         ee->ee_gain_select = 1;
105
106         /*
107          * Read values from EEPROM and store them in the capability structure
108          */
109         AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MAGIC, ee_magic);
110         AR5K_EEPROM_READ_HDR(AR5K_EEPROM_PROTECT, ee_protect);
111         AR5K_EEPROM_READ_HDR(AR5K_EEPROM_REG_DOMAIN, ee_regdomain);
112         AR5K_EEPROM_READ_HDR(AR5K_EEPROM_VERSION, ee_version);
113         AR5K_EEPROM_READ_HDR(AR5K_EEPROM_HDR, ee_header);
114
115         /* Return if we have an old EEPROM */
116         if (ah->ah_ee_version < AR5K_EEPROM_VERSION_3_0)
117                 return 0;
118
119 #ifdef notyet
120         /*
121          * Validate the checksum of the EEPROM date. There are some
122          * devices with invalid EEPROMs.
123          */
124         for (cksum = 0, offset = 0; offset < AR5K_EEPROM_INFO_MAX; offset++) {
125                 AR5K_EEPROM_READ(AR5K_EEPROM_INFO(offset), val);
126                 cksum ^= val;
127         }
128         if (cksum != AR5K_EEPROM_INFO_CKSUM) {
129                 ATH5K_ERR(ah->ah_sc, "Invalid EEPROM checksum 0x%04x\n", cksum);
130                 return -EIO;
131         }
132 #endif
133
134         AR5K_EEPROM_READ_HDR(AR5K_EEPROM_ANT_GAIN(ah->ah_ee_version),
135             ee_ant_gain);
136
137         if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) {
138                 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC0, ee_misc0);
139                 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC1, ee_misc1);
140         }
141
142         if (ah->ah_ee_version < AR5K_EEPROM_VERSION_3_3) {
143                 AR5K_EEPROM_READ(AR5K_EEPROM_OBDB0_2GHZ, val);
144                 ee->ee_ob[AR5K_EEPROM_MODE_11B][0] = val & 0x7;
145                 ee->ee_db[AR5K_EEPROM_MODE_11B][0] = (val >> 3) & 0x7;
146
147                 AR5K_EEPROM_READ(AR5K_EEPROM_OBDB1_2GHZ, val);
148                 ee->ee_ob[AR5K_EEPROM_MODE_11G][0] = val & 0x7;
149                 ee->ee_db[AR5K_EEPROM_MODE_11G][0] = (val >> 3) & 0x7;
150         }
151
152         return 0;
153 }
154
155
156 /*
157  * Read antenna infos from eeprom
158  */
159 static int ath5k_eeprom_read_ants(struct ath5k_hw *ah, u32 *offset,
160                 unsigned int mode)
161 {
162         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
163         u32 o = *offset;
164         u16 val;
165         int ret, i = 0;
166
167         AR5K_EEPROM_READ(o++, val);
168         ee->ee_switch_settling[mode]    = (val >> 8) & 0x7f;
169         ee->ee_atn_tx_rx[mode]          = (val >> 2) & 0x3f;
170         ee->ee_ant_control[mode][i]     = (val << 4) & 0x3f;
171
172         AR5K_EEPROM_READ(o++, val);
173         ee->ee_ant_control[mode][i++]   |= (val >> 12) & 0xf;
174         ee->ee_ant_control[mode][i++]   = (val >> 6) & 0x3f;
175         ee->ee_ant_control[mode][i++]   = val & 0x3f;
176
177         AR5K_EEPROM_READ(o++, val);
178         ee->ee_ant_control[mode][i++]   = (val >> 10) & 0x3f;
179         ee->ee_ant_control[mode][i++]   = (val >> 4) & 0x3f;
180         ee->ee_ant_control[mode][i]     = (val << 2) & 0x3f;
181
182         AR5K_EEPROM_READ(o++, val);
183         ee->ee_ant_control[mode][i++]   |= (val >> 14) & 0x3;
184         ee->ee_ant_control[mode][i++]   = (val >> 8) & 0x3f;
185         ee->ee_ant_control[mode][i++]   = (val >> 2) & 0x3f;
186         ee->ee_ant_control[mode][i]     = (val << 4) & 0x3f;
187
188         AR5K_EEPROM_READ(o++, val);
189         ee->ee_ant_control[mode][i++]   |= (val >> 12) & 0xf;
190         ee->ee_ant_control[mode][i++]   = (val >> 6) & 0x3f;
191         ee->ee_ant_control[mode][i++]   = val & 0x3f;
192
193         /* Get antenna modes */
194         ah->ah_antenna[mode][0] =
195             (ee->ee_ant_control[mode][0] << 4) | 0x1;
196         ah->ah_antenna[mode][AR5K_ANT_FIXED_A] =
197              ee->ee_ant_control[mode][1]        |
198             (ee->ee_ant_control[mode][2] << 6)  |
199             (ee->ee_ant_control[mode][3] << 12) |
200             (ee->ee_ant_control[mode][4] << 18) |
201             (ee->ee_ant_control[mode][5] << 24);
202         ah->ah_antenna[mode][AR5K_ANT_FIXED_B] =
203              ee->ee_ant_control[mode][6]        |
204             (ee->ee_ant_control[mode][7] << 6)  |
205             (ee->ee_ant_control[mode][8] << 12) |
206             (ee->ee_ant_control[mode][9] << 18) |
207             (ee->ee_ant_control[mode][10] << 24);
208
209         /* return new offset */
210         *offset = o;
211
212         return 0;
213 }
214
215 /*
216  * Read supported modes from eeprom
217  */
218 static int ath5k_eeprom_read_modes(struct ath5k_hw *ah, u32 *offset,
219                 unsigned int mode)
220 {
221         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
222         u32 o = *offset;
223         u16 val;
224         int ret;
225
226         ee->ee_n_piers[mode] = 0;
227         AR5K_EEPROM_READ(o++, val);
228         ee->ee_adc_desired_size[mode]   = (s8)((val >> 8) & 0xff);
229         switch(mode) {
230         case AR5K_EEPROM_MODE_11A:
231                 ee->ee_ob[mode][3]              = (val >> 5) & 0x7;
232                 ee->ee_db[mode][3]              = (val >> 2) & 0x7;
233                 ee->ee_ob[mode][2]              = (val << 1) & 0x7;
234
235                 AR5K_EEPROM_READ(o++, val);
236                 ee->ee_ob[mode][2]              |= (val >> 15) & 0x1;
237                 ee->ee_db[mode][2]              = (val >> 12) & 0x7;
238                 ee->ee_ob[mode][1]              = (val >> 9) & 0x7;
239                 ee->ee_db[mode][1]              = (val >> 6) & 0x7;
240                 ee->ee_ob[mode][0]              = (val >> 3) & 0x7;
241                 ee->ee_db[mode][0]              = val & 0x7;
242                 break;
243         case AR5K_EEPROM_MODE_11G:
244         case AR5K_EEPROM_MODE_11B:
245                 ee->ee_ob[mode][1]              = (val >> 4) & 0x7;
246                 ee->ee_db[mode][1]              = val & 0x7;
247                 break;
248         }
249
250         AR5K_EEPROM_READ(o++, val);
251         ee->ee_tx_end2xlna_enable[mode] = (val >> 8) & 0xff;
252         ee->ee_thr_62[mode]             = val & 0xff;
253
254         if (ah->ah_ee_version <= AR5K_EEPROM_VERSION_3_2)
255                 ee->ee_thr_62[mode] = mode == AR5K_EEPROM_MODE_11A ? 15 : 28;
256
257         AR5K_EEPROM_READ(o++, val);
258         ee->ee_tx_end2xpa_disable[mode] = (val >> 8) & 0xff;
259         ee->ee_tx_frm2xpa_enable[mode]  = val & 0xff;
260
261         AR5K_EEPROM_READ(o++, val);
262         ee->ee_pga_desired_size[mode]   = (val >> 8) & 0xff;
263
264         if ((val & 0xff) & 0x80)
265                 ee->ee_noise_floor_thr[mode] = -((((val & 0xff) ^ 0xff)) + 1);
266         else
267                 ee->ee_noise_floor_thr[mode] = val & 0xff;
268
269         if (ah->ah_ee_version <= AR5K_EEPROM_VERSION_3_2)
270                 ee->ee_noise_floor_thr[mode] =
271                     mode == AR5K_EEPROM_MODE_11A ? -54 : -1;
272
273         AR5K_EEPROM_READ(o++, val);
274         ee->ee_xlna_gain[mode]          = (val >> 5) & 0xff;
275         ee->ee_x_gain[mode]             = (val >> 1) & 0xf;
276         ee->ee_xpd[mode]                = val & 0x1;
277
278         if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0)
279                 ee->ee_fixed_bias[mode] = (val >> 13) & 0x1;
280
281         if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_3_3) {
282                 AR5K_EEPROM_READ(o++, val);
283                 ee->ee_false_detect[mode] = (val >> 6) & 0x7f;
284
285                 if (mode == AR5K_EEPROM_MODE_11A)
286                         ee->ee_xr_power[mode] = val & 0x3f;
287                 else {
288                         ee->ee_ob[mode][0] = val & 0x7;
289                         ee->ee_db[mode][0] = (val >> 3) & 0x7;
290                 }
291         }
292
293         if (ah->ah_ee_version < AR5K_EEPROM_VERSION_3_4) {
294                 ee->ee_i_gain[mode] = AR5K_EEPROM_I_GAIN;
295                 ee->ee_cck_ofdm_power_delta = AR5K_EEPROM_CCK_OFDM_DELTA;
296         } else {
297                 ee->ee_i_gain[mode] = (val >> 13) & 0x7;
298
299                 AR5K_EEPROM_READ(o++, val);
300                 ee->ee_i_gain[mode] |= (val << 3) & 0x38;
301
302                 if (mode == AR5K_EEPROM_MODE_11G) {
303                         ee->ee_cck_ofdm_power_delta = (val >> 3) & 0xff;
304                         if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_6)
305                                 ee->ee_scaled_cck_delta = (val >> 11) & 0x1f;
306                 }
307         }
308
309         if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0 &&
310                         mode == AR5K_EEPROM_MODE_11A) {
311                 ee->ee_i_cal[mode] = (val >> 8) & 0x3f;
312                 ee->ee_q_cal[mode] = (val >> 3) & 0x1f;
313         }
314
315         if (ah->ah_ee_version < AR5K_EEPROM_VERSION_4_0)
316                 goto done;
317
318         switch(mode) {
319         case AR5K_EEPROM_MODE_11A:
320                 if (ah->ah_ee_version < AR5K_EEPROM_VERSION_4_1)
321                         break;
322
323                 AR5K_EEPROM_READ(o++, val);
324                 ee->ee_margin_tx_rx[mode] = val & 0x3f;
325                 break;
326         case AR5K_EEPROM_MODE_11B:
327                 AR5K_EEPROM_READ(o++, val);
328
329                 ee->ee_pwr_cal_b[0].freq =
330                         ath5k_eeprom_bin2freq(ee, val & 0xff, mode);
331                 if (ee->ee_pwr_cal_b[0].freq != AR5K_EEPROM_CHANNEL_DIS)
332                         ee->ee_n_piers[mode]++;
333
334                 ee->ee_pwr_cal_b[1].freq =
335                         ath5k_eeprom_bin2freq(ee, (val >> 8) & 0xff, mode);
336                 if (ee->ee_pwr_cal_b[1].freq != AR5K_EEPROM_CHANNEL_DIS)
337                         ee->ee_n_piers[mode]++;
338
339                 AR5K_EEPROM_READ(o++, val);
340                 ee->ee_pwr_cal_b[2].freq =
341                         ath5k_eeprom_bin2freq(ee, val & 0xff, mode);
342                 if (ee->ee_pwr_cal_b[2].freq != AR5K_EEPROM_CHANNEL_DIS)
343                         ee->ee_n_piers[mode]++;
344
345                 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1)
346                         ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f;
347                 break;
348         case AR5K_EEPROM_MODE_11G:
349                 AR5K_EEPROM_READ(o++, val);
350
351                 ee->ee_pwr_cal_g[0].freq =
352                         ath5k_eeprom_bin2freq(ee, val & 0xff, mode);
353                 if (ee->ee_pwr_cal_g[0].freq != AR5K_EEPROM_CHANNEL_DIS)
354                         ee->ee_n_piers[mode]++;
355
356                 ee->ee_pwr_cal_g[1].freq =
357                         ath5k_eeprom_bin2freq(ee, (val >> 8) & 0xff, mode);
358                 if (ee->ee_pwr_cal_g[1].freq != AR5K_EEPROM_CHANNEL_DIS)
359                         ee->ee_n_piers[mode]++;
360
361                 AR5K_EEPROM_READ(o++, val);
362                 ee->ee_turbo_max_power[mode] = val & 0x7f;
363                 ee->ee_xr_power[mode] = (val >> 7) & 0x3f;
364
365                 AR5K_EEPROM_READ(o++, val);
366                 ee->ee_pwr_cal_g[2].freq =
367                         ath5k_eeprom_bin2freq(ee, val & 0xff, mode);
368                 if (ee->ee_pwr_cal_g[2].freq != AR5K_EEPROM_CHANNEL_DIS)
369                         ee->ee_n_piers[mode]++;
370
371                 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1)
372                         ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f;
373
374                 AR5K_EEPROM_READ(o++, val);
375                 ee->ee_i_cal[mode] = (val >> 8) & 0x3f;
376                 ee->ee_q_cal[mode] = (val >> 3) & 0x1f;
377
378                 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_2) {
379                         AR5K_EEPROM_READ(o++, val);
380                         ee->ee_cck_ofdm_gain_delta = val & 0xff;
381                 }
382                 break;
383         }
384
385 done:
386         /* return new offset */
387         *offset = o;
388
389         return 0;
390 }
391
392 /*
393  * Read turbo mode information on newer EEPROM versions
394  */
395 static int
396 ath5k_eeprom_read_turbo_modes(struct ath5k_hw *ah,
397                               u32 *offset, unsigned int mode)
398 {
399         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
400         u32 o = *offset;
401         u16 val;
402         int ret;
403
404         if (ee->ee_version < AR5K_EEPROM_VERSION_5_0)
405                 return 0;
406
407         switch (mode){
408         case AR5K_EEPROM_MODE_11A:
409                 ee->ee_switch_settling_turbo[mode] = (val >> 6) & 0x7f;
410
411                 ee->ee_atn_tx_rx_turbo[mode] = (val >> 13) & 0x7;
412                 AR5K_EEPROM_READ(o++, val);
413                 ee->ee_atn_tx_rx_turbo[mode] |= (val & 0x7) << 3;
414                 ee->ee_margin_tx_rx_turbo[mode] = (val >> 3) & 0x3f;
415
416                 ee->ee_adc_desired_size_turbo[mode] = (val >> 9) & 0x7f;
417                 AR5K_EEPROM_READ(o++, val);
418                 ee->ee_adc_desired_size_turbo[mode] |= (val & 0x1) << 7;
419                 ee->ee_pga_desired_size_turbo[mode] = (val >> 1) & 0xff;
420
421                 if (AR5K_EEPROM_EEMAP(ee->ee_misc0) >=2)
422                         ee->ee_pd_gain_overlap = (val >> 9) & 0xf;
423                 break;
424         case AR5K_EEPROM_MODE_11G:
425                 ee->ee_switch_settling_turbo[mode] = (val >> 8) & 0x7f;
426
427                 ee->ee_atn_tx_rx_turbo[mode] = (val >> 15) & 0x7;
428                 AR5K_EEPROM_READ(o++, val);
429                 ee->ee_atn_tx_rx_turbo[mode] |= (val & 0x1f) << 1;
430                 ee->ee_margin_tx_rx_turbo[mode] = (val >> 5) & 0x3f;
431
432                 ee->ee_adc_desired_size_turbo[mode] = (val >> 11) & 0x7f;
433                 AR5K_EEPROM_READ(o++, val);
434                 ee->ee_adc_desired_size_turbo[mode] |= (val & 0x7) << 5;
435                 ee->ee_pga_desired_size_turbo[mode] = (val >> 3) & 0xff;
436                 break;
437         }
438
439         /* return new offset */
440         *offset = o;
441
442         return 0;
443 }
444
445
446 static int
447 ath5k_eeprom_init_modes(struct ath5k_hw *ah)
448 {
449         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
450         u32 mode_offset[3];
451         unsigned int mode;
452         u32 offset;
453         int ret;
454
455         /*
456          * Get values for all modes
457          */
458         mode_offset[AR5K_EEPROM_MODE_11A] = AR5K_EEPROM_MODES_11A(ah->ah_ee_version);
459         mode_offset[AR5K_EEPROM_MODE_11B] = AR5K_EEPROM_MODES_11B(ah->ah_ee_version);
460         mode_offset[AR5K_EEPROM_MODE_11G] = AR5K_EEPROM_MODES_11G(ah->ah_ee_version);
461
462         ee->ee_turbo_max_power[AR5K_EEPROM_MODE_11A] =
463                 AR5K_EEPROM_HDR_T_5GHZ_DBM(ee->ee_header);
464
465         for (mode = AR5K_EEPROM_MODE_11A; mode <= AR5K_EEPROM_MODE_11G; mode++) {
466                 offset = mode_offset[mode];
467
468                 ret = ath5k_eeprom_read_ants(ah, &offset, mode);
469                 if (ret)
470                         return ret;
471
472                 ret = ath5k_eeprom_read_modes(ah, &offset, mode);
473                 if (ret)
474                         return ret;
475
476                 ret = ath5k_eeprom_read_turbo_modes(ah, &offset, mode);
477                 if (ret)
478                         return ret;
479         }
480
481         /* override for older eeprom versions for better performance */
482         if (ah->ah_ee_version <= AR5K_EEPROM_VERSION_3_2) {
483                 ee->ee_thr_62[AR5K_EEPROM_MODE_11A] = 15;
484                 ee->ee_thr_62[AR5K_EEPROM_MODE_11B] = 28;
485                 ee->ee_thr_62[AR5K_EEPROM_MODE_11G] = 28;
486         }
487
488         return 0;
489 }
490
491 static inline void
492 ath5k_get_pcdac_intercepts(struct ath5k_hw *ah, u8 min, u8 max, u8 *vp)
493 {
494         const static u16 intercepts3[] =
495                 { 0, 5, 10, 20, 30, 50, 70, 85, 90, 95, 100 };
496         const static u16 intercepts3_2[] =
497                 { 0, 10, 20, 30, 40, 50, 60, 70, 80, 90, 100 };
498         const u16 *ip;
499         int i;
500
501         if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_3_2)
502                 ip = intercepts3_2;
503         else
504                 ip = intercepts3;
505
506         for (i = 0; i < ARRAY_SIZE(intercepts3); i++)
507                 *vp++ = (ip[i] * max + (100 - ip[i]) * min) / 100;
508 }
509
510 static inline int
511 ath5k_eeprom_read_freq_list(struct ath5k_hw *ah, int *offset, int max,
512                             struct ath5k_chan_pcal_info *pc, u8 *count)
513 {
514         int o = *offset;
515         int i = 0;
516         u8 f1, f2;
517         int ret;
518         u16 val;
519
520         while(i < max) {
521                 AR5K_EEPROM_READ(o++, val);
522
523                 f1 = (val >> 8) & 0xff;
524                 f2 = val & 0xff;
525
526                 if (f1)
527                         pc[i++].freq = f1;
528
529                 if (f2)
530                         pc[i++].freq = f2;
531
532                 if (!f1 || !f2)
533                         break;
534         }
535         *offset = o;
536         *count = i;
537
538         return 0;
539 }
540
541 static int
542 ath5k_eeprom_init_11a_pcal_freq(struct ath5k_hw *ah, int offset)
543 {
544         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
545         struct ath5k_chan_pcal_info *pcal = ee->ee_pwr_cal_a;
546         int i, ret;
547         u16 val;
548         u8 mask;
549
550         if (ee->ee_version >= AR5K_EEPROM_VERSION_3_3) {
551                 ath5k_eeprom_read_freq_list(ah, &offset,
552                         AR5K_EEPROM_N_5GHZ_CHAN, pcal,
553                         &ee->ee_n_piers[AR5K_EEPROM_MODE_11A]);
554         } else {
555                 mask = AR5K_EEPROM_FREQ_M(ah->ah_ee_version);
556
557                 AR5K_EEPROM_READ(offset++, val);
558                 pcal[0].freq  = (val >> 9) & mask;
559                 pcal[1].freq  = (val >> 2) & mask;
560                 pcal[2].freq  = (val << 5) & mask;
561
562                 AR5K_EEPROM_READ(offset++, val);
563                 pcal[2].freq |= (val >> 11) & 0x1f;
564                 pcal[3].freq  = (val >> 4) & mask;
565                 pcal[4].freq  = (val << 3) & mask;
566
567                 AR5K_EEPROM_READ(offset++, val);
568                 pcal[4].freq |= (val >> 13) & 0x7;
569                 pcal[5].freq  = (val >> 6) & mask;
570                 pcal[6].freq  = (val << 1) & mask;
571
572                 AR5K_EEPROM_READ(offset++, val);
573                 pcal[6].freq |= (val >> 15) & 0x1;
574                 pcal[7].freq  = (val >> 8) & mask;
575                 pcal[8].freq  = (val >> 1) & mask;
576                 pcal[9].freq  = (val << 6) & mask;
577
578                 AR5K_EEPROM_READ(offset++, val);
579                 pcal[9].freq |= (val >> 10) & 0x3f;
580                 ee->ee_n_piers[AR5K_EEPROM_MODE_11A] = 10;
581         }
582
583         for(i = 0; i < AR5K_EEPROM_N_5GHZ_CHAN; i += 1) {
584                 pcal[i].freq = ath5k_eeprom_bin2freq(ee,
585                                 pcal[i].freq, AR5K_EEPROM_MODE_11A);
586         }
587
588         return 0;
589 }
590
591 static inline int
592 ath5k_eeprom_init_11bg_2413(struct ath5k_hw *ah, unsigned int mode, int offset)
593 {
594         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
595         struct ath5k_chan_pcal_info *pcal;
596         int i;
597
598         switch(mode) {
599         case AR5K_EEPROM_MODE_11B:
600                 pcal = ee->ee_pwr_cal_b;
601                 break;
602         case AR5K_EEPROM_MODE_11G:
603                 pcal = ee->ee_pwr_cal_g;
604                 break;
605         default:
606                 return -EINVAL;
607         }
608
609         ath5k_eeprom_read_freq_list(ah, &offset,
610                 AR5K_EEPROM_N_2GHZ_CHAN_2413, pcal,
611                 &ee->ee_n_piers[mode]);
612         for(i = 0; i < AR5K_EEPROM_N_2GHZ_CHAN_2413; i += 1) {
613                 pcal[i].freq = ath5k_eeprom_bin2freq(ee,
614                                 pcal[i].freq, mode);
615         }
616
617         return 0;
618 }
619
620
621 static int
622 ath5k_eeprom_read_pcal_info_5111(struct ath5k_hw *ah, int mode)
623 {
624         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
625         struct ath5k_chan_pcal_info *pcal;
626         int offset, ret;
627         int i, j;
628         u16 val;
629
630         offset = AR5K_EEPROM_GROUPS_START(ee->ee_version);
631         switch(mode) {
632         case AR5K_EEPROM_MODE_11A:
633                 if (!AR5K_EEPROM_HDR_11A(ee->ee_header))
634                         return 0;
635
636                 ret = ath5k_eeprom_init_11a_pcal_freq(ah,
637                         offset + AR5K_EEPROM_GROUP1_OFFSET);
638                 if (ret < 0)
639                         return ret;
640
641                 offset += AR5K_EEPROM_GROUP2_OFFSET;
642                 pcal = ee->ee_pwr_cal_a;
643                 break;
644         case AR5K_EEPROM_MODE_11B:
645                 if (!AR5K_EEPROM_HDR_11B(ee->ee_header) &&
646                     !AR5K_EEPROM_HDR_11G(ee->ee_header))
647                         return 0;
648
649                 pcal = ee->ee_pwr_cal_b;
650                 offset += AR5K_EEPROM_GROUP3_OFFSET;
651
652                 /* fixed piers */
653                 pcal[0].freq = 2412;
654                 pcal[1].freq = 2447;
655                 pcal[2].freq = 2484;
656                 ee->ee_n_piers[mode] = 3;
657                 break;
658         case AR5K_EEPROM_MODE_11G:
659                 if (!AR5K_EEPROM_HDR_11G(ee->ee_header))
660                         return 0;
661
662                 pcal = ee->ee_pwr_cal_g;
663                 offset += AR5K_EEPROM_GROUP4_OFFSET;
664
665                 /* fixed piers */
666                 pcal[0].freq = 2312;
667                 pcal[1].freq = 2412;
668                 pcal[2].freq = 2484;
669                 ee->ee_n_piers[mode] = 3;
670                 break;
671         default:
672                 return -EINVAL;
673         }
674
675         for (i = 0; i < ee->ee_n_piers[mode]; i++) {
676                 struct ath5k_chan_pcal_info_rf5111 *cdata =
677                         &pcal[i].rf5111_info;
678
679                 AR5K_EEPROM_READ(offset++, val);
680                 cdata->pcdac_max = ((val >> 10) & AR5K_EEPROM_PCDAC_M);
681                 cdata->pcdac_min = ((val >> 4) & AR5K_EEPROM_PCDAC_M);
682                 cdata->pwr[0] = ((val << 2) & AR5K_EEPROM_POWER_M);
683
684                 AR5K_EEPROM_READ(offset++, val);
685                 cdata->pwr[0] |= ((val >> 14) & 0x3);
686                 cdata->pwr[1] = ((val >> 8) & AR5K_EEPROM_POWER_M);
687                 cdata->pwr[2] = ((val >> 2) & AR5K_EEPROM_POWER_M);
688                 cdata->pwr[3] = ((val << 4) & AR5K_EEPROM_POWER_M);
689
690                 AR5K_EEPROM_READ(offset++, val);
691                 cdata->pwr[3] |= ((val >> 12) & 0xf);
692                 cdata->pwr[4] = ((val >> 6) & AR5K_EEPROM_POWER_M);
693                 cdata->pwr[5] = (val  & AR5K_EEPROM_POWER_M);
694
695                 AR5K_EEPROM_READ(offset++, val);
696                 cdata->pwr[6] = ((val >> 10) & AR5K_EEPROM_POWER_M);
697                 cdata->pwr[7] = ((val >> 4) & AR5K_EEPROM_POWER_M);
698                 cdata->pwr[8] = ((val << 2) & AR5K_EEPROM_POWER_M);
699
700                 AR5K_EEPROM_READ(offset++, val);
701                 cdata->pwr[8] |= ((val >> 14) & 0x3);
702                 cdata->pwr[9] = ((val >> 8) & AR5K_EEPROM_POWER_M);
703                 cdata->pwr[10] = ((val >> 2) & AR5K_EEPROM_POWER_M);
704
705                 ath5k_get_pcdac_intercepts(ah, cdata->pcdac_min,
706                         cdata->pcdac_max, cdata->pcdac);
707
708                 for (j = 0; j < AR5K_EEPROM_N_PCDAC; j++) {
709                         cdata->pwr[j] = (u16)
710                                 (AR5K_EEPROM_POWER_STEP * cdata->pwr[j]);
711                 }
712         }
713
714         return 0;
715 }
716
717 static int
718 ath5k_eeprom_read_pcal_info_5112(struct ath5k_hw *ah, int mode)
719 {
720         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
721         struct ath5k_chan_pcal_info_rf5112 *chan_pcal_info;
722         struct ath5k_chan_pcal_info *gen_chan_info;
723         u32 offset;
724         unsigned int i, c;
725         u16 val;
726         int ret;
727
728         switch (mode) {
729         case AR5K_EEPROM_MODE_11A:
730                 /*
731                  * Read 5GHz EEPROM channels
732                  */
733                 offset = AR5K_EEPROM_GROUPS_START(ee->ee_version);
734                 ath5k_eeprom_init_11a_pcal_freq(ah, offset);
735
736                 offset += AR5K_EEPROM_GROUP2_OFFSET;
737                 gen_chan_info = ee->ee_pwr_cal_a;
738                 break;
739         case AR5K_EEPROM_MODE_11B:
740                 offset = AR5K_EEPROM_GROUPS_START(ee->ee_version);
741                 if (AR5K_EEPROM_HDR_11A(ee->ee_header))
742                         offset += AR5K_EEPROM_GROUP3_OFFSET;
743
744                 /* NB: frequency piers parsed during mode init */
745                 gen_chan_info = ee->ee_pwr_cal_b;
746                 break;
747         case AR5K_EEPROM_MODE_11G:
748                 offset = AR5K_EEPROM_GROUPS_START(ee->ee_version);
749                 if (AR5K_EEPROM_HDR_11A(ee->ee_header))
750                         offset += AR5K_EEPROM_GROUP4_OFFSET;
751                 else if (AR5K_EEPROM_HDR_11B(ee->ee_header))
752                         offset += AR5K_EEPROM_GROUP2_OFFSET;
753
754                 /* NB: frequency piers parsed during mode init */
755                 gen_chan_info = ee->ee_pwr_cal_g;
756                 break;
757         default:
758                 return -EINVAL;
759         }
760
761         for (i = 0; i < ee->ee_n_piers[mode]; i++) {
762                 chan_pcal_info = &gen_chan_info[i].rf5112_info;
763
764                 /* Power values in dBm * 4
765                  * for the lower xpd gain curve
766                  * (0 dBm -> higher output power) */
767                 for (c = 0; c < AR5K_EEPROM_N_XPD0_POINTS; c++) {
768                         AR5K_EEPROM_READ(offset++, val);
769                         chan_pcal_info->pwr_x0[c] = (val & 0xff);
770                         chan_pcal_info->pwr_x0[++c] = ((val >> 8) & 0xff);
771                 }
772
773                 /* PCDAC steps
774                  * corresponding to the above power
775                  * measurements */
776                 AR5K_EEPROM_READ(offset++, val);
777                 chan_pcal_info->pcdac_x0[1] = (val & 0x1f);
778                 chan_pcal_info->pcdac_x0[2] = ((val >> 5) & 0x1f);
779                 chan_pcal_info->pcdac_x0[3] = ((val >> 10) & 0x1f);
780
781                 /* Power values in dBm * 4
782                  * for the higher xpd gain curve
783                  * (18 dBm -> lower output power) */
784                 AR5K_EEPROM_READ(offset++, val);
785                 chan_pcal_info->pwr_x3[0] = (val & 0xff);
786                 chan_pcal_info->pwr_x3[1] = ((val >> 8) & 0xff);
787
788                 AR5K_EEPROM_READ(offset++, val);
789                 chan_pcal_info->pwr_x3[2] = (val & 0xff);
790
791                 /* PCDAC steps
792                  * corresponding to the above power
793                  * measurements (static) */
794                 chan_pcal_info->pcdac_x3[0] = 20;
795                 chan_pcal_info->pcdac_x3[1] = 35;
796                 chan_pcal_info->pcdac_x3[2] = 63;
797
798                 if (ee->ee_version >= AR5K_EEPROM_VERSION_4_3) {
799                         chan_pcal_info->pcdac_x0[0] = ((val >> 8) & 0xff);
800
801                         /* Last xpd0 power level is also channel maximum */
802                         gen_chan_info[i].max_pwr = chan_pcal_info->pwr_x0[3];
803                 } else {
804                         chan_pcal_info->pcdac_x0[0] = 1;
805                         gen_chan_info[i].max_pwr = ((val >> 8) & 0xff);
806                 }
807
808                 /* Recreate pcdac_x0 table for this channel using pcdac steps */
809                 chan_pcal_info->pcdac_x0[1] += chan_pcal_info->pcdac_x0[0];
810                 chan_pcal_info->pcdac_x0[2] += chan_pcal_info->pcdac_x0[1];
811                 chan_pcal_info->pcdac_x0[3] += chan_pcal_info->pcdac_x0[2];
812         }
813
814         return 0;
815 }
816
817 static inline unsigned int
818 ath5k_pdgains_size_2413(struct ath5k_eeprom_info *ee, unsigned int mode)
819 {
820         static const unsigned int pdgains_size[] = { 4, 6, 9, 12 };
821         unsigned int sz;
822
823         sz = pdgains_size[ee->ee_pd_gains[mode] - 1];
824         sz *= ee->ee_n_piers[mode];
825
826         return sz;
827 }
828
829 static unsigned int
830 ath5k_cal_data_offset_2413(struct ath5k_eeprom_info *ee, int mode)
831 {
832         u32 offset = AR5K_EEPROM_CAL_DATA_START(ee->ee_misc4);
833
834         switch(mode) {
835         case AR5K_EEPROM_MODE_11G:
836                 if (AR5K_EEPROM_HDR_11B(ee->ee_header))
837                         offset += ath5k_pdgains_size_2413(ee, AR5K_EEPROM_MODE_11B) + 2;
838                 /* fall through */
839         case AR5K_EEPROM_MODE_11B:
840                 if (AR5K_EEPROM_HDR_11A(ee->ee_header))
841                         offset += ath5k_pdgains_size_2413(ee, AR5K_EEPROM_MODE_11A) + 5;
842                 /* fall through */
843         case AR5K_EEPROM_MODE_11A:
844                 break;
845         default:
846                 break;
847         }
848
849         return offset;
850 }
851
852 static int
853 ath5k_eeprom_read_pcal_info_2413(struct ath5k_hw *ah, int mode)
854 {
855         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
856         struct ath5k_chan_pcal_info_rf2413 *chan_pcal_info;
857         struct ath5k_chan_pcal_info *gen_chan_info;
858         unsigned int i, c;
859         u32 offset;
860         int ret;
861         u16 val;
862         u8 pd_gains = 0;
863
864         if (ee->ee_x_gain[mode] & 0x1) pd_gains++;
865         if ((ee->ee_x_gain[mode] >> 1) & 0x1) pd_gains++;
866         if ((ee->ee_x_gain[mode] >> 2) & 0x1) pd_gains++;
867         if ((ee->ee_x_gain[mode] >> 3) & 0x1) pd_gains++;
868         ee->ee_pd_gains[mode] = pd_gains;
869
870         offset = ath5k_cal_data_offset_2413(ee, mode);
871         switch (mode) {
872         case AR5K_EEPROM_MODE_11A:
873                 if (!AR5K_EEPROM_HDR_11A(ee->ee_header))
874                         return 0;
875
876                 ath5k_eeprom_init_11a_pcal_freq(ah, offset);
877                 offset += AR5K_EEPROM_N_5GHZ_CHAN / 2;
878                 gen_chan_info = ee->ee_pwr_cal_a;
879                 break;
880         case AR5K_EEPROM_MODE_11B:
881                 if (!AR5K_EEPROM_HDR_11B(ee->ee_header))
882                         return 0;
883
884                 ath5k_eeprom_init_11bg_2413(ah, mode, offset);
885                 offset += AR5K_EEPROM_N_2GHZ_CHAN_2413 / 2;
886                 gen_chan_info = ee->ee_pwr_cal_b;
887                 break;
888         case AR5K_EEPROM_MODE_11G:
889                 if (!AR5K_EEPROM_HDR_11G(ee->ee_header))
890                         return 0;
891
892                 ath5k_eeprom_init_11bg_2413(ah, mode, offset);
893                 offset += AR5K_EEPROM_N_2GHZ_CHAN_2413 / 2;
894                 gen_chan_info = ee->ee_pwr_cal_g;
895                 break;
896         default:
897                 return -EINVAL;
898         }
899
900         if (pd_gains == 0)
901                 return 0;
902
903         for (i = 0; i < ee->ee_n_piers[mode]; i++) {
904                 chan_pcal_info = &gen_chan_info[i].rf2413_info;
905
906                 /*
907                  * Read pwr_i, pddac_i and the first
908                  * 2 pd points (pwr, pddac)
909                  */
910                 AR5K_EEPROM_READ(offset++, val);
911                 chan_pcal_info->pwr_i[0] = val & 0x1f;
912                 chan_pcal_info->pddac_i[0] = (val >> 5) & 0x7f;
913                 chan_pcal_info->pwr[0][0] =
914                                         (val >> 12) & 0xf;
915
916                 AR5K_EEPROM_READ(offset++, val);
917                 chan_pcal_info->pddac[0][0] = val & 0x3f;
918                 chan_pcal_info->pwr[0][1] = (val >> 6) & 0xf;
919                 chan_pcal_info->pddac[0][1] =
920                                         (val >> 10) & 0x3f;
921
922                 AR5K_EEPROM_READ(offset++, val);
923                 chan_pcal_info->pwr[0][2] = val & 0xf;
924                 chan_pcal_info->pddac[0][2] =
925                                         (val >> 4) & 0x3f;
926
927                 chan_pcal_info->pwr[0][3] = 0;
928                 chan_pcal_info->pddac[0][3] = 0;
929
930                 if (pd_gains > 1) {
931                         /*
932                          * Pd gain 0 is not the last pd gain
933                          * so it only has 2 pd points.
934                          * Continue wih pd gain 1.
935                          */
936                         chan_pcal_info->pwr_i[1] = (val >> 10) & 0x1f;
937
938                         chan_pcal_info->pddac_i[1] = (val >> 15) & 0x1;
939                         AR5K_EEPROM_READ(offset++, val);
940                         chan_pcal_info->pddac_i[1] |= (val & 0x3F) << 1;
941
942                         chan_pcal_info->pwr[1][0] = (val >> 6) & 0xf;
943                         chan_pcal_info->pddac[1][0] =
944                                                 (val >> 10) & 0x3f;
945
946                         AR5K_EEPROM_READ(offset++, val);
947                         chan_pcal_info->pwr[1][1] = val & 0xf;
948                         chan_pcal_info->pddac[1][1] =
949                                                 (val >> 4) & 0x3f;
950                         chan_pcal_info->pwr[1][2] =
951                                                 (val >> 10) & 0xf;
952
953                         chan_pcal_info->pddac[1][2] =
954                                                 (val >> 14) & 0x3;
955                         AR5K_EEPROM_READ(offset++, val);
956                         chan_pcal_info->pddac[1][2] |=
957                                                 (val & 0xF) << 2;
958
959                         chan_pcal_info->pwr[1][3] = 0;
960                         chan_pcal_info->pddac[1][3] = 0;
961                 } else if (pd_gains == 1) {
962                         /*
963                          * Pd gain 0 is the last one so
964                          * read the extra point.
965                          */
966                         chan_pcal_info->pwr[0][3] =
967                                                 (val >> 10) & 0xf;
968
969                         chan_pcal_info->pddac[0][3] =
970                                                 (val >> 14) & 0x3;
971                         AR5K_EEPROM_READ(offset++, val);
972                         chan_pcal_info->pddac[0][3] |=
973                                                 (val & 0xF) << 2;
974                 }
975
976                 /*
977                  * Proceed with the other pd_gains
978                  * as above.
979                  */
980                 if (pd_gains > 2) {
981                         chan_pcal_info->pwr_i[2] = (val >> 4) & 0x1f;
982                         chan_pcal_info->pddac_i[2] = (val >> 9) & 0x7f;
983
984                         AR5K_EEPROM_READ(offset++, val);
985                         chan_pcal_info->pwr[2][0] =
986                                                 (val >> 0) & 0xf;
987                         chan_pcal_info->pddac[2][0] =
988                                                 (val >> 4) & 0x3f;
989                         chan_pcal_info->pwr[2][1] =
990                                                 (val >> 10) & 0xf;
991
992                         chan_pcal_info->pddac[2][1] =
993                                                 (val >> 14) & 0x3;
994                         AR5K_EEPROM_READ(offset++, val);
995                         chan_pcal_info->pddac[2][1] |=
996                                                 (val & 0xF) << 2;
997
998                         chan_pcal_info->pwr[2][2] =
999                                                 (val >> 4) & 0xf;
1000                         chan_pcal_info->pddac[2][2] =
1001                                                 (val >> 8) & 0x3f;
1002
1003                         chan_pcal_info->pwr[2][3] = 0;
1004                         chan_pcal_info->pddac[2][3] = 0;
1005                 } else if (pd_gains == 2) {
1006                         chan_pcal_info->pwr[1][3] =
1007                                                 (val >> 4) & 0xf;
1008                         chan_pcal_info->pddac[1][3] =
1009                                                 (val >> 8) & 0x3f;
1010                 }
1011
1012                 if (pd_gains > 3) {
1013                         chan_pcal_info->pwr_i[3] = (val >> 14) & 0x3;
1014                         AR5K_EEPROM_READ(offset++, val);
1015                         chan_pcal_info->pwr_i[3] |= ((val >> 0) & 0x7) << 2;
1016
1017                         chan_pcal_info->pddac_i[3] = (val >> 3) & 0x7f;
1018                         chan_pcal_info->pwr[3][0] =
1019                                                 (val >> 10) & 0xf;
1020                         chan_pcal_info->pddac[3][0] =
1021                                                 (val >> 14) & 0x3;
1022
1023                         AR5K_EEPROM_READ(offset++, val);
1024                         chan_pcal_info->pddac[3][0] |=
1025                                                 (val & 0xF) << 2;
1026                         chan_pcal_info->pwr[3][1] =
1027                                                 (val >> 4) & 0xf;
1028                         chan_pcal_info->pddac[3][1] =
1029                                                 (val >> 8) & 0x3f;
1030
1031                         chan_pcal_info->pwr[3][2] =
1032                                                 (val >> 14) & 0x3;
1033                         AR5K_EEPROM_READ(offset++, val);
1034                         chan_pcal_info->pwr[3][2] |=
1035                                                 ((val >> 0) & 0x3) << 2;
1036
1037                         chan_pcal_info->pddac[3][2] =
1038                                                 (val >> 2) & 0x3f;
1039                         chan_pcal_info->pwr[3][3] =
1040                                                 (val >> 8) & 0xf;
1041
1042                         chan_pcal_info->pddac[3][3] =
1043                                                 (val >> 12) & 0xF;
1044                         AR5K_EEPROM_READ(offset++, val);
1045                         chan_pcal_info->pddac[3][3] |=
1046                                                 ((val >> 0) & 0x3) << 4;
1047                 } else if (pd_gains == 3) {
1048                         chan_pcal_info->pwr[2][3] =
1049                                                 (val >> 14) & 0x3;
1050                         AR5K_EEPROM_READ(offset++, val);
1051                         chan_pcal_info->pwr[2][3] |=
1052                                                 ((val >> 0) & 0x3) << 2;
1053
1054                         chan_pcal_info->pddac[2][3] =
1055                                                 (val >> 2) & 0x3f;
1056                 }
1057
1058                 for (c = 0; c < pd_gains; c++) {
1059                         /* Recreate pwr table for this channel using pwr steps */
1060                         chan_pcal_info->pwr[c][0] += chan_pcal_info->pwr_i[c] * 2;
1061                         chan_pcal_info->pwr[c][1] += chan_pcal_info->pwr[c][0];
1062                         chan_pcal_info->pwr[c][2] += chan_pcal_info->pwr[c][1];
1063                         chan_pcal_info->pwr[c][3] += chan_pcal_info->pwr[c][2];
1064                         if (chan_pcal_info->pwr[c][3] == chan_pcal_info->pwr[c][2])
1065                                 chan_pcal_info->pwr[c][3] = 0;
1066
1067                         /* Recreate pddac table for this channel using pddac steps */
1068                         chan_pcal_info->pddac[c][0] += chan_pcal_info->pddac_i[c];
1069                         chan_pcal_info->pddac[c][1] += chan_pcal_info->pddac[c][0];
1070                         chan_pcal_info->pddac[c][2] += chan_pcal_info->pddac[c][1];
1071                         chan_pcal_info->pddac[c][3] += chan_pcal_info->pddac[c][2];
1072                         if (chan_pcal_info->pddac[c][3] == chan_pcal_info->pddac[c][2])
1073                                 chan_pcal_info->pddac[c][3] = 0;
1074                 }
1075         }
1076
1077         return 0;
1078 }
1079
1080 /*
1081  * Read per rate target power (this is the maximum tx power
1082  * supported by the card). This info is used when setting
1083  * tx power, no matter the channel.
1084  *
1085  * This also works for v5 EEPROMs.
1086  */
1087 static int ath5k_eeprom_read_target_rate_pwr_info(struct ath5k_hw *ah, unsigned int mode)
1088 {
1089         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1090         struct ath5k_rate_pcal_info *rate_pcal_info;
1091         u16 *rate_target_pwr_num;
1092         u32 offset;
1093         u16 val;
1094         int ret, i;
1095
1096         offset = AR5K_EEPROM_TARGET_PWRSTART(ee->ee_misc1);
1097         rate_target_pwr_num = &ee->ee_rate_target_pwr_num[mode];
1098         switch (mode) {
1099         case AR5K_EEPROM_MODE_11A:
1100                 offset += AR5K_EEPROM_TARGET_PWR_OFF_11A(ee->ee_version);
1101                 rate_pcal_info = ee->ee_rate_tpwr_a;
1102                 ee->ee_rate_target_pwr_num[mode] = AR5K_EEPROM_N_5GHZ_CHAN;
1103                 break;
1104         case AR5K_EEPROM_MODE_11B:
1105                 offset += AR5K_EEPROM_TARGET_PWR_OFF_11B(ee->ee_version);
1106                 rate_pcal_info = ee->ee_rate_tpwr_b;
1107                 ee->ee_rate_target_pwr_num[mode] = 2; /* 3rd is g mode's 1st */
1108                 break;
1109         case AR5K_EEPROM_MODE_11G:
1110                 offset += AR5K_EEPROM_TARGET_PWR_OFF_11G(ee->ee_version);
1111                 rate_pcal_info = ee->ee_rate_tpwr_g;
1112                 ee->ee_rate_target_pwr_num[mode] = AR5K_EEPROM_N_2GHZ_CHAN;
1113                 break;
1114         default:
1115                 return -EINVAL;
1116         }
1117
1118         /* Different freq mask for older eeproms (<= v3.2) */
1119         if (ee->ee_version <= AR5K_EEPROM_VERSION_3_2) {
1120                 for (i = 0; i < (*rate_target_pwr_num); i++) {
1121                         AR5K_EEPROM_READ(offset++, val);
1122                         rate_pcal_info[i].freq =
1123                             ath5k_eeprom_bin2freq(ee, (val >> 9) & 0x7f, mode);
1124
1125                         rate_pcal_info[i].target_power_6to24 = ((val >> 3) & 0x3f);
1126                         rate_pcal_info[i].target_power_36 = (val << 3) & 0x3f;
1127
1128                         AR5K_EEPROM_READ(offset++, val);
1129
1130                         if (rate_pcal_info[i].freq == AR5K_EEPROM_CHANNEL_DIS ||
1131                             val == 0) {
1132                                 (*rate_target_pwr_num) = i;
1133                                 break;
1134                         }
1135
1136                         rate_pcal_info[i].target_power_36 |= ((val >> 13) & 0x7);
1137                         rate_pcal_info[i].target_power_48 = ((val >> 7) & 0x3f);
1138                         rate_pcal_info[i].target_power_54 = ((val >> 1) & 0x3f);
1139                 }
1140         } else {
1141                 for (i = 0; i < (*rate_target_pwr_num); i++) {
1142                         AR5K_EEPROM_READ(offset++, val);
1143                         rate_pcal_info[i].freq =
1144                             ath5k_eeprom_bin2freq(ee, (val >> 8) & 0xff, mode);
1145
1146                         rate_pcal_info[i].target_power_6to24 = ((val >> 2) & 0x3f);
1147                         rate_pcal_info[i].target_power_36 = (val << 4) & 0x3f;
1148
1149                         AR5K_EEPROM_READ(offset++, val);
1150
1151                         if (rate_pcal_info[i].freq == AR5K_EEPROM_CHANNEL_DIS ||
1152                             val == 0) {
1153                                 (*rate_target_pwr_num) = i;
1154                                 break;
1155                         }
1156
1157                         rate_pcal_info[i].target_power_36 |= (val >> 12) & 0xf;
1158                         rate_pcal_info[i].target_power_48 = ((val >> 6) & 0x3f);
1159                         rate_pcal_info[i].target_power_54 = (val & 0x3f);
1160                 }
1161         }
1162
1163         return 0;
1164 }
1165
1166 static int
1167 ath5k_eeprom_read_pcal_info(struct ath5k_hw *ah)
1168 {
1169         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1170         int (*read_pcal)(struct ath5k_hw *hw, int mode);
1171         int mode;
1172         int err;
1173
1174         if ((ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) &&
1175                         (AR5K_EEPROM_EEMAP(ee->ee_misc0) == 1))
1176                 read_pcal = ath5k_eeprom_read_pcal_info_5112;
1177         else if ((ah->ah_ee_version >= AR5K_EEPROM_VERSION_5_0) &&
1178                         (AR5K_EEPROM_EEMAP(ee->ee_misc0) == 2))
1179                 read_pcal = ath5k_eeprom_read_pcal_info_2413;
1180         else
1181                 read_pcal = ath5k_eeprom_read_pcal_info_5111;
1182
1183         for (mode = AR5K_EEPROM_MODE_11A; mode <= AR5K_EEPROM_MODE_11G; mode++) {
1184                 err = read_pcal(ah, mode);
1185                 if (err)
1186                         return err;
1187
1188                 err = ath5k_eeprom_read_target_rate_pwr_info(ah, mode);
1189                 if (err < 0)
1190                         return err;
1191         }
1192
1193         return 0;
1194 }
1195
1196 /* Read conformance test limits */
1197 static int
1198 ath5k_eeprom_read_ctl_info(struct ath5k_hw *ah)
1199 {
1200         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1201         struct ath5k_edge_power *rep;
1202         unsigned int fmask, pmask;
1203         unsigned int ctl_mode;
1204         int ret, i, j;
1205         u32 offset;
1206         u16 val;
1207
1208         pmask = AR5K_EEPROM_POWER_M;
1209         fmask = AR5K_EEPROM_FREQ_M(ee->ee_version);
1210         offset = AR5K_EEPROM_CTL(ee->ee_version);
1211         ee->ee_ctls = AR5K_EEPROM_N_CTLS(ee->ee_version);
1212         for (i = 0; i < ee->ee_ctls; i += 2) {
1213                 AR5K_EEPROM_READ(offset++, val);
1214                 ee->ee_ctl[i] = (val >> 8) & 0xff;
1215                 ee->ee_ctl[i + 1] = val & 0xff;
1216         }
1217
1218         offset = AR5K_EEPROM_GROUP8_OFFSET;
1219         if (ee->ee_version >= AR5K_EEPROM_VERSION_4_0)
1220                 offset += AR5K_EEPROM_TARGET_PWRSTART(ee->ee_misc1) -
1221                         AR5K_EEPROM_GROUP5_OFFSET;
1222         else
1223                 offset += AR5K_EEPROM_GROUPS_START(ee->ee_version);
1224
1225         rep = ee->ee_ctl_pwr;
1226         for(i = 0; i < ee->ee_ctls; i++) {
1227                 switch(ee->ee_ctl[i] & AR5K_CTL_MODE_M) {
1228                 case AR5K_CTL_11A:
1229                 case AR5K_CTL_TURBO:
1230                         ctl_mode = AR5K_EEPROM_MODE_11A;
1231                         break;
1232                 default:
1233                         ctl_mode = AR5K_EEPROM_MODE_11G;
1234                         break;
1235                 }
1236                 if (ee->ee_ctl[i] == 0) {
1237                         if (ee->ee_version >= AR5K_EEPROM_VERSION_3_3)
1238                                 offset += 8;
1239                         else
1240                                 offset += 7;
1241                         rep += AR5K_EEPROM_N_EDGES;
1242                         continue;
1243                 }
1244                 if (ee->ee_version >= AR5K_EEPROM_VERSION_3_3) {
1245                         for (j = 0; j < AR5K_EEPROM_N_EDGES; j += 2) {
1246                                 AR5K_EEPROM_READ(offset++, val);
1247                                 rep[j].freq = (val >> 8) & fmask;
1248                                 rep[j + 1].freq = val & fmask;
1249                         }
1250                         for (j = 0; j < AR5K_EEPROM_N_EDGES; j += 2) {
1251                                 AR5K_EEPROM_READ(offset++, val);
1252                                 rep[j].edge = (val >> 8) & pmask;
1253                                 rep[j].flag = (val >> 14) & 1;
1254                                 rep[j + 1].edge = val & pmask;
1255                                 rep[j + 1].flag = (val >> 6) & 1;
1256                         }
1257                 } else {
1258                         AR5K_EEPROM_READ(offset++, val);
1259                         rep[0].freq = (val >> 9) & fmask;
1260                         rep[1].freq = (val >> 2) & fmask;
1261                         rep[2].freq = (val << 5) & fmask;
1262
1263                         AR5K_EEPROM_READ(offset++, val);
1264                         rep[2].freq |= (val >> 11) & 0x1f;
1265                         rep[3].freq = (val >> 4) & fmask;
1266                         rep[4].freq = (val << 3) & fmask;
1267
1268                         AR5K_EEPROM_READ(offset++, val);
1269                         rep[4].freq |= (val >> 13) & 0x7;
1270                         rep[5].freq = (val >> 6) & fmask;
1271                         rep[6].freq = (val << 1) & fmask;
1272
1273                         AR5K_EEPROM_READ(offset++, val);
1274                         rep[6].freq |= (val >> 15) & 0x1;
1275                         rep[7].freq = (val >> 8) & fmask;
1276
1277                         rep[0].edge = (val >> 2) & pmask;
1278                         rep[1].edge = (val << 4) & pmask;
1279
1280                         AR5K_EEPROM_READ(offset++, val);
1281                         rep[1].edge |= (val >> 12) & 0xf;
1282                         rep[2].edge = (val >> 6) & pmask;
1283                         rep[3].edge = val & pmask;
1284
1285                         AR5K_EEPROM_READ(offset++, val);
1286                         rep[4].edge = (val >> 10) & pmask;
1287                         rep[5].edge = (val >> 4) & pmask;
1288                         rep[6].edge = (val << 2) & pmask;
1289
1290                         AR5K_EEPROM_READ(offset++, val);
1291                         rep[6].edge |= (val >> 14) & 0x3;
1292                         rep[7].edge = (val >> 8) & pmask;
1293                 }
1294                 for (j = 0; j < AR5K_EEPROM_N_EDGES; j++) {
1295                         rep[j].freq = ath5k_eeprom_bin2freq(ee,
1296                                 rep[j].freq, ctl_mode);
1297                 }
1298                 rep += AR5K_EEPROM_N_EDGES;
1299         }
1300
1301         return 0;
1302 }
1303
1304
1305 /*
1306  * Initialize eeprom power tables
1307  */
1308 int
1309 ath5k_eeprom_init(struct ath5k_hw *ah)
1310 {
1311         int err;
1312
1313         err = ath5k_eeprom_init_header(ah);
1314         if (err < 0)
1315                 return err;
1316
1317         err = ath5k_eeprom_init_modes(ah);
1318         if (err < 0)
1319                 return err;
1320
1321         err = ath5k_eeprom_read_pcal_info(ah);
1322         if (err < 0)
1323                 return err;
1324
1325         err = ath5k_eeprom_read_ctl_info(ah);
1326         if (err < 0)
1327                 return err;
1328
1329         return 0;
1330 }
1331 /*
1332  * Read the MAC address from eeprom
1333  */
1334 int ath5k_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac)
1335 {
1336         u8 mac_d[ETH_ALEN];
1337         u32 total, offset;
1338         u16 data;
1339         int octet, ret;
1340
1341         memset(mac, 0, ETH_ALEN);
1342         memset(mac_d, 0, ETH_ALEN);
1343
1344         ret = ath5k_hw_eeprom_read(ah, 0x20, &data);
1345         if (ret)
1346                 return ret;
1347
1348         for (offset = 0x1f, octet = 0, total = 0; offset >= 0x1d; offset--) {
1349                 ret = ath5k_hw_eeprom_read(ah, offset, &data);
1350                 if (ret)
1351                         return ret;
1352
1353                 total += data;
1354                 mac_d[octet + 1] = data & 0xff;
1355                 mac_d[octet] = data >> 8;
1356                 octet += 2;
1357         }
1358
1359         memcpy(mac, mac_d, ETH_ALEN);
1360
1361         if (!total || total == 3 * 0xffff)
1362                 return -EINVAL;
1363
1364         return 0;
1365 }
1366