[SCSI] Merge up to linux-2.6 head
[linux-2.6] / arch / powerpc / boot / dts / mpc8541cds.dts
1 /*
2  * MPC8541 CDS Device Tree Source
3  *
4  * Copyright 2006 Freescale Semiconductor Inc.
5  *
6  * This program is free software; you can redistribute  it and/or modify it
7  * under  the terms of  the GNU General  Public License as published by the
8  * Free Software Foundation;  either version 2 of the  License, or (at your
9  * option) any later version.
10  */
11
12
13 / {
14         model = "MPC8541CDS";
15         compatible = "MPC8541CDS", "MPC85xxCDS";
16         #address-cells = <1>;
17         #size-cells = <1>;
18
19         cpus {
20                 #address-cells = <1>;
21                 #size-cells = <0>;
22
23                 PowerPC,8541@0 {
24                         device_type = "cpu";
25                         reg = <0>;
26                         d-cache-line-size = <20>;       // 32 bytes
27                         i-cache-line-size = <20>;       // 32 bytes
28                         d-cache-size = <8000>;          // L1, 32K
29                         i-cache-size = <8000>;          // L1, 32K
30                         timebase-frequency = <0>;       //  33 MHz, from uboot
31                         bus-frequency = <0>;    // 166 MHz
32                         clock-frequency = <0>;  // 825 MHz, from uboot
33                         32-bit;
34                 };
35         };
36
37         memory {
38                 device_type = "memory";
39                 reg = <00000000 08000000>;      // 128M at 0x0
40         };
41
42         soc8541@e0000000 {
43                 #address-cells = <1>;
44                 #size-cells = <1>;
45                 #interrupt-cells = <2>;
46                 device_type = "soc";
47                 ranges = <0 e0000000 00100000>;
48                 reg = <e0000000 00100000>;      // CCSRBAR 1M
49                 bus-frequency = <0>;
50
51                 memory-controller@2000 {
52                         compatible = "fsl,8541-memory-controller";
53                         reg = <2000 1000>;
54                         interrupt-parent = <&mpic>;
55                         interrupts = <2 2>;
56                 };
57
58                 l2-cache-controller@20000 {
59                         compatible = "fsl,8541-l2-cache-controller";
60                         reg = <20000 1000>;
61                         cache-line-size = <20>; // 32 bytes
62                         cache-size = <40000>;   // L2, 256K
63                         interrupt-parent = <&mpic>;
64                         interrupts = <0 2>;
65                 };
66
67                 i2c@3000 {
68                         device_type = "i2c";
69                         compatible = "fsl-i2c";
70                         reg = <3000 100>;
71                         interrupts = <1b 2>;
72                         interrupt-parent = <&mpic>;
73                         dfsrr;
74                 };
75
76                 mdio@24520 {
77                         #address-cells = <1>;
78                         #size-cells = <0>;
79                         device_type = "mdio";
80                         compatible = "gianfar";
81                         reg = <24520 20>;
82                         phy0: ethernet-phy@0 {
83                                 interrupt-parent = <&mpic>;
84                                 interrupts = <35 0>;
85                                 reg = <0>;
86                                 device_type = "ethernet-phy";
87                         };
88                         phy1: ethernet-phy@1 {
89                                 interrupt-parent = <&mpic>;
90                                 interrupts = <35 0>;
91                                 reg = <1>;
92                                 device_type = "ethernet-phy";
93                         };
94                 };
95
96                 ethernet@24000 {
97                         #address-cells = <1>;
98                         #size-cells = <0>;
99                         device_type = "network";
100                         model = "TSEC";
101                         compatible = "gianfar";
102                         reg = <24000 1000>;
103                         local-mac-address = [ 00 E0 0C 00 73 00 ];
104                         interrupts = <d 2 e 2 12 2>;
105                         interrupt-parent = <&mpic>;
106                         phy-handle = <&phy0>;
107                 };
108
109                 ethernet@25000 {
110                         #address-cells = <1>;
111                         #size-cells = <0>;
112                         device_type = "network";
113                         model = "TSEC";
114                         compatible = "gianfar";
115                         reg = <25000 1000>;
116                         local-mac-address = [ 00 E0 0C 00 73 01 ];
117                         interrupts = <13 2 14 2 18 2>;
118                         interrupt-parent = <&mpic>;
119                         phy-handle = <&phy1>;
120                 };
121
122                 serial@4500 {
123                         device_type = "serial";
124                         compatible = "ns16550";
125                         reg = <4500 100>;       // reg base, size
126                         clock-frequency = <0>;  // should we fill in in uboot?
127                         interrupts = <1a 2>;
128                         interrupt-parent = <&mpic>;
129                 };
130
131                 serial@4600 {
132                         device_type = "serial";
133                         compatible = "ns16550";
134                         reg = <4600 100>;       // reg base, size
135                         clock-frequency = <0>;  // should we fill in in uboot?
136                         interrupts = <1a 2>;
137                         interrupt-parent = <&mpic>;
138                 };
139
140                 pci1: pci@8000 {
141                         interrupt-map-mask = <1f800 0 0 7>;
142                         interrupt-map = <
143
144                                 /* IDSEL 0x10 */
145                                 08000 0 0 1 &mpic 30 1
146                                 08000 0 0 2 &mpic 31 1
147                                 08000 0 0 3 &mpic 32 1
148                                 08000 0 0 4 &mpic 33 1
149
150                                 /* IDSEL 0x11 */
151                                 08800 0 0 1 &mpic 30 1
152                                 08800 0 0 2 &mpic 31 1
153                                 08800 0 0 3 &mpic 32 1
154                                 08800 0 0 4 &mpic 33 1
155
156                                 /* IDSEL 0x12 (Slot 1) */
157                                 09000 0 0 1 &mpic 30 1
158                                 09000 0 0 2 &mpic 31 1
159                                 09000 0 0 3 &mpic 32 1
160                                 09000 0 0 4 &mpic 33 1
161
162                                 /* IDSEL 0x13 (Slot 2) */
163                                 09800 0 0 1 &mpic 31 1
164                                 09800 0 0 2 &mpic 32 1
165                                 09800 0 0 3 &mpic 33 1
166                                 09800 0 0 4 &mpic 30 1
167
168                                 /* IDSEL 0x14 (Slot 3) */
169                                 0a000 0 0 1 &mpic 32 1
170                                 0a000 0 0 2 &mpic 33 1
171                                 0a000 0 0 3 &mpic 30 1
172                                 0a000 0 0 4 &mpic 31 1
173
174                                 /* IDSEL 0x15 (Slot 4) */
175                                 0a800 0 0 1 &mpic 33 1
176                                 0a800 0 0 2 &mpic 30 1
177                                 0a800 0 0 3 &mpic 31 1
178                                 0a800 0 0 4 &mpic 32 1
179
180                                 /* Bus 1 (Tundra Bridge) */
181                                 /* IDSEL 0x12 (ISA bridge) */
182                                 19000 0 0 1 &mpic 30 1
183                                 19000 0 0 2 &mpic 31 1
184                                 19000 0 0 3 &mpic 32 1
185                                 19000 0 0 4 &mpic 33 1>;
186                         interrupt-parent = <&mpic>;
187                         interrupts = <08 2>;
188                         bus-range = <0 0>;
189                         ranges = <02000000 0 80000000 80000000 0 20000000
190                                   01000000 0 00000000 e2000000 0 00100000>;
191                         clock-frequency = <3f940aa>;
192                         #interrupt-cells = <1>;
193                         #size-cells = <2>;
194                         #address-cells = <3>;
195                         reg = <8000 1000>;
196                         compatible = "85xx";
197                         device_type = "pci";
198
199                         i8259@19000 {
200                                 clock-frequency = <0>;
201                                 interrupt-controller;
202                                 device_type = "interrupt-controller";
203                                 reg = <19000 0 0 0 1>;
204                                 #address-cells = <0>;
205                                 #interrupt-cells = <2>;
206                                 built-in;
207                                 compatible = "chrp,iic";
208                                 big-endian;
209                                 interrupts = <1>;
210                                 interrupt-parent = <&pci1>;
211                         };
212                 };
213
214                 pci@9000 {
215                         interrupt-map-mask = <f800 0 0 7>;
216                         interrupt-map = <
217
218                                 /* IDSEL 0x15 */
219                                 a800 0 0 1 &mpic 3b 1
220                                 a800 0 0 2 &mpic 3b 1
221                                 a800 0 0 3 &mpic 3b 1
222                                 a800 0 0 4 &mpic 3b 1>;
223                         interrupt-parent = <&mpic>;
224                         interrupts = <09 2>;
225                         bus-range = <0 0>;
226                         ranges = <02000000 0 a0000000 a0000000 0 20000000
227                                   01000000 0 00000000 e3000000 0 00100000>;
228                         clock-frequency = <3f940aa>;
229                         #interrupt-cells = <1>;
230                         #size-cells = <2>;
231                         #address-cells = <3>;
232                         reg = <9000 1000>;
233                         compatible = "85xx";
234                         device_type = "pci";
235                 };
236
237                 mpic: pic@40000 {
238                         clock-frequency = <0>;
239                         interrupt-controller;
240                         #address-cells = <0>;
241                         #interrupt-cells = <2>;
242                         reg = <40000 40000>;
243                         built-in;
244                         compatible = "chrp,open-pic";
245                         device_type = "open-pic";
246                         big-endian;
247                 };
248         };
249 };