4 * Copyright (C) 2007 Paul Mundt
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
10 #include <linux/platform_device.h>
11 #include <linux/init.h>
12 #include <linux/serial.h>
15 static struct plat_sci_port sci_platform_data[] = {
17 .mapbase = 0xffea0000,
18 .flags = UPF_BOOT_AUTOCONF,
20 .irqs = { 40, 41, 43, 42 },
22 .mapbase = 0xffeb0000,
23 .flags = UPF_BOOT_AUTOCONF,
25 .irqs = { 44, 45, 47, 46 },
29 * The rest of these all have multiplexed IRQs
32 .mapbase = 0xffec0000,
33 .flags = UPF_BOOT_AUTOCONF,
35 .irqs = { 60, 60, 60, 60 },
37 .mapbase = 0xffed0000,
38 .flags = UPF_BOOT_AUTOCONF,
40 .irqs = { 61, 61, 61, 61 },
42 .mapbase = 0xffee0000,
43 .flags = UPF_BOOT_AUTOCONF,
45 .irqs = { 62, 62, 62, 62 },
47 .mapbase = 0xffef0000,
48 .flags = UPF_BOOT_AUTOCONF,
50 .irqs = { 63, 63, 63, 63 },
56 static struct platform_device sci_device = {
60 .platform_data = sci_platform_data,
64 static struct platform_device *sh7785_devices[] __initdata = {
68 static int __init sh7785_devices_setup(void)
70 return platform_add_devices(sh7785_devices,
71 ARRAY_SIZE(sh7785_devices));
73 __initcall(sh7785_devices_setup);
78 /* interrupt sources */
80 IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
81 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
82 IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
83 IRL0_HHLL, IRL0_HHLH, IRL0_HHHL,
85 IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
86 IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
87 IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
88 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL,
90 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
92 TMU0, TMU1, TMU2, TMU2_TICPI,
94 DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2, DMAC0_DMINT3,
95 DMAC0_DMINT4, DMAC0_DMINT5, DMAC0_DMAE,
96 SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI,
97 SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI,
98 DMAC1_DMINT6, DMAC1_DMINT7, DMAC1_DMINT8, DMAC1_DMINT9,
99 DMAC1_DMINT10, DMAC1_DMINT11, DMAC1_DMAE,
101 SCIF2, SCIF3, SCIF4, SCIF5,
102 PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD,
103 PCIERR, PCIPWD3, PCIPWD2, PCIPWD1, PCIPWD0,
105 MMCIF_FSTAT, MMCIF_TRAN, MMCIF_ERR, MMCIF_FRDY,
107 GDTA_GACLI, GDTA_GAMCI, GDTA_GAERI,
111 FLCTL_FLSTE, FLCTL_FLEND, FLCTL_FLTRQ0, FLCTL_FLTRQ1,
112 GPIOI0, GPIOI1, GPIOI2, GPIOI3,
114 /* interrupt groups */
116 TMU012, DMAC0, SCIF0, SCIF1, DMAC1,
117 PCIC5, MMCIF, GDTA, TMU345, FLCTL, GPIO
120 static struct intc_vect vectors[] __initdata = {
121 INTC_VECT(WDT, 0x560),
122 INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0),
123 INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0),
124 INTC_VECT(HUDI, 0x600),
125 INTC_VECT(DMAC0_DMINT0, 0x620), INTC_VECT(DMAC0_DMINT1, 0x640),
126 INTC_VECT(DMAC0_DMINT2, 0x660), INTC_VECT(DMAC0_DMINT3, 0x680),
127 INTC_VECT(DMAC0_DMINT4, 0x6a0), INTC_VECT(DMAC0_DMINT5, 0x6c0),
128 INTC_VECT(DMAC0_DMAE, 0x6e0),
129 INTC_VECT(SCIF0_ERI, 0x700), INTC_VECT(SCIF0_RXI, 0x720),
130 INTC_VECT(SCIF0_BRI, 0x740), INTC_VECT(SCIF0_TXI, 0x760),
131 INTC_VECT(SCIF1_ERI, 0x780), INTC_VECT(SCIF1_RXI, 0x7a0),
132 INTC_VECT(SCIF1_BRI, 0x7c0), INTC_VECT(SCIF1_TXI, 0x7e0),
133 INTC_VECT(DMAC1_DMINT6, 0x880), INTC_VECT(DMAC1_DMINT7, 0x8a0),
134 INTC_VECT(DMAC1_DMINT8, 0x8c0), INTC_VECT(DMAC1_DMINT9, 0x8e0),
135 INTC_VECT(DMAC1_DMINT10, 0x900), INTC_VECT(DMAC1_DMINT11, 0x920),
136 INTC_VECT(DMAC1_DMAE, 0x940),
137 INTC_VECT(HSPI, 0x960),
138 INTC_VECT(SCIF2, 0x980), INTC_VECT(SCIF3, 0x9a0),
139 INTC_VECT(SCIF4, 0x9c0), INTC_VECT(SCIF5, 0x9e0),
140 INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20),
141 INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60),
142 INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIERR, 0xaa0),
143 INTC_VECT(PCIPWD3, 0xac0), INTC_VECT(PCIPWD2, 0xae0),
144 INTC_VECT(PCIPWD1, 0xb00), INTC_VECT(PCIPWD0, 0xb20),
145 INTC_VECT(SIOF, 0xc00),
146 INTC_VECT(MMCIF_FSTAT, 0xd00), INTC_VECT(MMCIF_TRAN, 0xd20),
147 INTC_VECT(MMCIF_ERR, 0xd40), INTC_VECT(MMCIF_FRDY, 0xd60),
148 INTC_VECT(DU, 0xd80),
149 INTC_VECT(GDTA_GACLI, 0xda0), INTC_VECT(GDTA_GAMCI, 0xdc0),
150 INTC_VECT(GDTA_GAERI, 0xde0),
151 INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
152 INTC_VECT(TMU5, 0xe40),
153 INTC_VECT(SSI0, 0xe80), INTC_VECT(SSI1, 0xea0),
154 INTC_VECT(HAC0, 0xec0), INTC_VECT(HAC1, 0xee0),
155 INTC_VECT(FLCTL_FLSTE, 0xf00), INTC_VECT(FLCTL_FLEND, 0xf20),
156 INTC_VECT(FLCTL_FLTRQ0, 0xf40), INTC_VECT(FLCTL_FLTRQ1, 0xf60),
157 INTC_VECT(GPIOI0, 0xf80), INTC_VECT(GPIOI1, 0xfa0),
158 INTC_VECT(GPIOI2, 0xfc0), INTC_VECT(GPIOI3, 0xfe0),
161 static struct intc_group groups[] __initdata = {
162 INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
163 INTC_GROUP(DMAC0, DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2,
164 DMAC0_DMINT3, DMAC0_DMINT4, DMAC0_DMINT5, DMAC0_DMAE),
165 INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI),
166 INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI),
167 INTC_GROUP(DMAC1, DMAC1_DMINT6, DMAC1_DMINT7, DMAC1_DMINT8,
168 DMAC1_DMINT9, DMAC1_DMINT10, DMAC1_DMINT11, DMAC1_DMAE),
169 INTC_GROUP(PCIC5, PCIERR, PCIPWD3, PCIPWD2, PCIPWD1, PCIPWD0),
170 INTC_GROUP(MMCIF, MMCIF_FSTAT, MMCIF_TRAN, MMCIF_ERR, MMCIF_FRDY),
171 INTC_GROUP(GDTA, GDTA_GACLI, GDTA_GAMCI, GDTA_GAERI),
172 INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
173 INTC_GROUP(FLCTL, FLCTL_FLSTE, FLCTL_FLEND,
174 FLCTL_FLTRQ0, FLCTL_FLTRQ1),
175 INTC_GROUP(GPIO, GPIOI0, GPIOI1, GPIOI2, GPIOI3),
178 static struct intc_prio priorities[] __initdata = {
187 static struct intc_mask_reg mask_registers[] __initdata = {
188 { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
189 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
191 { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
192 { IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
193 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
194 IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
195 IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 0,
196 IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
197 IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
198 IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
199 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } },
201 { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
202 { 0, 0, 0, GDTA, DU, SSI0, SSI1, GPIO,
203 FLCTL, MMCIF, HSPI, SIOF, PCIC5, PCIINTD, PCIINTC, PCIINTB,
204 PCIINTA, PCISERR, HAC1, HAC0, DMAC1, DMAC0, HUDI, WDT,
205 SCIF5, SCIF4, SCIF3, SCIF2, SCIF1, SCIF0, TMU345, TMU012 } },
208 static struct intc_prio_reg prio_registers[] __initdata = {
209 { 0xffd00010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
210 IRQ4, IRQ5, IRQ6, IRQ7 } },
211 { 0xffd40000, 0, 32, 8, /* INT2PRI0 */ { TMU0, TMU1,
212 TMU2, TMU2_TICPI } },
213 { 0xffd40004, 0, 32, 8, /* INT2PRI1 */ { TMU3, TMU4, TMU5, } },
214 { 0xffd40008, 0, 32, 8, /* INT2PRI2 */ { SCIF0, SCIF1,
216 { 0xffd4000c, 0, 32, 8, /* INT2PRI3 */ { SCIF4, SCIF5, WDT, } },
217 { 0xffd40010, 0, 32, 8, /* INT2PRI4 */ { HUDI, DMAC0, DMAC1, } },
218 { 0xffd40014, 0, 32, 8, /* INT2PRI5 */ { HAC0, HAC1,
219 PCISERR, PCIINTA } },
220 { 0xffd40018, 0, 32, 8, /* INT2PRI6 */ { PCIINTB, PCIINTC,
222 { 0xffd4001c, 0, 32, 8, /* INT2PRI7 */ { SIOF, HSPI, MMCIF, } },
223 { 0xffd40020, 0, 32, 8, /* INT2PRI8 */ { FLCTL, GPIO, SSI0, SSI1, } },
224 { 0xffd40024, 0, 32, 8, /* INT2PRI9 */ { DU, GDTA, } },
227 static DECLARE_INTC_DESC(intc_desc, "sh7785", vectors, groups, priorities,
228 mask_registers, prio_registers, NULL);
230 /* Support for external interrupt pins in IRQ mode */
232 static struct intc_vect vectors_irq0123[] __initdata = {
233 INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
234 INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
237 static struct intc_vect vectors_irq4567[] __initdata = {
238 INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
239 INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200),
242 static struct intc_sense_reg sense_registers[] __initdata = {
243 { 0xffd0001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3,
244 IRQ4, IRQ5, IRQ6, IRQ7 } },
247 static DECLARE_INTC_DESC(intc_desc_irq0123, "sh7785-irq0123", vectors_irq0123,
248 NULL, NULL, mask_registers, prio_registers,
251 static DECLARE_INTC_DESC(intc_desc_irq4567, "sh7785-irq4567", vectors_irq4567,
252 NULL, NULL, mask_registers, prio_registers,
255 /* External interrupt pins in IRL mode */
257 static struct intc_vect vectors_irl0123[] __initdata = {
258 INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220),
259 INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260),
260 INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0),
261 INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0),
262 INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320),
263 INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360),
264 INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0),
265 INTC_VECT(IRL0_HHHL, 0x3c0),
268 static struct intc_vect vectors_irl4567[] __initdata = {
269 INTC_VECT(IRL4_LLLL, 0xb00), INTC_VECT(IRL4_LLLH, 0xb20),
270 INTC_VECT(IRL4_LLHL, 0xb40), INTC_VECT(IRL4_LLHH, 0xb60),
271 INTC_VECT(IRL4_LHLL, 0xb80), INTC_VECT(IRL4_LHLH, 0xba0),
272 INTC_VECT(IRL4_LHHL, 0xbc0), INTC_VECT(IRL4_LHHH, 0xbe0),
273 INTC_VECT(IRL4_HLLL, 0xc00), INTC_VECT(IRL4_HLLH, 0xc20),
274 INTC_VECT(IRL4_HLHL, 0xc40), INTC_VECT(IRL4_HLHH, 0xc60),
275 INTC_VECT(IRL4_HHLL, 0xc80), INTC_VECT(IRL4_HHLH, 0xca0),
276 INTC_VECT(IRL4_HHHL, 0xcc0),
279 static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7785-irl0123", vectors_irl0123,
280 NULL, NULL, mask_registers, NULL, NULL);
282 static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7785-irl4567", vectors_irl4567,
283 NULL, NULL, mask_registers, NULL, NULL);
285 void __init plat_irq_setup(void)
287 register_intc_controller(&intc_desc);
290 void __init plat_irq_setup_pins(int mode)
293 case IRQ_MODE_IRQ7654:
294 register_intc_controller(&intc_desc_irq4567);
296 case IRQ_MODE_IRQ3210:
297 register_intc_controller(&intc_desc_irq0123);
299 case IRQ_MODE_IRL7654:
300 register_intc_controller(&intc_desc_irl4567);
302 case IRQ_MODE_IRL3210:
303 register_intc_controller(&intc_desc_irl0123);