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   1 /**************************************************************************
   2  *
   3  * Copyright © 2000-2008 Alacritech, Inc.  All rights reserved.
   4  *
   5  * $Id: sxg.h,v 1.3 2008/07/24 17:25:08 chris Exp $
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  *
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice, this list of conditions and the following disclaimer.
  13  * 2. Redistributions in binary form must reproduce the above
  14  *    copyright notice, this list of conditions and the following
  15  *    disclaimer in the documentation and/or other materials provided
  16  *    with the distribution.
  17  *
  18  * THIS SOFTWARE IS PROVIDED BY ALACRITECH, INC. ``AS IS'' AND ANY
  19  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  21  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL ALACRITECH, INC. OR
  22  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  23  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  24  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  25  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  26  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  27  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
  28  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  29  * SUCH DAMAGE.
  30  *
  31  * The views and conclusions contained in the software and documentation
  32  * are those of the authors and should not be interpreted as representing
  33  * official policies, either expressed or implied, of Alacritech, Inc.
  34  *
  35  **************************************************************************/
  36
  37 /*
  38  * FILENAME: sxg.h
  39  *
  40  * This is the base set of header definitions for the SXG driver.
  41  */
  42 #ifndef __SXG_DRIVER_H__
  43 #define __SXG_DRIVER_H__
  44
  45 #define SLIC_DUMP_ENABLED               0
  46
  47 #define SXG_DRV_NAME    "sxg"           /* TBD: This might be removed eventually */
  48 #define SXG_DRV_VERSION "1.0.1"
  49
  50 extern char sxg_driver_name[];
  51
  52 #define SXG_NETDEV_WEIGHT 64
  53
  54 /*
  55  * struct sxg_stats - Probably move these to someplace where
  56  * the slicstat (sxgstat?) program can get them.
  57  */
  58 struct sxg_stats {
  59         /* Xmt */
  60         u64     DumbXmtUcastPkts;       /* directed packets */
  61         u64     DumbXmtMcastPkts;       /* Multicast packets */
  62         u64     DumbXmtBcastPkts;       /* OID_GEN_BROADCAST_FRAMES_RCV */
  63         u64     DumbXmtUcastBytes;      /* OID_GEN_DIRECTED_BYTES_XMIT */
  64         u64     DumbXmtMcastBytes;      /* OID_GEN_MULTICAST_BYTES_XMIT */
  65         u64     DumbXmtBcastBytes;      /* OID_GEN_BROADCAST_BYTES_XMIT */
  66         u64     XmtQLen;                /* OID_GEN_TRANSMIT_QUEUE_LENGTH */
  67         u64     XmtZeroFull;            /* Transmit ring zero full */
  68         /* Rcv */
  69         u64     DumbRcvUcastBytes;      /* OID_GEN_DIRECTED_BYTES_RCV */
  70         u64     DumbRcvMcastBytes;      /* OID_GEN_MULTICAST_BYTES_RCV */
  71         u64     DumbRcvBcastBytes;      /* OID_GEN_BROADCAST_BYTES_RCV */
  72         u64     DumbRcvUcastPkts;       /* directed packets */
  73         u64     DumbRcvMcastPkts;       /* Multicast packets */
  74         u64     DumbRcvBcastPkts;       /* OID_GEN_BROADCAST_FRAMES_RCV */
  75         u64     PdqFull;                /* Processed Data Queue Full */
  76         u64     EventRingFull;          /* Event ring full */
  77         /* Verbose stats */
  78         u64     NoSglBuf;               /* SGL buffer allocation failure */
  79         u64     NoMem;                  /* Memory allocation failure */
  80         u64     NumInts;                /* Interrupts */
  81         u64     FalseInts;              /* Interrupt with ISR == 0 */
  82         /* Sahara receive status */
  83         u64     TransportCsum;          /* SXG_RCV_STATUS_TRANSPORT_CSUM */
  84         u64     TransportUflow;         /* SXG_RCV_STATUS_TRANSPORT_UFLOW */
  85         u64     TransportHdrLen;        /* SXG_RCV_STATUS_TRANSPORT_HDRLEN */
  86         u64     NetworkCsum;            /* SXG_RCV_STATUS_NETWORK_CSUM: */
  87         u64     NetworkUflow;           /* SXG_RCV_STATUS_NETWORK_UFLOW: */
  88         u64     NetworkHdrLen;          /* SXG_RCV_STATUS_NETWORK_HDRLEN: */
  89         u64     Parity;                 /* SXG_RCV_STATUS_PARITY */
  90         u64     LinkParity;             /* SXG_RCV_STATUS_LINK_PARITY: */
  91         u64     LinkEarly;              /* SXG_RCV_STATUS_LINK_EARLY: */
  92         u64     LinkBufOflow;           /* SXG_RCV_STATUS_LINK_BUFOFLOW: */
  93         u64     LinkCode;               /* SXG_RCV_STATUS_LINK_CODE: */
  94         u64     LinkDribble;            /* SXG_RCV_STATUS_LINK_DRIBBLE: */
  95         u64     LinkCrc;                /* SXG_RCV_STATUS_LINK_CRC: */
  96         u64     LinkOflow;              /* SXG_RCV_STATUS_LINK_OFLOW: */
  97         u64     LinkUflow;              /* SXG_RCV_STATUS_LINK_UFLOW: */
  98 };
  99
 100
 101 /* DUMB-NIC Send path definitions */
 102
 103 #define SXG_COMPLETE_DUMB_SEND(_pAdapt, _skb, _phys_addr, _size) {              \
 104         ASSERT(_skb);                                                           \
 105         pci_unmap_single(_pAdapt->pcidev, _size, _phys_addr, PCI_DMA_TODEVICE); \
 106         dev_kfree_skb_irq(_skb);                                                \
 107 }
 108
 109 #define SXG_DROP_DUMB_SEND(_pAdapt, _skb) {                             \
 110         ASSERT(_skb);                                                   \
 111 }
 112
 113 /*
 114  * Locate current receive header buffer location.  Use this
 115  * instead of RcvDataHdr->VirtualAddress since the data
 116  * may have been offset by SXG_ADVANCE_MDL_OFFSET
 117  */
 118 #define SXG_RECEIVE_DATA_LOCATION(_RcvDataHdr)        (_RcvDataHdr)->skb->data
 119
 120 /* Dumb-NIC receive processing */
 121 /* Define an SXG_PACKET as an NDIS_PACKET */
 122 #define PSXG_PACKET       struct sk_buff *
 123 /* Indications array size */
 124 #define SXG_RCV_ARRAYSIZE       64
 125
 126 #define SXG_ALLOCATE_RCV_PACKET(_pAdapt, _RcvDataBufferHdr, BufferSize) {\
 127     struct sk_buff * skb;                                               \
 128     skb = netdev_alloc_skb(_pAdapt->netdev, BufferSize);                \
 129     if (skb) {                                                          \
 130         (_RcvDataBufferHdr)->skb = skb;                                 \
 131         skb->next = NULL;                                               \
 132         _RcvDataBufferHdr->PhysicalAddress = pci_map_single(adapter->pcidev,\
 133             _RcvDataBufferHdr->skb->data, BufferSize, PCI_DMA_FROMDEVICE);      \
 134         if (SXG_INVALID_SGL(_RcvDataBufferHdr->PhysicalAddress,BufferSize))  \
 135                 printk(KERN_EMERG "SXG_ALLOCATE_RCV_PACKET: RCV packet" \
 136                                         "non-64k boundary aligned\n");  \
 137     } else {                                                            \
 138         (_RcvDataBufferHdr)->skb = NULL;                                \
 139     }                                                                   \
 140 }
 141
 142 #define SXG_FREE_RCV_PACKET(_RcvDataBufferHdr) {                        \
 143         if((_RcvDataBufferHdr)->skb) {                                  \
 144                 dev_kfree_skb((_RcvDataBufferHdr)->skb);                \
 145     }                                                                   \
 146 }
 147
 148 /*
 149  * Macro to add a NDIS_PACKET to an indication array
 150  * If we fill up our array of packet pointers, then indicate this
 151  * block up now and start on a new one.
 152  */
 153 #define SXG_ADD_RCV_PACKET(_pAdapt, _Packet, _PrevPacket, _IndicationList, \
 154                                 _NumPackets) {                          \
 155         (_IndicationList)[_NumPackets] = (_Packet);                     \
 156         (_NumPackets)++;                                                \
 157         if((_NumPackets) == SXG_RCV_ARRAYSIZE) {                        \
 158                 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "IndicRcv",   \
 159                                    (_NumPackets), 0, 0, 0);             \
 160         netif_rx((_IndicationList),(_NumPackets));                      \
 161                 (_NumPackets) = 0;                                      \
 162         }                                                               \
 163 }
 164
 165 #define SXG_INDICATE_PACKETS(_pAdapt, _IndicationList, _NumPackets) {   \
 166         if(_NumPackets) {                                               \
 167                 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "IndicRcv",   \
 168                                    (_NumPackets), 0, 0, 0);             \
 169         netif_rx((_IndicationList),(_NumPackets));                      \
 170                 (_NumPackets) = 0;                                      \
 171         }                                                               \
 172 }
 173
 174 #define SXG_REINIATIALIZE_PACKET(_Packet)                               \
 175         {}  /*_NdisReinitializePacket(_Packet)*/
 176                  /*  this is not necessary with an skb */
 177
 178 /* Definitions to initialize Dumb-nic Receive NBLs */
 179 #define SXG_RCV_PACKET_BUFFER_HDR(_Packet) (((struct sxg_rcv_nbl_reserved *)\
 180                         ((_Packet)->MiniportReservedEx))->RcvDataBufferHdr)
 181
 182 #define SXG_RCV_SET_CHECKSUM_INFO(_Packet, _Cpi)                                \
 183         NDIS_PER_PACKET_INFO_FROM_PACKET((_Packet),                             \
 184                         TcpIpChecksumPacketInfo) = (PVOID)(_Cpi)
 185
 186 #define SXG_RCV_SET_TOEPLITZ(_Packet, _Toeplitz, _Type, _Function) {            \
 187         NDIS_PACKET_SET_HASH_VALUE((_Packet), (_Toeplitz));                     \
 188         NDIS_PACKET_SET_HASH_TYPE((_Packet), (_Type));                          \
 189         NDIS_PACKET_SET_HASH_FUNCTION((_Packet), (_Function));                  \
 190 }
 191
 192 #define SXG_RCV_SET_VLAN_INFO(_Packet, _VlanId, _Priority) {                    \
 193         NDIS_PACKET_8021Q_INFO  _Packet8021qInfo;                               \
 194         _Packet8021qInfo.TagHeader.VlanId = (_VlanId);                          \
 195         _Packet8021qInfo.TagHeader.UserPriority = (_Priority);                  \
 196         NDIS_PER_PACKET_INFO_FROM_PACKET((_Packet), Ieee8021QNetBufferListInfo) =       \
 197                 _Packet8021qInfo.Value;                                         \
 198 }
 199
 200 #define SXG_ADJUST_RCV_PACKET(_Packet, _RcvDataBufferHdr, _Event) {             \
 201         SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "DumbRcv",            \
 202                            (_RcvDataBufferHdr), (_Packet),                      \
 203                            (_Event)->Status, 0);                                \
 204         /* ASSERT((_Event)->Length <= (_RcvDataBufferHdr)->Size); */            \
 205         skb_put(Packet, (_Event)->Length);                                      \
 206 }
 207
 208 /*
 209  * Macros to free a receive data buffer and receive data descriptor block
 210  * NOTE - Lock must be held with RCV macros
 211  */
 212 #define SXG_GET_RCV_DATA_BUFFER(_pAdapt, _Hdr) {                                \
 213         struct list_entry *_ple;                                                \
 214         _Hdr = NULL;                                                            \
 215         if((_pAdapt)->FreeRcvBufferCount) {                                     \
 216                 ASSERT(!(IsListEmpty(&(_pAdapt)->FreeRcvBuffers)));             \
 217                 _ple = RemoveHeadList(&(_pAdapt)->FreeRcvBuffers);              \
 218                 (_Hdr) = container_of(_ple, struct sxg_rcv_data_buffer_hdr,     \
 219                                                 FreeList);                      \
 220                 (_pAdapt)->FreeRcvBufferCount--;                                \
 221                 ASSERT((_Hdr)->State == SXG_BUFFER_FREE);                       \
 222         }                                                                       \
 223 }
 224
 225 #define SXG_FREE_RCV_DATA_BUFFER(_pAdapt, _Hdr) {                               \
 226         SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "RtnDHdr",            \
 227                            (_Hdr), (_pAdapt)->FreeRcvBufferCount,               \
 228                            (_Hdr)->State, 0/*(_Hdr)->VirtualAddress*/);         \
 229 /*      SXG_RESTORE_MDL_OFFSET(_Hdr);   */                                      \
 230         (_pAdapt)->FreeRcvBufferCount++;                                        \
 231         ASSERT(((_pAdapt)->AllRcvBlockCount * SXG_RCV_DESCRIPTORS_PER_BLOCK)    \
 232                                 >= (_pAdapt)->FreeRcvBufferCount);              \
 233         ASSERT((_Hdr)->State != SXG_BUFFER_FREE);                               \
 234         (_Hdr)->State = SXG_BUFFER_FREE;                                        \
 235         InsertTailList(&(_pAdapt)->FreeRcvBuffers, &((_Hdr)->FreeList));        \
 236 }
 237
 238 #define SXG_FREE_RCV_DESCRIPTOR_BLOCK(_pAdapt, _Hdr) {                          \
 239         ASSERT((_Hdr)->State != SXG_BUFFER_FREE);                               \
 240         (_Hdr)->State = SXG_BUFFER_FREE;                                        \
 241         (_pAdapt)->FreeRcvBlockCount++;                                         \
 242         ASSERT((_pAdapt)->AllRcvBlockCount >= (_pAdapt)->FreeRcvBlockCount);    \
 243         InsertTailList(&(_pAdapt)->FreeRcvBlocks, &(_Hdr)->FreeList);           \
 244 }
 245
 246 /* SGL macros */
 247 #define SXG_FREE_SGL_BUFFER(_pAdapt, _Sgl, _NB) {                               \
 248         spin_lock_irqsave(&(_pAdapt)->SglQLock, sgl_flags);                     \
 249         (_pAdapt)->FreeSglBufferCount++;                                        \
 250         ASSERT((_pAdapt)->AllSglBufferCount >= (_pAdapt)->FreeSglBufferCount);  \
 251         ASSERT(!((_Sgl)->State & SXG_BUFFER_FREE));                             \
 252         (_Sgl)->State = SXG_BUFFER_FREE;                                        \
 253         InsertTailList(&(_pAdapt)->FreeSglBuffers, &(_Sgl)->FreeList);          \
 254         spin_unlock_irqrestore(&(_pAdapt)->SglQLock, sgl_flags);                \
 255 }
 256
 257 /*
 258  * Get an SGL buffer from the free queue.  The first part of this macro
 259  * attempts to keep ahead of buffer depletion by allocating more when
 260  * we hit a minimum threshold.  Note that we don't grab the lock
 261  * until after that.  We're dealing with round numbers here, so we don't need to,
 262  * and not grabbing it avoids a possible double-trip.
 263  */
 264 #define SXG_GET_SGL_BUFFER(_pAdapt, _Sgl, _irq) {                       \
 265         struct list_entry *_ple;                                        \
 266         if ((_pAdapt->FreeSglBufferCount < SXG_MIN_SGL_BUFFERS) &&      \
 267            (_pAdapt->AllSglBufferCount < SXG_MAX_SGL_BUFFERS) &&        \
 268            (atomic_read(&_pAdapt->pending_allocations) == 0)) {         \
 269                 sxg_allocate_buffer_memory(_pAdapt,                     \
 270                         (sizeof(struct sxg_scatter_gather) + SXG_SGL_BUF_SIZE),\
 271                         SXG_BUFFER_TYPE_SGL);                           \
 272         }                                                               \
 273         _Sgl = NULL;                                                    \
 274         if(!_irq)                                                       \
 275                 spin_lock_irqsave(&(_pAdapt)->SglQLock, sgl_flags);     \
 276         else                                                            \
 277                 spin_lock_irqsave(&(_pAdapt)->SglQLock, sgl_flags);     \
 278         if((_pAdapt)->FreeSglBufferCount) {                             \
 279                 ASSERT(!(IsListEmpty(&(_pAdapt)->FreeSglBuffers)));     \
 280                 _ple = RemoveHeadList(&(_pAdapt)->FreeSglBuffers);      \
 281                 (_Sgl) = container_of(_ple, struct sxg_scatter_gather,  \
 282                                                 FreeList);              \
 283             (_pAdapt)->FreeSglBufferCount--;                            \
 284                 ASSERT((_Sgl)->State == SXG_BUFFER_FREE);               \
 285                 (_Sgl)->State = SXG_BUFFER_BUSY;                        \
 286                 (_Sgl)->pSgl = NULL;                                    \
 287         }                                                               \
 288         if(!_irq)                                                       \
 289                 spin_unlock_irqrestore(&(_pAdapt)->SglQLock, sgl_flags);\
 290         else                                                            \
 291                 spin_unlock_irqrestore(&(_pAdapt)->SglQLock, sgl_flags);\
 292 }
 293
 294 /*
 295  * struct sxg_multicast_address
 296  * Linked list of multicast addresses.
 297  */
 298 struct sxg_multicast_address {
 299         unsigned char                   Address[6];
 300         struct sxg_multicast_address    *Next;
 301 };
 302
 303 /*
 304  * Structure to maintain chimney send and receive buffer queues.
 305  * This structure maintains NET_BUFFER_LIST queues that are
 306  * given to us via the Chimney MiniportTcpOffloadSend and
 307  * MiniportTcpOffloadReceive routines.  This structure DOES NOT
 308  * manage our data buffer queue
 309  */
 310 struct sxg_buffer_queue {
 311         u32     Type;                   /* Slow or fast - See below */
 312         u32     Direction;              /* Xmt or Rcv */
 313         u32     Bytes;                  /* Byte count */
 314         u32 *   Head;                   /* Send queue head */
 315         u32 *   Tail;                   /* Send queue tail */
 316 /*      PNET_BUFFER_LIST        NextNBL;*/      /* Short cut - next NBL */
 317 /*      PNET_BUFFER             NextNB; */      /* Short cut - next NB */
 318 };
 319
 320 #define         SXG_SLOW_SEND_BUFFER    0
 321 #define         SXG_FAST_SEND_BUFFER    1
 322 #define         SXG_RECEIVE_BUFFER              2
 323
 324 #define SXG_INIT_BUFFER(_Buffer, _Type) {                               \
 325         (_Buffer)->Type = (_Type);                                      \
 326         if((_Type) == SXG_RECEIVE_BUFFER) {                             \
 327                 (_Buffer)->Direction = 0;                               \
 328         } else {                                                        \
 329                 (_Buffer)->Direction = NDIS_SG_LIST_WRITE_TO_DEVICE;    \
 330         }                                                               \
 331         (_Buffer)->Bytes = 0;                                           \
 332         (_Buffer)->Head = NULL;                                         \
 333         (_Buffer)->Tail = NULL;                                         \
 334 }
 335
 336
 337 #define SXG_RSS_CPU_COUNT(_pAdapt)                                      \
 338         ((_pAdapt)->RssEnabled  ?  NR_CPUS : 1)
 339
 340 /* DRIVER and ADAPTER structures */
 341
 342 /*
 343  * Adapter states - These states closely match the adapter states
 344  * documented in the DDK (with a few exceptions).
 345  */
 346 enum SXG_STATE {
 347         SXG_STATE_INITIALIZING,                 /* Initializing */
 348         SXG_STATE_BOOTDIAG,                     /* Boot-Diagnostic mode */
 349         SXG_STATE_PAUSING,                      /* Pausing */
 350         SXG_STATE_PAUSED,                       /* Paused */
 351         SXG_STATE_RUNNING,                      /* Running */
 352         SXG_STATE_RESETTING,                    /* Reset in progress */
 353         SXG_STATE_SLEEP,                        /* Sleeping */
 354         SXG_STATE_DIAG,                         /* Diagnostic mode */
 355         SXG_STATE_HALTING,                      /* Halting */
 356         SXG_STATE_HALTED,                       /* Down or not-initialized */
 357         SXG_STATE_SHUTDOWN                      /* shutdown */
 358 };
 359
 360 /* Link state */
 361 enum SXG_LINK_STATE {
 362         SXG_LINK_DOWN,
 363         SXG_LINK_UP
 364 };
 365
 366 /* Link initialization timeout in 100us units */
 367 #define SXG_LINK_TIMEOUT        100000          /* 10 Seconds - REDUCE! */
 368
 369
 370 /* Microcode file selection codes */
 371 enum SXG_UCODE_SEL {
 372         SXG_UCODE_SYSTEM,       /* System (operational) uucode */
 373         SXG_UCODE_SDIAGCPU,     /* System CPU diagnostic ucode */
 374         SXG_UCODE_SDIAGSYS      /* System diagnostic ucode */
 375 };
 376
 377
 378 #define SXG_DISABLE_ALL_INTERRUPTS(_padapt) sxg_disable_interrupt(_padapt)
 379 #define SXG_ENABLE_ALL_INTERRUPTS(_padapt) sxg_enable_interrupt(_padapt)
 380
 381 /* This probably lives in a proto.h file.  Move later */
 382 #define SXG_MULTICAST_PACKET(_pether) ((_pether)->ether_dhost[0] & 0x01)
 383 #define SXG_BROADCAST_PACKET(_pether)                                   \
 384                 ((*(u32 *)(_pether)->ether_dhost == 0xFFFFFFFF) &&      \
 385                 (*(u16 *)&(_pether)->ether_dhost[4] == 0xFFFF))
 386
 387 /* For DbgPrints */
 388 #define SXG_ID      DPFLTR_IHVNETWORK_ID
 389 #define SXG_ERROR   DPFLTR_ERROR_LEVEL
 390
 391 /*
 392  * struct sxg_driver structure -
 393  *
 394  * contains information about the sxg driver.  There is only
 395  * one of these, and it is defined as a global.
 396  */
 397
 398 struct sxg_driver {
 399         struct adapter_t        *Adapters;      /* Linked list of adapters */
 400         ushort                  AdapterID;      /* Maintain unique adapter ID */
 401 };
 402
 403 #ifdef STATUS_SUCCESS
 404 #undef STATUS_SUCCESS
 405 #endif
 406
 407 /* TODO: We need to try and use NETDEV_TX_* before posting this out */
 408 #define STATUS_SUCCESS              0
 409 #define STATUS_PENDING              0
 410 #define STATUS_FAILURE             -1
 411 #define STATUS_ERROR               -2
 412 #define STATUS_NOT_SUPPORTED       -3
 413 #define STATUS_BUFFER_TOO_SHORT    -4
 414 #define STATUS_RESOURCES           -5
 415
 416 #define SLIC_MAX_CARDS              32
 417 #define SLIC_MAX_PORTS              4        /* Max # of ports per card   */
 418 #if SLIC_DUMP_ENABLED
 419
 420 /*
 421  * Dump buffer size
 422  * This cannot be bigger than the max DMA size the card supports,
 423  * given the current code structure in the host and ucode.
 424  * Mojave supports 16K, Oasis supports 16K-1, so
 425  * just set this at 15K, shouldnt make that much of a diff.
 426  */
 427 #define DUMP_BUF_SIZE   0x3C00
 428 #endif
 429
 430 #define MIN(a, b) ((u32)(a) < (u32)(b) ? (a) : (b))
 431 #define MAX(a, b) ((u32)(a) > (u32)(b) ? (a) : (b))
 432
 433 struct mcast_address {
 434     unsigned char          address[6];
 435     struct mcast_address   *next;
 436 };
 437
 438 #define CARD_DOWN                       0x00000000
 439 #define CARD_UP                         0x00000001
 440 #define CARD_FAIL                       0x00000002
 441 #define CARD_DIAG                       0x00000003
 442 #define CARD_SLEEP                      0x00000004
 443
 444 #define ADAPT_DOWN                      0x00
 445 #define ADAPT_UP                        0x01
 446 #define ADAPT_FAIL                      0x02
 447 #define ADAPT_RESET                     0x03
 448 #define ADAPT_SLEEP                     0x04
 449
 450 #define ADAPT_FLAGS_BOOTTIME            0x0001
 451 #define ADAPT_FLAGS_IS64BIT             0x0002
 452 #define ADAPT_FLAGS_PENDINGLINKDOWN     0x0004
 453 #define ADAPT_FLAGS_FIBERMEDIA          0x0008
 454 #define ADAPT_FLAGS_LOCKS_ALLOCED       0x0010
 455 #define ADAPT_FLAGS_INT_REGISTERED      0x0020
 456 #define ADAPT_FLAGS_LOAD_TIMER_SET      0x0040
 457 #define ADAPT_FLAGS_STATS_TIMER_SET     0x0080
 458 #define ADAPT_FLAGS_RESET_TIMER_SET     0x0100
 459
 460 #define LINK_DOWN                       0x00
 461 #define LINK_CONFIG                     0x01
 462 #define LINK_UP                         0x02
 463
 464 #define LINK_10MB                       0x00
 465 #define LINK_100MB                      0x01
 466 #define LINK_AUTOSPEED                  0x02
 467 #define LINK_1000MB                     0x03
 468 #define LINK_10000MB                    0x04
 469
 470 #define LINK_HALFD                      0x00
 471 #define LINK_FULLD                      0x01
 472 #define LINK_AUTOD                      0x02
 473
 474 #define MAC_DIRECTED                    0x00000001
 475 #define MAC_BCAST                       0x00000002
 476 #define MAC_MCAST                       0x00000004
 477 #define MAC_PROMISC                     0x00000008
 478 #define MAC_LOOPBACK                    0x00000010
 479 #define MAC_ALLMCAST                    0x00000020
 480
 481 #define SLIC_DUPLEX(x)    ((x==LINK_FULLD) ? "FDX" : "HDX")
 482 #define SLIC_SPEED(x)     ((x==LINK_100MB) ? "100Mb" :                  \
 483                                 ((x==LINK_1000MB) ? "1000Mb" : " 10Mb"))
 484 #define SLIC_LINKSTATE(x) ((x==LINK_DOWN) ? "Down" : "Up  ")
 485 #define SLIC_ADAPTER_STATE(x) ((x==ADAPT_UP) ? "UP" : "Down")
 486 #define SLIC_CARD_STATE(x)    ((x==CARD_UP) ? "UP" : "Down")
 487
 488
 489 struct ether_header {
 490     unsigned char    ether_dhost[6];
 491     unsigned char    ether_shost[6];
 492     ushort   ether_type;
 493 };
 494
 495
 496 #define NUM_CFG_SPACES      2
 497 #define NUM_CFG_REGS        64
 498
 499 /*
 500  * We split LSS sends across four microcode queues derived from
 501  * destination TCP port (if TCP/IP).
 502  */
 503 #define SXG_LARGE_SEND_QUEUE_MASK    0x3
 504 #define ISCSI_PORT                   0xbc0c                  /* 3260 */
 505
 506 struct physcard {
 507     struct adapter_t            *adapter[SLIC_MAX_PORTS];
 508     struct physcard             *next;
 509     unsigned int                adapters_allocd;
 510 };
 511
 512 struct sxgbase_driver {
 513         spinlock_t      driver_lock;
 514         unsigned long   flags;  /* irqsave for spinlock */
 515         u32             num_sxg_cards;
 516         u32             num_sxg_ports;
 517         u32             num_sxg_ports_active;
 518         u32             dynamic_intagg;
 519         struct physcard *phys_card;
 520 };
 521
 522
 523 struct adapter_t {
 524         void *               ifp;
 525         unsigned int                port;
 526         struct napi_struct      napi;
 527         struct physcard        *physcard;
 528         unsigned int                physport;
 529         unsigned int                slotnumber;
 530         unsigned int                functionnumber;
 531         ushort              vendid;
 532         ushort              devid;
 533         ushort              subsysid;
 534         u32             irq;
 535
 536         void __iomem *  base_addr;
 537         u32             memorylength;
 538         u32             drambase;
 539         u32             dramlength;
 540         enum asic_type  asictype;      /* type of ASIC (chip) */
 541         unsigned int                activated;
 542         u32             intrregistered;
 543         unsigned int                isp_initialized;
 544         unsigned char               state;
 545         unsigned char               linkstate;
 546         unsigned int                flags;
 547         unsigned char               macaddr[6];
 548         unsigned char               currmacaddr[6];
 549         u32             macopts;
 550         ushort              devflags_prev;
 551         u64             mcastmask;
 552         struct mcast_address   *mcastaddrs;
 553         struct timer_list   pingtimer;
 554         u32             pingtimerset;
 555         struct timer_list   statstimer;
 556         u32             statstimerset;
 557         struct timer_list   vpci_timer;
 558         u32             vpci_timerset;
 559         struct timer_list   loadtimer;
 560         u32             loadtimerset;
 561
 562         u32             xmitq_full;
 563         u32             all_reg_writes;
 564         u32             icr_reg_writes;
 565         u32             isr_reg_writes;
 566         u32             error_interrupts;
 567         u32             error_rmiss_interrupts;
 568         u32             rx_errors;
 569         u32             rcv_drops;
 570         u32             rcv_interrupts;
 571         u32             xmit_interrupts;
 572         u32             linkevent_interrupts;
 573         u32             upr_interrupts;
 574         u32             num_isrs;
 575         u32             false_interrupts;
 576         u32             tx_packets;
 577         u32             xmit_completes;
 578         u32             tx_drops;
 579         u32             rcv_broadcasts;
 580         u32             rcv_multicasts;
 581         u32             rcv_unicasts;
 582         u32             max_isr_rcvs;
 583         u32             max_isr_xmits;
 584         u32             rcv_interrupt_yields;
 585         u32             intagg_period;
 586         struct net_device_stats stats;
 587         u32 *                   MiniportHandle;         /* Our miniport handle */
 588         enum SXG_STATE          State;                  /* Adapter state */
 589         enum SXG_LINK_STATE     LinkState;              /* Link state */
 590         u64                     LinkSpeed;              /* Link Speed */
 591         u32                     PowerState;             /* NDIS power state */
 592         struct adapter_t        *Next;                  /* Linked list */
 593         ushort                  AdapterID;              /* 1..n */
 594         struct net_device *         netdev;
 595         struct net_device *         next_netdevice;
 596         struct pci_dev            *pcidev;
 597
 598         struct sxg_multicast_address    *MulticastAddrs; /* Multicast list */
 599         u64                     MulticastMask;          /* Multicast mask */
 600         u32                     *InterruptHandle;       /* Register Interrupt handle */
 601         u32                     InterruptLevel;         /* From Resource list */
 602         u32                     InterruptVector;        /* From Resource list */
 603         spinlock_t              AdapterLock;    /* Serialize access adapter routines */
 604         spinlock_t              Bit64RegLock;   /* For writing 64-bit addresses */
 605         struct sxg_hw_regs      *HwRegs;        /* Sahara HW Register Memory (BAR0/1) */
 606         struct sxg_ucode_regs   *UcodeRegs;     /* Microcode Register Memory (BAR2/3) */
 607         struct sxg_tcb_regs     *TcbRegs;       /* Same as Ucode regs - See sxghw.h */
 608         ushort          FrameSize;      /* Maximum frame size */
 609         u32 *           DmaHandle;      /* NDIS DMA handle */
 610         u32 *           PacketPoolHandle;       /* Used with NDIS 5.2 only.  Don't ifdef out */
 611         u32 *           BufferPoolHandle;       /* Used with NDIS 5.2 only.  Don't ifdef out */
 612         u32             MacFilter;              /* NDIS MAC Filter */
 613         struct sxg_event_ring   *EventRings;    /* Host event rings.  1/CPU to 16 max */
 614         dma_addr_t              PEventRings;    /* Physical address */
 615         u32             NextEvent[SXG_MAX_RSS]; /* Current location in ring */
 616         dma_addr_t      PTcbBuffers;            /* TCB Buffers - physical address */
 617         dma_addr_t      PTcbCompBuffers;        /* TCB Composite Buffers - phys addr */
 618         struct sxg_xmt_ring     *XmtRings;      /* Transmit rings */
 619         dma_addr_t              PXmtRings;      /* Transmit rings - physical address */
 620         struct sxg_ring_info    XmtRingZeroInfo;        /* Transmit ring 0 info */
 621
 622         spinlock_t      XmtZeroLock;    /* Transmit ring 0 lock */
 623         u32 *           XmtRingZeroIndex;       /* Shared XMT ring 0 index */
 624         dma_addr_t      PXmtRingZeroIndex;      /* Shared XMT ring 0 index - physical */
 625         struct list_entry       FreeProtocolHeaders;/* Free protocol headers */
 626         u32             FreeProtoHdrCount;      /* Count */
 627         void *          ProtocolHeaders;        /* Block of protocol header */
 628         dma_addr_t      PProtocolHeaders;       /* Block of protocol headers - phys */
 629
 630         struct sxg_rcv_ring     *RcvRings;      /* Receive rings */
 631         dma_addr_t      PRcvRings;              /* Receive rings - physical address */
 632         struct sxg_ucode_stats  *ucode_stats;           /* Ucode Stats  */
 633         /* Ucode Stats - physical address */
 634         dma_addr_t              pucode_stats;
 635
 636         struct sxg_ring_info    RcvRingZeroInfo;        /* Receive ring 0 info */
 637
 638         u32 *           Isr;            /* Interrupt status register */
 639         dma_addr_t      PIsr;           /* ISR - physical address */
 640         u32             IsrCopy[SXG_MAX_RSS];   /* Copy of ISR */
 641         ushort          InterruptsEnabled;      /* Bitmask of enabled vectors */
 642         unsigned char   *IndirectionTable;      /* RSS indirection table */
 643         dma_addr_t      PIndirectionTable;      /* Physical address */
 644         ushort          RssTableSize;           /* From NDIS_RECEIVE_SCALE_PARAMETERS */
 645         ushort          HashKeySize;            /* From NDIS_RECEIVE_SCALE_PARAMETERS */
 646         unsigned char   HashSecretKey[40];      /* rss key */
 647         u32             HashInformation;
 648         /* Receive buffer queues */
 649         spinlock_t      RcvQLock;               /* Receive Queue Lock */
 650         struct list_entry       FreeRcvBuffers;         /* Free SXG_DATA_BUFFER queue */
 651         struct list_entry       FreeRcvBlocks;          /* Free SXG_RCV_DESCRIPTOR_BLOCK Q */
 652         struct list_entry       AllRcvBlocks;           /* All SXG_RCV_BLOCKs */
 653         ushort          FreeRcvBufferCount;     /* Number of free rcv data buffers */
 654         ushort          FreeRcvBlockCount;      /* # of free rcv descriptor blocks */
 655         ushort          AllRcvBlockCount;       /* Number of total receive blocks */
 656         ushort          ReceiveBufferSize;      /* SXG_RCV_DATA/JUMBO_BUFFER_SIZE only */
 657         /* Converted this to a atomic variable
 658         u32                     AllocationsPending;     */
 659         atomic_t                pending_allocations;
 660         u32             AllocationsPending;     /* Receive allocation pending */
 661         u32             RcvBuffersOnCard;       /* SXG_DATA_BUFFERS owned by card */
 662         /* SGL buffers */
 663         spinlock_t      SglQLock;       /* SGL Queue Lock */
 664         struct list_entry       FreeSglBuffers;         /* Free struct sxg_scatter_gather */
 665         struct list_entry       AllSglBuffers;          /* All struct sxg_scatter_gather */
 666         ushort          FreeSglBufferCount;     /* Number of free SGL buffers */
 667         ushort          AllSglBufferCount;      /* Number of total SGL buffers */
 668         u32             CurrentTime;            /* Tick count */
 669         u32             FastpathConnections;/* # of fastpath connections */
 670         /* Various single-bit flags: */
 671         u32             BasicAllocations:1;     /* Locks and listheads */
 672         u32             IntRegistered:1;        /* Interrupt registered */
 673         u32             PingOutstanding:1;      /* Ping outstanding to card */
 674         u32             Dead:1;                         /* Card dead */
 675         u32             DumpDriver:1;           /* OID_SLIC_DRIVER_DUMP request */
 676         u32             DumpCard:1;                     /* OID_SLIC_CARD_DUMP request */
 677         u32             DumpCmdRunning:1;       /* Dump command in progress */
 678         u32             DebugRunning:1;         /* AGDB debug in progress */
 679         u32             JumboEnabled:1;         /* Jumbo frames enabled */
 680         u32             msi_enabled:1;          /* MSI interrupt enabled */
 681         u32             RssEnabled:1;           /* RSS Enabled */
 682         u32             FailOnBadEeprom:1;      /* Fail on Bad Eeprom */
 683         u32             DiagStart:1;            /* Init adapter for diagnostic start */
 684         u32             XmtFcEnabled:1;
 685         u32             RcvFcEnabled:1;
 686         /* Stats */
 687         u32             PendingRcvCount;        /* Outstanding rcv indications */
 688         u32             PendingXmtCount;        /* Outstanding send requests */
 689         struct sxg_stats        Stats;                          /* Statistics */
 690         u32             ReassBufs;                      /* Number of reassembly buffers */
 691         /* Card Crash Info */
 692         ushort          CrashLocation;          /* Microcode crash location */
 693         unsigned char   CrashCpu;                       /* Sahara CPU ID */
 694         /* Diagnostics */
 695         /*      PDIAG_CMD       DiagCmds; */                    /* List of free diagnostic commands */
 696         /*      PDIAG_BUFFER    DiagBuffers; */         /* List of free diagnostic buffers */
 697         /*      PDIAG_REQ       DiagReqQ; */                    /* List of outstanding (asynchronous) diag requests */
 698         /*      u32             DiagCmdTimeout; */              /* Time out for diag cmds (seconds) XXXTODO - replace with SXG_PARAM var? */
 699         /*      unsigned char   DiagDmaDesc[DMA_CPU_CTXS]; */           /* Free DMA descriptors bit field (32 CPU ctx * 8 DMA ctx) */
 700         /*
 701          * Put preprocessor-conditional fields at the end so we don't
 702          * have to recompile sxgdbg everytime we reconfigure the driver
 703          */
 704 #if defined(CONFIG_X86)
 705         u32             AddrUpper;                      /* Upper 32 bits of 64-bit register */
 706 #endif
 707         unsigned short max_aggregation;
 708         unsigned short min_aggregation;
 709         /*#if SXG_FAILURE_DUMP */
 710         /*      NDIS_EVENT      DumpThreadEvent; */     /* syncronize dump thread */
 711         /*      BOOLEAN         DumpThreadRunning; */   /* termination flag */
 712         /*      PSXG_DUMP_CMD   DumpBuffer; */                  /* 68k - Cmd and Buffer */
 713         /*      dma_addr_t      PDumpBuffer; */         /* Physical address */
 714         /*#endif */ /* SXG_FAILURE_DUMP */
 715         /*MSI-X related data elements*/
 716         u32 nr_msix_entries;
 717         struct msix_entry *msi_entries;
 718         struct timer_list watchdog_timer;
 719         struct work_struct update_link_status;
 720         u32     link_status_changed;
 721 };
 722
 723 #if SLIC_DUMP_ENABLED
 724 #define SLIC_DUMP_REQUESTED      1
 725 #define SLIC_DUMP_IN_PROGRESS    2
 726 #define SLIC_DUMP_DONE           3
 727
 728 /*
 729  * Microcode crash information structure.  This
 730  * structure is written out to the card's SRAM when the microcode panic's.
 731  */
 732 struct slic_crash_info {
 733     ushort  cpu_id;
 734     ushort  crash_pc;
 735 };
 736
 737 #define CRASH_INFO_OFFSET   0x155C
 738
 739 #endif
 740
 741 #define UPDATE_STATS(largestat, newstat, oldstat)                        \
 742 {                                                                        \
 743     if ((newstat) < (oldstat))                                           \
 744         (largestat) += ((newstat) + (0xFFFFFFFF - oldstat + 1));         \
 745     else                                                                 \
 746         (largestat) += ((newstat) - (oldstat));                          \
 747 }
 748
 749 #define UPDATE_STATS_GB(largestat, newstat, oldstat)                     \
 750 {                                                                        \
 751     (largestat) += ((newstat) - (oldstat));                              \
 752 }
 753
 754 #define ETHER_EQ_ADDR(_AddrA, _AddrB, _Result)                          \
 755 {                                                                       \
 756     _Result = TRUE;                                                     \
 757     if (*(u32 *)(_AddrA) != *(u32 *)(_AddrB))                           \
 758         _Result = FALSE;                                                \
 759     if (*(u16 *)(&((_AddrA)[4])) != *(u16 *)(&((_AddrB)[4])))           \
 760         _Result = FALSE;                                                \
 761 }
 762
 763 #define ETHERMAXFRAME   1514
 764 #define JUMBOMAXFRAME   9014
 765
 766 #define SXG_JUMBO_MTU 9000
 767 #define SXG_DEFAULT_MTU 1500
 768
 769 #if defined(CONFIG_X86_64) || defined(CONFIG_IA64)
 770 #define   SXG_GET_ADDR_LOW(_addr)  (u32)((u64)(_addr) & 0x00000000FFFFFFFF)
 771 #define   SXG_GET_ADDR_HIGH(_addr)                                      \
 772                         (u32)(((u64)(_addr) >> 32) & 0x00000000FFFFFFFF)
 773 #else
 774 #define   SXG_GET_ADDR_LOW(_addr)   (u32)_addr
 775 #define   SXG_GET_ADDR_HIGH(_addr)  (u32)0
 776 #endif
 777
 778 #define FLUSH       TRUE
 779 #define DONT_FLUSH  FALSE
 780
 781 #define SIOCSLICDUMPCARD         (SIOCDEVPRIVATE+9)
 782 #define SIOCSLICSETINTAGG        (SIOCDEVPRIVATE+10)
 783 #define SIOCSLICTRACEDUMP        (SIOCDEVPRIVATE+11)
 784
 785 extern struct ethtool_ops sxg_nic_ethtool_ops;
 786 #define SXG_COMPLETE_SLOW_SEND_LIMIT    128
 787 #endif /*  __SXG_DRIVER_H__ */