1 #ifndef _SPARC64_HYPERVISOR_H
2 #define _SPARC64_HYPERVISOR_H
4 /* Sun4v hypervisor interfaces and defines.
6 * Hypervisor calls are made via traps to software traps number 0x80
7 * and above. Registers %o0 to %o5 serve as argument, status, and
8 * return value registers.
10 * There are two kinds of these traps. First there are the normal
11 * "fast traps" which use software trap 0x80 and encode the function
12 * to invoke by number in register %o5. Argument and return value
13 * handling is as follows:
15 * -----------------------------------------------
16 * | %o5 | function number | undefined |
17 * | %o0 | argument 0 | return status |
18 * | %o1 | argument 1 | return value 1 |
19 * | %o2 | argument 2 | return value 2 |
20 * | %o3 | argument 3 | return value 3 |
21 * | %o4 | argument 4 | return value 4 |
22 * -----------------------------------------------
24 * The second type are "hyper-fast traps" which encode the function
25 * number in the software trap number itself. So these use trap
26 * numbers > 0x80. The register usage for hyper-fast traps is as
29 * -----------------------------------------------
30 * | %o0 | argument 0 | return status |
31 * | %o1 | argument 1 | return value 1 |
32 * | %o2 | argument 2 | return value 2 |
33 * | %o3 | argument 3 | return value 3 |
34 * | %o4 | argument 4 | return value 4 |
35 * -----------------------------------------------
37 * Registers providing explicit arguments to the hypervisor calls
38 * are volatile across the call. Upon return their values are
39 * undefined unless explicitly specified as containing a particular
40 * return value by the specific call. The return status is always
41 * returned in register %o0, zero indicates a successful execution of
42 * the hypervisor call and other values indicate an error status as
43 * defined below. So, for example, if a hyper-fast trap takes
44 * arguments 0, 1, and 2, then %o0, %o1, and %o2 are volatile across
45 * the call and %o3, %o4, and %o5 would be preserved.
47 * If the hypervisor trap is invalid, or the fast trap function number
48 * is invalid, HV_EBADTRAP will be returned in %o0. Also, all 64-bits
49 * of the argument and return values are significant.
53 #define HV_FAST_TRAP 0x80
54 #define HV_MMU_MAP_ADDR_TRAP 0x83
55 #define HV_MMU_UNMAP_ADDR_TRAP 0x84
56 #define HV_TTRACE_ADDENTRY_TRAP 0x85
57 #define HV_CORE_TRAP 0xff
60 #define HV_EOK 0 /* Successful return */
61 #define HV_ENOCPU 1 /* Invalid CPU id */
62 #define HV_ENORADDR 2 /* Invalid real address */
63 #define HV_ENOINTR 3 /* Invalid interrupt id */
64 #define HV_EBADPGSZ 4 /* Invalid pagesize encoding */
65 #define HV_EBADTSB 5 /* Invalid TSB description */
66 #define HV_EINVAL 6 /* Invalid argument */
67 #define HV_EBADTRAP 7 /* Invalid function number */
68 #define HV_EBADALIGN 8 /* Invalid address alignment */
69 #define HV_EWOULDBLOCK 9 /* Cannot complete w/o blocking */
70 #define HV_ENOACCESS 10 /* No access to resource */
71 #define HV_EIO 11 /* I/O error */
72 #define HV_ECPUERROR 12 /* CPU in error state */
73 #define HV_ENOTSUPPORTED 13 /* Function not supported */
74 #define HV_ENOMAP 14 /* No mapping found */
75 #define HV_ETOOMANY 15 /* Too many items specified */
79 * FUNCTION: HV_FAST_MACH_EXIT
81 * ERRORS: This service does not return.
83 * Stop all CPUs in the virtual domain and place them into the stopped
84 * state. The 64-bit exit code may be passed to a service entity as
85 * the domain's exit status. On systems without a service entity, the
86 * domain will undergo a reset, and the boot firmware will be
89 * This function will never return to the guest that invokes it.
91 * Note: By convention an exit code of zero denotes a successful exit by
92 * the guest code. A non-zero exit code denotes a guest specific
96 #define HV_FAST_MACH_EXIT 0x00
98 /* Domain services. */
102 * FUNCTION: HV_FAST_MACH_DESC
107 * ERRORS: HV_EBADALIGN Buffer is badly aligned
108 * HV_ENORADDR Buffer is to an illegal real address.
109 * HV_EINVAL Buffer length is too small for complete
110 * machine description.
112 * Copy the most current machine description into the buffer indicated
113 * by the real address in ARG0. The buffer provided must be 16 byte
114 * aligned. Upon success or HV_EINVAL, this service returns the
115 * actual size of the machine description in the RET1 return value.
117 * Note: A method of determining the appropriate buffer size for the
118 * machine description is to first call this service with a buffer
121 #define HV_FAST_MACH_DESC 0x01
124 extern unsigned long sun4v_mach_desc(unsigned long buffer_pa, unsigned long buf_len,
125 unsigned long *real_buf_len);
130 * FUNCTION: HV_FAST_MACH_SIR
131 * ERRORS: This service does not return.
133 * Perform a software initiated reset of the virtual machine domain.
134 * All CPUs are captured as soon as possible, all hardware devices are
135 * returned to the entry default state, and the domain is restarted at
136 * the SIR (trap type 0x04) real trap table (RTBA) entry point on one
137 * of the CPUs. The single CPU restarted is selected as determined by
138 * platform specific policy. Memory is preserved across this
141 #define HV_FAST_MACH_SIR 0x02
143 /* mach_set_soft_state()
145 * FUNCTION: HV_FAST_MACH_SET_SOFT_STATE
146 * ARG0: software state
147 * ARG1: software state description pointer
149 * ERRORS: EINVAL software state not valid or software state
150 * description is not NULL terminated
151 * ENORADDR software state description pointer is not a
153 * EBADALIGNED software state description is not correctly
156 * This allows the guest to report it's soft state to the hypervisor. There
157 * are two primary components to this state. The first part states whether
158 * the guest software is running or not. The second containts optional
159 * details specific to the software.
161 * The software state argument is defined below in HV_SOFT_STATE_*, and
162 * indicates whether the guest is operating normally or in a transitional
165 * The software state description argument is a real address of a data buffer
166 * of size 32-bytes aligned on a 32-byte boundary. It is treated as a NULL
167 * terminated 7-bit ASCII string of up to 31 characters not including the
170 #define HV_FAST_MACH_SET_SOFT_STATE 0x70
171 #define HV_SOFT_STATE_NORMAL 0x01
172 #define HV_SOFT_STATE_TRANSITION 0x02
175 extern unsigned long sun4v_mach_set_soft_state(unsigned long soft_state,
176 unsigned long msg_string_ra);
179 /* mach_get_soft_state()
181 * FUNCTION: HV_FAST_MACH_GET_SOFT_STATE
182 * ARG0: software state description pointer
184 * RET1: software state
185 * ERRORS: ENORADDR software state description pointer is not a
187 * EBADALIGNED software state description is not correctly
190 * Retrieve the current value of the guest's software state. The rules
191 * for the software state pointer are the same as for mach_set_soft_state()
194 #define HV_FAST_MACH_GET_SOFT_STATE 0x71
198 * CPUs represent devices that can execute software threads. A single
199 * chip that contains multiple cores or strands is represented as
200 * multiple CPUs with unique CPU identifiers. CPUs are exported to
201 * OBP via the machine description (and to the OS via the OBP device
202 * tree). CPUs are always in one of three states: stopped, running,
205 * A CPU ID is a pre-assigned 16-bit value that uniquely identifies a
206 * CPU within a logical domain. Operations that are to be performed
207 * on multiple CPUs specify them via a CPU list. A CPU list is an
208 * array in real memory, of which each 16-bit word is a CPU ID. CPU
209 * lists are passed through the API as two arguments. The first is
210 * the number of entries (16-bit words) in the CPU list, and the
211 * second is the (real address) pointer to the CPU ID list.
216 * FUNCTION: HV_FAST_CPU_START
222 * ERRORS: ENOCPU Invalid CPU ID
223 * EINVAL Target CPU ID is not in the stopped state
224 * ENORADDR Invalid PC or RTBA real address
225 * EBADALIGN Unaligned PC or unaligned RTBA
226 * EWOULDBLOCK Starting resources are not available
228 * Start CPU with given CPU ID with PC in %pc and with a real trap
229 * base address value of RTBA. The indicated CPU must be in the
230 * stopped state. The supplied RTBA must be aligned on a 256 byte
231 * boundary. On successful completion, the specified CPU will be in
232 * the running state and will be supplied with "target ARG0" in %o0
235 #define HV_FAST_CPU_START 0x10
239 * FUNCTION: HV_FAST_CPU_STOP
242 * ERRORS: ENOCPU Invalid CPU ID
243 * EINVAL Target CPU ID is the current cpu
244 * EINVAL Target CPU ID is not in the running state
245 * EWOULDBLOCK Stopping resources are not available
246 * ENOTSUPPORTED Not supported on this platform
248 * The specified CPU is stopped. The indicated CPU must be in the
249 * running state. On completion, it will be in the stopped state. It
250 * is not legal to stop the current CPU.
252 * Note: As this service cannot be used to stop the current cpu, this service
253 * may not be used to stop the last running CPU in a domain. To stop
254 * and exit a running domain, a guest must use the mach_exit() service.
256 #define HV_FAST_CPU_STOP 0x11
260 * FUNCTION: HV_FAST_CPU_YIELD
262 * ERRORS: No possible error.
264 * Suspend execution on the current CPU. Execution will resume when
265 * an interrupt (device, %stick_compare, or cross-call) is targeted to
266 * the CPU. On some CPUs, this API may be used by the hypervisor to
267 * save power by disabling hardware strands.
269 #define HV_FAST_CPU_YIELD 0x12
272 extern unsigned long sun4v_cpu_yield(void);
277 * FUNCTION: HV_FAST_CPU_QCONF
279 * ARG1: base real address
280 * ARG2: number of entries
282 * ERRORS: ENORADDR Invalid base real address
283 * EINVAL Invalid queue or number of entries is less
284 * than 2 or too large.
285 * EBADALIGN Base real address is not correctly aligned
288 * Configure the given queue to be placed at the given base real
289 * address, with the given number of entries. The number of entries
290 * must be a power of 2. The base real address must be aligned
291 * exactly to match the queue size. Each queue entry is 64 bytes
292 * long, so for example a 32 entry queue must be aligned on a 2048
293 * byte real address boundary.
295 * The specified queue is unconfigured if the number of entries is given
298 * For the current version of this API service, the argument queue is defined
302 * ----- -------------------------
303 * 0x3c cpu mondo queue
304 * 0x3d device mondo queue
305 * 0x3e resumable error queue
306 * 0x3f non-resumable error queue
308 * Note: The maximum number of entries for each queue for a specific cpu may
309 * be determined from the machine description.
311 #define HV_FAST_CPU_QCONF 0x14
312 #define HV_CPU_QUEUE_CPU_MONDO 0x3c
313 #define HV_CPU_QUEUE_DEVICE_MONDO 0x3d
314 #define HV_CPU_QUEUE_RES_ERROR 0x3e
315 #define HV_CPU_QUEUE_NONRES_ERROR 0x3f
318 extern unsigned long sun4v_cpu_qconf(unsigned long type,
319 unsigned long queue_paddr,
320 unsigned long num_queue_entries);
325 * FUNCTION: HV_FAST_CPU_QINFO
328 * RET1: base real address
329 * RET1: number of entries
330 * ERRORS: EINVAL Invalid queue
332 * Return the configuration info for the given queue. The base real
333 * address and number of entries of the defined queue are returned.
334 * The queue argument values are the same as for cpu_qconf() above.
336 * If the specified queue is a valid queue number, but no queue has
337 * been defined, the number of entries will be set to zero and the
338 * base real address returned is undefined.
340 #define HV_FAST_CPU_QINFO 0x15
344 * FUNCTION: HV_FAST_CPU_MONDO_SEND
346 * ARG2: data real address
348 * ERRORS: EBADALIGN Mondo data is not 64-byte aligned or CPU list
349 * is not 2-byte aligned.
350 * ENORADDR Invalid data mondo address, or invalid cpu list
352 * ENOCPU Invalid cpu in CPU list
353 * EWOULDBLOCK Some or all of the listed CPUs did not receive
355 * ECPUERROR One or more of the listed CPUs are in error
356 * state, use HV_FAST_CPU_STATE to see which ones
357 * EINVAL CPU list includes caller's CPU ID
359 * Send a mondo interrupt to the CPUs in the given CPU list with the
360 * 64-bytes at the given data real address. The data must be 64-byte
361 * aligned. The mondo data will be delivered to the cpu_mondo queues
362 * of the recipient CPUs.
364 * In all cases, error or not, the CPUs in the CPU list to which the
365 * mondo has been successfully delivered will be indicated by having
366 * their entry in CPU list updated with the value 0xffff.
368 #define HV_FAST_CPU_MONDO_SEND 0x42
371 extern unsigned long sun4v_cpu_mondo_send(unsigned long cpu_count, unsigned long cpu_list_pa, unsigned long mondo_block_pa);
376 * FUNCTION: HV_FAST_CPU_MYID
379 * ERRORS: No errors defined.
381 * Return the hypervisor ID handle for the current CPU. Use by a
382 * virtual CPU to discover it's own identity.
384 #define HV_FAST_CPU_MYID 0x16
388 * FUNCTION: HV_FAST_CPU_STATE
392 * ERRORS: ENOCPU Invalid CPU ID
394 * Retrieve the current state of the CPU with the given CPU ID.
396 #define HV_FAST_CPU_STATE 0x17
397 #define HV_CPU_STATE_STOPPED 0x01
398 #define HV_CPU_STATE_RUNNING 0x02
399 #define HV_CPU_STATE_ERROR 0x03
402 extern long sun4v_cpu_state(unsigned long cpuid);
407 * FUNCTION: HV_FAST_CPU_SET_RTBA
410 * RET1: previous RTBA
411 * ERRORS: ENORADDR Invalid RTBA real address
412 * EBADALIGN RTBA is incorrectly aligned for a trap table
414 * Set the real trap base address of the local cpu to the given RTBA.
415 * The supplied RTBA must be aligned on a 256 byte boundary. Upon
416 * success the previous value of the RTBA is returned in RET1.
418 * Note: This service does not affect %tba
420 #define HV_FAST_CPU_SET_RTBA 0x18
424 * FUNCTION: HV_FAST_CPU_GET_RTBA
426 * RET1: previous RTBA
427 * ERRORS: No possible error.
429 * Returns the current value of RTBA in RET1.
431 #define HV_FAST_CPU_GET_RTBA 0x19
435 * Layout of a TSB description for mmu_tsb_ctx{,non}0() calls.
438 struct hv_tsb_descr {
439 unsigned short pgsz_idx;
440 unsigned short assoc;
441 unsigned int num_ttes; /* in TTEs */
442 unsigned int ctx_idx;
443 unsigned int pgsz_mask;
444 unsigned long tsb_base;
448 #define HV_TSB_DESCR_PGSZ_IDX_OFFSET 0x00
449 #define HV_TSB_DESCR_ASSOC_OFFSET 0x02
450 #define HV_TSB_DESCR_NUM_TTES_OFFSET 0x04
451 #define HV_TSB_DESCR_CTX_IDX_OFFSET 0x08
452 #define HV_TSB_DESCR_PGSZ_MASK_OFFSET 0x0c
453 #define HV_TSB_DESCR_TSB_BASE_OFFSET 0x10
454 #define HV_TSB_DESCR_RESV_OFFSET 0x18
456 /* Page size bitmask. */
457 #define HV_PGSZ_MASK_8K (1 << 0)
458 #define HV_PGSZ_MASK_64K (1 << 1)
459 #define HV_PGSZ_MASK_512K (1 << 2)
460 #define HV_PGSZ_MASK_4MB (1 << 3)
461 #define HV_PGSZ_MASK_32MB (1 << 4)
462 #define HV_PGSZ_MASK_256MB (1 << 5)
463 #define HV_PGSZ_MASK_2GB (1 << 6)
464 #define HV_PGSZ_MASK_16GB (1 << 7)
466 /* Page size index. The value given in the TSB descriptor must correspond
467 * to the smallest page size specified in the pgsz_mask page size bitmask.
469 #define HV_PGSZ_IDX_8K 0
470 #define HV_PGSZ_IDX_64K 1
471 #define HV_PGSZ_IDX_512K 2
472 #define HV_PGSZ_IDX_4MB 3
473 #define HV_PGSZ_IDX_32MB 4
474 #define HV_PGSZ_IDX_256MB 5
475 #define HV_PGSZ_IDX_2GB 6
476 #define HV_PGSZ_IDX_16GB 7
478 /* MMU fault status area.
480 * MMU related faults have their status and fault address information
481 * placed into a memory region made available by privileged code. Each
482 * virtual processor must make a mmu_fault_area_conf() call to tell the
483 * hypervisor where that processor's fault status should be stored.
485 * The fault status block is a multiple of 64-bytes and must be aligned
486 * on a 64-byte boundary.
489 struct hv_fault_status {
490 unsigned long i_fault_type;
491 unsigned long i_fault_addr;
492 unsigned long i_fault_ctx;
493 unsigned long i_reserved[5];
494 unsigned long d_fault_type;
495 unsigned long d_fault_addr;
496 unsigned long d_fault_ctx;
497 unsigned long d_reserved[5];
500 #define HV_FAULT_I_TYPE_OFFSET 0x00
501 #define HV_FAULT_I_ADDR_OFFSET 0x08
502 #define HV_FAULT_I_CTX_OFFSET 0x10
503 #define HV_FAULT_D_TYPE_OFFSET 0x40
504 #define HV_FAULT_D_ADDR_OFFSET 0x48
505 #define HV_FAULT_D_CTX_OFFSET 0x50
507 #define HV_FAULT_TYPE_FAST_MISS 1
508 #define HV_FAULT_TYPE_FAST_PROT 2
509 #define HV_FAULT_TYPE_MMU_MISS 3
510 #define HV_FAULT_TYPE_INV_RA 4
511 #define HV_FAULT_TYPE_PRIV_VIOL 5
512 #define HV_FAULT_TYPE_PROT_VIOL 6
513 #define HV_FAULT_TYPE_NFO 7
514 #define HV_FAULT_TYPE_NFO_SEFF 8
515 #define HV_FAULT_TYPE_INV_VA 9
516 #define HV_FAULT_TYPE_INV_ASI 10
517 #define HV_FAULT_TYPE_NC_ATOMIC 11
518 #define HV_FAULT_TYPE_PRIV_ACT 12
519 #define HV_FAULT_TYPE_RESV1 13
520 #define HV_FAULT_TYPE_UNALIGNED 14
521 #define HV_FAULT_TYPE_INV_PGSZ 15
522 /* Values 16 --> -2 are reserved. */
523 #define HV_FAULT_TYPE_MULTIPLE -1
525 /* Flags argument for mmu_{map,unmap}_addr(), mmu_demap_{page,context,all}(),
526 * and mmu_{map,unmap}_perm_addr().
528 #define HV_MMU_DMMU 0x01
529 #define HV_MMU_IMMU 0x02
530 #define HV_MMU_ALL (HV_MMU_DMMU | HV_MMU_IMMU)
533 * TRAP: HV_MMU_MAP_ADDR_TRAP
534 * ARG0: virtual address
537 * ARG3: flags (HV_MMU_{IMMU,DMMU})
538 * ERRORS: EINVAL Invalid virtual address, mmu context, or flags
539 * EBADPGSZ Invalid page size value
540 * ENORADDR Invalid real address in TTE
542 * Create a non-permanent mapping using the given TTE, virtual
543 * address, and mmu context. The flags argument determines which
544 * (data, or instruction, or both) TLB the mapping gets loaded into.
546 * The behavior is undefined if the valid bit is clear in the TTE.
548 * Note: This API call is for privileged code to specify temporary translation
549 * mappings without the need to create and manage a TSB.
553 * TRAP: HV_MMU_UNMAP_ADDR_TRAP
554 * ARG0: virtual address
556 * ARG2: flags (HV_MMU_{IMMU,DMMU})
557 * ERRORS: EINVAL Invalid virtual address, mmu context, or flags
559 * Demaps the given virtual address in the given mmu context on this
560 * CPU. This function is intended to be used to demap pages mapped
561 * with mmu_map_addr. This service is equivalent to invoking
562 * mmu_demap_page() with only the current CPU in the CPU list. The
563 * flags argument determines which (data, or instruction, or both) TLB
564 * the mapping gets unmapped from.
566 * Attempting to perform an unmap operation for a previously defined
567 * permanent mapping will have undefined results.
572 * FUNCTION: HV_FAST_MMU_TSB_CTX0
573 * ARG0: number of TSB descriptions
574 * ARG1: TSB descriptions pointer
576 * ERRORS: ENORADDR Invalid TSB descriptions pointer or
577 * TSB base within a descriptor
578 * EBADALIGN TSB descriptions pointer is not aligned
579 * to an 8-byte boundary, or TSB base
580 * within a descriptor is not aligned for
582 * EBADPGSZ Invalid page size in a TSB descriptor
583 * EBADTSB Invalid associativity or size in a TSB
585 * EINVAL Invalid number of TSB descriptions, or
586 * invalid context index in a TSB
587 * descriptor, or index page size not
588 * equal to smallest page size in page
589 * size bitmask field.
591 * Configures the TSBs for the current CPU for virtual addresses with
592 * context zero. The TSB descriptions pointer is a pointer to an
593 * array of the given number of TSB descriptions.
595 * Note: The maximum number of TSBs available to a virtual CPU is given by the
596 * mmu-max-#tsbs property of the cpu's corresponding "cpu" node in the
597 * machine description.
599 #define HV_FAST_MMU_TSB_CTX0 0x20
603 * FUNCTION: HV_FAST_MMU_TSB_CTXNON0
604 * ARG0: number of TSB descriptions
605 * ARG1: TSB descriptions pointer
607 * ERRORS: Same as for mmu_tsb_ctx0() above.
609 * Configures the TSBs for the current CPU for virtual addresses with
610 * non-zero contexts. The TSB descriptions pointer is a pointer to an
611 * array of the given number of TSB descriptions.
613 * Note: A maximum of 16 TSBs may be specified in the TSB description list.
615 #define HV_FAST_MMU_TSB_CTXNON0 0x21
619 * FUNCTION: HV_FAST_MMU_DEMAP_PAGE
620 * ARG0: reserved, must be zero
621 * ARG1: reserved, must be zero
622 * ARG2: virtual address
624 * ARG4: flags (HV_MMU_{IMMU,DMMU})
626 * ERRORS: EINVAL Invalid virutal address, context, or
628 * ENOTSUPPORTED ARG0 or ARG1 is non-zero
630 * Demaps any page mapping of the given virtual address in the given
631 * mmu context for the current virtual CPU. Any virtually tagged
632 * caches are guaranteed to be kept consistent. The flags argument
633 * determines which TLB (instruction, or data, or both) participate in
636 * ARG0 and ARG1 are both reserved and must be set to zero.
638 #define HV_FAST_MMU_DEMAP_PAGE 0x22
642 * FUNCTION: HV_FAST_MMU_DEMAP_CTX
643 * ARG0: reserved, must be zero
644 * ARG1: reserved, must be zero
646 * ARG3: flags (HV_MMU_{IMMU,DMMU})
648 * ERRORS: EINVAL Invalid context or flags value
649 * ENOTSUPPORTED ARG0 or ARG1 is non-zero
651 * Demaps all non-permanent virtual page mappings previously specified
652 * for the given context for the current virtual CPU. Any virtual
653 * tagged caches are guaranteed to be kept consistent. The flags
654 * argument determines which TLB (instruction, or data, or both)
655 * participate in the operation.
657 * ARG0 and ARG1 are both reserved and must be set to zero.
659 #define HV_FAST_MMU_DEMAP_CTX 0x23
663 * FUNCTION: HV_FAST_MMU_DEMAP_ALL
664 * ARG0: reserved, must be zero
665 * ARG1: reserved, must be zero
666 * ARG2: flags (HV_MMU_{IMMU,DMMU})
668 * ERRORS: EINVAL Invalid flags value
669 * ENOTSUPPORTED ARG0 or ARG1 is non-zero
671 * Demaps all non-permanent virtual page mappings previously specified
672 * for the current virtual CPU. Any virtual tagged caches are
673 * guaranteed to be kept consistent. The flags argument determines
674 * which TLB (instruction, or data, or both) participate in the
677 * ARG0 and ARG1 are both reserved and must be set to zero.
679 #define HV_FAST_MMU_DEMAP_ALL 0x24
681 /* mmu_map_perm_addr()
683 * FUNCTION: HV_FAST_MMU_MAP_PERM_ADDR
684 * ARG0: virtual address
685 * ARG1: reserved, must be zero
687 * ARG3: flags (HV_MMU_{IMMU,DMMU})
689 * ERRORS: EINVAL Invalid virutal address or flags value
690 * EBADPGSZ Invalid page size value
691 * ENORADDR Invalid real address in TTE
692 * ETOOMANY Too many mappings (max of 8 reached)
694 * Create a permanent mapping using the given TTE and virtual address
695 * for context 0 on the calling virtual CPU. A maximum of 8 such
696 * permanent mappings may be specified by privileged code. Mappings
697 * may be removed with mmu_unmap_perm_addr().
699 * The behavior is undefined if a TTE with the valid bit clear is given.
701 * Note: This call is used to specify address space mappings for which
702 * privileged code does not expect to receive misses. For example,
703 * this mechanism can be used to map kernel nucleus code and data.
705 #define HV_FAST_MMU_MAP_PERM_ADDR 0x25
707 /* mmu_fault_area_conf()
709 * FUNCTION: HV_FAST_MMU_FAULT_AREA_CONF
712 * RET1: previous mmu fault area real address
713 * ERRORS: ENORADDR Invalid real address
714 * EBADALIGN Invalid alignment for fault area
716 * Configure the MMU fault status area for the calling CPU. A 64-byte
717 * aligned real address specifies where MMU fault status information
718 * is placed. The return value is the previously specified area, or 0
719 * for the first invocation. Specifying a fault area at real address
722 #define HV_FAST_MMU_FAULT_AREA_CONF 0x26
726 * FUNCTION: HV_FAST_MMU_ENABLE
728 * ARG1: return target address
730 * ERRORS: ENORADDR Invalid real address when disabling
732 * EBADALIGN The return target address is not
733 * aligned to an instruction.
734 * EINVAL The enable flag request the current
735 * operating mode (e.g. disable if already
738 * Enable or disable virtual address translation for the calling CPU
739 * within the virtual machine domain. If the enable flag is zero,
740 * translation is disabled, any non-zero value will enable
743 * When this function returns, the newly selected translation mode
744 * will be active. If the mmu is being enabled, then the return
745 * target address is a virtual address else it is a real address.
747 * Upon successful completion, control will be returned to the given
748 * return target address (ie. the cpu will jump to that address). On
749 * failure, the previous mmu mode remains and the trap simply returns
750 * as normal with the appropriate error code in RET0.
752 #define HV_FAST_MMU_ENABLE 0x27
754 /* mmu_unmap_perm_addr()
756 * FUNCTION: HV_FAST_MMU_UNMAP_PERM_ADDR
757 * ARG0: virtual address
758 * ARG1: reserved, must be zero
759 * ARG2: flags (HV_MMU_{IMMU,DMMU})
761 * ERRORS: EINVAL Invalid virutal address or flags value
762 * ENOMAP Specified mapping was not found
764 * Demaps any permanent page mapping (established via
765 * mmu_map_perm_addr()) at the given virtual address for context 0 on
766 * the current virtual CPU. Any virtual tagged caches are guaranteed
767 * to be kept consistent.
769 #define HV_FAST_MMU_UNMAP_PERM_ADDR 0x28
771 /* mmu_tsb_ctx0_info()
773 * FUNCTION: HV_FAST_MMU_TSB_CTX0_INFO
775 * ARG1: buffer pointer
777 * RET1: number of TSBs
778 * ERRORS: EINVAL Supplied buffer is too small
779 * EBADALIGN The buffer pointer is badly aligned
780 * ENORADDR Invalid real address for buffer pointer
782 * Return the TSB configuration as previous defined by mmu_tsb_ctx0()
783 * into the provided buffer. The size of the buffer is given in ARG1
784 * in terms of the number of TSB description entries.
786 * Upon return, RET1 always contains the number of TSB descriptions
787 * previously configured. If zero TSBs were configured, EOK is
788 * returned with RET1 containing 0.
790 #define HV_FAST_MMU_TSB_CTX0_INFO 0x29
792 /* mmu_tsb_ctxnon0_info()
794 * FUNCTION: HV_FAST_MMU_TSB_CTXNON0_INFO
796 * ARG1: buffer pointer
798 * RET1: number of TSBs
799 * ERRORS: EINVAL Supplied buffer is too small
800 * EBADALIGN The buffer pointer is badly aligned
801 * ENORADDR Invalid real address for buffer pointer
803 * Return the TSB configuration as previous defined by
804 * mmu_tsb_ctxnon0() into the provided buffer. The size of the buffer
805 * is given in ARG1 in terms of the number of TSB description entries.
807 * Upon return, RET1 always contains the number of TSB descriptions
808 * previously configured. If zero TSBs were configured, EOK is
809 * returned with RET1 containing 0.
811 #define HV_FAST_MMU_TSB_CTXNON0_INFO 0x2a
813 /* mmu_fault_area_info()
815 * FUNCTION: HV_FAST_MMU_FAULT_AREA_INFO
817 * RET1: fault area real address
818 * ERRORS: No errors defined.
820 * Return the currently defined MMU fault status area for the current
821 * CPU. The real address of the fault status area is returned in
822 * RET1, or 0 is returned in RET1 if no fault status area is defined.
824 * Note: mmu_fault_area_conf() may be called with the return value (RET1)
825 * from this service if there is a need to save and restore the fault
828 #define HV_FAST_MMU_FAULT_AREA_INFO 0x2b
830 /* Cache and Memory services. */
834 * FUNCTION: HV_FAST_MEM_SCRUB
838 * RET1: length scrubbed
839 * ERRORS: ENORADDR Invalid real address
840 * EBADALIGN Start address or length are not correctly
842 * EINVAL Length is zero
844 * Zero the memory contents in the range real address to real address
845 * plus length minus 1. Also, valid ECC will be generated for that
846 * memory address range. Scrubbing is started at the given real
847 * address, but may not scrub the entire given length. The actual
848 * length scrubbed will be returned in RET1.
850 * The real address and length must be aligned on an 8K boundary, or
851 * contain the start address and length from a sun4v error report.
853 * Note: There are two uses for this function. The first use is to block clear
854 * and initialize memory and the second is to scrub an u ncorrectable
855 * error reported via a resumable or non-resumable trap. The second
856 * use requires the arguments to be equal to the real address and length
857 * provided in a sun4v memory error report.
859 #define HV_FAST_MEM_SCRUB 0x31
863 * FUNCTION: HV_FAST_MEM_SYNC
867 * RET1: length synced
868 * ERRORS: ENORADDR Invalid real address
869 * EBADALIGN Start address or length are not correctly
871 * EINVAL Length is zero
873 * Force the next access within the real address to real address plus
874 * length minus 1 to be fetches from main system memory. Less than
875 * the given length may be synced, the actual amount synced is
876 * returned in RET1. The real address and length must be aligned on
879 #define HV_FAST_MEM_SYNC 0x32
881 /* Time of day services.
883 * The hypervisor maintains the time of day on a per-domain basis.
884 * Changing the time of day in one domain does not affect the time of
885 * day on any other domain.
887 * Time is described by a single unsigned 64-bit word which is the
888 * number of seconds since the UNIX Epoch (00:00:00 UTC, January 1,
894 * FUNCTION: HV_FAST_TOD_GET
897 * ERRORS: EWOULDBLOCK TOD resource is temporarily unavailable
898 * ENOTSUPPORTED If TOD not supported on this platform
900 * Return the current time of day. May block if TOD access is
901 * temporarily not possible.
903 #define HV_FAST_TOD_GET 0x50
907 * FUNCTION: HV_FAST_TOD_SET
910 * ERRORS: EWOULDBLOCK TOD resource is temporarily unavailable
911 * ENOTSUPPORTED If TOD not supported on this platform
913 * The current time of day is set to the value specified in ARG0. May
914 * block if TOD access is temporarily not possible.
916 #define HV_FAST_TOD_SET 0x51
918 /* Console services */
922 * FUNCTION: HV_FAST_CONS_GETCHAR
925 * ERRORS: EWOULDBLOCK No character available.
927 * Returns a character from the console device. If no character is
928 * available then an EWOULDBLOCK error is returned. If a character is
929 * available, then the returned status is EOK and the character value
932 * A virtual BREAK is represented by the 64-bit value -1.
934 * A virtual HUP signal is represented by the 64-bit value -2.
936 #define HV_FAST_CONS_GETCHAR 0x60
940 * FUNCTION: HV_FAST_CONS_PUTCHAR
943 * ERRORS: EINVAL Illegal character
944 * EWOULDBLOCK Output buffer currently full, would block
946 * Send a character to the console device. Only character values
947 * between 0 and 255 may be used. Values outside this range are
948 * invalid except for the 64-bit value -1 which is used to send a
951 #define HV_FAST_CONS_PUTCHAR 0x61
955 * FUNCTION: HV_FAST_CONS_READ
956 * ARG0: buffer real address
957 * ARG1: buffer size in bytes
959 * RET1: bytes read or BREAK or HUP
960 * ERRORS: EWOULDBLOCK No character available.
962 * Reads characters into a buffer from the console device. If no
963 * character is available then an EWOULDBLOCK error is returned.
964 * If a character is available, then the returned status is EOK
965 * and the number of bytes read into the given buffer is provided
968 * A virtual BREAK is represented by the 64-bit RET1 value -1.
970 * A virtual HUP signal is represented by the 64-bit RET1 value -2.
972 * If BREAK or HUP are indicated, no bytes were read into buffer.
974 #define HV_FAST_CONS_READ 0x62
978 * FUNCTION: HV_FAST_CONS_WRITE
979 * ARG0: buffer real address
980 * ARG1: buffer size in bytes
982 * RET1: bytes written
983 * ERRORS: EWOULDBLOCK Output buffer currently full, would block
985 * Send a characters in buffer to the console device. Breaks must be
986 * sent using con_putchar().
988 #define HV_FAST_CONS_WRITE 0x63
991 extern long sun4v_con_getchar(long *status);
992 extern long sun4v_con_putchar(long c);
993 extern long sun4v_con_read(unsigned long buffer,
995 unsigned long *bytes_read);
996 extern unsigned long sun4v_con_write(unsigned long buffer,
998 unsigned long *bytes_written);
1001 /* Trap trace services.
1003 * The hypervisor provides a trap tracing capability for privileged
1004 * code running on each virtual CPU. Privileged code provides a
1005 * round-robin trap trace queue within which the hypervisor writes
1006 * 64-byte entries detailing hyperprivileged traps taken n behalf of
1007 * privileged code. This is provided as a debugging capability for
1010 * The trap trace control structure is 64-bytes long and placed at the
1011 * start (offset 0) of the trap trace buffer, and is described as
1014 #ifndef __ASSEMBLY__
1015 struct hv_trap_trace_control {
1016 unsigned long head_offset;
1017 unsigned long tail_offset;
1018 unsigned long __reserved[0x30 / sizeof(unsigned long)];
1021 #define HV_TRAP_TRACE_CTRL_HEAD_OFFSET 0x00
1022 #define HV_TRAP_TRACE_CTRL_TAIL_OFFSET 0x08
1024 /* The head offset is the offset of the most recently completed entry
1025 * in the trap-trace buffer. The tail offset is the offset of the
1026 * next entry to be written. The control structure is owned and
1027 * modified by the hypervisor. A guest may not modify the control
1028 * structure contents. Attempts to do so will result in undefined
1029 * behavior for the guest.
1031 * Each trap trace buffer entry is layed out as follows:
1033 #ifndef __ASSEMBLY__
1034 struct hv_trap_trace_entry {
1035 unsigned char type; /* Hypervisor or guest entry? */
1036 unsigned char hpstate; /* Hyper-privileged state */
1037 unsigned char tl; /* Trap level */
1038 unsigned char gl; /* Global register level */
1039 unsigned short tt; /* Trap type */
1040 unsigned short tag; /* Extended trap identifier */
1041 unsigned long tstate; /* Trap state */
1042 unsigned long tick; /* Tick */
1043 unsigned long tpc; /* Trap PC */
1044 unsigned long f1; /* Entry specific */
1045 unsigned long f2; /* Entry specific */
1046 unsigned long f3; /* Entry specific */
1047 unsigned long f4; /* Entry specific */
1050 #define HV_TRAP_TRACE_ENTRY_TYPE 0x00
1051 #define HV_TRAP_TRACE_ENTRY_HPSTATE 0x01
1052 #define HV_TRAP_TRACE_ENTRY_TL 0x02
1053 #define HV_TRAP_TRACE_ENTRY_GL 0x03
1054 #define HV_TRAP_TRACE_ENTRY_TT 0x04
1055 #define HV_TRAP_TRACE_ENTRY_TAG 0x06
1056 #define HV_TRAP_TRACE_ENTRY_TSTATE 0x08
1057 #define HV_TRAP_TRACE_ENTRY_TICK 0x10
1058 #define HV_TRAP_TRACE_ENTRY_TPC 0x18
1059 #define HV_TRAP_TRACE_ENTRY_F1 0x20
1060 #define HV_TRAP_TRACE_ENTRY_F2 0x28
1061 #define HV_TRAP_TRACE_ENTRY_F3 0x30
1062 #define HV_TRAP_TRACE_ENTRY_F4 0x38
1064 /* The type field is encoded as follows. */
1065 #define HV_TRAP_TYPE_UNDEF 0x00 /* Entry content undefined */
1066 #define HV_TRAP_TYPE_HV 0x01 /* Hypervisor trap entry */
1067 #define HV_TRAP_TYPE_GUEST 0xff /* Added via ttrace_addentry() */
1069 /* ttrace_buf_conf()
1070 * TRAP: HV_FAST_TRAP
1071 * FUNCTION: HV_FAST_TTRACE_BUF_CONF
1072 * ARG0: real address
1073 * ARG1: number of entries
1075 * RET1: number of entries
1076 * ERRORS: ENORADDR Invalid real address
1077 * EINVAL Size is too small
1078 * EBADALIGN Real address not aligned on 64-byte boundary
1080 * Requests hypervisor trap tracing and declares a virtual CPU's trap
1081 * trace buffer to the hypervisor. The real address supplies the real
1082 * base address of the trap trace queue and must be 64-byte aligned.
1083 * Specifying a value of 0 for the number of entries disables trap
1084 * tracing for the calling virtual CPU. The buffer allocated must be
1085 * sized for a power of two number of 64-byte trap trace entries plus
1086 * an initial 64-byte control structure.
1088 * This may be invoked any number of times so that a virtual CPU may
1089 * relocate a trap trace buffer or create "snapshots" of information.
1091 * If the real address is illegal or badly aligned, then trap tracing
1092 * is disabled and an error is returned.
1094 * Upon failure with EINVAL, this service call returns in RET1 the
1095 * minimum number of buffer entries required. Upon other failures
1096 * RET1 is undefined.
1098 #define HV_FAST_TTRACE_BUF_CONF 0x90
1100 /* ttrace_buf_info()
1101 * TRAP: HV_FAST_TRAP
1102 * FUNCTION: HV_FAST_TTRACE_BUF_INFO
1104 * RET1: real address
1106 * ERRORS: None defined.
1108 * Returns the size and location of the previously declared trap-trace
1109 * buffer. In the event that no buffer was previously defined, or the
1110 * buffer is disabled, this call will return a size of zero bytes.
1112 #define HV_FAST_TTRACE_BUF_INFO 0x91
1115 * TRAP: HV_FAST_TRAP
1116 * FUNCTION: HV_FAST_TTRACE_ENABLE
1119 * RET1: previous enable state
1120 * ERRORS: EINVAL No trap trace buffer currently defined
1122 * Enable or disable trap tracing, and return the previous enabled
1123 * state in RET1. Future systems may define various flags for the
1124 * enable argument (ARG0), for the moment a guest should pass
1125 * "(uint64_t) -1" to enable, and "(uint64_t) 0" to disable all
1126 * tracing - which will ensure future compatability.
1128 #define HV_FAST_TTRACE_ENABLE 0x92
1131 * TRAP: HV_FAST_TRAP
1132 * FUNCTION: HV_FAST_TTRACE_FREEZE
1135 * RET1: previous freeze state
1136 * ERRORS: EINVAL No trap trace buffer currently defined
1138 * Freeze or unfreeze trap tracing, returning the previous freeze
1139 * state in RET1. A guest should pass a non-zero value to freeze and
1140 * a zero value to unfreeze all tracing. The returned previous state
1141 * is 0 for not frozen and 1 for frozen.
1143 #define HV_FAST_TTRACE_FREEZE 0x93
1145 /* ttrace_addentry()
1146 * TRAP: HV_TTRACE_ADDENTRY_TRAP
1147 * ARG0: tag (16-bits)
1153 * ERRORS: EINVAL No trap trace buffer currently defined
1155 * Add an entry to the trap trace buffer. Upon return only ARG0/RET0
1156 * is modified - none of the other registers holding arguments are
1157 * volatile across this hypervisor service.
1160 /* Core dump services.
1162 * Since the hypervisor viraulizes and thus obscures a lot of the
1163 * physical machine layout and state, traditional OS crash dumps can
1164 * be difficult to diagnose especially when the problem is a
1165 * configuration error of some sort.
1167 * The dump services provide an opaque buffer into which the
1168 * hypervisor can place it's internal state in order to assist in
1169 * debugging such situations. The contents are opaque and extremely
1170 * platform and hypervisor implementation specific. The guest, during
1171 * a core dump, requests that the hypervisor update any information in
1172 * the dump buffer in preparation to being dumped as part of the
1173 * domain's memory image.
1176 /* dump_buf_update()
1177 * TRAP: HV_FAST_TRAP
1178 * FUNCTION: HV_FAST_DUMP_BUF_UPDATE
1179 * ARG0: real address
1182 * RET1: required size of dump buffer
1183 * ERRORS: ENORADDR Invalid real address
1184 * EBADALIGN Real address is not aligned on a 64-byte
1186 * EINVAL Size is non-zero but less than minimum size
1188 * ENOTSUPPORTED Operation not supported on current logical
1191 * Declare a domain dump buffer to the hypervisor. The real address
1192 * provided for the domain dump buffer must be 64-byte aligned. The
1193 * size specifies the size of the dump buffer and may be larger than
1194 * the minimum size specified in the machine description. The
1195 * hypervisor will fill the dump buffer with opaque data.
1197 * Note: A guest may elect to include dump buffer contents as part of a crash
1198 * dump to assist with debugging. This function may be called any number
1199 * of times so that a guest may relocate a dump buffer, or create
1200 * "snapshots" of any dump-buffer information. Each call to
1201 * dump_buf_update() atomically declares the new dump buffer to the
1204 * A specified size of 0 unconfigures the dump buffer. If the real
1205 * address is illegal or badly aligned, then any currently active dump
1206 * buffer is disabled and an error is returned.
1208 * In the event that the call fails with EINVAL, RET1 contains the
1209 * minimum size requires by the hypervisor for a valid dump buffer.
1211 #define HV_FAST_DUMP_BUF_UPDATE 0x94
1214 * TRAP: HV_FAST_TRAP
1215 * FUNCTION: HV_FAST_DUMP_BUF_INFO
1217 * RET1: real address of current dump buffer
1218 * RET2: size of current dump buffer
1219 * ERRORS: No errors defined.
1221 * Return the currently configures dump buffer description. A
1222 * returned size of 0 bytes indicates an undefined dump buffer. In
1223 * this case the return address in RET1 is undefined.
1225 #define HV_FAST_DUMP_BUF_INFO 0x95
1227 /* Device interrupt services.
1229 * Device interrupts are allocated to system bus bridges by the hypervisor,
1230 * and described to OBP in the machine description. OBP then describes
1231 * these interrupts to the OS via properties in the device tree.
1235 * cpuid Unique opaque value which represents a target cpu.
1237 * devhandle Device handle. It uniquely identifies a device, and
1238 * consistes of the lower 28-bits of the hi-cell of the
1239 * first entry of the device's "reg" property in the
1242 * devino Device interrupt number. Specifies the relative
1243 * interrupt number within the device. The unique
1244 * combination of devhandle and devino are used to
1245 * identify a specific device interrupt.
1247 * Note: The devino value is the same as the values in the
1248 * "interrupts" property or "interrupt-map" property
1249 * in the OBP device tree for that device.
1251 * sysino System interrupt number. A 64-bit unsigned interger
1252 * representing a unique interrupt within a virtual
1255 * intr_state A flag representing the interrupt state for a given
1256 * sysino. The state values are defined below.
1258 * intr_enabled A flag representing the 'enabled' state for a given
1259 * sysino. The enable values are defined below.
1262 #define HV_INTR_STATE_IDLE 0 /* Nothing pending */
1263 #define HV_INTR_STATE_RECEIVED 1 /* Interrupt received by hardware */
1264 #define HV_INTR_STATE_DELIVERED 2 /* Interrupt delivered to queue */
1266 #define HV_INTR_DISABLED 0 /* sysino not enabled */
1267 #define HV_INTR_ENABLED 1 /* sysino enabled */
1269 /* intr_devino_to_sysino()
1270 * TRAP: HV_FAST_TRAP
1271 * FUNCTION: HV_FAST_INTR_DEVINO2SYSINO
1276 * ERRORS: EINVAL Invalid devhandle/devino
1278 * Converts a device specific interrupt number of the given
1279 * devhandle/devino into a system specific ino (sysino).
1281 #define HV_FAST_INTR_DEVINO2SYSINO 0xa0
1283 #ifndef __ASSEMBLY__
1284 extern unsigned long sun4v_devino_to_sysino(unsigned long devhandle,
1285 unsigned long devino);
1288 /* intr_getenabled()
1289 * TRAP: HV_FAST_TRAP
1290 * FUNCTION: HV_FAST_INTR_GETENABLED
1293 * RET1: intr_enabled (HV_INTR_{DISABLED,ENABLED})
1294 * ERRORS: EINVAL Invalid sysino
1296 * Returns interrupt enabled state in RET1 for the interrupt defined
1297 * by the given sysino.
1299 #define HV_FAST_INTR_GETENABLED 0xa1
1301 #ifndef __ASSEMBLY__
1302 extern unsigned long sun4v_intr_getenabled(unsigned long sysino);
1305 /* intr_setenabled()
1306 * TRAP: HV_FAST_TRAP
1307 * FUNCTION: HV_FAST_INTR_SETENABLED
1309 * ARG1: intr_enabled (HV_INTR_{DISABLED,ENABLED})
1311 * ERRORS: EINVAL Invalid sysino or intr_enabled value
1313 * Set the 'enabled' state of the interrupt sysino.
1315 #define HV_FAST_INTR_SETENABLED 0xa2
1317 #ifndef __ASSEMBLY__
1318 extern unsigned long sun4v_intr_setenabled(unsigned long sysino, unsigned long intr_enabled);
1322 * TRAP: HV_FAST_TRAP
1323 * FUNCTION: HV_FAST_INTR_GETSTATE
1326 * RET1: intr_state (HV_INTR_STATE_*)
1327 * ERRORS: EINVAL Invalid sysino
1329 * Returns current state of the interrupt defined by the given sysino.
1331 #define HV_FAST_INTR_GETSTATE 0xa3
1333 #ifndef __ASSEMBLY__
1334 extern unsigned long sun4v_intr_getstate(unsigned long sysino);
1338 * TRAP: HV_FAST_TRAP
1339 * FUNCTION: HV_FAST_INTR_SETSTATE
1341 * ARG1: intr_state (HV_INTR_STATE_*)
1343 * ERRORS: EINVAL Invalid sysino or intr_state value
1345 * Sets the current state of the interrupt described by the given sysino
1348 * Note: Setting the state to HV_INTR_STATE_IDLE clears any pending
1349 * interrupt for sysino.
1351 #define HV_FAST_INTR_SETSTATE 0xa4
1353 #ifndef __ASSEMBLY__
1354 extern unsigned long sun4v_intr_setstate(unsigned long sysino, unsigned long intr_state);
1358 * TRAP: HV_FAST_TRAP
1359 * FUNCTION: HV_FAST_INTR_GETTARGET
1363 * ERRORS: EINVAL Invalid sysino
1365 * Returns CPU that is the current target of the interrupt defined by
1366 * the given sysino. The CPU value returned is undefined if the target
1367 * has not been set via intr_settarget().
1369 #define HV_FAST_INTR_GETTARGET 0xa5
1371 #ifndef __ASSEMBLY__
1372 extern unsigned long sun4v_intr_gettarget(unsigned long sysino);
1376 * TRAP: HV_FAST_TRAP
1377 * FUNCTION: HV_FAST_INTR_SETTARGET
1381 * ERRORS: EINVAL Invalid sysino
1382 * ENOCPU Invalid cpuid
1384 * Set the target CPU for the interrupt defined by the given sysino.
1386 #define HV_FAST_INTR_SETTARGET 0xa6
1388 #ifndef __ASSEMBLY__
1389 extern unsigned long sun4v_intr_settarget(unsigned long sysino, unsigned long cpuid);
1394 * See the terminology descriptions in the device interrupt services
1395 * section above as those apply here too. Here are terminology
1396 * definitions specific to these PCI IO services:
1398 * tsbnum TSB number. Indentifies which io-tsb is used.
1399 * For this version of the specification, tsbnum
1402 * tsbindex TSB index. Identifies which entry in the TSB
1403 * is used. The first entry is zero.
1405 * tsbid A 64-bit aligned data structure which contains
1406 * a tsbnum and a tsbindex. Bits 63:32 contain the
1407 * tsbnum and bits 31:00 contain the tsbindex.
1409 * Use the HV_PCI_TSBID() macro to construct such
1412 * io_attributes IO attributes for IOMMU mappings. One of more
1413 * of the attritbute bits are stores in a 64-bit
1414 * value. The values are defined below.
1416 * r_addr 64-bit real address
1418 * pci_device PCI device address. A PCI device address identifies
1419 * a specific device on a specific PCI bus segment.
1420 * A PCI device address ia a 32-bit unsigned integer
1421 * with the following format:
1423 * 00000000.bbbbbbbb.dddddfff.00000000
1425 * Use the HV_PCI_DEVICE_BUILD() macro to construct
1429 * PCI configureation space offset. For conventional
1430 * PCI a value between 0 and 255. For extended
1431 * configuration space, a value between 0 and 4095.
1433 * Note: For PCI configuration space accesses, the offset
1434 * must be aligned to the access size.
1436 * error_flag A return value which specifies if the action succeeded
1437 * or failed. 0 means no error, non-0 means some error
1438 * occurred while performing the service.
1441 * Direction definition for pci_dma_sync(), defined
1442 * below in HV_PCI_SYNC_*.
1444 * io_page_list A list of io_page_addresses, an io_page_address is
1447 * io_page_list_p A pointer to an io_page_list.
1449 * "size based byte swap" - Some functions do size based byte swapping
1450 * which allows sw to access pointers and
1451 * counters in native form when the processor
1452 * operates in a different endianness than the
1453 * IO bus. Size-based byte swapping converts a
1454 * multi-byte field between big-endian and
1455 * little-endian format.
1458 #define HV_PCI_MAP_ATTR_READ 0x01
1459 #define HV_PCI_MAP_ATTR_WRITE 0x02
1461 #define HV_PCI_DEVICE_BUILD(b,d,f) \
1462 ((((b) & 0xff) << 16) | \
1463 (((d) & 0x1f) << 11) | \
1464 (((f) & 0x07) << 8))
1466 #define HV_PCI_TSBID(__tsb_num, __tsb_index) \
1467 ((((u64)(__tsb_num)) << 32UL) | ((u64)(__tsb_index)))
1469 #define HV_PCI_SYNC_FOR_DEVICE 0x01
1470 #define HV_PCI_SYNC_FOR_CPU 0x02
1473 * TRAP: HV_FAST_TRAP
1474 * FUNCTION: HV_FAST_PCI_IOMMU_MAP
1478 * ARG3: io_attributes
1479 * ARG4: io_page_list_p
1481 * RET1: #ttes mapped
1482 * ERRORS: EINVAL Invalid devhandle/tsbnum/tsbindex/io_attributes
1483 * EBADALIGN Improperly aligned real address
1484 * ENORADDR Invalid real address
1486 * Create IOMMU mappings in the sun4v device defined by the given
1487 * devhandle. The mappings are created in the TSB defined by the
1488 * tsbnum component of the given tsbid. The first mapping is created
1489 * in the TSB i ndex defined by the tsbindex component of the given tsbid.
1490 * The call creates up to #ttes mappings, the first one at tsbnum, tsbindex,
1491 * the second at tsbnum, tsbindex + 1, etc.
1493 * All mappings are created with the attributes defined by the io_attributes
1494 * argument. The page mapping addresses are described in the io_page_list
1495 * defined by the given io_page_list_p, which is a pointer to the io_page_list.
1496 * The first entry in the io_page_list is the address for the first iotte, the
1497 * 2nd for the 2nd iotte, and so on.
1499 * Each io_page_address in the io_page_list must be appropriately aligned.
1500 * #ttes must be greater than zero. For this version of the spec, the tsbnum
1501 * component of the given tsbid must be zero.
1503 * Returns the actual number of mappings creates, which may be less than
1504 * or equal to the argument #ttes. If the function returns a value which
1505 * is less than the #ttes, the caller may continus to call the function with
1506 * an updated tsbid, #ttes, io_page_list_p arguments until all pages are
1509 * Note: This function does not imply an iotte cache flush. The guest must
1510 * demap an entry before re-mapping it.
1512 #define HV_FAST_PCI_IOMMU_MAP 0xb0
1514 /* pci_iommu_demap()
1515 * TRAP: HV_FAST_TRAP
1516 * FUNCTION: HV_FAST_PCI_IOMMU_DEMAP
1521 * RET1: #ttes demapped
1522 * ERRORS: EINVAL Invalid devhandle/tsbnum/tsbindex
1524 * Demap and flush IOMMU mappings in the device defined by the given
1525 * devhandle. Demaps up to #ttes entries in the TSB defined by the tsbnum
1526 * component of the given tsbid, starting at the TSB index defined by the
1527 * tsbindex component of the given tsbid.
1529 * For this version of the spec, the tsbnum of the given tsbid must be zero.
1530 * #ttes must be greater than zero.
1532 * Returns the actual number of ttes demapped, which may be less than or equal
1533 * to the argument #ttes. If #ttes demapped is less than #ttes, the caller
1534 * may continue to call this function with updated tsbid and #ttes arguments
1535 * until all pages are demapped.
1537 * Note: Entries do not have to be mapped to be demapped. A demap of an
1538 * unmapped page will flush the entry from the tte cache.
1540 #define HV_FAST_PCI_IOMMU_DEMAP 0xb1
1542 /* pci_iommu_getmap()
1543 * TRAP: HV_FAST_TRAP
1544 * FUNCTION: HV_FAST_PCI_IOMMU_GETMAP
1548 * RET1: io_attributes
1549 * RET2: real address
1550 * ERRORS: EINVAL Invalid devhandle/tsbnum/tsbindex
1551 * ENOMAP Mapping is not valid, no translation exists
1553 * Read and return the mapping in the device described by the given devhandle
1554 * and tsbid. If successful, the io_attributes shall be returned in RET1
1555 * and the page address of the mapping shall be returned in RET2.
1557 * For this version of the spec, the tsbnum component of the given tsbid
1560 #define HV_FAST_PCI_IOMMU_GETMAP 0xb2
1562 /* pci_iommu_getbypass()
1563 * TRAP: HV_FAST_TRAP
1564 * FUNCTION: HV_FAST_PCI_IOMMU_GETBYPASS
1566 * ARG1: real address
1567 * ARG2: io_attributes
1570 * ERRORS: EINVAL Invalid devhandle/io_attributes
1571 * ENORADDR Invalid real address
1572 * ENOTSUPPORTED Function not supported in this implementation.
1574 * Create a "special" mapping in the device described by the given devhandle,
1575 * for the given real address and attributes. Return the IO address in RET1
1578 #define HV_FAST_PCI_IOMMU_GETBYPASS 0xb3
1581 * TRAP: HV_FAST_TRAP
1582 * FUNCTION: HV_FAST_PCI_CONFIG_GET
1585 * ARG2: pci_config_offset
1590 * ERRORS: EINVAL Invalid devhandle/pci_device/offset/size
1591 * EBADALIGN pci_config_offset not size aligned
1592 * ENOACCESS Access to this offset is not permitted
1594 * Read PCI configuration space for the adapter described by the given
1595 * devhandle. Read size (1, 2, or 4) bytes of data from the given
1596 * pci_device, at pci_config_offset from the beginning of the device's
1597 * configuration space. If there was no error, RET1 is set to zero and
1598 * RET2 is set to the data read. Insignificant bits in RET2 are not
1599 * guarenteed to have any specific value and therefore must be ignored.
1601 * The data returned in RET2 is size based byte swapped.
1603 * If an error occurs during the read, set RET1 to a non-zero value. The
1604 * given pci_config_offset must be 'size' aligned.
1606 #define HV_FAST_PCI_CONFIG_GET 0xb4
1609 * TRAP: HV_FAST_TRAP
1610 * FUNCTION: HV_FAST_PCI_CONFIG_PUT
1613 * ARG2: pci_config_offset
1618 * ERRORS: EINVAL Invalid devhandle/pci_device/offset/size
1619 * EBADALIGN pci_config_offset not size aligned
1620 * ENOACCESS Access to this offset is not permitted
1622 * Write PCI configuration space for the adapter described by the given
1623 * devhandle. Write size (1, 2, or 4) bytes of data in a single operation,
1624 * at pci_config_offset from the beginning of the device's configuration
1625 * space. The data argument contains the data to be written to configuration
1626 * space. Prior to writing, the data is size based byte swapped.
1628 * If an error occurs during the write access, do not generate an error
1629 * report, do set RET1 to a non-zero value. Otherwise RET1 is zero.
1630 * The given pci_config_offset must be 'size' aligned.
1632 * This function is permitted to read from offset zero in the configuration
1633 * space described by the given pci_device if necessary to ensure that the
1634 * write access to config space completes.
1636 #define HV_FAST_PCI_CONFIG_PUT 0xb5
1639 * TRAP: HV_FAST_TRAP
1640 * FUNCTION: HV_FAST_PCI_PEEK
1642 * ARG1: real address
1647 * ERRORS: EINVAL Invalid devhandle or size
1648 * EBADALIGN Improperly aligned real address
1649 * ENORADDR Bad real address
1650 * ENOACCESS Guest access prohibited
1652 * Attempt to read the IO address given by the given devhandle, real address,
1653 * and size. Size must be 1, 2, 4, or 8. The read is performed as a single
1654 * access operation using the given size. If an error occurs when reading
1655 * from the given location, do not generate an error report, but return a
1656 * non-zero value in RET1. If the read was successful, return zero in RET1
1657 * and return the actual data read in RET2. The data returned is size based
1660 * Non-significant bits in RET2 are not guarenteed to have any specific value
1661 * and therefore must be ignored. If RET1 is returned as non-zero, the data
1662 * value is not guarenteed to have any specific value and should be ignored.
1664 * The caller must have permission to read from the given devhandle, real
1665 * address, which must be an IO address. The argument real address must be a
1666 * size aligned address.
1668 * The hypervisor implementation of this function must block access to any
1669 * IO address that the guest does not have explicit permission to access.
1671 #define HV_FAST_PCI_PEEK 0xb6
1674 * TRAP: HV_FAST_TRAP
1675 * FUNCTION: HV_FAST_PCI_POKE
1677 * ARG1: real address
1683 * ERRORS: EINVAL Invalid devhandle, size, or pci_device
1684 * EBADALIGN Improperly aligned real address
1685 * ENORADDR Bad real address
1686 * ENOACCESS Guest access prohibited
1687 * ENOTSUPPORTED Function is not supported by implementation
1689 * Attempt to write data to the IO address given by the given devhandle,
1690 * real address, and size. Size must be 1, 2, 4, or 8. The write is
1691 * performed as a single access operation using the given size. Prior to
1692 * writing the data is size based swapped.
1694 * If an error occurs when writing to the given location, do not generate an
1695 * error report, but return a non-zero value in RET1. If the write was
1696 * successful, return zero in RET1.
1698 * pci_device describes the configuration address of the device being
1699 * written to. The implementation may safely read from offset 0 with
1700 * the configuration space of the device described by devhandle and
1701 * pci_device in order to guarantee that the write portion of the operation
1704 * Any error that occurs due to the read shall be reported using the normal
1705 * error reporting mechanisms .. the read error is not suppressed.
1707 * The caller must have permission to write to the given devhandle, real
1708 * address, which must be an IO address. The argument real address must be a
1709 * size aligned address. The caller must have permission to read from
1710 * the given devhandle, pci_device cofiguration space offset 0.
1712 * The hypervisor implementation of this function must block access to any
1713 * IO address that the guest does not have explicit permission to access.
1715 #define HV_FAST_PCI_POKE 0xb7
1718 * TRAP: HV_FAST_TRAP
1719 * FUNCTION: HV_FAST_PCI_DMA_SYNC
1721 * ARG1: real address
1723 * ARG3: io_sync_direction
1726 * ERRORS: EINVAL Invalid devhandle or io_sync_direction
1727 * ENORADDR Bad real address
1729 * Synchronize a memory region described by the given real address and size,
1730 * for the device defined by the given devhandle using the direction(s)
1731 * defined by the given io_sync_direction. The argument size is the size of
1732 * the memory region in bytes.
1734 * Return the actual number of bytes synchronized in the return value #synced,
1735 * which may be less than or equal to the argument size. If the return
1736 * value #synced is less than size, the caller must continue to call this
1737 * function with updated real address and size arguments until the entire
1738 * memory region is synchronized.
1740 #define HV_FAST_PCI_DMA_SYNC 0xb8
1742 /* PCI MSI services. */
1744 #define HV_MSITYPE_MSI32 0x00
1745 #define HV_MSITYPE_MSI64 0x01
1747 #define HV_MSIQSTATE_IDLE 0x00
1748 #define HV_MSIQSTATE_ERROR 0x01
1750 #define HV_MSIQ_INVALID 0x00
1751 #define HV_MSIQ_VALID 0x01
1753 #define HV_MSISTATE_IDLE 0x00
1754 #define HV_MSISTATE_DELIVERED 0x01
1756 #define HV_MSIVALID_INVALID 0x00
1757 #define HV_MSIVALID_VALID 0x01
1759 #define HV_PCIE_MSGTYPE_PME_MSG 0x18
1760 #define HV_PCIE_MSGTYPE_PME_ACK_MSG 0x1b
1761 #define HV_PCIE_MSGTYPE_CORR_MSG 0x30
1762 #define HV_PCIE_MSGTYPE_NONFATAL_MSG 0x31
1763 #define HV_PCIE_MSGTYPE_FATAL_MSG 0x33
1765 #define HV_MSG_INVALID 0x00
1766 #define HV_MSG_VALID 0x01
1769 * TRAP: HV_FAST_TRAP
1770 * FUNCTION: HV_FAST_PCI_MSIQ_CONF
1773 * ARG2: real address
1774 * ARG3: number of entries
1776 * ERRORS: EINVAL Invalid devhandle, msiqid or nentries
1777 * EBADALIGN Improperly aligned real address
1778 * ENORADDR Bad real address
1780 * Configure the MSI queue given by the devhandle and msiqid arguments,
1781 * and to be placed at the given real address and be of the given
1782 * number of entries. The real address must be aligned exactly to match
1783 * the queue size. Each queue entry is 64-bytes long, so f.e. a 32 entry
1784 * queue must be aligned on a 2048 byte real address boundary. The MSI-EQ
1785 * Head and Tail are initialized so that the MSI-EQ is 'empty'.
1787 * Implementation Note: Certain implementations have fixed sized queues. In
1788 * that case, number of entries must contain the correct
1791 #define HV_FAST_PCI_MSIQ_CONF 0xc0
1794 * TRAP: HV_FAST_TRAP
1795 * FUNCTION: HV_FAST_PCI_MSIQ_INFO
1799 * RET1: real address
1800 * RET2: number of entries
1801 * ERRORS: EINVAL Invalid devhandle or msiqid
1803 * Return the configuration information for the MSI queue described
1804 * by the given devhandle and msiqid. The base address of the queue
1805 * is returned in ARG1 and the number of entries is returned in ARG2.
1806 * If the queue is unconfigured, the real address is undefined and the
1807 * number of entries will be returned as zero.
1809 #define HV_FAST_PCI_MSIQ_INFO 0xc1
1811 /* pci_msiq_getvalid()
1812 * TRAP: HV_FAST_TRAP
1813 * FUNCTION: HV_FAST_PCI_MSIQ_GETVALID
1817 * RET1: msiqvalid (HV_MSIQ_VALID or HV_MSIQ_INVALID)
1818 * ERRORS: EINVAL Invalid devhandle or msiqid
1820 * Get the valid state of the MSI-EQ described by the given devhandle and
1823 #define HV_FAST_PCI_MSIQ_GETVALID 0xc2
1825 /* pci_msiq_setvalid()
1826 * TRAP: HV_FAST_TRAP
1827 * FUNCTION: HV_FAST_PCI_MSIQ_SETVALID
1830 * ARG2: msiqvalid (HV_MSIQ_VALID or HV_MSIQ_INVALID)
1832 * ERRORS: EINVAL Invalid devhandle or msiqid or msiqvalid
1833 * value or MSI EQ is uninitialized
1835 * Set the valid state of the MSI-EQ described by the given devhandle and
1836 * msiqid to the given msiqvalid.
1838 #define HV_FAST_PCI_MSIQ_SETVALID 0xc3
1840 /* pci_msiq_getstate()
1841 * TRAP: HV_FAST_TRAP
1842 * FUNCTION: HV_FAST_PCI_MSIQ_GETSTATE
1846 * RET1: msiqstate (HV_MSIQSTATE_IDLE or HV_MSIQSTATE_ERROR)
1847 * ERRORS: EINVAL Invalid devhandle or msiqid
1849 * Get the state of the MSI-EQ described by the given devhandle and
1852 #define HV_FAST_PCI_MSIQ_GETSTATE 0xc4
1854 /* pci_msiq_getvalid()
1855 * TRAP: HV_FAST_TRAP
1856 * FUNCTION: HV_FAST_PCI_MSIQ_GETVALID
1859 * ARG2: msiqstate (HV_MSIQSTATE_IDLE or HV_MSIQSTATE_ERROR)
1861 * ERRORS: EINVAL Invalid devhandle or msiqid or msiqstate
1862 * value or MSI EQ is uninitialized
1864 * Set the state of the MSI-EQ described by the given devhandle and
1865 * msiqid to the given msiqvalid.
1867 #define HV_FAST_PCI_MSIQ_SETSTATE 0xc5
1869 /* pci_msiq_gethead()
1870 * TRAP: HV_FAST_TRAP
1871 * FUNCTION: HV_FAST_PCI_MSIQ_GETHEAD
1876 * ERRORS: EINVAL Invalid devhandle or msiqid
1878 * Get the current MSI EQ queue head for the MSI-EQ described by the
1879 * given devhandle and msiqid.
1881 #define HV_FAST_PCI_MSIQ_GETHEAD 0xc6
1883 /* pci_msiq_sethead()
1884 * TRAP: HV_FAST_TRAP
1885 * FUNCTION: HV_FAST_PCI_MSIQ_SETHEAD
1890 * ERRORS: EINVAL Invalid devhandle or msiqid or msiqhead,
1891 * or MSI EQ is uninitialized
1893 * Set the current MSI EQ queue head for the MSI-EQ described by the
1894 * given devhandle and msiqid.
1896 #define HV_FAST_PCI_MSIQ_SETHEAD 0xc7
1898 /* pci_msiq_gettail()
1899 * TRAP: HV_FAST_TRAP
1900 * FUNCTION: HV_FAST_PCI_MSIQ_GETTAIL
1905 * ERRORS: EINVAL Invalid devhandle or msiqid
1907 * Get the current MSI EQ queue tail for the MSI-EQ described by the
1908 * given devhandle and msiqid.
1910 #define HV_FAST_PCI_MSIQ_GETTAIL 0xc8
1912 /* pci_msi_getvalid()
1913 * TRAP: HV_FAST_TRAP
1914 * FUNCTION: HV_FAST_PCI_MSI_GETVALID
1918 * RET1: msivalidstate
1919 * ERRORS: EINVAL Invalid devhandle or msinum
1921 * Get the current valid/enabled state for the MSI defined by the
1922 * given devhandle and msinum.
1924 #define HV_FAST_PCI_MSI_GETVALID 0xc9
1926 /* pci_msi_setvalid()
1927 * TRAP: HV_FAST_TRAP
1928 * FUNCTION: HV_FAST_PCI_MSI_SETVALID
1931 * ARG2: msivalidstate
1933 * ERRORS: EINVAL Invalid devhandle or msinum or msivalidstate
1935 * Set the current valid/enabled state for the MSI defined by the
1936 * given devhandle and msinum.
1938 #define HV_FAST_PCI_MSI_SETVALID 0xca
1940 /* pci_msi_getmsiq()
1941 * TRAP: HV_FAST_TRAP
1942 * FUNCTION: HV_FAST_PCI_MSI_GETMSIQ
1947 * ERRORS: EINVAL Invalid devhandle or msinum or MSI is unbound
1949 * Get the MSI EQ that the MSI defined by the given devhandle and
1950 * msinum is bound to.
1952 #define HV_FAST_PCI_MSI_GETMSIQ 0xcb
1954 /* pci_msi_setmsiq()
1955 * TRAP: HV_FAST_TRAP
1956 * FUNCTION: HV_FAST_PCI_MSI_SETMSIQ
1962 * ERRORS: EINVAL Invalid devhandle or msinum or msiqid
1964 * Set the MSI EQ that the MSI defined by the given devhandle and
1965 * msinum is bound to.
1967 #define HV_FAST_PCI_MSI_SETMSIQ 0xcc
1969 /* pci_msi_getstate()
1970 * TRAP: HV_FAST_TRAP
1971 * FUNCTION: HV_FAST_PCI_MSI_GETSTATE
1976 * ERRORS: EINVAL Invalid devhandle or msinum
1978 * Get the state of the MSI defined by the given devhandle and msinum.
1979 * If not initialized, return HV_MSISTATE_IDLE.
1981 #define HV_FAST_PCI_MSI_GETSTATE 0xcd
1983 /* pci_msi_setstate()
1984 * TRAP: HV_FAST_TRAP
1985 * FUNCTION: HV_FAST_PCI_MSI_SETSTATE
1990 * ERRORS: EINVAL Invalid devhandle or msinum or msistate
1992 * Set the state of the MSI defined by the given devhandle and msinum.
1994 #define HV_FAST_PCI_MSI_SETSTATE 0xce
1996 /* pci_msg_getmsiq()
1997 * TRAP: HV_FAST_TRAP
1998 * FUNCTION: HV_FAST_PCI_MSG_GETMSIQ
2003 * ERRORS: EINVAL Invalid devhandle or msgtype
2005 * Get the MSI EQ of the MSG defined by the given devhandle and msgtype.
2007 #define HV_FAST_PCI_MSG_GETMSIQ 0xd0
2009 /* pci_msg_setmsiq()
2010 * TRAP: HV_FAST_TRAP
2011 * FUNCTION: HV_FAST_PCI_MSG_SETMSIQ
2016 * ERRORS: EINVAL Invalid devhandle, msgtype, or msiqid
2018 * Set the MSI EQ of the MSG defined by the given devhandle and msgtype.
2020 #define HV_FAST_PCI_MSG_SETMSIQ 0xd1
2022 /* pci_msg_getvalid()
2023 * TRAP: HV_FAST_TRAP
2024 * FUNCTION: HV_FAST_PCI_MSG_GETVALID
2028 * RET1: msgvalidstate
2029 * ERRORS: EINVAL Invalid devhandle or msgtype
2031 * Get the valid/enabled state of the MSG defined by the given
2032 * devhandle and msgtype.
2034 #define HV_FAST_PCI_MSG_GETVALID 0xd2
2036 /* pci_msg_setvalid()
2037 * TRAP: HV_FAST_TRAP
2038 * FUNCTION: HV_FAST_PCI_MSG_SETVALID
2041 * ARG2: msgvalidstate
2043 * ERRORS: EINVAL Invalid devhandle or msgtype or msgvalidstate
2045 * Set the valid/enabled state of the MSG defined by the given
2046 * devhandle and msgtype.
2048 #define HV_FAST_PCI_MSG_SETVALID 0xd3
2050 /* Performance counter services. */
2052 #define HV_PERF_JBUS_PERF_CTRL_REG 0x00
2053 #define HV_PERF_JBUS_PERF_CNT_REG 0x01
2054 #define HV_PERF_DRAM_PERF_CTRL_REG_0 0x02
2055 #define HV_PERF_DRAM_PERF_CNT_REG_0 0x03
2056 #define HV_PERF_DRAM_PERF_CTRL_REG_1 0x04
2057 #define HV_PERF_DRAM_PERF_CNT_REG_1 0x05
2058 #define HV_PERF_DRAM_PERF_CTRL_REG_2 0x06
2059 #define HV_PERF_DRAM_PERF_CNT_REG_2 0x07
2060 #define HV_PERF_DRAM_PERF_CTRL_REG_3 0x08
2061 #define HV_PERF_DRAM_PERF_CNT_REG_3 0x09
2064 * TRAP: HV_FAST_TRAP
2065 * FUNCTION: HV_FAST_GET_PERFREG
2066 * ARG0: performance reg number
2068 * RET1: performance reg value
2069 * ERRORS: EINVAL Invalid performance register number
2070 * ENOACCESS No access allowed to performance counters
2072 * Read the value of the given DRAM/JBUS performance counter/control register.
2074 #define HV_FAST_GET_PERFREG 0x100
2077 * TRAP: HV_FAST_TRAP
2078 * FUNCTION: HV_FAST_SET_PERFREG
2079 * ARG0: performance reg number
2080 * ARG1: performance reg value
2082 * ERRORS: EINVAL Invalid performance register number
2083 * ENOACCESS No access allowed to performance counters
2085 * Write the given performance reg value to the given DRAM/JBUS
2086 * performance counter/control register.
2088 #define HV_FAST_SET_PERFREG 0x101
2090 /* MMU statistics services.
2092 * The hypervisor maintains MMU statistics and privileged code provides
2093 * a buffer where these statistics can be collected. It is continually
2094 * updated once configured. The layout is as follows:
2096 #ifndef __ASSEMBLY__
2097 struct hv_mmu_statistics {
2098 unsigned long immu_tsb_hits_ctx0_8k_tte;
2099 unsigned long immu_tsb_ticks_ctx0_8k_tte;
2100 unsigned long immu_tsb_hits_ctx0_64k_tte;
2101 unsigned long immu_tsb_ticks_ctx0_64k_tte;
2102 unsigned long __reserved1[2];
2103 unsigned long immu_tsb_hits_ctx0_4mb_tte;
2104 unsigned long immu_tsb_ticks_ctx0_4mb_tte;
2105 unsigned long __reserved2[2];
2106 unsigned long immu_tsb_hits_ctx0_256mb_tte;
2107 unsigned long immu_tsb_ticks_ctx0_256mb_tte;
2108 unsigned long __reserved3[4];
2109 unsigned long immu_tsb_hits_ctxnon0_8k_tte;
2110 unsigned long immu_tsb_ticks_ctxnon0_8k_tte;
2111 unsigned long immu_tsb_hits_ctxnon0_64k_tte;
2112 unsigned long immu_tsb_ticks_ctxnon0_64k_tte;
2113 unsigned long __reserved4[2];
2114 unsigned long immu_tsb_hits_ctxnon0_4mb_tte;
2115 unsigned long immu_tsb_ticks_ctxnon0_4mb_tte;
2116 unsigned long __reserved5[2];
2117 unsigned long immu_tsb_hits_ctxnon0_256mb_tte;
2118 unsigned long immu_tsb_ticks_ctxnon0_256mb_tte;
2119 unsigned long __reserved6[4];
2120 unsigned long dmmu_tsb_hits_ctx0_8k_tte;
2121 unsigned long dmmu_tsb_ticks_ctx0_8k_tte;
2122 unsigned long dmmu_tsb_hits_ctx0_64k_tte;
2123 unsigned long dmmu_tsb_ticks_ctx0_64k_tte;
2124 unsigned long __reserved7[2];
2125 unsigned long dmmu_tsb_hits_ctx0_4mb_tte;
2126 unsigned long dmmu_tsb_ticks_ctx0_4mb_tte;
2127 unsigned long __reserved8[2];
2128 unsigned long dmmu_tsb_hits_ctx0_256mb_tte;
2129 unsigned long dmmu_tsb_ticks_ctx0_256mb_tte;
2130 unsigned long __reserved9[4];
2131 unsigned long dmmu_tsb_hits_ctxnon0_8k_tte;
2132 unsigned long dmmu_tsb_ticks_ctxnon0_8k_tte;
2133 unsigned long dmmu_tsb_hits_ctxnon0_64k_tte;
2134 unsigned long dmmu_tsb_ticks_ctxnon0_64k_tte;
2135 unsigned long __reserved10[2];
2136 unsigned long dmmu_tsb_hits_ctxnon0_4mb_tte;
2137 unsigned long dmmu_tsb_ticks_ctxnon0_4mb_tte;
2138 unsigned long __reserved11[2];
2139 unsigned long dmmu_tsb_hits_ctxnon0_256mb_tte;
2140 unsigned long dmmu_tsb_ticks_ctxnon0_256mb_tte;
2141 unsigned long __reserved12[4];
2146 * TRAP: HV_FAST_TRAP
2147 * FUNCTION: HV_FAST_MMUSTAT_CONF
2148 * ARG0: real address
2150 * RET1: real address
2151 * ERRORS: ENORADDR Invalid real address
2152 * EBADALIGN Real address not aligned on 64-byte boundary
2153 * EBADTRAP API not supported on this processor
2155 * Enable MMU statistic gathering using the buffer at the given real
2156 * address on the current virtual CPU. The new buffer real address
2157 * is given in ARG1, and the previously specified buffer real address
2158 * is returned in RET1, or is returned as zero for the first invocation.
2160 * If the passed in real address argument is zero, this will disable
2161 * MMU statistic collection on the current virtual CPU. If an error is
2162 * returned then no statistics are collected.
2164 * The buffer contents should be initialized to all zeros before being
2165 * given to the hypervisor or else the statistics will be meaningless.
2167 #define HV_FAST_MMUSTAT_CONF 0x102
2170 * TRAP: HV_FAST_TRAP
2171 * FUNCTION: HV_FAST_MMUSTAT_INFO
2173 * RET1: real address
2174 * ERRORS: EBADTRAP API not supported on this processor
2176 * Return the current state and real address of the currently configured
2177 * MMU statistics buffer on the current virtual CPU.
2179 #define HV_FAST_MMUSTAT_INFO 0x103
2181 /* Function numbers for HV_CORE_TRAP. */
2182 #define HV_CORE_SET_VER 0x00
2183 #define HV_CORE_PUTCHAR 0x01
2184 #define HV_CORE_EXIT 0x02
2185 #define HV_CORE_GET_VER 0x03
2187 /* Hypervisor API groups for use with HV_CORE_SET_VER and
2190 #define HV_GRP_SUN4V 0x0000
2191 #define HV_GRP_CORE 0x0001
2192 #define HV_GRP_INTR 0x0002
2193 #define HV_GRP_SOFT_STATE 0x0003
2194 #define HV_GRP_PCI 0x0100
2195 #define HV_GRP_LDOM 0x0101
2196 #define HV_GRP_SVC_CHAN 0x0102
2197 #define HV_GRP_NCS 0x0103
2198 #define HV_GRP_NIAG_PERF 0x0200
2199 #define HV_GRP_FIRE_PERF 0x0201
2200 #define HV_GRP_DIAG 0x0300
2202 #ifndef __ASSEMBLY__
2203 extern unsigned long sun4v_get_version(unsigned long group,
2204 unsigned long *major,
2205 unsigned long *minor);
2206 extern unsigned long sun4v_set_version(unsigned long group,
2207 unsigned long major,
2208 unsigned long minor,
2209 unsigned long *actual_minor);
2211 extern int sun4v_hvapi_register(unsigned long group, unsigned long major,
2212 unsigned long *minor);
2213 extern void sun4v_hvapi_unregister(unsigned long group);
2214 extern int sun4v_hvapi_get(unsigned long group,
2215 unsigned long *major,
2216 unsigned long *minor);
2217 extern void sun4v_hvapi_init(void);
2220 #endif /* !(_SPARC64_HYPERVISOR_H) */
projects / linux-2.6 / blob