2 * arch/sh/kernel/cpu/sh4a/clock-sh7722.c
4 * SH7722 support for the clock framework
6 * Copyright (c) 2006-2007 Nomad Global Solutions Inc
7 * Based on code for sh7343 by Paul Mundt
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
13 #include <linux/init.h>
14 #include <linux/kernel.h>
16 #include <linux/errno.h>
17 #include <asm/clock.h>
20 #define SH7722_PLL_FREQ (32000000/8)
23 #define ROUND_NEAREST 0
27 static int adjust_algos[][3] = {
29 { NM, N, 1 }, /* N:1, N:1 */
30 { 3, 2, 2 }, /* 3:2:2 */
31 { 5, 2, 2 }, /* 5:2:2 */
32 { N, 1, 1 }, /* N:1:1 */
44 static unsigned long adjust_pair_of_clocks(unsigned long r1, unsigned long r2,
45 int m1, int m2, int round_flag)
47 unsigned long rem, div;
50 pr_debug( "Actual values: r1 = %ld\n", r1);
51 pr_debug( "...............r2 = %ld\n", r2);
55 pr_debug( "setting equal rates: r2 now %ld\n", r2);
56 } else if ((m2 == N && m1 == 1) ||
57 (m2 == NM && m1 == N)) { /* N:1 or NM:N */
58 pr_debug( "Setting rates as 1:N (N:N*M)\n");
60 pr_debug( "...remainder = %ld\n", rem);
63 pr_debug( "...div = %ld\n", div);
66 the_one = rem >= r1/2 ? 1 : 0; break;
73 r2 = r1 * (div + the_one);
74 pr_debug( "...setting r2 to %ld\n", r2);
76 } else if ((m2 == 1 && m1 == N) ||
77 (m2 == N && m1 == NM)) { /* 1:N or N:NM */
78 pr_debug( "Setting rates as N:1 (N*M:N)\n");
80 pr_debug( "...remainder = %ld\n", rem);
83 pr_debug( "...div = %ld\n", div);
86 the_one = rem > r2/2 ? 1 : 0; break;
93 r2 = r1 / (div + the_one);
94 pr_debug( "...setting r2 to %ld\n", r2);
96 } else { /* value:value */
97 pr_debug( "Setting rates as %d:%d\n", m1, m2);
100 pr_debug( "...div = %ld\n", div);
101 pr_debug( "...setting r2 to %ld\n", r2);
107 static void adjust_clocks(int originate, int *l, unsigned long v[],
112 pr_debug( "Go down from %d...\n", originate);
113 /* go up recalculation clocks */
114 for (x = originate; x>0; x -- )
115 v[x-1] = adjust_pair_of_clocks(v[x], v[x-1],
119 pr_debug( "Go up from %d...\n", originate);
120 /* go down recalculation clocks */
121 for (x = originate; x<n_in_line - 1; x ++ )
122 v[x+1] = adjust_pair_of_clocks(v[x], v[x+1],
129 * SH7722 uses a common set of multipliers and divisors, so this
134 * Instead of having two separate multipliers/divisors set, like this:
136 * static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
137 * static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 };
139 * I created the divisors2 array, which is used to calculate rate like
140 * rate = parent * 2 / divisors2[ divisor ];
142 static int divisors2[] = { 2, 3, 4, 5, 6, 8, 10, 12, 16, 20, 24, 32, 40 };
144 static void master_clk_init(struct clk *clk)
146 clk_set_rate(clk, clk_get_rate(clk));
149 static void master_clk_recalc(struct clk *clk)
151 unsigned long frqcr = ctrl_inl(FRQCR);
153 clk->rate = CONFIG_SH_PCLK_FREQ * (1 + (frqcr >> 24 & 0xF));
156 static int master_clk_setrate(struct clk *clk, unsigned long rate, int id)
158 int div = rate / SH7722_PLL_FREQ;
159 int master_divs[] = { 2, 3, 4, 6, 8, 16 };
163 if (rate < SH7722_PLL_FREQ * 2)
166 for (index = 1; index < ARRAY_SIZE(master_divs); index++)
167 if (div >= master_divs[index - 1] && div < master_divs[index])
170 if (index >= ARRAY_SIZE(master_divs))
171 index = ARRAY_SIZE(master_divs);
172 div = master_divs[index - 1];
174 frqcr = ctrl_inl(FRQCR);
175 frqcr &= ~(0xF << 24);
176 frqcr |= ( (div-1) << 24);
177 ctrl_outl(frqcr, FRQCR);
182 static struct clk_ops sh7722_master_clk_ops = {
183 .init = master_clk_init,
184 .recalc = master_clk_recalc,
185 .set_rate = master_clk_setrate,
188 struct frqcr_context {
193 struct frqcr_context sh7722_get_clk_context(const char *name)
195 struct frqcr_context ctx = { 0, };
197 if (!strcmp(name, "peripheral_clk")) {
200 } else if (!strcmp(name, "sdram_clk")) {
203 } else if (!strcmp(name, "bus_clk")) {
206 } else if (!strcmp(name, "sh_clk")) {
209 } else if (!strcmp(name, "umem_clk")) {
212 } else if (!strcmp(name, "cpu_clk")) {
220 * sh7722_find_divisors - find divisor for setting rate
222 * All sh7722 clocks use the same set of multipliers/divisors. This function
223 * chooses correct divisor to set the rate of clock with parent clock that
224 * generates frequency of 'parent_rate'
226 * @parent_rate: rate of parent clock
227 * @rate: requested rate to be set
229 static int sh7722_find_divisors(unsigned long parent_rate, unsigned rate)
231 unsigned div2 = parent_rate * 2 / rate;
234 if (rate > parent_rate)
237 for (index = 1; index < ARRAY_SIZE(divisors2); index++) {
238 if (div2 > divisors2[index] && div2 <= divisors2[index])
241 if (index >= ARRAY_SIZE(divisors2))
242 index = ARRAY_SIZE(divisors2) - 1;
243 return divisors2[index];
246 static void sh7722_frqcr_recalc(struct clk *clk)
248 struct frqcr_context ctx = sh7722_get_clk_context(clk->name);
249 unsigned long frqcr = ctrl_inl(FRQCR);
252 index = (frqcr >> ctx.shift) & ctx.mask;
253 clk->rate = clk->parent->rate * 2 / divisors2[index];
256 static int sh7722_frqcr_set_rate(struct clk *clk, unsigned long rate,
259 struct frqcr_context ctx = sh7722_get_clk_context(clk->name);
260 unsigned long parent_rate = clk->parent->rate;
266 if (parent_rate < rate)
269 /* look for multiplier/divisor pair */
270 div = sh7722_find_divisors(parent_rate, rate);
274 /* calculate new value of clock rate */
275 clk->rate = parent_rate * 2 / div;
276 frqcr = ctrl_inl(FRQCR);
278 /* FIXME: adjust as algo_id specifies */
279 if (algo_id != NO_CHANGE) {
281 char *algo_group_1[] = { "cpu_clk", "umem_clk", "sh_clk" };
282 char *algo_group_2[] = { "sh_clk", "bus_clk" };
283 char *algo_group_3[] = { "sh_clk", "sdram_clk" };
284 char *algo_group_4[] = { "bus_clk", "peripheral_clk" };
285 char *algo_group_5[] = { "cpu_clk", "peripheral_clk" };
286 char **algo_current = NULL;
287 /* 3 is the maximum number of clocks in relation */
289 unsigned long values[3]; /* the same comment as above */
290 int part_length = -1;
294 * all the steps below only required if adjustion was
297 if (algo_id == IUS_N1_N1 ||
298 algo_id == IUS_322 ||
299 algo_id == IUS_522 ||
300 algo_id == IUS_N11) {
301 algo_current = algo_group_1;
304 if (algo_id == SB_N1) {
305 algo_current = algo_group_2;
308 if (algo_id == SB3_N1 ||
312 algo_current = algo_group_3;
315 if (algo_id == BP_N1) {
316 algo_current = algo_group_4;
319 if (algo_id == IP_N1) {
320 algo_current = algo_group_5;
324 goto incorrect_algo_id;
327 for (i = 0; i < part_length; i ++ ) {
328 if (originator >= 0 && !strcmp(clk->name,
331 ck[i] = clk_get(NULL, algo_current[i]);
332 values[i] = clk_get_rate(ck[i]);
336 adjust_clocks(originator, adjust_algos[algo_id],
337 values, part_length);
339 for (i = 0; i < part_length; i ++ ) {
340 struct frqcr_context part_ctx;
344 part_div = sh7722_find_divisors(parent_rate,
347 part_ctx = sh7722_get_clk_context(
349 frqcr &= ~(part_ctx.mask <<
351 frqcr |= part_div << part_ctx.shift;
356 ck[i]->ops->recalc(ck[i]);
361 /* was there any error during recalculation ? If so, bail out.. */
362 if (unlikely(err!=0))
365 /* clear FRQCR bits */
366 frqcr &= ~(ctx.mask << ctx.shift);
367 frqcr |= div << ctx.shift;
369 /* ...and perform actual change */
370 ctrl_outl(frqcr, FRQCR);
379 static struct clk_ops sh7722_frqcr_clk_ops = {
380 .recalc = sh7722_frqcr_recalc,
381 .set_rate = sh7722_frqcr_set_rate,
385 * clock ops methods for SIU A/B and IrDA clock
388 static int sh7722_siu_which(struct clk *clk)
390 if (!strcmp(clk->name, "siu_a_clk"))
392 if (!strcmp(clk->name, "siu_b_clk"))
394 if (!strcmp(clk->name, "irda_clk"))
399 static unsigned long sh7722_siu_regs[] = {
405 static int sh7722_siu_start_stop(struct clk *clk, int enable)
407 int siu = sh7722_siu_which(clk);
413 r = ctrl_inl(sh7722_siu_regs[siu]);
415 ctrl_outl(r & ~(1 << 8), sh7722_siu_regs[siu]);
417 ctrl_outl(r | (1 << 8), sh7722_siu_regs[siu]);
421 static void sh7722_siu_enable(struct clk *clk)
423 sh7722_siu_start_stop(clk, 1);
426 static void sh7722_siu_disable(struct clk *clk)
428 sh7722_siu_start_stop(clk, 0);
431 static void sh7722_video_enable(struct clk *clk)
435 r = ctrl_inl(VCLKCR);
436 ctrl_outl( r & ~(1<<8), VCLKCR);
439 static void sh7722_video_disable(struct clk *clk)
443 r = ctrl_inl(VCLKCR);
444 ctrl_outl( r | (1<<8), VCLKCR);
447 static int sh7722_video_set_rate(struct clk *clk, unsigned long rate,
452 r = ctrl_inl(VCLKCR);
454 r |= ((clk->parent->rate / rate - 1) & 0x3F);
455 ctrl_outl(r, VCLKCR);
459 static void sh7722_video_recalc(struct clk *clk)
463 r = ctrl_inl(VCLKCR);
464 clk->rate = clk->parent->rate / ((r & 0x3F) + 1);
467 static int sh7722_siu_set_rate(struct clk *clk, unsigned long rate, int algo_id)
469 int siu = sh7722_siu_which(clk);
476 r = ctrl_inl(sh7722_siu_regs[siu]);
477 div = sh7722_find_divisors(clk->parent->rate, rate);
480 r = (r & ~0xF) | div;
481 ctrl_outl(r, sh7722_siu_regs[siu]);
485 static void sh7722_siu_recalc(struct clk *clk)
487 int siu = sh7722_siu_which(clk);
493 r = ctrl_inl(sh7722_siu_regs[siu]);
494 clk->rate = clk->parent->rate * 2 / divisors2[r & 0xF];
497 static struct clk_ops sh7722_siu_clk_ops = {
498 .recalc = sh7722_siu_recalc,
499 .set_rate = sh7722_siu_set_rate,
500 .enable = sh7722_siu_enable,
501 .disable = sh7722_siu_disable,
504 static struct clk_ops sh7722_video_clk_ops = {
505 .recalc = sh7722_video_recalc,
506 .set_rate = sh7722_video_set_rate,
507 .enable = sh7722_video_enable,
508 .disable = sh7722_video_disable,
511 * and at last, clock definitions themselves
513 static struct clk sh7722_umem_clock = {
515 .ops = &sh7722_frqcr_clk_ops,
518 static struct clk sh7722_sh_clock = {
520 .ops = &sh7722_frqcr_clk_ops,
523 static struct clk sh7722_peripheral_clock = {
524 .name = "peripheral_clk",
525 .ops = &sh7722_frqcr_clk_ops,
528 static struct clk sh7722_sdram_clock = {
530 .ops = &sh7722_frqcr_clk_ops,
534 * these three clocks - SIU A, SIU B, IrDA - share the same clk_ops
535 * methods of clk_ops determine which register they should access by
536 * examining clk->name field
538 static struct clk sh7722_siu_a_clock = {
540 .ops = &sh7722_siu_clk_ops,
543 static struct clk sh7722_siu_b_clock = {
545 .ops = &sh7722_siu_clk_ops,
548 static struct clk sh7722_irda_clock = {
550 .ops = &sh7722_siu_clk_ops,
553 static struct clk sh7722_video_clock = {
555 .ops = &sh7722_video_clk_ops,
558 static struct clk *sh7722_clocks[] = {
561 &sh7722_peripheral_clock,
570 * init in order: master, module, bus, cpu
572 struct clk_ops *onchip_ops[] = {
573 &sh7722_master_clk_ops,
574 &sh7722_frqcr_clk_ops,
575 &sh7722_frqcr_clk_ops,
576 &sh7722_frqcr_clk_ops,
580 arch_init_clk_ops(struct clk_ops **ops, int type)
582 BUG_ON(type < 0 || type > ARRAY_SIZE(onchip_ops));
583 *ops = onchip_ops[type];
586 int __init sh7722_clock_init(void)
591 master = clk_get(NULL, "master_clk");
592 for (i = 0; i < ARRAY_SIZE(sh7722_clocks); i++) {
593 pr_debug( "Registering clock '%s'\n", sh7722_clocks[i]->name);
594 sh7722_clocks[i]->parent = master;
595 clk_register(sh7722_clocks[i]);
600 arch_initcall(sh7722_clock_init);