2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
40 #include <acpi/acpi_bus.h>
42 #include <linux/bootmem.h>
43 #include <linux/dmar.h>
44 #include <linux/hpet.h>
51 #include <asm/proto.h>
54 #include <asm/timer.h>
55 #include <asm/i8259.h>
57 #include <asm/msidef.h>
58 #include <asm/hypertransport.h>
59 #include <asm/setup.h>
60 #include <asm/irq_remapping.h>
62 #include <asm/uv/uv_hub.h>
63 #include <asm/uv/uv_irq.h>
67 #define __apicdebuginit(type) static type __init
70 * Is the SiS APIC rmw bug present ?
71 * -1 = don't know, 0 = no, 1 = yes
73 int sis_apic_bug = -1;
75 static DEFINE_SPINLOCK(ioapic_lock);
76 static DEFINE_SPINLOCK(vector_lock);
79 * # of IRQ routing registers
81 int nr_ioapic_registers[MAX_IO_APICS];
83 /* I/O APIC entries */
84 struct mpc_ioapic mp_ioapics[MAX_IO_APICS];
87 /* MP IRQ source entries */
88 struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
90 /* # of MP IRQ source entries */
93 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
94 int mp_bus_id_to_type[MAX_MP_BUSSES];
97 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
99 int skip_ioapic_setup;
101 void arch_disable_smp_support(void)
105 noioapicreroute = -1;
107 skip_ioapic_setup = 1;
110 static int __init parse_noapic(char *str)
112 /* disable IO-APIC */
113 arch_disable_smp_support();
116 early_param("noapic", parse_noapic);
121 * This is performance-critical, we want to do it O(1)
123 * the indexing order of this array favors 1:1 mappings
124 * between pins and IRQs.
127 struct irq_pin_list {
129 struct irq_pin_list *next;
132 static struct irq_pin_list *get_one_free_irq_2_pin(int cpu)
134 struct irq_pin_list *pin;
137 node = cpu_to_node(cpu);
139 pin = kzalloc_node(sizeof(*pin), GFP_ATOMIC, node);
145 struct irq_pin_list *irq_2_pin;
146 cpumask_var_t domain;
147 cpumask_var_t old_domain;
148 unsigned move_cleanup_count;
150 u8 move_in_progress : 1;
151 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
152 u8 move_desc_pending : 1;
156 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
157 #ifdef CONFIG_SPARSE_IRQ
158 static struct irq_cfg irq_cfgx[] = {
160 static struct irq_cfg irq_cfgx[NR_IRQS] = {
162 [0] = { .vector = IRQ0_VECTOR, },
163 [1] = { .vector = IRQ1_VECTOR, },
164 [2] = { .vector = IRQ2_VECTOR, },
165 [3] = { .vector = IRQ3_VECTOR, },
166 [4] = { .vector = IRQ4_VECTOR, },
167 [5] = { .vector = IRQ5_VECTOR, },
168 [6] = { .vector = IRQ6_VECTOR, },
169 [7] = { .vector = IRQ7_VECTOR, },
170 [8] = { .vector = IRQ8_VECTOR, },
171 [9] = { .vector = IRQ9_VECTOR, },
172 [10] = { .vector = IRQ10_VECTOR, },
173 [11] = { .vector = IRQ11_VECTOR, },
174 [12] = { .vector = IRQ12_VECTOR, },
175 [13] = { .vector = IRQ13_VECTOR, },
176 [14] = { .vector = IRQ14_VECTOR, },
177 [15] = { .vector = IRQ15_VECTOR, },
180 int __init arch_early_irq_init(void)
183 struct irq_desc *desc;
188 count = ARRAY_SIZE(irq_cfgx);
190 for (i = 0; i < count; i++) {
191 desc = irq_to_desc(i);
192 desc->chip_data = &cfg[i];
193 alloc_bootmem_cpumask_var(&cfg[i].domain);
194 alloc_bootmem_cpumask_var(&cfg[i].old_domain);
195 if (i < NR_IRQS_LEGACY)
196 cpumask_setall(cfg[i].domain);
202 #ifdef CONFIG_SPARSE_IRQ
203 static struct irq_cfg *irq_cfg(unsigned int irq)
205 struct irq_cfg *cfg = NULL;
206 struct irq_desc *desc;
208 desc = irq_to_desc(irq);
210 cfg = desc->chip_data;
215 static struct irq_cfg *get_one_free_irq_cfg(int cpu)
220 node = cpu_to_node(cpu);
222 cfg = kzalloc_node(sizeof(*cfg), GFP_ATOMIC, node);
224 if (!alloc_cpumask_var_node(&cfg->domain, GFP_ATOMIC, node)) {
227 } else if (!alloc_cpumask_var_node(&cfg->old_domain,
229 free_cpumask_var(cfg->domain);
233 cpumask_clear(cfg->domain);
234 cpumask_clear(cfg->old_domain);
241 int arch_init_chip_data(struct irq_desc *desc, int cpu)
245 cfg = desc->chip_data;
247 desc->chip_data = get_one_free_irq_cfg(cpu);
248 if (!desc->chip_data) {
249 printk(KERN_ERR "can not alloc irq_cfg\n");
257 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
260 init_copy_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg, int cpu)
262 struct irq_pin_list *old_entry, *head, *tail, *entry;
264 cfg->irq_2_pin = NULL;
265 old_entry = old_cfg->irq_2_pin;
269 entry = get_one_free_irq_2_pin(cpu);
273 entry->apic = old_entry->apic;
274 entry->pin = old_entry->pin;
277 old_entry = old_entry->next;
279 entry = get_one_free_irq_2_pin(cpu);
287 /* still use the old one */
290 entry->apic = old_entry->apic;
291 entry->pin = old_entry->pin;
294 old_entry = old_entry->next;
298 cfg->irq_2_pin = head;
301 static void free_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg)
303 struct irq_pin_list *entry, *next;
305 if (old_cfg->irq_2_pin == cfg->irq_2_pin)
308 entry = old_cfg->irq_2_pin;
315 old_cfg->irq_2_pin = NULL;
318 void arch_init_copy_chip_data(struct irq_desc *old_desc,
319 struct irq_desc *desc, int cpu)
322 struct irq_cfg *old_cfg;
324 cfg = get_one_free_irq_cfg(cpu);
329 desc->chip_data = cfg;
331 old_cfg = old_desc->chip_data;
333 memcpy(cfg, old_cfg, sizeof(struct irq_cfg));
335 init_copy_irq_2_pin(old_cfg, cfg, cpu);
338 static void free_irq_cfg(struct irq_cfg *old_cfg)
343 void arch_free_chip_data(struct irq_desc *old_desc, struct irq_desc *desc)
345 struct irq_cfg *old_cfg, *cfg;
347 old_cfg = old_desc->chip_data;
348 cfg = desc->chip_data;
354 free_irq_2_pin(old_cfg, cfg);
355 free_irq_cfg(old_cfg);
356 old_desc->chip_data = NULL;
361 set_extra_move_desc(struct irq_desc *desc, const struct cpumask *mask)
363 struct irq_cfg *cfg = desc->chip_data;
365 if (!cfg->move_in_progress) {
366 /* it means that domain is not changed */
367 if (!cpumask_intersects(desc->affinity, mask))
368 cfg->move_desc_pending = 1;
374 static struct irq_cfg *irq_cfg(unsigned int irq)
376 return irq < nr_irqs ? irq_cfgx + irq : NULL;
381 #ifndef CONFIG_NUMA_MIGRATE_IRQ_DESC
383 set_extra_move_desc(struct irq_desc *desc, const struct cpumask *mask)
390 unsigned int unused[3];
392 unsigned int unused2[11];
396 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
398 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
399 + (mp_ioapics[idx].apicaddr & ~PAGE_MASK);
402 static inline void io_apic_eoi(unsigned int apic, unsigned int vector)
404 struct io_apic __iomem *io_apic = io_apic_base(apic);
405 writel(vector, &io_apic->eoi);
408 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
410 struct io_apic __iomem *io_apic = io_apic_base(apic);
411 writel(reg, &io_apic->index);
412 return readl(&io_apic->data);
415 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
417 struct io_apic __iomem *io_apic = io_apic_base(apic);
418 writel(reg, &io_apic->index);
419 writel(value, &io_apic->data);
423 * Re-write a value: to be used for read-modify-write
424 * cycles where the read already set up the index register.
426 * Older SiS APIC requires we rewrite the index register
428 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
430 struct io_apic __iomem *io_apic = io_apic_base(apic);
433 writel(reg, &io_apic->index);
434 writel(value, &io_apic->data);
437 static bool io_apic_level_ack_pending(struct irq_cfg *cfg)
439 struct irq_pin_list *entry;
442 spin_lock_irqsave(&ioapic_lock, flags);
443 entry = cfg->irq_2_pin;
451 reg = io_apic_read(entry->apic, 0x10 + pin*2);
452 /* Is the remote IRR bit set? */
453 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
454 spin_unlock_irqrestore(&ioapic_lock, flags);
461 spin_unlock_irqrestore(&ioapic_lock, flags);
467 struct { u32 w1, w2; };
468 struct IO_APIC_route_entry entry;
471 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
473 union entry_union eu;
475 spin_lock_irqsave(&ioapic_lock, flags);
476 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
477 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
478 spin_unlock_irqrestore(&ioapic_lock, flags);
483 * When we write a new IO APIC routing entry, we need to write the high
484 * word first! If the mask bit in the low word is clear, we will enable
485 * the interrupt, and we need to make sure the entry is fully populated
486 * before that happens.
489 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
491 union entry_union eu;
493 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
494 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
497 void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
500 spin_lock_irqsave(&ioapic_lock, flags);
501 __ioapic_write_entry(apic, pin, e);
502 spin_unlock_irqrestore(&ioapic_lock, flags);
506 * When we mask an IO APIC routing entry, we need to write the low
507 * word first, in order to set the mask bit before we change the
510 static void ioapic_mask_entry(int apic, int pin)
513 union entry_union eu = { .entry.mask = 1 };
515 spin_lock_irqsave(&ioapic_lock, flags);
516 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
517 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
518 spin_unlock_irqrestore(&ioapic_lock, flags);
522 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
523 * shared ISA-space IRQs, so we have to support them. We are super
524 * fast in the common case, and fast for shared ISA-space IRQs.
526 static void add_pin_to_irq_cpu(struct irq_cfg *cfg, int cpu, int apic, int pin)
528 struct irq_pin_list *entry;
530 entry = cfg->irq_2_pin;
532 entry = get_one_free_irq_2_pin(cpu);
534 printk(KERN_ERR "can not alloc irq_2_pin to add %d - %d\n",
538 cfg->irq_2_pin = entry;
544 while (entry->next) {
545 /* not again, please */
546 if (entry->apic == apic && entry->pin == pin)
552 entry->next = get_one_free_irq_2_pin(cpu);
559 * Reroute an IRQ to a different pin.
561 static void __init replace_pin_at_irq_cpu(struct irq_cfg *cfg, int cpu,
562 int oldapic, int oldpin,
563 int newapic, int newpin)
565 struct irq_pin_list *entry = cfg->irq_2_pin;
569 if (entry->apic == oldapic && entry->pin == oldpin) {
570 entry->apic = newapic;
573 /* every one is different, right? */
579 /* why? call replace before add? */
581 add_pin_to_irq_cpu(cfg, cpu, newapic, newpin);
584 static inline void io_apic_modify_irq(struct irq_cfg *cfg,
585 int mask_and, int mask_or,
586 void (*final)(struct irq_pin_list *entry))
589 struct irq_pin_list *entry;
591 for (entry = cfg->irq_2_pin; entry != NULL; entry = entry->next) {
594 reg = io_apic_read(entry->apic, 0x10 + pin * 2);
597 io_apic_modify(entry->apic, 0x10 + pin * 2, reg);
603 static void __unmask_IO_APIC_irq(struct irq_cfg *cfg)
605 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL);
609 static void io_apic_sync(struct irq_pin_list *entry)
612 * Synchronize the IO-APIC and the CPU by doing
613 * a dummy read from the IO-APIC
615 struct io_apic __iomem *io_apic;
616 io_apic = io_apic_base(entry->apic);
617 readl(&io_apic->data);
620 static void __mask_IO_APIC_irq(struct irq_cfg *cfg)
622 io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
624 #else /* CONFIG_X86_32 */
625 static void __mask_IO_APIC_irq(struct irq_cfg *cfg)
627 io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, NULL);
630 static void __mask_and_edge_IO_APIC_irq(struct irq_cfg *cfg)
632 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_LEVEL_TRIGGER,
633 IO_APIC_REDIR_MASKED, NULL);
636 static void __unmask_and_level_IO_APIC_irq(struct irq_cfg *cfg)
638 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED,
639 IO_APIC_REDIR_LEVEL_TRIGGER, NULL);
641 #endif /* CONFIG_X86_32 */
643 static void mask_IO_APIC_irq_desc(struct irq_desc *desc)
645 struct irq_cfg *cfg = desc->chip_data;
650 spin_lock_irqsave(&ioapic_lock, flags);
651 __mask_IO_APIC_irq(cfg);
652 spin_unlock_irqrestore(&ioapic_lock, flags);
655 static void unmask_IO_APIC_irq_desc(struct irq_desc *desc)
657 struct irq_cfg *cfg = desc->chip_data;
660 spin_lock_irqsave(&ioapic_lock, flags);
661 __unmask_IO_APIC_irq(cfg);
662 spin_unlock_irqrestore(&ioapic_lock, flags);
665 static void mask_IO_APIC_irq(unsigned int irq)
667 struct irq_desc *desc = irq_to_desc(irq);
669 mask_IO_APIC_irq_desc(desc);
671 static void unmask_IO_APIC_irq(unsigned int irq)
673 struct irq_desc *desc = irq_to_desc(irq);
675 unmask_IO_APIC_irq_desc(desc);
678 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
680 struct IO_APIC_route_entry entry;
682 /* Check delivery_mode to be sure we're not clearing an SMI pin */
683 entry = ioapic_read_entry(apic, pin);
684 if (entry.delivery_mode == dest_SMI)
687 * Disable it in the IO-APIC irq-routing table:
689 ioapic_mask_entry(apic, pin);
692 static void clear_IO_APIC (void)
696 for (apic = 0; apic < nr_ioapics; apic++)
697 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
698 clear_IO_APIC_pin(apic, pin);
703 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
704 * specific CPU-side IRQs.
708 static int pirq_entries[MAX_PIRQS] = {
709 [0 ... MAX_PIRQS - 1] = -1
712 static int __init ioapic_pirq_setup(char *str)
715 int ints[MAX_PIRQS+1];
717 get_options(str, ARRAY_SIZE(ints), ints);
719 apic_printk(APIC_VERBOSE, KERN_INFO
720 "PIRQ redirection, working around broken MP-BIOS.\n");
722 if (ints[0] < MAX_PIRQS)
725 for (i = 0; i < max; i++) {
726 apic_printk(APIC_VERBOSE, KERN_DEBUG
727 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
729 * PIRQs are mapped upside down, usually.
731 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
736 __setup("pirq=", ioapic_pirq_setup);
737 #endif /* CONFIG_X86_32 */
739 #ifdef CONFIG_INTR_REMAP
740 struct IO_APIC_route_entry **alloc_ioapic_entries(void)
743 struct IO_APIC_route_entry **ioapic_entries;
745 ioapic_entries = kzalloc(sizeof(*ioapic_entries) * nr_ioapics,
750 for (apic = 0; apic < nr_ioapics; apic++) {
751 ioapic_entries[apic] =
752 kzalloc(sizeof(struct IO_APIC_route_entry) *
753 nr_ioapic_registers[apic], GFP_ATOMIC);
754 if (!ioapic_entries[apic])
758 return ioapic_entries;
762 kfree(ioapic_entries[apic]);
763 kfree(ioapic_entries);
769 * Saves all the IO-APIC RTE's
771 int save_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
778 for (apic = 0; apic < nr_ioapics; apic++) {
779 if (!ioapic_entries[apic])
782 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
783 ioapic_entries[apic][pin] =
784 ioapic_read_entry(apic, pin);
791 * Mask all IO APIC entries.
793 void mask_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
800 for (apic = 0; apic < nr_ioapics; apic++) {
801 if (!ioapic_entries[apic])
804 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
805 struct IO_APIC_route_entry entry;
807 entry = ioapic_entries[apic][pin];
810 ioapic_write_entry(apic, pin, entry);
817 * Restore IO APIC entries which was saved in ioapic_entries.
819 int restore_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
826 for (apic = 0; apic < nr_ioapics; apic++) {
827 if (!ioapic_entries[apic])
830 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
831 ioapic_write_entry(apic, pin,
832 ioapic_entries[apic][pin]);
837 void reinit_intr_remapped_IO_APIC(int intr_remapping,
838 struct IO_APIC_route_entry **ioapic_entries)
842 * for now plain restore of previous settings.
843 * TBD: In the case of OS enabling interrupt-remapping,
844 * IO-APIC RTE's need to be setup to point to interrupt-remapping
845 * table entries. for now, do a plain restore, and wait for
846 * the setup_IO_APIC_irqs() to do proper initialization.
848 restore_IO_APIC_setup(ioapic_entries);
851 void free_ioapic_entries(struct IO_APIC_route_entry **ioapic_entries)
855 for (apic = 0; apic < nr_ioapics; apic++)
856 kfree(ioapic_entries[apic]);
858 kfree(ioapic_entries);
863 * Find the IRQ entry number of a certain pin.
865 static int find_irq_entry(int apic, int pin, int type)
869 for (i = 0; i < mp_irq_entries; i++)
870 if (mp_irqs[i].irqtype == type &&
871 (mp_irqs[i].dstapic == mp_ioapics[apic].apicid ||
872 mp_irqs[i].dstapic == MP_APIC_ALL) &&
873 mp_irqs[i].dstirq == pin)
880 * Find the pin to which IRQ[irq] (ISA) is connected
882 static int __init find_isa_irq_pin(int irq, int type)
886 for (i = 0; i < mp_irq_entries; i++) {
887 int lbus = mp_irqs[i].srcbus;
889 if (test_bit(lbus, mp_bus_not_pci) &&
890 (mp_irqs[i].irqtype == type) &&
891 (mp_irqs[i].srcbusirq == irq))
893 return mp_irqs[i].dstirq;
898 static int __init find_isa_irq_apic(int irq, int type)
902 for (i = 0; i < mp_irq_entries; i++) {
903 int lbus = mp_irqs[i].srcbus;
905 if (test_bit(lbus, mp_bus_not_pci) &&
906 (mp_irqs[i].irqtype == type) &&
907 (mp_irqs[i].srcbusirq == irq))
910 if (i < mp_irq_entries) {
912 for(apic = 0; apic < nr_ioapics; apic++) {
913 if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic)
922 * Find a specific PCI IRQ entry.
923 * Not an __init, possibly needed by modules
925 static int pin_2_irq(int idx, int apic, int pin);
927 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
929 int apic, i, best_guess = -1;
931 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
933 if (test_bit(bus, mp_bus_not_pci)) {
934 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
937 for (i = 0; i < mp_irq_entries; i++) {
938 int lbus = mp_irqs[i].srcbus;
940 for (apic = 0; apic < nr_ioapics; apic++)
941 if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic ||
942 mp_irqs[i].dstapic == MP_APIC_ALL)
945 if (!test_bit(lbus, mp_bus_not_pci) &&
946 !mp_irqs[i].irqtype &&
948 (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) {
949 int irq = pin_2_irq(i, apic, mp_irqs[i].dstirq);
951 if (!(apic || IO_APIC_IRQ(irq)))
954 if (pin == (mp_irqs[i].srcbusirq & 3))
957 * Use the first all-but-pin matching entry as a
958 * best-guess fuzzy result for broken mptables.
967 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
969 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
971 * EISA Edge/Level control register, ELCR
973 static int EISA_ELCR(unsigned int irq)
975 if (irq < NR_IRQS_LEGACY) {
976 unsigned int port = 0x4d0 + (irq >> 3);
977 return (inb(port) >> (irq & 7)) & 1;
979 apic_printk(APIC_VERBOSE, KERN_INFO
980 "Broken MPtable reports ISA irq %d\n", irq);
986 /* ISA interrupts are always polarity zero edge triggered,
987 * when listed as conforming in the MP table. */
989 #define default_ISA_trigger(idx) (0)
990 #define default_ISA_polarity(idx) (0)
992 /* EISA interrupts are always polarity zero and can be edge or level
993 * trigger depending on the ELCR value. If an interrupt is listed as
994 * EISA conforming in the MP table, that means its trigger type must
995 * be read in from the ELCR */
997 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq))
998 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
1000 /* PCI interrupts are always polarity one level triggered,
1001 * when listed as conforming in the MP table. */
1003 #define default_PCI_trigger(idx) (1)
1004 #define default_PCI_polarity(idx) (1)
1006 /* MCA interrupts are always polarity zero level triggered,
1007 * when listed as conforming in the MP table. */
1009 #define default_MCA_trigger(idx) (1)
1010 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
1012 static int MPBIOS_polarity(int idx)
1014 int bus = mp_irqs[idx].srcbus;
1018 * Determine IRQ line polarity (high active or low active):
1020 switch (mp_irqs[idx].irqflag & 3)
1022 case 0: /* conforms, ie. bus-type dependent polarity */
1023 if (test_bit(bus, mp_bus_not_pci))
1024 polarity = default_ISA_polarity(idx);
1026 polarity = default_PCI_polarity(idx);
1028 case 1: /* high active */
1033 case 2: /* reserved */
1035 printk(KERN_WARNING "broken BIOS!!\n");
1039 case 3: /* low active */
1044 default: /* invalid */
1046 printk(KERN_WARNING "broken BIOS!!\n");
1054 static int MPBIOS_trigger(int idx)
1056 int bus = mp_irqs[idx].srcbus;
1060 * Determine IRQ trigger mode (edge or level sensitive):
1062 switch ((mp_irqs[idx].irqflag>>2) & 3)
1064 case 0: /* conforms, ie. bus-type dependent */
1065 if (test_bit(bus, mp_bus_not_pci))
1066 trigger = default_ISA_trigger(idx);
1068 trigger = default_PCI_trigger(idx);
1069 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1070 switch (mp_bus_id_to_type[bus]) {
1071 case MP_BUS_ISA: /* ISA pin */
1073 /* set before the switch */
1076 case MP_BUS_EISA: /* EISA pin */
1078 trigger = default_EISA_trigger(idx);
1081 case MP_BUS_PCI: /* PCI pin */
1083 /* set before the switch */
1086 case MP_BUS_MCA: /* MCA pin */
1088 trigger = default_MCA_trigger(idx);
1093 printk(KERN_WARNING "broken BIOS!!\n");
1105 case 2: /* reserved */
1107 printk(KERN_WARNING "broken BIOS!!\n");
1116 default: /* invalid */
1118 printk(KERN_WARNING "broken BIOS!!\n");
1126 static inline int irq_polarity(int idx)
1128 return MPBIOS_polarity(idx);
1131 static inline int irq_trigger(int idx)
1133 return MPBIOS_trigger(idx);
1136 int (*ioapic_renumber_irq)(int ioapic, int irq);
1137 static int pin_2_irq(int idx, int apic, int pin)
1140 int bus = mp_irqs[idx].srcbus;
1143 * Debugging check, we are in big trouble if this message pops up!
1145 if (mp_irqs[idx].dstirq != pin)
1146 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1148 if (test_bit(bus, mp_bus_not_pci)) {
1149 irq = mp_irqs[idx].srcbusirq;
1152 * PCI IRQs are mapped in order
1156 irq += nr_ioapic_registers[i++];
1159 * For MPS mode, so far only needed by ES7000 platform
1161 if (ioapic_renumber_irq)
1162 irq = ioapic_renumber_irq(apic, irq);
1165 #ifdef CONFIG_X86_32
1167 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1169 if ((pin >= 16) && (pin <= 23)) {
1170 if (pirq_entries[pin-16] != -1) {
1171 if (!pirq_entries[pin-16]) {
1172 apic_printk(APIC_VERBOSE, KERN_DEBUG
1173 "disabling PIRQ%d\n", pin-16);
1175 irq = pirq_entries[pin-16];
1176 apic_printk(APIC_VERBOSE, KERN_DEBUG
1177 "using PIRQ%d -> IRQ %d\n",
1187 void lock_vector_lock(void)
1189 /* Used to the online set of cpus does not change
1190 * during assign_irq_vector.
1192 spin_lock(&vector_lock);
1195 void unlock_vector_lock(void)
1197 spin_unlock(&vector_lock);
1201 __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1204 * NOTE! The local APIC isn't very good at handling
1205 * multiple interrupts at the same interrupt level.
1206 * As the interrupt level is determined by taking the
1207 * vector number and shifting that right by 4, we
1208 * want to spread these out a bit so that they don't
1209 * all fall in the same interrupt level.
1211 * Also, we've got to be careful not to trash gate
1212 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1214 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
1215 unsigned int old_vector;
1217 cpumask_var_t tmp_mask;
1219 if ((cfg->move_in_progress) || cfg->move_cleanup_count)
1222 if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC))
1225 old_vector = cfg->vector;
1227 cpumask_and(tmp_mask, mask, cpu_online_mask);
1228 cpumask_and(tmp_mask, cfg->domain, tmp_mask);
1229 if (!cpumask_empty(tmp_mask)) {
1230 free_cpumask_var(tmp_mask);
1235 /* Only try and allocate irqs on cpus that are present */
1237 for_each_cpu_and(cpu, mask, cpu_online_mask) {
1241 apic->vector_allocation_domain(cpu, tmp_mask);
1243 vector = current_vector;
1244 offset = current_offset;
1247 if (vector >= first_system_vector) {
1248 /* If out of vectors on large boxen, must share them. */
1249 offset = (offset + 1) % 8;
1250 vector = FIRST_DEVICE_VECTOR + offset;
1252 if (unlikely(current_vector == vector))
1255 if (test_bit(vector, used_vectors))
1258 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1259 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
1262 current_vector = vector;
1263 current_offset = offset;
1265 cfg->move_in_progress = 1;
1266 cpumask_copy(cfg->old_domain, cfg->domain);
1268 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1269 per_cpu(vector_irq, new_cpu)[vector] = irq;
1270 cfg->vector = vector;
1271 cpumask_copy(cfg->domain, tmp_mask);
1275 free_cpumask_var(tmp_mask);
1280 assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1283 unsigned long flags;
1285 spin_lock_irqsave(&vector_lock, flags);
1286 err = __assign_irq_vector(irq, cfg, mask);
1287 spin_unlock_irqrestore(&vector_lock, flags);
1291 static void __clear_irq_vector(int irq, struct irq_cfg *cfg)
1295 BUG_ON(!cfg->vector);
1297 vector = cfg->vector;
1298 for_each_cpu_and(cpu, cfg->domain, cpu_online_mask)
1299 per_cpu(vector_irq, cpu)[vector] = -1;
1302 cpumask_clear(cfg->domain);
1304 if (likely(!cfg->move_in_progress))
1306 for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) {
1307 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
1309 if (per_cpu(vector_irq, cpu)[vector] != irq)
1311 per_cpu(vector_irq, cpu)[vector] = -1;
1315 cfg->move_in_progress = 0;
1318 void __setup_vector_irq(int cpu)
1320 /* Initialize vector_irq on a new cpu */
1321 /* This function must be called with vector_lock held */
1323 struct irq_cfg *cfg;
1324 struct irq_desc *desc;
1326 /* Mark the inuse vectors */
1327 for_each_irq_desc(irq, desc) {
1328 cfg = desc->chip_data;
1329 if (!cpumask_test_cpu(cpu, cfg->domain))
1331 vector = cfg->vector;
1332 per_cpu(vector_irq, cpu)[vector] = irq;
1334 /* Mark the free vectors */
1335 for (vector = 0; vector < NR_VECTORS; ++vector) {
1336 irq = per_cpu(vector_irq, cpu)[vector];
1341 if (!cpumask_test_cpu(cpu, cfg->domain))
1342 per_cpu(vector_irq, cpu)[vector] = -1;
1346 static struct irq_chip ioapic_chip;
1347 static struct irq_chip ir_ioapic_chip;
1349 #define IOAPIC_AUTO -1
1350 #define IOAPIC_EDGE 0
1351 #define IOAPIC_LEVEL 1
1353 #ifdef CONFIG_X86_32
1354 static inline int IO_APIC_irq_trigger(int irq)
1358 for (apic = 0; apic < nr_ioapics; apic++) {
1359 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1360 idx = find_irq_entry(apic, pin, mp_INT);
1361 if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1362 return irq_trigger(idx);
1366 * nonexistent IRQs are edge default
1371 static inline int IO_APIC_irq_trigger(int irq)
1377 static void ioapic_register_intr(int irq, struct irq_desc *desc, unsigned long trigger)
1380 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1381 trigger == IOAPIC_LEVEL)
1382 desc->status |= IRQ_LEVEL;
1384 desc->status &= ~IRQ_LEVEL;
1386 if (irq_remapped(irq)) {
1387 desc->status |= IRQ_MOVE_PCNTXT;
1389 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1393 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1394 handle_edge_irq, "edge");
1398 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1399 trigger == IOAPIC_LEVEL)
1400 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1404 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1405 handle_edge_irq, "edge");
1408 int setup_ioapic_entry(int apic_id, int irq,
1409 struct IO_APIC_route_entry *entry,
1410 unsigned int destination, int trigger,
1411 int polarity, int vector, int pin)
1414 * add it to the IO-APIC irq-routing table:
1416 memset(entry,0,sizeof(*entry));
1418 if (intr_remapping_enabled) {
1419 struct intel_iommu *iommu = map_ioapic_to_ir(apic_id);
1421 struct IR_IO_APIC_route_entry *ir_entry =
1422 (struct IR_IO_APIC_route_entry *) entry;
1426 panic("No mapping iommu for ioapic %d\n", apic_id);
1428 index = alloc_irte(iommu, irq, 1);
1430 panic("Failed to allocate IRTE for ioapic %d\n", apic_id);
1432 memset(&irte, 0, sizeof(irte));
1435 irte.dst_mode = apic->irq_dest_mode;
1437 * Trigger mode in the IRTE will always be edge, and the
1438 * actual level or edge trigger will be setup in the IO-APIC
1439 * RTE. This will help simplify level triggered irq migration.
1440 * For more details, see the comments above explainig IO-APIC
1441 * irq migration in the presence of interrupt-remapping.
1443 irte.trigger_mode = 0;
1444 irte.dlvry_mode = apic->irq_delivery_mode;
1445 irte.vector = vector;
1446 irte.dest_id = IRTE_DEST(destination);
1448 modify_irte(irq, &irte);
1450 ir_entry->index2 = (index >> 15) & 0x1;
1452 ir_entry->format = 1;
1453 ir_entry->index = (index & 0x7fff);
1455 * IO-APIC RTE will be configured with virtual vector.
1456 * irq handler will do the explicit EOI to the io-apic.
1458 ir_entry->vector = pin;
1460 entry->delivery_mode = apic->irq_delivery_mode;
1461 entry->dest_mode = apic->irq_dest_mode;
1462 entry->dest = destination;
1463 entry->vector = vector;
1466 entry->mask = 0; /* enable IRQ */
1467 entry->trigger = trigger;
1468 entry->polarity = polarity;
1470 /* Mask level triggered irqs.
1471 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1478 static void setup_IO_APIC_irq(int apic_id, int pin, unsigned int irq, struct irq_desc *desc,
1479 int trigger, int polarity)
1481 struct irq_cfg *cfg;
1482 struct IO_APIC_route_entry entry;
1485 if (!IO_APIC_IRQ(irq))
1488 cfg = desc->chip_data;
1490 if (assign_irq_vector(irq, cfg, apic->target_cpus()))
1493 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
1495 apic_printk(APIC_VERBOSE,KERN_DEBUG
1496 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1497 "IRQ %d Mode:%i Active:%i)\n",
1498 apic_id, mp_ioapics[apic_id].apicid, pin, cfg->vector,
1499 irq, trigger, polarity);
1502 if (setup_ioapic_entry(mp_ioapics[apic_id].apicid, irq, &entry,
1503 dest, trigger, polarity, cfg->vector, pin)) {
1504 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1505 mp_ioapics[apic_id].apicid, pin);
1506 __clear_irq_vector(irq, cfg);
1510 ioapic_register_intr(irq, desc, trigger);
1511 if (irq < NR_IRQS_LEGACY)
1512 disable_8259A_irq(irq);
1514 ioapic_write_entry(apic_id, pin, entry);
1517 static void __init setup_IO_APIC_irqs(void)
1519 int apic_id, pin, idx, irq;
1521 struct irq_desc *desc;
1522 struct irq_cfg *cfg;
1523 int cpu = boot_cpu_id;
1525 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1527 for (apic_id = 0; apic_id < nr_ioapics; apic_id++) {
1528 for (pin = 0; pin < nr_ioapic_registers[apic_id]; pin++) {
1530 idx = find_irq_entry(apic_id, pin, mp_INT);
1534 apic_printk(APIC_VERBOSE,
1535 KERN_DEBUG " %d-%d",
1536 mp_ioapics[apic_id].apicid, pin);
1538 apic_printk(APIC_VERBOSE, " %d-%d",
1539 mp_ioapics[apic_id].apicid, pin);
1543 apic_printk(APIC_VERBOSE,
1544 " (apicid-pin) not connected\n");
1548 irq = pin_2_irq(idx, apic_id, pin);
1551 * Skip the timer IRQ if there's a quirk handler
1552 * installed and if it returns 1:
1554 if (apic->multi_timer_check &&
1555 apic->multi_timer_check(apic_id, irq))
1558 desc = irq_to_desc_alloc_cpu(irq, cpu);
1560 printk(KERN_INFO "can not get irq_desc for %d\n", irq);
1563 cfg = desc->chip_data;
1564 add_pin_to_irq_cpu(cfg, cpu, apic_id, pin);
1566 setup_IO_APIC_irq(apic_id, pin, irq, desc,
1567 irq_trigger(idx), irq_polarity(idx));
1572 apic_printk(APIC_VERBOSE,
1573 " (apicid-pin) not connected\n");
1577 * Set up the timer pin, possibly with the 8259A-master behind.
1579 static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin,
1582 struct IO_APIC_route_entry entry;
1584 if (intr_remapping_enabled)
1587 memset(&entry, 0, sizeof(entry));
1590 * We use logical delivery to get the timer IRQ
1593 entry.dest_mode = apic->irq_dest_mode;
1594 entry.mask = 0; /* don't mask IRQ for edge */
1595 entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus());
1596 entry.delivery_mode = apic->irq_delivery_mode;
1599 entry.vector = vector;
1602 * The timer IRQ doesn't have to know that behind the
1603 * scene we may have a 8259A-master in AEOI mode ...
1605 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
1608 * Add it to the IO-APIC irq-routing table:
1610 ioapic_write_entry(apic_id, pin, entry);
1614 __apicdebuginit(void) print_IO_APIC(void)
1617 union IO_APIC_reg_00 reg_00;
1618 union IO_APIC_reg_01 reg_01;
1619 union IO_APIC_reg_02 reg_02;
1620 union IO_APIC_reg_03 reg_03;
1621 unsigned long flags;
1622 struct irq_cfg *cfg;
1623 struct irq_desc *desc;
1626 if (apic_verbosity == APIC_QUIET)
1629 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1630 for (i = 0; i < nr_ioapics; i++)
1631 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1632 mp_ioapics[i].apicid, nr_ioapic_registers[i]);
1635 * We are a bit conservative about what we expect. We have to
1636 * know about every hardware change ASAP.
1638 printk(KERN_INFO "testing the IO APIC.......................\n");
1640 for (apic = 0; apic < nr_ioapics; apic++) {
1642 spin_lock_irqsave(&ioapic_lock, flags);
1643 reg_00.raw = io_apic_read(apic, 0);
1644 reg_01.raw = io_apic_read(apic, 1);
1645 if (reg_01.bits.version >= 0x10)
1646 reg_02.raw = io_apic_read(apic, 2);
1647 if (reg_01.bits.version >= 0x20)
1648 reg_03.raw = io_apic_read(apic, 3);
1649 spin_unlock_irqrestore(&ioapic_lock, flags);
1652 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].apicid);
1653 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1654 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1655 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1656 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1658 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
1659 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1661 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1662 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1665 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1666 * but the value of reg_02 is read as the previous read register
1667 * value, so ignore it if reg_02 == reg_01.
1669 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1670 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1671 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1675 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1676 * or reg_03, but the value of reg_0[23] is read as the previous read
1677 * register value, so ignore it if reg_03 == reg_0[12].
1679 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1680 reg_03.raw != reg_01.raw) {
1681 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1682 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1685 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1687 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1688 " Stat Dmod Deli Vect: \n");
1690 for (i = 0; i <= reg_01.bits.entries; i++) {
1691 struct IO_APIC_route_entry entry;
1693 entry = ioapic_read_entry(apic, i);
1695 printk(KERN_DEBUG " %02x %03X ",
1700 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1705 entry.delivery_status,
1707 entry.delivery_mode,
1712 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1713 for_each_irq_desc(irq, desc) {
1714 struct irq_pin_list *entry;
1716 cfg = desc->chip_data;
1717 entry = cfg->irq_2_pin;
1720 printk(KERN_DEBUG "IRQ%d ", irq);
1722 printk("-> %d:%d", entry->apic, entry->pin);
1725 entry = entry->next;
1730 printk(KERN_INFO ".................................... done.\n");
1735 __apicdebuginit(void) print_APIC_bitfield(int base)
1740 if (apic_verbosity == APIC_QUIET)
1743 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1744 for (i = 0; i < 8; i++) {
1745 v = apic_read(base + i*0x10);
1746 for (j = 0; j < 32; j++) {
1756 __apicdebuginit(void) print_local_APIC(void *dummy)
1758 unsigned int v, ver, maxlvt;
1761 if (apic_verbosity == APIC_QUIET)
1764 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1765 smp_processor_id(), hard_smp_processor_id());
1766 v = apic_read(APIC_ID);
1767 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id());
1768 v = apic_read(APIC_LVR);
1769 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1770 ver = GET_APIC_VERSION(v);
1771 maxlvt = lapic_get_maxlvt();
1773 v = apic_read(APIC_TASKPRI);
1774 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1776 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1777 if (!APIC_XAPIC(ver)) {
1778 v = apic_read(APIC_ARBPRI);
1779 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1780 v & APIC_ARBPRI_MASK);
1782 v = apic_read(APIC_PROCPRI);
1783 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1787 * Remote read supported only in the 82489DX and local APIC for
1788 * Pentium processors.
1790 if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
1791 v = apic_read(APIC_RRR);
1792 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1795 v = apic_read(APIC_LDR);
1796 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1797 if (!x2apic_enabled()) {
1798 v = apic_read(APIC_DFR);
1799 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1801 v = apic_read(APIC_SPIV);
1802 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1804 printk(KERN_DEBUG "... APIC ISR field:\n");
1805 print_APIC_bitfield(APIC_ISR);
1806 printk(KERN_DEBUG "... APIC TMR field:\n");
1807 print_APIC_bitfield(APIC_TMR);
1808 printk(KERN_DEBUG "... APIC IRR field:\n");
1809 print_APIC_bitfield(APIC_IRR);
1811 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1812 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1813 apic_write(APIC_ESR, 0);
1815 v = apic_read(APIC_ESR);
1816 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1819 icr = apic_icr_read();
1820 printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
1821 printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
1823 v = apic_read(APIC_LVTT);
1824 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1826 if (maxlvt > 3) { /* PC is LVT#4. */
1827 v = apic_read(APIC_LVTPC);
1828 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1830 v = apic_read(APIC_LVT0);
1831 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1832 v = apic_read(APIC_LVT1);
1833 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1835 if (maxlvt > 2) { /* ERR is LVT#3. */
1836 v = apic_read(APIC_LVTERR);
1837 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1840 v = apic_read(APIC_TMICT);
1841 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1842 v = apic_read(APIC_TMCCT);
1843 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1844 v = apic_read(APIC_TDCR);
1845 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1849 __apicdebuginit(void) print_all_local_APICs(void)
1854 for_each_online_cpu(cpu)
1855 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
1859 __apicdebuginit(void) print_PIC(void)
1862 unsigned long flags;
1864 if (apic_verbosity == APIC_QUIET)
1867 printk(KERN_DEBUG "\nprinting PIC contents\n");
1869 spin_lock_irqsave(&i8259A_lock, flags);
1871 v = inb(0xa1) << 8 | inb(0x21);
1872 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1874 v = inb(0xa0) << 8 | inb(0x20);
1875 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1879 v = inb(0xa0) << 8 | inb(0x20);
1883 spin_unlock_irqrestore(&i8259A_lock, flags);
1885 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1887 v = inb(0x4d1) << 8 | inb(0x4d0);
1888 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1891 __apicdebuginit(int) print_all_ICs(void)
1894 print_all_local_APICs();
1900 fs_initcall(print_all_ICs);
1903 /* Where if anywhere is the i8259 connect in external int mode */
1904 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1906 void __init enable_IO_APIC(void)
1908 union IO_APIC_reg_01 reg_01;
1909 int i8259_apic, i8259_pin;
1911 unsigned long flags;
1914 * The number of IO-APIC IRQ registers (== #pins):
1916 for (apic = 0; apic < nr_ioapics; apic++) {
1917 spin_lock_irqsave(&ioapic_lock, flags);
1918 reg_01.raw = io_apic_read(apic, 1);
1919 spin_unlock_irqrestore(&ioapic_lock, flags);
1920 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1922 for(apic = 0; apic < nr_ioapics; apic++) {
1924 /* See if any of the pins is in ExtINT mode */
1925 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1926 struct IO_APIC_route_entry entry;
1927 entry = ioapic_read_entry(apic, pin);
1929 /* If the interrupt line is enabled and in ExtInt mode
1930 * I have found the pin where the i8259 is connected.
1932 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1933 ioapic_i8259.apic = apic;
1934 ioapic_i8259.pin = pin;
1940 /* Look to see what if the MP table has reported the ExtINT */
1941 /* If we could not find the appropriate pin by looking at the ioapic
1942 * the i8259 probably is not connected the ioapic but give the
1943 * mptable a chance anyway.
1945 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1946 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1947 /* Trust the MP table if nothing is setup in the hardware */
1948 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1949 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1950 ioapic_i8259.pin = i8259_pin;
1951 ioapic_i8259.apic = i8259_apic;
1953 /* Complain if the MP table and the hardware disagree */
1954 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1955 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1957 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1961 * Do not trust the IO-APIC being empty at bootup
1967 * Not an __init, needed by the reboot code
1969 void disable_IO_APIC(void)
1972 * Clear the IO-APIC before rebooting:
1977 * If the i8259 is routed through an IOAPIC
1978 * Put that IOAPIC in virtual wire mode
1979 * so legacy interrupts can be delivered.
1981 * With interrupt-remapping, for now we will use virtual wire A mode,
1982 * as virtual wire B is little complex (need to configure both
1983 * IOAPIC RTE aswell as interrupt-remapping table entry).
1984 * As this gets called during crash dump, keep this simple for now.
1986 if (ioapic_i8259.pin != -1 && !intr_remapping_enabled) {
1987 struct IO_APIC_route_entry entry;
1989 memset(&entry, 0, sizeof(entry));
1990 entry.mask = 0; /* Enabled */
1991 entry.trigger = 0; /* Edge */
1993 entry.polarity = 0; /* High */
1994 entry.delivery_status = 0;
1995 entry.dest_mode = 0; /* Physical */
1996 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1998 entry.dest = read_apic_id();
2001 * Add it to the IO-APIC irq-routing table:
2003 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
2007 * Use virtual wire A mode when interrupt remapping is enabled.
2009 disconnect_bsp_APIC(!intr_remapping_enabled && ioapic_i8259.pin != -1);
2012 #ifdef CONFIG_X86_32
2014 * function to set the IO-APIC physical IDs based on the
2015 * values stored in the MPC table.
2017 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
2020 static void __init setup_ioapic_ids_from_mpc(void)
2022 union IO_APIC_reg_00 reg_00;
2023 physid_mask_t phys_id_present_map;
2026 unsigned char old_id;
2027 unsigned long flags;
2029 if (x86_quirks->setup_ioapic_ids && x86_quirks->setup_ioapic_ids())
2033 * Don't check I/O APIC IDs for xAPIC systems. They have
2034 * no meaning without the serial APIC bus.
2036 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
2037 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
2040 * This is broken; anything with a real cpu count has to
2041 * circumvent this idiocy regardless.
2043 phys_id_present_map = apic->ioapic_phys_id_map(phys_cpu_present_map);
2046 * Set the IOAPIC ID to the value stored in the MPC table.
2048 for (apic_id = 0; apic_id < nr_ioapics; apic_id++) {
2050 /* Read the register 0 value */
2051 spin_lock_irqsave(&ioapic_lock, flags);
2052 reg_00.raw = io_apic_read(apic_id, 0);
2053 spin_unlock_irqrestore(&ioapic_lock, flags);
2055 old_id = mp_ioapics[apic_id].apicid;
2057 if (mp_ioapics[apic_id].apicid >= get_physical_broadcast()) {
2058 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
2059 apic_id, mp_ioapics[apic_id].apicid);
2060 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2062 mp_ioapics[apic_id].apicid = reg_00.bits.ID;
2066 * Sanity check, is the ID really free? Every APIC in a
2067 * system must have a unique ID or we get lots of nice
2068 * 'stuck on smp_invalidate_needed IPI wait' messages.
2070 if (apic->check_apicid_used(phys_id_present_map,
2071 mp_ioapics[apic_id].apicid)) {
2072 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
2073 apic_id, mp_ioapics[apic_id].apicid);
2074 for (i = 0; i < get_physical_broadcast(); i++)
2075 if (!physid_isset(i, phys_id_present_map))
2077 if (i >= get_physical_broadcast())
2078 panic("Max APIC ID exceeded!\n");
2079 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2081 physid_set(i, phys_id_present_map);
2082 mp_ioapics[apic_id].apicid = i;
2085 tmp = apic->apicid_to_cpu_present(mp_ioapics[apic_id].apicid);
2086 apic_printk(APIC_VERBOSE, "Setting %d in the "
2087 "phys_id_present_map\n",
2088 mp_ioapics[apic_id].apicid);
2089 physids_or(phys_id_present_map, phys_id_present_map, tmp);
2094 * We need to adjust the IRQ routing table
2095 * if the ID changed.
2097 if (old_id != mp_ioapics[apic_id].apicid)
2098 for (i = 0; i < mp_irq_entries; i++)
2099 if (mp_irqs[i].dstapic == old_id)
2101 = mp_ioapics[apic_id].apicid;
2104 * Read the right value from the MPC table and
2105 * write it into the ID register.
2107 apic_printk(APIC_VERBOSE, KERN_INFO
2108 "...changing IO-APIC physical APIC ID to %d ...",
2109 mp_ioapics[apic_id].apicid);
2111 reg_00.bits.ID = mp_ioapics[apic_id].apicid;
2112 spin_lock_irqsave(&ioapic_lock, flags);
2113 io_apic_write(apic_id, 0, reg_00.raw);
2114 spin_unlock_irqrestore(&ioapic_lock, flags);
2119 spin_lock_irqsave(&ioapic_lock, flags);
2120 reg_00.raw = io_apic_read(apic_id, 0);
2121 spin_unlock_irqrestore(&ioapic_lock, flags);
2122 if (reg_00.bits.ID != mp_ioapics[apic_id].apicid)
2123 printk("could not set ID!\n");
2125 apic_printk(APIC_VERBOSE, " ok.\n");
2130 int no_timer_check __initdata;
2132 static int __init notimercheck(char *s)
2137 __setup("no_timer_check", notimercheck);
2140 * There is a nasty bug in some older SMP boards, their mptable lies
2141 * about the timer IRQ. We do the following to work around the situation:
2143 * - timer IRQ defaults to IO-APIC IRQ
2144 * - if this function detects that timer IRQs are defunct, then we fall
2145 * back to ISA timer IRQs
2147 static int __init timer_irq_works(void)
2149 unsigned long t1 = jiffies;
2150 unsigned long flags;
2155 local_save_flags(flags);
2157 /* Let ten ticks pass... */
2158 mdelay((10 * 1000) / HZ);
2159 local_irq_restore(flags);
2162 * Expect a few ticks at least, to be sure some possible
2163 * glue logic does not lock up after one or two first
2164 * ticks in a non-ExtINT mode. Also the local APIC
2165 * might have cached one ExtINT interrupt. Finally, at
2166 * least one tick may be lost due to delays.
2170 if (time_after(jiffies, t1 + 4))
2176 * In the SMP+IOAPIC case it might happen that there are an unspecified
2177 * number of pending IRQ events unhandled. These cases are very rare,
2178 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2179 * better to do it this way as thus we do not have to be aware of
2180 * 'pending' interrupts in the IRQ path, except at this point.
2183 * Edge triggered needs to resend any interrupt
2184 * that was delayed but this is now handled in the device
2189 * Starting up a edge-triggered IO-APIC interrupt is
2190 * nasty - we need to make sure that we get the edge.
2191 * If it is already asserted for some reason, we need
2192 * return 1 to indicate that is was pending.
2194 * This is not complete - we should be able to fake
2195 * an edge even if it isn't on the 8259A...
2198 static unsigned int startup_ioapic_irq(unsigned int irq)
2200 int was_pending = 0;
2201 unsigned long flags;
2202 struct irq_cfg *cfg;
2204 spin_lock_irqsave(&ioapic_lock, flags);
2205 if (irq < NR_IRQS_LEGACY) {
2206 disable_8259A_irq(irq);
2207 if (i8259A_irq_pending(irq))
2211 __unmask_IO_APIC_irq(cfg);
2212 spin_unlock_irqrestore(&ioapic_lock, flags);
2217 #ifdef CONFIG_X86_64
2218 static int ioapic_retrigger_irq(unsigned int irq)
2221 struct irq_cfg *cfg = irq_cfg(irq);
2222 unsigned long flags;
2224 spin_lock_irqsave(&vector_lock, flags);
2225 apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector);
2226 spin_unlock_irqrestore(&vector_lock, flags);
2231 static int ioapic_retrigger_irq(unsigned int irq)
2233 apic->send_IPI_self(irq_cfg(irq)->vector);
2240 * Level and edge triggered IO-APIC interrupts need different handling,
2241 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2242 * handled with the level-triggered descriptor, but that one has slightly
2243 * more overhead. Level-triggered interrupts cannot be handled with the
2244 * edge-triggered handler, without risking IRQ storms and other ugly
2249 static void send_cleanup_vector(struct irq_cfg *cfg)
2251 cpumask_var_t cleanup_mask;
2253 if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) {
2255 cfg->move_cleanup_count = 0;
2256 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
2257 cfg->move_cleanup_count++;
2258 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
2259 apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR);
2261 cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask);
2262 cfg->move_cleanup_count = cpumask_weight(cleanup_mask);
2263 apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
2264 free_cpumask_var(cleanup_mask);
2266 cfg->move_in_progress = 0;
2270 __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg)
2273 struct irq_pin_list *entry;
2274 u8 vector = cfg->vector;
2276 entry = cfg->irq_2_pin;
2286 * With interrupt-remapping, destination information comes
2287 * from interrupt-remapping table entry.
2289 if (!irq_remapped(irq))
2290 io_apic_write(apic, 0x11 + pin*2, dest);
2291 reg = io_apic_read(apic, 0x10 + pin*2);
2292 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
2294 io_apic_modify(apic, 0x10 + pin*2, reg);
2297 entry = entry->next;
2302 * Either sets desc->affinity to a valid value, and returns
2303 * ->cpu_mask_to_apicid of that, or returns BAD_APICID and
2304 * leaves desc->affinity untouched.
2307 set_desc_affinity(struct irq_desc *desc, const struct cpumask *mask)
2309 struct irq_cfg *cfg;
2312 if (!cpumask_intersects(mask, cpu_online_mask))
2316 cfg = desc->chip_data;
2317 if (assign_irq_vector(irq, cfg, mask))
2320 /* check that before desc->addinity get updated */
2321 set_extra_move_desc(desc, mask);
2323 cpumask_copy(desc->affinity, mask);
2325 return apic->cpu_mask_to_apicid_and(desc->affinity, cfg->domain);
2329 set_ioapic_affinity_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
2331 struct irq_cfg *cfg;
2332 unsigned long flags;
2337 cfg = desc->chip_data;
2339 spin_lock_irqsave(&ioapic_lock, flags);
2340 dest = set_desc_affinity(desc, mask);
2341 if (dest != BAD_APICID) {
2342 /* Only the high 8 bits are valid. */
2343 dest = SET_APIC_LOGICAL_ID(dest);
2344 __target_IO_APIC_irq(irq, dest, cfg);
2346 spin_unlock_irqrestore(&ioapic_lock, flags);
2350 set_ioapic_affinity_irq(unsigned int irq, const struct cpumask *mask)
2352 struct irq_desc *desc;
2354 desc = irq_to_desc(irq);
2356 set_ioapic_affinity_irq_desc(desc, mask);
2359 #ifdef CONFIG_INTR_REMAP
2362 * Migrate the IO-APIC irq in the presence of intr-remapping.
2364 * For both level and edge triggered, irq migration is a simple atomic
2365 * update(of vector and cpu destination) of IRTE and flush the hardware cache.
2367 * For level triggered, we eliminate the io-apic RTE modification (with the
2368 * updated vector information), by using a virtual vector (io-apic pin number).
2369 * Real vector that is used for interrupting cpu will be coming from
2370 * the interrupt-remapping table entry.
2373 migrate_ioapic_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
2375 struct irq_cfg *cfg;
2380 if (!cpumask_intersects(mask, cpu_online_mask))
2384 if (get_irte(irq, &irte))
2387 cfg = desc->chip_data;
2388 if (assign_irq_vector(irq, cfg, mask))
2391 set_extra_move_desc(desc, mask);
2393 dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask);
2395 irte.vector = cfg->vector;
2396 irte.dest_id = IRTE_DEST(dest);
2399 * Modified the IRTE and flushes the Interrupt entry cache.
2401 modify_irte(irq, &irte);
2403 if (cfg->move_in_progress)
2404 send_cleanup_vector(cfg);
2406 cpumask_copy(desc->affinity, mask);
2410 * Migrates the IRQ destination in the process context.
2412 static void set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
2413 const struct cpumask *mask)
2415 migrate_ioapic_irq_desc(desc, mask);
2417 static void set_ir_ioapic_affinity_irq(unsigned int irq,
2418 const struct cpumask *mask)
2420 struct irq_desc *desc = irq_to_desc(irq);
2422 set_ir_ioapic_affinity_irq_desc(desc, mask);
2425 static inline void set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
2426 const struct cpumask *mask)
2431 asmlinkage void smp_irq_move_cleanup_interrupt(void)
2433 unsigned vector, me;
2439 me = smp_processor_id();
2440 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
2443 struct irq_desc *desc;
2444 struct irq_cfg *cfg;
2445 irq = __get_cpu_var(vector_irq)[vector];
2450 desc = irq_to_desc(irq);
2455 spin_lock(&desc->lock);
2456 if (!cfg->move_cleanup_count)
2459 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2462 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
2464 * Check if the vector that needs to be cleanedup is
2465 * registered at the cpu's IRR. If so, then this is not
2466 * the best time to clean it up. Lets clean it up in the
2467 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
2470 if (irr & (1 << (vector % 32))) {
2471 apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR);
2474 __get_cpu_var(vector_irq)[vector] = -1;
2475 cfg->move_cleanup_count--;
2477 spin_unlock(&desc->lock);
2483 static void irq_complete_move(struct irq_desc **descp)
2485 struct irq_desc *desc = *descp;
2486 struct irq_cfg *cfg = desc->chip_data;
2487 unsigned vector, me;
2489 if (likely(!cfg->move_in_progress)) {
2490 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
2491 if (likely(!cfg->move_desc_pending))
2494 /* domain has not changed, but affinity did */
2495 me = smp_processor_id();
2496 if (cpumask_test_cpu(me, desc->affinity)) {
2497 *descp = desc = move_irq_desc(desc, me);
2498 /* get the new one */
2499 cfg = desc->chip_data;
2500 cfg->move_desc_pending = 0;
2506 vector = ~get_irq_regs()->orig_ax;
2507 me = smp_processor_id();
2509 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) {
2510 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
2511 *descp = desc = move_irq_desc(desc, me);
2512 /* get the new one */
2513 cfg = desc->chip_data;
2515 send_cleanup_vector(cfg);
2519 static inline void irq_complete_move(struct irq_desc **descp) {}
2522 static void __eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg)
2525 struct irq_pin_list *entry;
2527 entry = cfg->irq_2_pin;
2535 io_apic_eoi(apic, pin);
2536 entry = entry->next;
2541 eoi_ioapic_irq(struct irq_desc *desc)
2543 struct irq_cfg *cfg;
2544 unsigned long flags;
2548 cfg = desc->chip_data;
2550 spin_lock_irqsave(&ioapic_lock, flags);
2551 __eoi_ioapic_irq(irq, cfg);
2552 spin_unlock_irqrestore(&ioapic_lock, flags);
2555 static void ack_apic_edge(unsigned int irq)
2557 struct irq_desc *desc = irq_to_desc(irq);
2559 irq_complete_move(&desc);
2560 move_native_irq(irq);
2564 atomic_t irq_mis_count;
2566 static void ack_apic_level(unsigned int irq)
2568 struct irq_desc *desc = irq_to_desc(irq);
2570 #ifdef CONFIG_X86_32
2574 struct irq_cfg *cfg;
2575 int do_unmask_irq = 0;
2577 irq_complete_move(&desc);
2578 #ifdef CONFIG_GENERIC_PENDING_IRQ
2579 /* If we are moving the irq we need to mask it */
2580 if (unlikely(desc->status & IRQ_MOVE_PENDING)) {
2582 mask_IO_APIC_irq_desc(desc);
2586 #ifdef CONFIG_X86_32
2588 * It appears there is an erratum which affects at least version 0x11
2589 * of I/O APIC (that's the 82093AA and cores integrated into various
2590 * chipsets). Under certain conditions a level-triggered interrupt is
2591 * erroneously delivered as edge-triggered one but the respective IRR
2592 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2593 * message but it will never arrive and further interrupts are blocked
2594 * from the source. The exact reason is so far unknown, but the
2595 * phenomenon was observed when two consecutive interrupt requests
2596 * from a given source get delivered to the same CPU and the source is
2597 * temporarily disabled in between.
2599 * A workaround is to simulate an EOI message manually. We achieve it
2600 * by setting the trigger mode to edge and then to level when the edge
2601 * trigger mode gets detected in the TMR of a local APIC for a
2602 * level-triggered interrupt. We mask the source for the time of the
2603 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2604 * The idea is from Manfred Spraul. --macro
2606 cfg = desc->chip_data;
2609 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2613 * We must acknowledge the irq before we move it or the acknowledge will
2614 * not propagate properly.
2618 /* Now we can move and renable the irq */
2619 if (unlikely(do_unmask_irq)) {
2620 /* Only migrate the irq if the ack has been received.
2622 * On rare occasions the broadcast level triggered ack gets
2623 * delayed going to ioapics, and if we reprogram the
2624 * vector while Remote IRR is still set the irq will never
2627 * To prevent this scenario we read the Remote IRR bit
2628 * of the ioapic. This has two effects.
2629 * - On any sane system the read of the ioapic will
2630 * flush writes (and acks) going to the ioapic from
2632 * - We get to see if the ACK has actually been delivered.
2634 * Based on failed experiments of reprogramming the
2635 * ioapic entry from outside of irq context starting
2636 * with masking the ioapic entry and then polling until
2637 * Remote IRR was clear before reprogramming the
2638 * ioapic I don't trust the Remote IRR bit to be
2639 * completey accurate.
2641 * However there appears to be no other way to plug
2642 * this race, so if the Remote IRR bit is not
2643 * accurate and is causing problems then it is a hardware bug
2644 * and you can go talk to the chipset vendor about it.
2646 cfg = desc->chip_data;
2647 if (!io_apic_level_ack_pending(cfg))
2648 move_masked_irq(irq);
2649 unmask_IO_APIC_irq_desc(desc);
2652 #ifdef CONFIG_X86_32
2653 if (!(v & (1 << (i & 0x1f)))) {
2654 atomic_inc(&irq_mis_count);
2655 spin_lock(&ioapic_lock);
2656 __mask_and_edge_IO_APIC_irq(cfg);
2657 __unmask_and_level_IO_APIC_irq(cfg);
2658 spin_unlock(&ioapic_lock);
2663 #ifdef CONFIG_INTR_REMAP
2664 static void ir_ack_apic_edge(unsigned int irq)
2669 static void ir_ack_apic_level(unsigned int irq)
2671 struct irq_desc *desc = irq_to_desc(irq);
2674 eoi_ioapic_irq(desc);
2676 #endif /* CONFIG_INTR_REMAP */
2678 static struct irq_chip ioapic_chip __read_mostly = {
2680 .startup = startup_ioapic_irq,
2681 .mask = mask_IO_APIC_irq,
2682 .unmask = unmask_IO_APIC_irq,
2683 .ack = ack_apic_edge,
2684 .eoi = ack_apic_level,
2686 .set_affinity = set_ioapic_affinity_irq,
2688 .retrigger = ioapic_retrigger_irq,
2691 static struct irq_chip ir_ioapic_chip __read_mostly = {
2692 .name = "IR-IO-APIC",
2693 .startup = startup_ioapic_irq,
2694 .mask = mask_IO_APIC_irq,
2695 .unmask = unmask_IO_APIC_irq,
2696 #ifdef CONFIG_INTR_REMAP
2697 .ack = ir_ack_apic_edge,
2698 .eoi = ir_ack_apic_level,
2700 .set_affinity = set_ir_ioapic_affinity_irq,
2703 .retrigger = ioapic_retrigger_irq,
2706 static inline void init_IO_APIC_traps(void)
2709 struct irq_desc *desc;
2710 struct irq_cfg *cfg;
2713 * NOTE! The local APIC isn't very good at handling
2714 * multiple interrupts at the same interrupt level.
2715 * As the interrupt level is determined by taking the
2716 * vector number and shifting that right by 4, we
2717 * want to spread these out a bit so that they don't
2718 * all fall in the same interrupt level.
2720 * Also, we've got to be careful not to trash gate
2721 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2723 for_each_irq_desc(irq, desc) {
2724 cfg = desc->chip_data;
2725 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
2727 * Hmm.. We don't have an entry for this,
2728 * so default to an old-fashioned 8259
2729 * interrupt if we can..
2731 if (irq < NR_IRQS_LEGACY)
2732 make_8259A_irq(irq);
2734 /* Strange. Oh, well.. */
2735 desc->chip = &no_irq_chip;
2741 * The local APIC irq-chip implementation:
2744 static void mask_lapic_irq(unsigned int irq)
2748 v = apic_read(APIC_LVT0);
2749 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2752 static void unmask_lapic_irq(unsigned int irq)
2756 v = apic_read(APIC_LVT0);
2757 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2760 static void ack_lapic_irq(unsigned int irq)
2765 static struct irq_chip lapic_chip __read_mostly = {
2766 .name = "local-APIC",
2767 .mask = mask_lapic_irq,
2768 .unmask = unmask_lapic_irq,
2769 .ack = ack_lapic_irq,
2772 static void lapic_register_intr(int irq, struct irq_desc *desc)
2774 desc->status &= ~IRQ_LEVEL;
2775 set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2779 static void __init setup_nmi(void)
2782 * Dirty trick to enable the NMI watchdog ...
2783 * We put the 8259A master into AEOI mode and
2784 * unmask on all local APICs LVT0 as NMI.
2786 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2787 * is from Maciej W. Rozycki - so we do not have to EOI from
2788 * the NMI handler or the timer interrupt.
2790 apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2792 enable_NMI_through_LVT0();
2794 apic_printk(APIC_VERBOSE, " done.\n");
2798 * This looks a bit hackish but it's about the only one way of sending
2799 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2800 * not support the ExtINT mode, unfortunately. We need to send these
2801 * cycles as some i82489DX-based boards have glue logic that keeps the
2802 * 8259A interrupt line asserted until INTA. --macro
2804 static inline void __init unlock_ExtINT_logic(void)
2807 struct IO_APIC_route_entry entry0, entry1;
2808 unsigned char save_control, save_freq_select;
2810 pin = find_isa_irq_pin(8, mp_INT);
2815 apic = find_isa_irq_apic(8, mp_INT);
2821 entry0 = ioapic_read_entry(apic, pin);
2822 clear_IO_APIC_pin(apic, pin);
2824 memset(&entry1, 0, sizeof(entry1));
2826 entry1.dest_mode = 0; /* physical delivery */
2827 entry1.mask = 0; /* unmask IRQ now */
2828 entry1.dest = hard_smp_processor_id();
2829 entry1.delivery_mode = dest_ExtINT;
2830 entry1.polarity = entry0.polarity;
2834 ioapic_write_entry(apic, pin, entry1);
2836 save_control = CMOS_READ(RTC_CONTROL);
2837 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2838 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2840 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2845 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2849 CMOS_WRITE(save_control, RTC_CONTROL);
2850 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2851 clear_IO_APIC_pin(apic, pin);
2853 ioapic_write_entry(apic, pin, entry0);
2856 static int disable_timer_pin_1 __initdata;
2857 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2858 static int __init disable_timer_pin_setup(char *arg)
2860 disable_timer_pin_1 = 1;
2863 early_param("disable_timer_pin_1", disable_timer_pin_setup);
2865 int timer_through_8259 __initdata;
2868 * This code may look a bit paranoid, but it's supposed to cooperate with
2869 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2870 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2871 * fanatically on his truly buggy board.
2873 * FIXME: really need to revamp this for all platforms.
2875 static inline void __init check_timer(void)
2877 struct irq_desc *desc = irq_to_desc(0);
2878 struct irq_cfg *cfg = desc->chip_data;
2879 int cpu = boot_cpu_id;
2880 int apic1, pin1, apic2, pin2;
2881 unsigned long flags;
2884 local_irq_save(flags);
2887 * get/set the timer IRQ vector:
2889 disable_8259A_irq(0);
2890 assign_irq_vector(0, cfg, apic->target_cpus());
2893 * As IRQ0 is to be enabled in the 8259A, the virtual
2894 * wire has to be disabled in the local APIC. Also
2895 * timer interrupts need to be acknowledged manually in
2896 * the 8259A for the i82489DX when using the NMI
2897 * watchdog as that APIC treats NMIs as level-triggered.
2898 * The AEOI mode will finish them in the 8259A
2901 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2903 #ifdef CONFIG_X86_32
2907 ver = apic_read(APIC_LVR);
2908 ver = GET_APIC_VERSION(ver);
2909 timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver));
2913 pin1 = find_isa_irq_pin(0, mp_INT);
2914 apic1 = find_isa_irq_apic(0, mp_INT);
2915 pin2 = ioapic_i8259.pin;
2916 apic2 = ioapic_i8259.apic;
2918 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2919 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2920 cfg->vector, apic1, pin1, apic2, pin2);
2923 * Some BIOS writers are clueless and report the ExtINTA
2924 * I/O APIC input from the cascaded 8259A as the timer
2925 * interrupt input. So just in case, if only one pin
2926 * was found above, try it both directly and through the
2930 if (intr_remapping_enabled)
2931 panic("BIOS bug: timer not connected to IO-APIC");
2935 } else if (pin2 == -1) {
2942 * Ok, does IRQ0 through the IOAPIC work?
2945 add_pin_to_irq_cpu(cfg, cpu, apic1, pin1);
2946 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
2948 /* for edge trigger, setup_IO_APIC_irq already
2949 * leave it unmasked.
2950 * so only need to unmask if it is level-trigger
2951 * do we really have level trigger timer?
2954 idx = find_irq_entry(apic1, pin1, mp_INT);
2955 if (idx != -1 && irq_trigger(idx))
2956 unmask_IO_APIC_irq_desc(desc);
2958 if (timer_irq_works()) {
2959 if (nmi_watchdog == NMI_IO_APIC) {
2961 enable_8259A_irq(0);
2963 if (disable_timer_pin_1 > 0)
2964 clear_IO_APIC_pin(0, pin1);
2967 if (intr_remapping_enabled)
2968 panic("timer doesn't work through Interrupt-remapped IO-APIC");
2969 local_irq_disable();
2970 clear_IO_APIC_pin(apic1, pin1);
2972 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2973 "8254 timer not connected to IO-APIC\n");
2975 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2976 "(IRQ0) through the 8259A ...\n");
2977 apic_printk(APIC_QUIET, KERN_INFO
2978 "..... (found apic %d pin %d) ...\n", apic2, pin2);
2980 * legacy devices should be connected to IO APIC #0
2982 replace_pin_at_irq_cpu(cfg, cpu, apic1, pin1, apic2, pin2);
2983 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
2984 enable_8259A_irq(0);
2985 if (timer_irq_works()) {
2986 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2987 timer_through_8259 = 1;
2988 if (nmi_watchdog == NMI_IO_APIC) {
2989 disable_8259A_irq(0);
2991 enable_8259A_irq(0);
2996 * Cleanup, just in case ...
2998 local_irq_disable();
2999 disable_8259A_irq(0);
3000 clear_IO_APIC_pin(apic2, pin2);
3001 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
3004 if (nmi_watchdog == NMI_IO_APIC) {
3005 apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work "
3006 "through the IO-APIC - disabling NMI Watchdog!\n");
3007 nmi_watchdog = NMI_NONE;
3009 #ifdef CONFIG_X86_32
3013 apic_printk(APIC_QUIET, KERN_INFO
3014 "...trying to set up timer as Virtual Wire IRQ...\n");
3016 lapic_register_intr(0, desc);
3017 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
3018 enable_8259A_irq(0);
3020 if (timer_irq_works()) {
3021 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
3024 local_irq_disable();
3025 disable_8259A_irq(0);
3026 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
3027 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
3029 apic_printk(APIC_QUIET, KERN_INFO
3030 "...trying to set up timer as ExtINT IRQ...\n");
3034 apic_write(APIC_LVT0, APIC_DM_EXTINT);
3036 unlock_ExtINT_logic();
3038 if (timer_irq_works()) {
3039 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
3042 local_irq_disable();
3043 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
3044 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
3045 "report. Then try booting with the 'noapic' option.\n");
3047 local_irq_restore(flags);
3051 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
3052 * to devices. However there may be an I/O APIC pin available for
3053 * this interrupt regardless. The pin may be left unconnected, but
3054 * typically it will be reused as an ExtINT cascade interrupt for
3055 * the master 8259A. In the MPS case such a pin will normally be
3056 * reported as an ExtINT interrupt in the MP table. With ACPI
3057 * there is no provision for ExtINT interrupts, and in the absence
3058 * of an override it would be treated as an ordinary ISA I/O APIC
3059 * interrupt, that is edge-triggered and unmasked by default. We
3060 * used to do this, but it caused problems on some systems because
3061 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
3062 * the same ExtINT cascade interrupt to drive the local APIC of the
3063 * bootstrap processor. Therefore we refrain from routing IRQ2 to
3064 * the I/O APIC in all cases now. No actual device should request
3065 * it anyway. --macro
3067 #define PIC_IRQS (1 << PIC_CASCADE_IR)
3069 void __init setup_IO_APIC(void)
3073 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
3076 io_apic_irqs = ~PIC_IRQS;
3078 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
3080 * Set up IO-APIC IRQ routing.
3082 #ifdef CONFIG_X86_32
3084 setup_ioapic_ids_from_mpc();
3087 setup_IO_APIC_irqs();
3088 init_IO_APIC_traps();
3093 * Called after all the initialization is done. If we didnt find any
3094 * APIC bugs then we can allow the modify fast path
3097 static int __init io_apic_bug_finalize(void)
3099 if (sis_apic_bug == -1)
3104 late_initcall(io_apic_bug_finalize);
3106 struct sysfs_ioapic_data {
3107 struct sys_device dev;
3108 struct IO_APIC_route_entry entry[0];
3110 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
3112 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
3114 struct IO_APIC_route_entry *entry;
3115 struct sysfs_ioapic_data *data;
3118 data = container_of(dev, struct sysfs_ioapic_data, dev);
3119 entry = data->entry;
3120 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
3121 *entry = ioapic_read_entry(dev->id, i);
3126 static int ioapic_resume(struct sys_device *dev)
3128 struct IO_APIC_route_entry *entry;
3129 struct sysfs_ioapic_data *data;
3130 unsigned long flags;
3131 union IO_APIC_reg_00 reg_00;
3134 data = container_of(dev, struct sysfs_ioapic_data, dev);
3135 entry = data->entry;
3137 spin_lock_irqsave(&ioapic_lock, flags);
3138 reg_00.raw = io_apic_read(dev->id, 0);
3139 if (reg_00.bits.ID != mp_ioapics[dev->id].apicid) {
3140 reg_00.bits.ID = mp_ioapics[dev->id].apicid;
3141 io_apic_write(dev->id, 0, reg_00.raw);
3143 spin_unlock_irqrestore(&ioapic_lock, flags);
3144 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
3145 ioapic_write_entry(dev->id, i, entry[i]);
3150 static struct sysdev_class ioapic_sysdev_class = {
3152 .suspend = ioapic_suspend,
3153 .resume = ioapic_resume,
3156 static int __init ioapic_init_sysfs(void)
3158 struct sys_device * dev;
3161 error = sysdev_class_register(&ioapic_sysdev_class);
3165 for (i = 0; i < nr_ioapics; i++ ) {
3166 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
3167 * sizeof(struct IO_APIC_route_entry);
3168 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
3169 if (!mp_ioapic_data[i]) {
3170 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3173 dev = &mp_ioapic_data[i]->dev;
3175 dev->cls = &ioapic_sysdev_class;
3176 error = sysdev_register(dev);
3178 kfree(mp_ioapic_data[i]);
3179 mp_ioapic_data[i] = NULL;
3180 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3188 device_initcall(ioapic_init_sysfs);
3190 static int nr_irqs_gsi = NR_IRQS_LEGACY;
3192 * Dynamic irq allocate and deallocation
3194 unsigned int create_irq_nr(unsigned int irq_want)
3196 /* Allocate an unused irq */
3199 unsigned long flags;
3200 struct irq_cfg *cfg_new = NULL;
3201 int cpu = boot_cpu_id;
3202 struct irq_desc *desc_new = NULL;
3205 if (irq_want < nr_irqs_gsi)
3206 irq_want = nr_irqs_gsi;
3208 spin_lock_irqsave(&vector_lock, flags);
3209 for (new = irq_want; new < nr_irqs; new++) {
3210 desc_new = irq_to_desc_alloc_cpu(new, cpu);
3212 printk(KERN_INFO "can not get irq_desc for %d\n", new);
3215 cfg_new = desc_new->chip_data;
3217 if (cfg_new->vector != 0)
3219 if (__assign_irq_vector(new, cfg_new, apic->target_cpus()) == 0)
3223 spin_unlock_irqrestore(&vector_lock, flags);
3226 dynamic_irq_init(irq);
3227 /* restore it, in case dynamic_irq_init clear it */
3229 desc_new->chip_data = cfg_new;
3234 int create_irq(void)
3236 unsigned int irq_want;
3239 irq_want = nr_irqs_gsi;
3240 irq = create_irq_nr(irq_want);
3248 void destroy_irq(unsigned int irq)
3250 unsigned long flags;
3251 struct irq_cfg *cfg;
3252 struct irq_desc *desc;
3254 /* store it, in case dynamic_irq_cleanup clear it */
3255 desc = irq_to_desc(irq);
3256 cfg = desc->chip_data;
3257 dynamic_irq_cleanup(irq);
3258 /* connect back irq_cfg */
3260 desc->chip_data = cfg;
3263 spin_lock_irqsave(&vector_lock, flags);
3264 __clear_irq_vector(irq, cfg);
3265 spin_unlock_irqrestore(&vector_lock, flags);
3269 * MSI message composition
3271 #ifdef CONFIG_PCI_MSI
3272 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
3274 struct irq_cfg *cfg;
3282 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3286 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
3288 if (irq_remapped(irq)) {
3293 ir_index = map_irq_to_irte_handle(irq, &sub_handle);
3294 BUG_ON(ir_index == -1);
3296 memset (&irte, 0, sizeof(irte));
3299 irte.dst_mode = apic->irq_dest_mode;
3300 irte.trigger_mode = 0; /* edge */
3301 irte.dlvry_mode = apic->irq_delivery_mode;
3302 irte.vector = cfg->vector;
3303 irte.dest_id = IRTE_DEST(dest);
3305 modify_irte(irq, &irte);
3307 msg->address_hi = MSI_ADDR_BASE_HI;
3308 msg->data = sub_handle;
3309 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
3311 MSI_ADDR_IR_INDEX1(ir_index) |
3312 MSI_ADDR_IR_INDEX2(ir_index);
3314 if (x2apic_enabled())
3315 msg->address_hi = MSI_ADDR_BASE_HI |
3316 MSI_ADDR_EXT_DEST_ID(dest);
3318 msg->address_hi = MSI_ADDR_BASE_HI;
3322 ((apic->irq_dest_mode == 0) ?
3323 MSI_ADDR_DEST_MODE_PHYSICAL:
3324 MSI_ADDR_DEST_MODE_LOGICAL) |
3325 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3326 MSI_ADDR_REDIRECTION_CPU:
3327 MSI_ADDR_REDIRECTION_LOWPRI) |
3328 MSI_ADDR_DEST_ID(dest);
3331 MSI_DATA_TRIGGER_EDGE |
3332 MSI_DATA_LEVEL_ASSERT |
3333 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3334 MSI_DATA_DELIVERY_FIXED:
3335 MSI_DATA_DELIVERY_LOWPRI) |
3336 MSI_DATA_VECTOR(cfg->vector);
3342 static void set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3344 struct irq_desc *desc = irq_to_desc(irq);
3345 struct irq_cfg *cfg;
3349 dest = set_desc_affinity(desc, mask);
3350 if (dest == BAD_APICID)
3353 cfg = desc->chip_data;
3355 read_msi_msg_desc(desc, &msg);
3357 msg.data &= ~MSI_DATA_VECTOR_MASK;
3358 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3359 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3360 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3362 write_msi_msg_desc(desc, &msg);
3364 #ifdef CONFIG_INTR_REMAP
3366 * Migrate the MSI irq to another cpumask. This migration is
3367 * done in the process context using interrupt-remapping hardware.
3370 ir_set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3372 struct irq_desc *desc = irq_to_desc(irq);
3373 struct irq_cfg *cfg = desc->chip_data;
3377 if (get_irte(irq, &irte))
3380 dest = set_desc_affinity(desc, mask);
3381 if (dest == BAD_APICID)
3384 irte.vector = cfg->vector;
3385 irte.dest_id = IRTE_DEST(dest);
3388 * atomically update the IRTE with the new destination and vector.
3390 modify_irte(irq, &irte);
3393 * After this point, all the interrupts will start arriving
3394 * at the new destination. So, time to cleanup the previous
3395 * vector allocation.
3397 if (cfg->move_in_progress)
3398 send_cleanup_vector(cfg);
3402 #endif /* CONFIG_SMP */
3405 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3406 * which implement the MSI or MSI-X Capability Structure.
3408 static struct irq_chip msi_chip = {
3410 .unmask = unmask_msi_irq,
3411 .mask = mask_msi_irq,
3412 .ack = ack_apic_edge,
3414 .set_affinity = set_msi_irq_affinity,
3416 .retrigger = ioapic_retrigger_irq,
3419 static struct irq_chip msi_ir_chip = {
3420 .name = "IR-PCI-MSI",
3421 .unmask = unmask_msi_irq,
3422 .mask = mask_msi_irq,
3423 #ifdef CONFIG_INTR_REMAP
3424 .ack = ir_ack_apic_edge,
3426 .set_affinity = ir_set_msi_irq_affinity,
3429 .retrigger = ioapic_retrigger_irq,
3433 * Map the PCI dev to the corresponding remapping hardware unit
3434 * and allocate 'nvec' consecutive interrupt-remapping table entries
3437 static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec)
3439 struct intel_iommu *iommu;
3442 iommu = map_dev_to_ir(dev);
3445 "Unable to map PCI %s to iommu\n", pci_name(dev));
3449 index = alloc_irte(iommu, irq, nvec);
3452 "Unable to allocate %d IRTE for PCI %s\n", nvec,
3459 static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq)
3464 ret = msi_compose_msg(dev, irq, &msg);
3468 set_irq_msi(irq, msidesc);
3469 write_msi_msg(irq, &msg);
3471 if (irq_remapped(irq)) {
3472 struct irq_desc *desc = irq_to_desc(irq);
3474 * irq migration in process context
3476 desc->status |= IRQ_MOVE_PCNTXT;
3477 set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge");
3479 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
3481 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq);
3486 int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
3489 int ret, sub_handle;
3490 struct msi_desc *msidesc;
3491 unsigned int irq_want;
3492 struct intel_iommu *iommu = NULL;
3495 /* x86 doesn't support multiple MSI yet */
3496 if (type == PCI_CAP_ID_MSI && nvec > 1)
3499 irq_want = nr_irqs_gsi;
3501 list_for_each_entry(msidesc, &dev->msi_list, list) {
3502 irq = create_irq_nr(irq_want);
3506 if (!intr_remapping_enabled)
3511 * allocate the consecutive block of IRTE's
3514 index = msi_alloc_irte(dev, irq, nvec);
3520 iommu = map_dev_to_ir(dev);
3526 * setup the mapping between the irq and the IRTE
3527 * base index, the sub_handle pointing to the
3528 * appropriate interrupt remap table entry.
3530 set_irte_irq(irq, iommu, index, sub_handle);
3533 ret = setup_msi_irq(dev, msidesc, irq);
3545 void arch_teardown_msi_irq(unsigned int irq)
3550 #if defined (CONFIG_DMAR) || defined (CONFIG_INTR_REMAP)
3552 static void dmar_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
3554 struct irq_desc *desc = irq_to_desc(irq);
3555 struct irq_cfg *cfg;
3559 dest = set_desc_affinity(desc, mask);
3560 if (dest == BAD_APICID)
3563 cfg = desc->chip_data;
3565 dmar_msi_read(irq, &msg);
3567 msg.data &= ~MSI_DATA_VECTOR_MASK;
3568 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3569 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3570 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3572 dmar_msi_write(irq, &msg);
3575 #endif /* CONFIG_SMP */
3577 struct irq_chip dmar_msi_type = {
3579 .unmask = dmar_msi_unmask,
3580 .mask = dmar_msi_mask,
3581 .ack = ack_apic_edge,
3583 .set_affinity = dmar_msi_set_affinity,
3585 .retrigger = ioapic_retrigger_irq,
3588 int arch_setup_dmar_msi(unsigned int irq)
3593 ret = msi_compose_msg(NULL, irq, &msg);
3596 dmar_msi_write(irq, &msg);
3597 set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
3603 #ifdef CONFIG_HPET_TIMER
3606 static void hpet_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
3608 struct irq_desc *desc = irq_to_desc(irq);
3609 struct irq_cfg *cfg;
3613 dest = set_desc_affinity(desc, mask);
3614 if (dest == BAD_APICID)
3617 cfg = desc->chip_data;
3619 hpet_msi_read(irq, &msg);
3621 msg.data &= ~MSI_DATA_VECTOR_MASK;
3622 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3623 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3624 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3626 hpet_msi_write(irq, &msg);
3629 #endif /* CONFIG_SMP */
3631 static struct irq_chip hpet_msi_type = {
3633 .unmask = hpet_msi_unmask,
3634 .mask = hpet_msi_mask,
3635 .ack = ack_apic_edge,
3637 .set_affinity = hpet_msi_set_affinity,
3639 .retrigger = ioapic_retrigger_irq,
3642 int arch_setup_hpet_msi(unsigned int irq)
3647 ret = msi_compose_msg(NULL, irq, &msg);
3651 hpet_msi_write(irq, &msg);
3652 set_irq_chip_and_handler_name(irq, &hpet_msi_type, handle_edge_irq,
3659 #endif /* CONFIG_PCI_MSI */
3661 * Hypertransport interrupt support
3663 #ifdef CONFIG_HT_IRQ
3667 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
3669 struct ht_irq_msg msg;
3670 fetch_ht_irq_msg(irq, &msg);
3672 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
3673 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
3675 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
3676 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
3678 write_ht_irq_msg(irq, &msg);
3681 static void set_ht_irq_affinity(unsigned int irq, const struct cpumask *mask)
3683 struct irq_desc *desc = irq_to_desc(irq);
3684 struct irq_cfg *cfg;
3687 dest = set_desc_affinity(desc, mask);
3688 if (dest == BAD_APICID)
3691 cfg = desc->chip_data;
3693 target_ht_irq(irq, dest, cfg->vector);
3698 static struct irq_chip ht_irq_chip = {
3700 .mask = mask_ht_irq,
3701 .unmask = unmask_ht_irq,
3702 .ack = ack_apic_edge,
3704 .set_affinity = set_ht_irq_affinity,
3706 .retrigger = ioapic_retrigger_irq,
3709 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
3711 struct irq_cfg *cfg;
3718 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3720 struct ht_irq_msg msg;
3723 dest = apic->cpu_mask_to_apicid_and(cfg->domain,
3724 apic->target_cpus());
3726 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
3730 HT_IRQ_LOW_DEST_ID(dest) |
3731 HT_IRQ_LOW_VECTOR(cfg->vector) |
3732 ((apic->irq_dest_mode == 0) ?
3733 HT_IRQ_LOW_DM_PHYSICAL :
3734 HT_IRQ_LOW_DM_LOGICAL) |
3735 HT_IRQ_LOW_RQEOI_EDGE |
3736 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3737 HT_IRQ_LOW_MT_FIXED :
3738 HT_IRQ_LOW_MT_ARBITRATED) |
3739 HT_IRQ_LOW_IRQ_MASKED;
3741 write_ht_irq_msg(irq, &msg);
3743 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
3744 handle_edge_irq, "edge");
3746 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq);
3750 #endif /* CONFIG_HT_IRQ */
3752 #ifdef CONFIG_X86_UV
3754 * Re-target the irq to the specified CPU and enable the specified MMR located
3755 * on the specified blade to allow the sending of MSIs to the specified CPU.
3757 int arch_enable_uv_irq(char *irq_name, unsigned int irq, int cpu, int mmr_blade,
3758 unsigned long mmr_offset)
3760 const struct cpumask *eligible_cpu = cpumask_of(cpu);
3761 struct irq_cfg *cfg;
3763 unsigned long mmr_value;
3764 struct uv_IO_APIC_route_entry *entry;
3765 unsigned long flags;
3770 err = assign_irq_vector(irq, cfg, eligible_cpu);
3774 spin_lock_irqsave(&vector_lock, flags);
3775 set_irq_chip_and_handler_name(irq, &uv_irq_chip, handle_percpu_irq,
3777 spin_unlock_irqrestore(&vector_lock, flags);
3780 entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
3781 BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
3783 entry->vector = cfg->vector;
3784 entry->delivery_mode = apic->irq_delivery_mode;
3785 entry->dest_mode = apic->irq_dest_mode;
3786 entry->polarity = 0;
3789 entry->dest = apic->cpu_mask_to_apicid(eligible_cpu);
3791 mmr_pnode = uv_blade_to_pnode(mmr_blade);
3792 uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
3798 * Disable the specified MMR located on the specified blade so that MSIs are
3799 * longer allowed to be sent.
3801 void arch_disable_uv_irq(int mmr_blade, unsigned long mmr_offset)
3803 unsigned long mmr_value;
3804 struct uv_IO_APIC_route_entry *entry;
3808 entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
3809 BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
3813 mmr_pnode = uv_blade_to_pnode(mmr_blade);
3814 uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
3816 #endif /* CONFIG_X86_64 */
3818 int __init io_apic_get_redir_entries (int ioapic)
3820 union IO_APIC_reg_01 reg_01;
3821 unsigned long flags;
3823 spin_lock_irqsave(&ioapic_lock, flags);
3824 reg_01.raw = io_apic_read(ioapic, 1);
3825 spin_unlock_irqrestore(&ioapic_lock, flags);
3827 return reg_01.bits.entries;
3830 void __init probe_nr_irqs_gsi(void)
3834 nr = acpi_probe_gsi();
3835 if (nr > nr_irqs_gsi) {
3838 /* for acpi=off or acpi is not compiled in */
3842 for (idx = 0; idx < nr_ioapics; idx++)
3843 nr += io_apic_get_redir_entries(idx) + 1;
3845 if (nr > nr_irqs_gsi)
3849 printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi);
3852 #ifdef CONFIG_SPARSE_IRQ
3853 int __init arch_probe_nr_irqs(void)
3857 if (nr_irqs > (NR_VECTORS * nr_cpu_ids))
3858 nr_irqs = NR_VECTORS * nr_cpu_ids;
3860 nr = nr_irqs_gsi + 8 * nr_cpu_ids;
3861 #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
3863 * for MSI and HT dyn irq
3865 nr += nr_irqs_gsi * 16;
3874 /* --------------------------------------------------------------------------
3875 ACPI-based IOAPIC Configuration
3876 -------------------------------------------------------------------------- */
3880 #ifdef CONFIG_X86_32
3881 int __init io_apic_get_unique_id(int ioapic, int apic_id)
3883 union IO_APIC_reg_00 reg_00;
3884 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
3886 unsigned long flags;
3890 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3891 * buses (one for LAPICs, one for IOAPICs), where predecessors only
3892 * supports up to 16 on one shared APIC bus.
3894 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3895 * advantage of new APIC bus architecture.
3898 if (physids_empty(apic_id_map))
3899 apic_id_map = apic->ioapic_phys_id_map(phys_cpu_present_map);
3901 spin_lock_irqsave(&ioapic_lock, flags);
3902 reg_00.raw = io_apic_read(ioapic, 0);
3903 spin_unlock_irqrestore(&ioapic_lock, flags);
3905 if (apic_id >= get_physical_broadcast()) {
3906 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
3907 "%d\n", ioapic, apic_id, reg_00.bits.ID);
3908 apic_id = reg_00.bits.ID;
3912 * Every APIC in a system must have a unique ID or we get lots of nice
3913 * 'stuck on smp_invalidate_needed IPI wait' messages.
3915 if (apic->check_apicid_used(apic_id_map, apic_id)) {
3917 for (i = 0; i < get_physical_broadcast(); i++) {
3918 if (!apic->check_apicid_used(apic_id_map, i))
3922 if (i == get_physical_broadcast())
3923 panic("Max apic_id exceeded!\n");
3925 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
3926 "trying %d\n", ioapic, apic_id, i);
3931 tmp = apic->apicid_to_cpu_present(apic_id);
3932 physids_or(apic_id_map, apic_id_map, tmp);
3934 if (reg_00.bits.ID != apic_id) {
3935 reg_00.bits.ID = apic_id;
3937 spin_lock_irqsave(&ioapic_lock, flags);
3938 io_apic_write(ioapic, 0, reg_00.raw);
3939 reg_00.raw = io_apic_read(ioapic, 0);
3940 spin_unlock_irqrestore(&ioapic_lock, flags);
3943 if (reg_00.bits.ID != apic_id) {
3944 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
3949 apic_printk(APIC_VERBOSE, KERN_INFO
3950 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
3955 int __init io_apic_get_version(int ioapic)
3957 union IO_APIC_reg_01 reg_01;
3958 unsigned long flags;
3960 spin_lock_irqsave(&ioapic_lock, flags);
3961 reg_01.raw = io_apic_read(ioapic, 1);
3962 spin_unlock_irqrestore(&ioapic_lock, flags);
3964 return reg_01.bits.version;
3968 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
3970 struct irq_desc *desc;
3971 struct irq_cfg *cfg;
3972 int cpu = boot_cpu_id;
3974 if (!IO_APIC_IRQ(irq)) {
3975 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
3980 desc = irq_to_desc_alloc_cpu(irq, cpu);
3982 printk(KERN_INFO "can not get irq_desc %d\n", irq);
3987 * IRQs < 16 are already in the irq_2_pin[] map
3989 if (irq >= NR_IRQS_LEGACY) {
3990 cfg = desc->chip_data;
3991 add_pin_to_irq_cpu(cfg, cpu, ioapic, pin);
3994 setup_IO_APIC_irq(ioapic, pin, irq, desc, triggering, polarity);
4000 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
4004 if (skip_ioapic_setup)
4007 for (i = 0; i < mp_irq_entries; i++)
4008 if (mp_irqs[i].irqtype == mp_INT &&
4009 mp_irqs[i].srcbusirq == bus_irq)
4011 if (i >= mp_irq_entries)
4014 *trigger = irq_trigger(i);
4015 *polarity = irq_polarity(i);
4019 #endif /* CONFIG_ACPI */
4022 * This function currently is only a helper for the i386 smp boot process where
4023 * we need to reprogram the ioredtbls to cater for the cpus which have come online
4024 * so mask in all cases should simply be apic->target_cpus()
4027 void __init setup_ioapic_dest(void)
4029 int pin, ioapic, irq, irq_entry;
4030 struct irq_desc *desc;
4031 struct irq_cfg *cfg;
4032 const struct cpumask *mask;
4034 if (skip_ioapic_setup == 1)
4037 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
4038 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
4039 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
4040 if (irq_entry == -1)
4042 irq = pin_2_irq(irq_entry, ioapic, pin);
4044 /* setup_IO_APIC_irqs could fail to get vector for some device
4045 * when you have too many devices, because at that time only boot
4048 desc = irq_to_desc(irq);
4049 cfg = desc->chip_data;
4051 setup_IO_APIC_irq(ioapic, pin, irq, desc,
4052 irq_trigger(irq_entry),
4053 irq_polarity(irq_entry));
4059 * Honour affinities which have been set in early boot
4062 (IRQ_NO_BALANCING | IRQ_AFFINITY_SET))
4063 mask = desc->affinity;
4065 mask = apic->target_cpus();
4067 if (intr_remapping_enabled)
4068 set_ir_ioapic_affinity_irq_desc(desc, mask);
4070 set_ioapic_affinity_irq_desc(desc, mask);
4077 #define IOAPIC_RESOURCE_NAME_SIZE 11
4079 static struct resource *ioapic_resources;
4081 static struct resource * __init ioapic_setup_resources(void)
4084 struct resource *res;
4088 if (nr_ioapics <= 0)
4091 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
4094 mem = alloc_bootmem(n);
4098 mem += sizeof(struct resource) * nr_ioapics;
4100 for (i = 0; i < nr_ioapics; i++) {
4102 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
4103 sprintf(mem, "IOAPIC %u", i);
4104 mem += IOAPIC_RESOURCE_NAME_SIZE;
4108 ioapic_resources = res;
4113 void __init ioapic_init_mappings(void)
4115 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
4116 struct resource *ioapic_res;
4119 ioapic_res = ioapic_setup_resources();
4120 for (i = 0; i < nr_ioapics; i++) {
4121 if (smp_found_config) {
4122 ioapic_phys = mp_ioapics[i].apicaddr;
4123 #ifdef CONFIG_X86_32
4126 "WARNING: bogus zero IO-APIC "
4127 "address found in MPTABLE, "
4128 "disabling IO/APIC support!\n");
4129 smp_found_config = 0;
4130 skip_ioapic_setup = 1;
4131 goto fake_ioapic_page;
4135 #ifdef CONFIG_X86_32
4138 ioapic_phys = (unsigned long)
4139 alloc_bootmem_pages(PAGE_SIZE);
4140 ioapic_phys = __pa(ioapic_phys);
4142 set_fixmap_nocache(idx, ioapic_phys);
4143 apic_printk(APIC_VERBOSE,
4144 "mapped IOAPIC to %08lx (%08lx)\n",
4145 __fix_to_virt(idx), ioapic_phys);
4148 if (ioapic_res != NULL) {
4149 ioapic_res->start = ioapic_phys;
4150 ioapic_res->end = ioapic_phys + (4 * 1024) - 1;
4156 static int __init ioapic_insert_resources(void)
4159 struct resource *r = ioapic_resources;
4162 if (nr_ioapics > 0) {
4164 "IO APIC resources couldn't be allocated.\n");
4170 for (i = 0; i < nr_ioapics; i++) {
4171 insert_resource(&iomem_resource, r);
4178 /* Insert the IO APIC resources after PCI initialization has occured to handle
4179 * IO APICS that are mapped in on a BAR in PCI space. */
4180 late_initcall(ioapic_insert_resources);