git.oblomov.eu Git - linux-2.6/blob - drivers/net/ipg.h

   1 /*
   2  * Include file for Gigabit Ethernet device driver for Network
   3  * Interface Cards (NICs) utilizing the Tamarack Microelectronics
   4  * Inc. IPG Gigabit or Triple Speed Ethernet Media Access
   5  * Controller.
   6  */
   7 #ifndef __LINUX_IPG_H
   8 #define __LINUX_IPG_H
   9
  10 #include <linux/module.h>
  11
  12 #include <linux/kernel.h>
  13 #include <linux/pci.h>
  14 #include <linux/ioport.h>
  15 #include <linux/errno.h>
  16 #include <asm/io.h>
  17 #include <linux/delay.h>
  18 #include <linux/types.h>
  19 #include <linux/netdevice.h>
  20 #include <linux/etherdevice.h>
  21 #include <linux/init.h>
  22 #include <linux/skbuff.h>
  23 #include <asm/bitops.h>
  24
  25 /*
  26  *      Constants
  27  */
  28
  29 /* GMII based PHY IDs */
  30 #define         NS                              0x2000
  31 #define         MARVELL                         0x0141
  32 #define         ICPLUS_PHY              0x243
  33
  34 /* NIC Physical Layer Device MII register fields. */
  35 #define         MII_PHY_SELECTOR_IEEE8023       0x0001
  36 #define         MII_PHY_TECHABILITYFIELD        0x1FE0
  37
  38 /* GMII_PHY_1000 need to set to prefer master */
  39 #define         GMII_PHY_1000BASETCONTROL_PreferMaster 0x0400
  40
  41 /* NIC Physical Layer Device GMII constants. */
  42 #define         GMII_PREAMBLE                    0xFFFFFFFF
  43 #define         GMII_ST                          0x1
  44 #define         GMII_READ                        0x2
  45 #define         GMII_WRITE                       0x1
  46 #define         GMII_TA_READ_MASK                0x1
  47 #define         GMII_TA_WRITE                    0x2
  48
  49 /* I/O register offsets. */
  50 enum ipg_regs {
  51         DMA_CTRL                = 0x00,
  52         RX_DMA_STATUS           = 0x08, /* Unused + reserved */
  53         TFD_LIST_PTR_0          = 0x10,
  54         TFD_LIST_PTR_1          = 0x14,
  55         TX_DMA_BURST_THRESH     = 0x18,
  56         TX_DMA_URGENT_THRESH    = 0x19,
  57         TX_DMA_POLL_PERIOD      = 0x1a,
  58         RFD_LIST_PTR_0          = 0x1c,
  59         RFD_LIST_PTR_1          = 0x20,
  60         RX_DMA_BURST_THRESH     = 0x24,
  61         RX_DMA_URGENT_THRESH    = 0x25,
  62         RX_DMA_POLL_PERIOD      = 0x26,
  63         DEBUG_CTRL              = 0x2c,
  64         ASIC_CTRL               = 0x30,
  65         FIFO_CTRL               = 0x38, /* Unused */
  66         FLOW_OFF_THRESH         = 0x3c,
  67         FLOW_ON_THRESH          = 0x3e,
  68         EEPROM_DATA             = 0x48,
  69         EEPROM_CTRL             = 0x4a,
  70         EXPROM_ADDR             = 0x4c, /* Unused */
  71         EXPROM_DATA             = 0x50, /* Unused */
  72         WAKE_EVENT              = 0x51, /* Unused */
  73         COUNTDOWN               = 0x54, /* Unused */
  74         INT_STATUS_ACK          = 0x5a,
  75         INT_ENABLE              = 0x5c,
  76         INT_STATUS              = 0x5e, /* Unused */
  77         TX_STATUS               = 0x60,
  78         MAC_CTRL                = 0x6c,
  79         VLAN_TAG                = 0x70, /* Unused */
  80         PHY_SET                 = 0x75,
  81         PHY_CTRL                = 0x76,
  82         STATION_ADDRESS_0       = 0x78,
  83         STATION_ADDRESS_1       = 0x7a,
  84         STATION_ADDRESS_2       = 0x7c,
  85         MAX_FRAME_SIZE          = 0x86,
  86         RECEIVE_MODE            = 0x88,
  87         HASHTABLE_0             = 0x8c,
  88         HASHTABLE_1             = 0x90,
  89         RMON_STATISTICS_MASK    = 0x98,
  90         STATISTICS_MASK         = 0x9c,
  91         RX_JUMBO_FRAMES         = 0xbc, /* Unused */
  92         TCP_CHECKSUM_ERRORS     = 0xc0, /* Unused */
  93         IP_CHECKSUM_ERRORS      = 0xc2, /* Unused */
  94         UDP_CHECKSUM_ERRORS     = 0xc4, /* Unused */
  95         TX_JUMBO_FRAMES         = 0xf4  /* Unused */
  96 };
  97
  98 /* Ethernet MIB statistic register offsets. */
  99 #define IPG_OCTETRCVOK          0xA8
 100 #define IPG_MCSTOCTETRCVDOK             0xAC
 101 #define IPG_BCSTOCTETRCVOK              0xB0
 102 #define IPG_FRAMESRCVDOK                0xB4
 103 #define IPG_MCSTFRAMESRCVDOK            0xB8
 104 #define IPG_BCSTFRAMESRCVDOK            0xBE
 105 #define IPG_MACCONTROLFRAMESRCVD        0xC6
 106 #define IPG_FRAMETOOLONGERRRORS 0xC8
 107 #define IPG_INRANGELENGTHERRORS 0xCA
 108 #define IPG_FRAMECHECKSEQERRORS 0xCC
 109 #define IPG_FRAMESLOSTRXERRORS  0xCE
 110 #define IPG_OCTETXMTOK          0xD0
 111 #define IPG_MCSTOCTETXMTOK              0xD4
 112 #define IPG_BCSTOCTETXMTOK              0xD8
 113 #define IPG_FRAMESXMTDOK                0xDC
 114 #define IPG_MCSTFRAMESXMTDOK            0xE0
 115 #define IPG_FRAMESWDEFERREDXMT  0xE4
 116 #define IPG_LATECOLLISIONS              0xE8
 117 #define IPG_MULTICOLFRAMES              0xEC
 118 #define IPG_SINGLECOLFRAMES             0xF0
 119 #define IPG_BCSTFRAMESXMTDOK            0xF6
 120 #define IPG_CARRIERSENSEERRORS  0xF8
 121 #define IPG_MACCONTROLFRAMESXMTDOK      0xFA
 122 #define IPG_FRAMESABORTXSCOLLS  0xFC
 123 #define IPG_FRAMESWEXDEFERRAL   0xFE
 124
 125 /* RMON statistic register offsets. */
 126 #define IPG_ETHERSTATSCOLLISIONS                        0x100
 127 #define IPG_ETHERSTATSOCTETSTRANSMIT                    0x104
 128 #define IPG_ETHERSTATSPKTSTRANSMIT                      0x108
 129 #define IPG_ETHERSTATSPKTS64OCTESTSTRANSMIT             0x10C
 130 #define IPG_ETHERSTATSPKTS65TO127OCTESTSTRANSMIT        0x110
 131 #define IPG_ETHERSTATSPKTS128TO255OCTESTSTRANSMIT       0x114
 132 #define IPG_ETHERSTATSPKTS256TO511OCTESTSTRANSMIT       0x118
 133 #define IPG_ETHERSTATSPKTS512TO1023OCTESTSTRANSMIT      0x11C
 134 #define IPG_ETHERSTATSPKTS1024TO1518OCTESTSTRANSMIT     0x120
 135 #define IPG_ETHERSTATSCRCALIGNERRORS                    0x124
 136 #define IPG_ETHERSTATSUNDERSIZEPKTS                     0x128
 137 #define IPG_ETHERSTATSFRAGMENTS                 0x12C
 138 #define IPG_ETHERSTATSJABBERS                   0x130
 139 #define IPG_ETHERSTATSOCTETS                            0x134
 140 #define IPG_ETHERSTATSPKTS                              0x138
 141 #define IPG_ETHERSTATSPKTS64OCTESTS                     0x13C
 142 #define IPG_ETHERSTATSPKTS65TO127OCTESTS                0x140
 143 #define IPG_ETHERSTATSPKTS128TO255OCTESTS               0x144
 144 #define IPG_ETHERSTATSPKTS256TO511OCTESTS               0x148
 145 #define IPG_ETHERSTATSPKTS512TO1023OCTESTS              0x14C
 146 #define IPG_ETHERSTATSPKTS1024TO1518OCTESTS             0x150
 147
 148 /* RMON statistic register equivalents. */
 149 #define IPG_ETHERSTATSMULTICASTPKTSTRANSMIT             0xE0
 150 #define IPG_ETHERSTATSBROADCASTPKTSTRANSMIT             0xF6
 151 #define IPG_ETHERSTATSMULTICASTPKTS                     0xB8
 152 #define IPG_ETHERSTATSBROADCASTPKTS                     0xBE
 153 #define IPG_ETHERSTATSOVERSIZEPKTS                      0xC8
 154 #define IPG_ETHERSTATSDROPEVENTS                        0xCE
 155
 156 /* Serial EEPROM offsets */
 157 #define IPG_EEPROM_CONFIGPARAM  0x00
 158 #define IPG_EEPROM_ASICCTRL             0x01
 159 #define IPG_EEPROM_SUBSYSTEMVENDORID    0x02
 160 #define IPG_EEPROM_SUBSYSTEMID  0x03
 161 #define IPG_EEPROM_STATIONADDRESS0      0x10
 162 #define IPG_EEPROM_STATIONADDRESS1      0x11
 163 #define IPG_EEPROM_STATIONADDRESS2      0x12
 164
 165 /* Register & data structure bit masks */
 166
 167 /* PCI register masks. */
 168
 169 /* IOBaseAddress */
 170 #define         IPG_PIB_RSVD_MASK               0xFFFFFE01
 171 #define         IPG_PIB_IOBASEADDRESS   0xFFFFFF00
 172 #define         IPG_PIB_IOBASEADDRIND   0x00000001
 173
 174 /* MemBaseAddress */
 175 #define         IPG_PMB_RSVD_MASK               0xFFFFFE07
 176 #define         IPG_PMB_MEMBASEADDRIND  0x00000001
 177 #define         IPG_PMB_MEMMAPTYPE              0x00000006
 178 #define         IPG_PMB_MEMMAPTYPE0             0x00000002
 179 #define         IPG_PMB_MEMMAPTYPE1             0x00000004
 180 #define         IPG_PMB_MEMBASEADDRESS  0xFFFFFE00
 181
 182 /* ConfigStatus */
 183 #define IPG_CS_RSVD_MASK                0xFFB0
 184 #define IPG_CS_CAPABILITIES             0x0010
 185 #define IPG_CS_66MHZCAPABLE             0x0020
 186 #define IPG_CS_FASTBACK2BACK            0x0080
 187 #define IPG_CS_DATAPARITYREPORTED       0x0100
 188 #define IPG_CS_DEVSELTIMING             0x0600
 189 #define IPG_CS_SIGNALEDTARGETABORT      0x0800
 190 #define IPG_CS_RECEIVEDTARGETABORT      0x1000
 191 #define IPG_CS_RECEIVEDMASTERABORT      0x2000
 192 #define IPG_CS_SIGNALEDSYSTEMERROR      0x4000
 193 #define IPG_CS_DETECTEDPARITYERROR      0x8000
 194
 195 /* TFD data structure masks. */
 196
 197 /* TFDList, TFC */
 198 #define IPG_TFC_RSVD_MASK                       0x0000FFFF9FFFFFFF
 199 #define IPG_TFC_FRAMEID                 0x000000000000FFFF
 200 #define IPG_TFC_WORDALIGN                       0x0000000000030000
 201 #define IPG_TFC_WORDALIGNTODWORD                0x0000000000000000
 202 #define IPG_TFC_WORDALIGNTOWORD         0x0000000000020000
 203 #define IPG_TFC_WORDALIGNDISABLED               0x0000000000030000
 204 #define IPG_TFC_TCPCHECKSUMENABLE               0x0000000000040000
 205 #define IPG_TFC_UDPCHECKSUMENABLE               0x0000000000080000
 206 #define IPG_TFC_IPCHECKSUMENABLE                0x0000000000100000
 207 #define IPG_TFC_FCSAPPENDDISABLE                0x0000000000200000
 208 #define IPG_TFC_TXINDICATE                      0x0000000000400000
 209 #define IPG_TFC_TXDMAINDICATE           0x0000000000800000
 210 #define IPG_TFC_FRAGCOUNT                       0x000000000F000000
 211 #define IPG_TFC_VLANTAGINSERT           0x0000000010000000
 212 #define IPG_TFC_TFDDONE                 0x0000000080000000
 213 #define IPG_TFC_VID                             0x00000FFF00000000
 214 #define IPG_TFC_CFI                             0x0000100000000000
 215 #define IPG_TFC_USERPRIORITY                    0x0000E00000000000
 216
 217 /* TFDList, FragInfo */
 218 #define IPG_TFI_RSVD_MASK                       0xFFFF00FFFFFFFFFF
 219 #define IPG_TFI_FRAGADDR                        0x000000FFFFFFFFFF
 220 #define IPG_TFI_FRAGLEN                 0xFFFF000000000000LL
 221
 222 /* RFD data structure masks. */
 223
 224 /* RFDList, RFS */
 225 #define IPG_RFS_RSVD_MASK                       0x0000FFFFFFFFFFFF
 226 #define IPG_RFS_RXFRAMELEN                      0x000000000000FFFF
 227 #define IPG_RFS_RXFIFOOVERRUN           0x0000000000010000
 228 #define IPG_RFS_RXRUNTFRAME                     0x0000000000020000
 229 #define IPG_RFS_RXALIGNMENTERROR                0x0000000000040000
 230 #define IPG_RFS_RXFCSERROR                      0x0000000000080000
 231 #define IPG_RFS_RXOVERSIZEDFRAME                0x0000000000100000
 232 #define IPG_RFS_RXLENGTHERROR           0x0000000000200000
 233 #define IPG_RFS_VLANDETECTED                    0x0000000000400000
 234 #define IPG_RFS_TCPDETECTED                     0x0000000000800000
 235 #define IPG_RFS_TCPERROR                        0x0000000001000000
 236 #define IPG_RFS_UDPDETECTED                     0x0000000002000000
 237 #define IPG_RFS_UDPERROR                        0x0000000004000000
 238 #define IPG_RFS_IPDETECTED                      0x0000000008000000
 239 #define IPG_RFS_IPERROR                 0x0000000010000000
 240 #define IPG_RFS_FRAMESTART                      0x0000000020000000
 241 #define IPG_RFS_FRAMEEND                        0x0000000040000000
 242 #define IPG_RFS_RFDDONE                 0x0000000080000000
 243 #define IPG_RFS_TCI                             0x0000FFFF00000000
 244
 245 /* RFDList, FragInfo */
 246 #define IPG_RFI_RSVD_MASK                       0xFFFF00FFFFFFFFFF
 247 #define IPG_RFI_FRAGADDR                        0x000000FFFFFFFFFF
 248 #define IPG_RFI_FRAGLEN                 0xFFFF000000000000LL
 249
 250 /* I/O Register masks. */
 251
 252 /* RMON Statistics Mask */
 253 #define IPG_RZ_ALL                                      0x0FFFFFFF
 254
 255 /* Statistics Mask */
 256 #define IPG_SM_ALL                                      0x0FFFFFFF
 257 #define IPG_SM_OCTETRCVOK_FRAMESRCVDOK          0x00000001
 258 #define IPG_SM_MCSTOCTETRCVDOK_MCSTFRAMESRCVDOK 0x00000002
 259 #define IPG_SM_BCSTOCTETRCVDOK_BCSTFRAMESRCVDOK 0x00000004
 260 #define IPG_SM_RXJUMBOFRAMES                            0x00000008
 261 #define IPG_SM_TCPCHECKSUMERRORS                        0x00000010
 262 #define IPG_SM_IPCHECKSUMERRORS                 0x00000020
 263 #define IPG_SM_UDPCHECKSUMERRORS                        0x00000040
 264 #define IPG_SM_MACCONTROLFRAMESRCVD                     0x00000080
 265 #define IPG_SM_FRAMESTOOLONGERRORS                      0x00000100
 266 #define IPG_SM_INRANGELENGTHERRORS                      0x00000200
 267 #define IPG_SM_FRAMECHECKSEQERRORS                      0x00000400
 268 #define IPG_SM_FRAMESLOSTRXERRORS                       0x00000800
 269 #define IPG_SM_OCTETXMTOK_FRAMESXMTOK           0x00001000
 270 #define IPG_SM_MCSTOCTETXMTOK_MCSTFRAMESXMTDOK  0x00002000
 271 #define IPG_SM_BCSTOCTETXMTOK_BCSTFRAMESXMTDOK  0x00004000
 272 #define IPG_SM_FRAMESWDEFERREDXMT                       0x00008000
 273 #define IPG_SM_LATECOLLISIONS                   0x00010000
 274 #define IPG_SM_MULTICOLFRAMES                   0x00020000
 275 #define IPG_SM_SINGLECOLFRAMES                  0x00040000
 276 #define IPG_SM_TXJUMBOFRAMES                            0x00080000
 277 #define IPG_SM_CARRIERSENSEERRORS                       0x00100000
 278 #define IPG_SM_MACCONTROLFRAMESXMTD                     0x00200000
 279 #define IPG_SM_FRAMESABORTXSCOLLS                       0x00400000
 280 #define IPG_SM_FRAMESWEXDEFERAL                 0x00800000
 281
 282 /* Countdown */
 283 #define IPG_CD_RSVD_MASK                0x0700FFFF
 284 #define IPG_CD_COUNT                    0x0000FFFF
 285 #define IPG_CD_COUNTDOWNSPEED   0x01000000
 286 #define IPG_CD_COUNTDOWNMODE            0x02000000
 287 #define IPG_CD_COUNTINTENABLED  0x04000000
 288
 289 /* TxDMABurstThresh */
 290 #define IPG_TB_RSVD_MASK                0xFF
 291
 292 /* TxDMAUrgentThresh */
 293 #define IPG_TU_RSVD_MASK                0xFF
 294
 295 /* TxDMAPollPeriod */
 296 #define IPG_TP_RSVD_MASK                0xFF
 297
 298 /* RxDMAUrgentThresh */
 299 #define IPG_RU_RSVD_MASK                0xFF
 300
 301 /* RxDMAPollPeriod */
 302 #define IPG_RP_RSVD_MASK                0xFF
 303
 304 /* ReceiveMode */
 305 #define IPG_RM_RSVD_MASK                0x3F
 306 #define IPG_RM_RECEIVEUNICAST           0x01
 307 #define IPG_RM_RECEIVEMULTICAST         0x02
 308 #define IPG_RM_RECEIVEBROADCAST         0x04
 309 #define IPG_RM_RECEIVEALLFRAMES         0x08
 310 #define IPG_RM_RECEIVEMULTICASTHASH     0x10
 311 #define IPG_RM_RECEIVEIPMULTICAST       0x20
 312
 313 /* PhySet */
 314 #define IPG_PS_MEM_LENB9B               0x01
 315 #define IPG_PS_MEM_LEN9                 0x02
 316 #define IPG_PS_NON_COMPDET              0x04
 317
 318 /* PhyCtrl */
 319 #define IPG_PC_RSVD_MASK                0xFF
 320 #define IPG_PC_MGMTCLK_LO               0x00
 321 #define IPG_PC_MGMTCLK_HI               0x01
 322 #define IPG_PC_MGMTCLK                  0x01
 323 #define IPG_PC_MGMTDATA                 0x02
 324 #define IPG_PC_MGMTDIR                  0x04
 325 #define IPG_PC_DUPLEX_POLARITY          0x08
 326 #define IPG_PC_DUPLEX_STATUS            0x10
 327 #define IPG_PC_LINK_POLARITY            0x20
 328 #define IPG_PC_LINK_SPEED               0xC0
 329 #define IPG_PC_LINK_SPEED_10MBPS        0x40
 330 #define IPG_PC_LINK_SPEED_100MBPS       0x80
 331 #define IPG_PC_LINK_SPEED_1000MBPS      0xC0
 332
 333 /* DMACtrl */
 334 #define IPG_DC_RSVD_MASK                0xC07D9818
 335 #define IPG_DC_RX_DMA_COMPLETE          0x00000008
 336 #define IPG_DC_RX_DMA_POLL_NOW          0x00000010
 337 #define IPG_DC_TX_DMA_COMPLETE          0x00000800
 338 #define IPG_DC_TX_DMA_POLL_NOW          0x00001000
 339 #define IPG_DC_TX_DMA_IN_PROG           0x00008000
 340 #define IPG_DC_RX_EARLY_DISABLE         0x00010000
 341 #define IPG_DC_MWI_DISABLE              0x00040000
 342 #define IPG_DC_TX_WRITE_BACK_DISABLE    0x00080000
 343 #define IPG_DC_TX_BURST_LIMIT           0x00700000
 344 #define IPG_DC_TARGET_ABORT             0x40000000
 345 #define IPG_DC_MASTER_ABORT             0x80000000
 346
 347 /* ASICCtrl */
 348 #define IPG_AC_RSVD_MASK                0x07FFEFF2
 349 #define IPG_AC_EXP_ROM_SIZE             0x00000002
 350 #define IPG_AC_PHY_SPEED10              0x00000010
 351 #define IPG_AC_PHY_SPEED100             0x00000020
 352 #define IPG_AC_PHY_SPEED1000            0x00000040
 353 #define IPG_AC_PHY_MEDIA                0x00000080
 354 #define IPG_AC_FORCED_CFG               0x00000700
 355 #define IPG_AC_D3RESETDISABLE           0x00000800
 356 #define IPG_AC_SPEED_UP_MODE            0x00002000
 357 #define IPG_AC_LED_MODE                 0x00004000
 358 #define IPG_AC_RST_OUT_POLARITY         0x00008000
 359 #define IPG_AC_GLOBAL_RESET             0x00010000
 360 #define IPG_AC_RX_RESET                 0x00020000
 361 #define IPG_AC_TX_RESET                 0x00040000
 362 #define IPG_AC_DMA                      0x00080000
 363 #define IPG_AC_FIFO                     0x00100000
 364 #define IPG_AC_NETWORK                  0x00200000
 365 #define IPG_AC_HOST                     0x00400000
 366 #define IPG_AC_AUTO_INIT                0x00800000
 367 #define IPG_AC_RST_OUT                  0x01000000
 368 #define IPG_AC_INT_REQUEST              0x02000000
 369 #define IPG_AC_RESET_BUSY               0x04000000
 370 #define IPG_AC_LED_SPEED                0x08000000
 371 #define IPG_AC_LED_MODE_BIT_1           0x20000000
 372
 373 /* EepromCtrl */
 374 #define IPG_EC_RSVD_MASK                0x83FF
 375 #define IPG_EC_EEPROM_ADDR              0x00FF
 376 #define IPG_EC_EEPROM_OPCODE            0x0300
 377 #define IPG_EC_EEPROM_SUBCOMMAD         0x0000
 378 #define IPG_EC_EEPROM_WRITEOPCODE       0x0100
 379 #define IPG_EC_EEPROM_READOPCODE        0x0200
 380 #define IPG_EC_EEPROM_ERASEOPCODE       0x0300
 381 #define IPG_EC_EEPROM_BUSY              0x8000
 382
 383 /* FIFOCtrl */
 384 #define IPG_FC_RSVD_MASK                0xC001
 385 #define IPG_FC_RAM_TEST_MODE            0x0001
 386 #define IPG_FC_TRANSMITTING             0x4000
 387 #define IPG_FC_RECEIVING                0x8000
 388
 389 /* TxStatus */
 390 #define IPG_TS_RSVD_MASK                0xFFFF00DD
 391 #define IPG_TS_TX_ERROR                 0x00000001
 392 #define IPG_TS_LATE_COLLISION           0x00000004
 393 #define IPG_TS_TX_MAX_COLL              0x00000008
 394 #define IPG_TS_TX_UNDERRUN              0x00000010
 395 #define IPG_TS_TX_IND_REQD              0x00000040
 396 #define IPG_TS_TX_COMPLETE              0x00000080
 397 #define IPG_TS_TX_FRAMEID               0xFFFF0000
 398
 399 /* WakeEvent */
 400 #define IPG_WE_WAKE_PKT_ENABLE          0x01
 401 #define IPG_WE_MAGIC_PKT_ENABLE         0x02
 402 #define IPG_WE_LINK_EVT_ENABLE          0x04
 403 #define IPG_WE_WAKE_POLARITY            0x08
 404 #define IPG_WE_WAKE_PKT_EVT             0x10
 405 #define IPG_WE_MAGIC_PKT_EVT            0x20
 406 #define IPG_WE_LINK_EVT                 0x40
 407 #define IPG_WE_WOL_ENABLE               0x80
 408
 409 /* IntEnable */
 410 #define IPG_IE_RSVD_MASK                0x1FFE
 411 #define IPG_IE_HOST_ERROR               0x0002
 412 #define IPG_IE_TX_COMPLETE              0x0004
 413 #define IPG_IE_MAC_CTRL_FRAME           0x0008
 414 #define IPG_IE_RX_COMPLETE              0x0010
 415 #define IPG_IE_RX_EARLY                 0x0020
 416 #define IPG_IE_INT_REQUESTED            0x0040
 417 #define IPG_IE_UPDATE_STATS             0x0080
 418 #define IPG_IE_LINK_EVENT               0x0100
 419 #define IPG_IE_TX_DMA_COMPLETE          0x0200
 420 #define IPG_IE_RX_DMA_COMPLETE          0x0400
 421 #define IPG_IE_RFD_LIST_END             0x0800
 422 #define IPG_IE_RX_DMA_PRIORITY          0x1000
 423
 424 /* IntStatus */
 425 #define IPG_IS_RSVD_MASK                0x1FFF
 426 #define IPG_IS_INTERRUPT_STATUS         0x0001
 427 #define IPG_IS_HOST_ERROR               0x0002
 428 #define IPG_IS_TX_COMPLETE              0x0004
 429 #define IPG_IS_MAC_CTRL_FRAME           0x0008
 430 #define IPG_IS_RX_COMPLETE              0x0010
 431 #define IPG_IS_RX_EARLY                 0x0020
 432 #define IPG_IS_INT_REQUESTED            0x0040
 433 #define IPG_IS_UPDATE_STATS             0x0080
 434 #define IPG_IS_LINK_EVENT               0x0100
 435 #define IPG_IS_TX_DMA_COMPLETE          0x0200
 436 #define IPG_IS_RX_DMA_COMPLETE          0x0400
 437 #define IPG_IS_RFD_LIST_END             0x0800
 438 #define IPG_IS_RX_DMA_PRIORITY          0x1000
 439
 440 /* MACCtrl */
 441 #define IPG_MC_RSVD_MASK                0x7FE33FA3
 442 #define IPG_MC_IFS_SELECT               0x00000003
 443 #define IPG_MC_IFS_4352BIT              0x00000003
 444 #define IPG_MC_IFS_1792BIT              0x00000002
 445 #define IPG_MC_IFS_1024BIT              0x00000001
 446 #define IPG_MC_IFS_96BIT                0x00000000
 447 #define IPG_MC_DUPLEX_SELECT            0x00000020
 448 #define IPG_MC_DUPLEX_SELECT_FD         0x00000020
 449 #define IPG_MC_DUPLEX_SELECT_HD         0x00000000
 450 #define IPG_MC_TX_FLOW_CONTROL_ENABLE   0x00000080
 451 #define IPG_MC_RX_FLOW_CONTROL_ENABLE   0x00000100
 452 #define IPG_MC_RCV_FCS                  0x00000200
 453 #define IPG_MC_FIFO_LOOPBACK            0x00000400
 454 #define IPG_MC_MAC_LOOPBACK             0x00000800
 455 #define IPG_MC_AUTO_VLAN_TAGGING        0x00001000
 456 #define IPG_MC_AUTO_VLAN_UNTAGGING      0x00002000
 457 #define IPG_MC_COLLISION_DETECT         0x00010000
 458 #define IPG_MC_CARRIER_SENSE            0x00020000
 459 #define IPG_MC_STATISTICS_ENABLE        0x00200000
 460 #define IPG_MC_STATISTICS_DISABLE       0x00400000
 461 #define IPG_MC_STATISTICS_ENABLED       0x00800000
 462 #define IPG_MC_TX_ENABLE                0x01000000
 463 #define IPG_MC_TX_DISABLE               0x02000000
 464 #define IPG_MC_TX_ENABLED               0x04000000
 465 #define IPG_MC_RX_ENABLE                0x08000000
 466 #define IPG_MC_RX_DISABLE               0x10000000
 467 #define IPG_MC_RX_ENABLED               0x20000000
 468 #define IPG_MC_PAUSED                   0x40000000
 469
 470 /*
 471  *      Tune
 472  */
 473
 474 /* Assign IPG_APPEND_FCS_ON_TX > 0 for auto FCS append on TX. */
 475 #define         IPG_APPEND_FCS_ON_TX         1
 476
 477 /* Assign IPG_APPEND_FCS_ON_TX > 0 for auto FCS strip on RX. */
 478 #define         IPG_STRIP_FCS_ON_RX          1
 479
 480 /* Assign IPG_DROP_ON_RX_ETH_ERRORS > 0 to drop RX frames with
 481  * Ethernet errors.
 482  */
 483 #define         IPG_DROP_ON_RX_ETH_ERRORS    1
 484
 485 /* Assign IPG_INSERT_MANUAL_VLAN_TAG > 0 to insert VLAN tags manually
 486  * (via TFC).
 487  */
 488 #define         IPG_INSERT_MANUAL_VLAN_TAG   0
 489
 490 /* Assign IPG_ADD_IPCHECKSUM_ON_TX > 0 for auto IP checksum on TX. */
 491 #define         IPG_ADD_IPCHECKSUM_ON_TX     0
 492
 493 /* Assign IPG_ADD_TCPCHECKSUM_ON_TX > 0 for auto TCP checksum on TX.
 494  * DO NOT USE FOR SILICON REVISIONS B3 AND EARLIER.
 495  */
 496 #define         IPG_ADD_TCPCHECKSUM_ON_TX    0
 497
 498 /* Assign IPG_ADD_UDPCHECKSUM_ON_TX > 0 for auto UDP checksum on TX.
 499  * DO NOT USE FOR SILICON REVISIONS B3 AND EARLIER.
 500  */
 501 #define         IPG_ADD_UDPCHECKSUM_ON_TX    0
 502
 503 /* If inserting VLAN tags manually, assign the IPG_MANUAL_VLAN_xx
 504  * constants as desired.
 505  */
 506 #define         IPG_MANUAL_VLAN_VID             0xABC
 507 #define         IPG_MANUAL_VLAN_CFI             0x1
 508 #define         IPG_MANUAL_VLAN_USERPRIORITY 0x5
 509
 510 #define         IPG_IO_REG_RANGE                0xFF
 511 #define         IPG_MEM_REG_RANGE               0x154
 512 #define         IPG_DRIVER_NAME         "Sundance Technology IPG Triple-Speed Ethernet"
 513 #define         IPG_NIC_PHY_ADDRESS          0x01
 514 #define         IPG_DMALIST_ALIGN_PAD   0x07
 515 #define         IPG_MULTICAST_HASHTABLE_SIZE    0x40
 516
 517 /* Number of milliseconds to wait after issuing a software reset.
 518  * 0x05 <= IPG_AC_RESETWAIT to account for proper 10Mbps operation.
 519  */
 520 #define         IPG_AC_RESETWAIT             0x05
 521
 522 /* Number of IPG_AC_RESETWAIT timeperiods before declaring timeout. */
 523 #define         IPG_AC_RESET_TIMEOUT         0x0A
 524
 525 /* Minimum number of nanoseconds used to toggle MDC clock during
 526  * MII/GMII register access.
 527  */
 528 #define         IPG_PC_PHYCTRLWAIT_NS           200
 529
 530 #define         IPG_TFDLIST_LENGTH              0x100
 531
 532 /* Number of frames between TxDMAComplete interrupt.
 533  * 0 < IPG_FRAMESBETWEENTXDMACOMPLETES <= IPG_TFDLIST_LENGTH
 534  */
 535 #define         IPG_FRAMESBETWEENTXDMACOMPLETES 0x1
 536
 537 #define         IPG_RFDLIST_LENGTH              0x100
 538
 539 /* Maximum number of RFDs to process per interrupt.
 540  * 1 < IPG_MAXRFDPROCESS_COUNT < IPG_RFDLIST_LENGTH
 541  */
 542 #define         IPG_MAXRFDPROCESS_COUNT 0x80
 543
 544 /* Minimum margin between last freed RFD, and current RFD.
 545  * 1 < IPG_MINUSEDRFDSTOFREE < IPG_RFDLIST_LENGTH
 546  */
 547 #define         IPG_MINUSEDRFDSTOFREE   0x80
 548
 549 /* specify the jumbo frame maximum size
 550  * per unit is 0x600 (the rx_buffer size that one RFD can carry)
 551  */
 552 #define     MAX_JUMBOSIZE               0x8     /* max is 12K */
 553
 554 /* Key register values loaded at driver start up. */
 555
 556 /* TXDMAPollPeriod is specified in 320ns increments.
 557  *
 558  * Value        Time
 559  * ---------------------
 560  * 0x00-0x01    320ns
 561  * 0x03         ~1us
 562  * 0x1F         ~10us
 563  * 0xFF         ~82us
 564  */
 565 #define         IPG_TXDMAPOLLPERIOD_VALUE       0x26
 566
 567 /* TxDMAUrgentThresh specifies the minimum amount of
 568  * data in the transmit FIFO before asserting an
 569  * urgent transmit DMA request.
 570  *
 571  * Value        Min TxFIFO occupied space before urgent TX request
 572  * ---------------------------------------------------------------
 573  * 0x00-0x04    128 bytes (1024 bits)
 574  * 0x27         1248 bytes (~10000 bits)
 575  * 0x30         1536 bytes (12288 bits)
 576  * 0xFF         8192 bytes (65535 bits)
 577  */
 578 #define         IPG_TXDMAURGENTTHRESH_VALUE     0x04
 579
 580 /* TxDMABurstThresh specifies the minimum amount of
 581  * free space in the transmit FIFO before asserting an
 582  * transmit DMA request.
 583  *
 584  * Value        Min TxFIFO free space before TX request
 585  * ----------------------------------------------------
 586  * 0x00-0x08    256 bytes
 587  * 0x30         1536 bytes
 588  * 0xFF         8192 bytes
 589  */
 590 #define         IPG_TXDMABURSTTHRESH_VALUE      0x30
 591
 592 /* RXDMAPollPeriod is specified in 320ns increments.
 593  *
 594  * Value        Time
 595  * ---------------------
 596  * 0x00-0x01    320ns
 597  * 0x03         ~1us
 598  * 0x1F         ~10us
 599  * 0xFF         ~82us
 600  */
 601 #define         IPG_RXDMAPOLLPERIOD_VALUE       0x01
 602
 603 /* RxDMAUrgentThresh specifies the minimum amount of
 604  * free space within the receive FIFO before asserting
 605  * a urgent receive DMA request.
 606  *
 607  * Value        Min RxFIFO free space before urgent RX request
 608  * ---------------------------------------------------------------
 609  * 0x00-0x04    128 bytes (1024 bits)
 610  * 0x27         1248 bytes (~10000 bits)
 611  * 0x30         1536 bytes (12288 bits)
 612  * 0xFF         8192 bytes (65535 bits)
 613  */
 614 #define         IPG_RXDMAURGENTTHRESH_VALUE     0x30
 615
 616 /* RxDMABurstThresh specifies the minimum amount of
 617  * occupied space within the receive FIFO before asserting
 618  * a receive DMA request.
 619  *
 620  * Value        Min TxFIFO free space before TX request
 621  * ----------------------------------------------------
 622  * 0x00-0x08    256 bytes
 623  * 0x30         1536 bytes
 624  * 0xFF         8192 bytes
 625  */
 626 #define         IPG_RXDMABURSTTHRESH_VALUE      0x30
 627
 628 /* FlowOnThresh specifies the maximum amount of occupied
 629  * space in the receive FIFO before a PAUSE frame with
 630  * maximum pause time transmitted.
 631  *
 632  * Value        Max RxFIFO occupied space before PAUSE
 633  * ---------------------------------------------------
 634  * 0x0000       0 bytes
 635  * 0x0740       29,696 bytes
 636  * 0x07FF       32,752 bytes
 637  */
 638 #define         IPG_FLOWONTHRESH_VALUE  0x0740
 639
 640 /* FlowOffThresh specifies the minimum amount of occupied
 641  * space in the receive FIFO before a PAUSE frame with
 642  * zero pause time is transmitted.
 643  *
 644  * Value        Max RxFIFO occupied space before PAUSE
 645  * ---------------------------------------------------
 646  * 0x0000       0 bytes
 647  * 0x00BF       3056 bytes
 648  * 0x07FF       32,752 bytes
 649  */
 650 #define         IPG_FLOWOFFTHRESH_VALUE 0x00BF
 651
 652 /*
 653  * Miscellaneous macros.
 654  */
 655
 656 /* Marco for printing debug statements. */
 657 #ifdef IPG_DEBUG
 658 #  define IPG_DEBUG_MSG(args...)
 659 #  define IPG_DDEBUG_MSG(args...) printk(KERN_DEBUG "IPG: " args)
 660 #  define IPG_DUMPRFDLIST(args) ipg_dump_rfdlist(args)
 661 #  define IPG_DUMPTFDLIST(args) ipg_dump_tfdlist(args)
 662 #else
 663 #  define IPG_DEBUG_MSG(args...)
 664 #  define IPG_DDEBUG_MSG(args...)
 665 #  define IPG_DUMPRFDLIST(args)
 666 #  define IPG_DUMPTFDLIST(args)
 667 #endif
 668
 669 /*
 670  * End miscellaneous macros.
 671  */
 672
 673 /* Transmit Frame Descriptor. The IPG supports 15 fragments,
 674  * however Linux requires only a single fragment. Note, each
 675  * TFD field is 64 bits wide.
 676  */
 677 struct ipg_tx {
 678         __le64 next_desc;
 679         __le64 tfc;
 680         __le64 frag_info;
 681 };
 682
 683 /* Receive Frame Descriptor. Note, each RFD field is 64 bits wide.
 684  */
 685 struct ipg_rx {
 686         __le64 next_desc;
 687         __le64 rfs;
 688         __le64 frag_info;
 689 };
 690
 691 struct ipg_jumbo {
 692         int found_start;
 693         int current_size;
 694         struct sk_buff *skb;
 695 };
 696
 697 /* Structure of IPG NIC specific data. */
 698 struct ipg_nic_private {
 699         void __iomem *ioaddr;
 700         struct ipg_tx *txd;
 701         struct ipg_rx *rxd;
 702         dma_addr_t txd_map;
 703         dma_addr_t rxd_map;
 704         struct sk_buff *tx_buff[IPG_TFDLIST_LENGTH];
 705         struct sk_buff *rx_buff[IPG_RFDLIST_LENGTH];
 706         unsigned int tx_current;
 707         unsigned int tx_dirty;
 708         unsigned int rx_current;
 709         unsigned int rx_dirty;
 710         bool is_jumbo;
 711         struct ipg_jumbo jumbo;
 712         unsigned long rxfrag_size;
 713         unsigned long rxsupport_size;
 714         unsigned long max_rxframe_size;
 715         unsigned int rx_buf_sz;
 716         struct pci_dev *pdev;
 717         struct net_device *dev;
 718         struct net_device_stats stats;
 719         spinlock_t lock;
 720         int tenmbpsmode;
 721
 722         u16 led_mode;
 723         u16 station_addr[3];    /* Station Address in EEPROM Reg 0x10..0x12 */
 724
 725         struct mutex            mii_mutex;
 726         struct mii_if_info      mii_if;
 727         int reset_current_tfd;
 728 #ifdef IPG_DEBUG
 729         int RFDlistendCount;
 730         int RFDListCheckedCount;
 731         int EmptyRFDListCount;
 732 #endif
 733         struct delayed_work task;
 734 };
 735
 736 #endif                          /* __LINUX_IPG_H */