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   1 /*
   2  *  linux/arch/m32r/kernel/setup_m32700ut.c
   3  *
   4  *  Setup routines for Renesas M32700UT Board
   5  *
   6  *  Copyright (c) 2002-2005  Hiroyuki Kondo, Hirokazu Takata,
   7  *                           Hitoshi Yamamoto, Takeo Takahashi
   8  *
   9  *  This file is subject to the terms and conditions of the GNU General
  10  *  Public License.  See the file "COPYING" in the main directory of this
  11  *  archive for more details.
  12  */
  13
  14 #include <linux/config.h>
  15 #include <linux/irq.h>
  16 #include <linux/kernel.h>
  17 #include <linux/init.h>
  18 #include <linux/platform_device.h>
  19
  20 #include <asm/system.h>
  21 #include <asm/m32r.h>
  22 #include <asm/io.h>
  23
  24 /*
  25  * M32700 Interrupt Control Unit (Level 1)
  26  */
  27 #define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long)))
  28
  29 icu_data_t icu_data[M32700UT_NUM_CPU_IRQ];
  30
  31 static void disable_m32700ut_irq(unsigned int irq)
  32 {
  33         unsigned long port, data;
  34
  35         port = irq2port(irq);
  36         data = icu_data[irq].icucr|M32R_ICUCR_ILEVEL7;
  37         outl(data, port);
  38 }
  39
  40 static void enable_m32700ut_irq(unsigned int irq)
  41 {
  42         unsigned long port, data;
  43
  44         port = irq2port(irq);
  45         data = icu_data[irq].icucr|M32R_ICUCR_IEN|M32R_ICUCR_ILEVEL6;
  46         outl(data, port);
  47 }
  48
  49 static void mask_and_ack_m32700ut(unsigned int irq)
  50 {
  51         disable_m32700ut_irq(irq);
  52 }
  53
  54 static void end_m32700ut_irq(unsigned int irq)
  55 {
  56         enable_m32700ut_irq(irq);
  57 }
  58
  59 static unsigned int startup_m32700ut_irq(unsigned int irq)
  60 {
  61         enable_m32700ut_irq(irq);
  62         return (0);
  63 }
  64
  65 static void shutdown_m32700ut_irq(unsigned int irq)
  66 {
  67         unsigned long port;
  68
  69         port = irq2port(irq);
  70         outl(M32R_ICUCR_ILEVEL7, port);
  71 }
  72
  73 static struct hw_interrupt_type m32700ut_irq_type =
  74 {
  75         .typename = "M32700UT-IRQ",
  76         .startup = startup_m32700ut_irq,
  77         .shutdown = shutdown_m32700ut_irq,
  78         .enable = enable_m32700ut_irq,
  79         .disable = disable_m32700ut_irq,
  80         .ack = mask_and_ack_m32700ut,
  81         .end = end_m32700ut_irq
  82 };
  83
  84 /*
  85  * Interrupt Control Unit of PLD on M32700UT (Level 2)
  86  */
  87 #define irq2pldirq(x)           ((x) - M32700UT_PLD_IRQ_BASE)
  88 #define pldirq2port(x)          (unsigned long)((int)PLD_ICUCR1 + \
  89                                  (((x) - 1) * sizeof(unsigned short)))
  90
  91 typedef struct {
  92         unsigned short icucr;  /* ICU Control Register */
  93 } pld_icu_data_t;
  94
  95 static pld_icu_data_t pld_icu_data[M32700UT_NUM_PLD_IRQ];
  96
  97 static void disable_m32700ut_pld_irq(unsigned int irq)
  98 {
  99         unsigned long port, data;
 100         unsigned int pldirq;
 101
 102         pldirq = irq2pldirq(irq);
 103 //      disable_m32700ut_irq(M32R_IRQ_INT1);
 104         port = pldirq2port(pldirq);
 105         data = pld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
 106         outw(data, port);
 107 }
 108
 109 static void enable_m32700ut_pld_irq(unsigned int irq)
 110 {
 111         unsigned long port, data;
 112         unsigned int pldirq;
 113
 114         pldirq = irq2pldirq(irq);
 115 //      enable_m32700ut_irq(M32R_IRQ_INT1);
 116         port = pldirq2port(pldirq);
 117         data = pld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
 118         outw(data, port);
 119 }
 120
 121 static void mask_and_ack_m32700ut_pld(unsigned int irq)
 122 {
 123         disable_m32700ut_pld_irq(irq);
 124 //      mask_and_ack_m32700ut(M32R_IRQ_INT1);
 125 }
 126
 127 static void end_m32700ut_pld_irq(unsigned int irq)
 128 {
 129         enable_m32700ut_pld_irq(irq);
 130         end_m32700ut_irq(M32R_IRQ_INT1);
 131 }
 132
 133 static unsigned int startup_m32700ut_pld_irq(unsigned int irq)
 134 {
 135         enable_m32700ut_pld_irq(irq);
 136         return (0);
 137 }
 138
 139 static void shutdown_m32700ut_pld_irq(unsigned int irq)
 140 {
 141         unsigned long port;
 142         unsigned int pldirq;
 143
 144         pldirq = irq2pldirq(irq);
 145 //      shutdown_m32700ut_irq(M32R_IRQ_INT1);
 146         port = pldirq2port(pldirq);
 147         outw(PLD_ICUCR_ILEVEL7, port);
 148 }
 149
 150 static struct hw_interrupt_type m32700ut_pld_irq_type =
 151 {
 152         .typename = "M32700UT-PLD-IRQ",
 153         .startup = startup_m32700ut_pld_irq,
 154         .shutdown = shutdown_m32700ut_pld_irq,
 155         .enable = enable_m32700ut_pld_irq,
 156         .disable = disable_m32700ut_pld_irq,
 157         .ack = mask_and_ack_m32700ut_pld,
 158         .end = end_m32700ut_pld_irq
 159 };
 160
 161 /*
 162  * Interrupt Control Unit of PLD on M32700UT-LAN (Level 2)
 163  */
 164 #define irq2lanpldirq(x)        ((x) - M32700UT_LAN_PLD_IRQ_BASE)
 165 #define lanpldirq2port(x)       (unsigned long)((int)M32700UT_LAN_ICUCR1 + \
 166                                  (((x) - 1) * sizeof(unsigned short)))
 167
 168 static pld_icu_data_t lanpld_icu_data[M32700UT_NUM_LAN_PLD_IRQ];
 169
 170 static void disable_m32700ut_lanpld_irq(unsigned int irq)
 171 {
 172         unsigned long port, data;
 173         unsigned int pldirq;
 174
 175         pldirq = irq2lanpldirq(irq);
 176         port = lanpldirq2port(pldirq);
 177         data = lanpld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
 178         outw(data, port);
 179 }
 180
 181 static void enable_m32700ut_lanpld_irq(unsigned int irq)
 182 {
 183         unsigned long port, data;
 184         unsigned int pldirq;
 185
 186         pldirq = irq2lanpldirq(irq);
 187         port = lanpldirq2port(pldirq);
 188         data = lanpld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
 189         outw(data, port);
 190 }
 191
 192 static void mask_and_ack_m32700ut_lanpld(unsigned int irq)
 193 {
 194         disable_m32700ut_lanpld_irq(irq);
 195 }
 196
 197 static void end_m32700ut_lanpld_irq(unsigned int irq)
 198 {
 199         enable_m32700ut_lanpld_irq(irq);
 200         end_m32700ut_irq(M32R_IRQ_INT0);
 201 }
 202
 203 static unsigned int startup_m32700ut_lanpld_irq(unsigned int irq)
 204 {
 205         enable_m32700ut_lanpld_irq(irq);
 206         return (0);
 207 }
 208
 209 static void shutdown_m32700ut_lanpld_irq(unsigned int irq)
 210 {
 211         unsigned long port;
 212         unsigned int pldirq;
 213
 214         pldirq = irq2lanpldirq(irq);
 215         port = lanpldirq2port(pldirq);
 216         outw(PLD_ICUCR_ILEVEL7, port);
 217 }
 218
 219 static struct hw_interrupt_type m32700ut_lanpld_irq_type =
 220 {
 221         .typename = "M32700UT-PLD-LAN-IRQ",
 222         .startup = startup_m32700ut_lanpld_irq,
 223         .shutdown = shutdown_m32700ut_lanpld_irq,
 224         .enable = enable_m32700ut_lanpld_irq,
 225         .disable = disable_m32700ut_lanpld_irq,
 226         .ack = mask_and_ack_m32700ut_lanpld,
 227         .end = end_m32700ut_lanpld_irq
 228 };
 229
 230 /*
 231  * Interrupt Control Unit of PLD on M32700UT-LCD (Level 2)
 232  */
 233 #define irq2lcdpldirq(x)        ((x) - M32700UT_LCD_PLD_IRQ_BASE)
 234 #define lcdpldirq2port(x)       (unsigned long)((int)M32700UT_LCD_ICUCR1 + \
 235                                  (((x) - 1) * sizeof(unsigned short)))
 236
 237 static pld_icu_data_t lcdpld_icu_data[M32700UT_NUM_LCD_PLD_IRQ];
 238
 239 static void disable_m32700ut_lcdpld_irq(unsigned int irq)
 240 {
 241         unsigned long port, data;
 242         unsigned int pldirq;
 243
 244         pldirq = irq2lcdpldirq(irq);
 245         port = lcdpldirq2port(pldirq);
 246         data = lcdpld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
 247         outw(data, port);
 248 }
 249
 250 static void enable_m32700ut_lcdpld_irq(unsigned int irq)
 251 {
 252         unsigned long port, data;
 253         unsigned int pldirq;
 254
 255         pldirq = irq2lcdpldirq(irq);
 256         port = lcdpldirq2port(pldirq);
 257         data = lcdpld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
 258         outw(data, port);
 259 }
 260
 261 static void mask_and_ack_m32700ut_lcdpld(unsigned int irq)
 262 {
 263         disable_m32700ut_lcdpld_irq(irq);
 264 }
 265
 266 static void end_m32700ut_lcdpld_irq(unsigned int irq)
 267 {
 268         enable_m32700ut_lcdpld_irq(irq);
 269         end_m32700ut_irq(M32R_IRQ_INT2);
 270 }
 271
 272 static unsigned int startup_m32700ut_lcdpld_irq(unsigned int irq)
 273 {
 274         enable_m32700ut_lcdpld_irq(irq);
 275         return (0);
 276 }
 277
 278 static void shutdown_m32700ut_lcdpld_irq(unsigned int irq)
 279 {
 280         unsigned long port;
 281         unsigned int pldirq;
 282
 283         pldirq = irq2lcdpldirq(irq);
 284         port = lcdpldirq2port(pldirq);
 285         outw(PLD_ICUCR_ILEVEL7, port);
 286 }
 287
 288 static struct hw_interrupt_type m32700ut_lcdpld_irq_type =
 289 {
 290         .typename = "M32700UT-PLD-LCD-IRQ",
 291         .startup = startup_m32700ut_lcdpld_irq,
 292         .shutdown = shutdown_m32700ut_lcdpld_irq,
 293         .enable = enable_m32700ut_lcdpld_irq,
 294         .disable = disable_m32700ut_lcdpld_irq,
 295         .ack = mask_and_ack_m32700ut_lcdpld,
 296         .end = end_m32700ut_lcdpld_irq
 297 };
 298
 299 void __init init_IRQ(void)
 300 {
 301 #if defined(CONFIG_SMC91X)
 302         /* INT#0: LAN controller on M32700UT-LAN (SMC91C111)*/
 303         irq_desc[M32700UT_LAN_IRQ_LAN].status = IRQ_DISABLED;
 304         irq_desc[M32700UT_LAN_IRQ_LAN].handler = &m32700ut_lanpld_irq_type;
 305         irq_desc[M32700UT_LAN_IRQ_LAN].action = 0;
 306         irq_desc[M32700UT_LAN_IRQ_LAN].depth = 1;       /* disable nested irq */
 307         lanpld_icu_data[irq2lanpldirq(M32700UT_LAN_IRQ_LAN)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02;   /* "H" edge sense */
 308         disable_m32700ut_lanpld_irq(M32700UT_LAN_IRQ_LAN);
 309 #endif  /* CONFIG_SMC91X */
 310
 311         /* MFT2 : system timer */
 312         irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED;
 313         irq_desc[M32R_IRQ_MFT2].handler = &m32700ut_irq_type;
 314         irq_desc[M32R_IRQ_MFT2].action = 0;
 315         irq_desc[M32R_IRQ_MFT2].depth = 1;
 316         icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
 317         disable_m32700ut_irq(M32R_IRQ_MFT2);
 318
 319         /* SIO0 : receive */
 320         irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED;
 321         irq_desc[M32R_IRQ_SIO0_R].handler = &m32700ut_irq_type;
 322         irq_desc[M32R_IRQ_SIO0_R].action = 0;
 323         irq_desc[M32R_IRQ_SIO0_R].depth = 1;
 324         icu_data[M32R_IRQ_SIO0_R].icucr = 0;
 325         disable_m32700ut_irq(M32R_IRQ_SIO0_R);
 326
 327         /* SIO0 : send */
 328         irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED;
 329         irq_desc[M32R_IRQ_SIO0_S].handler = &m32700ut_irq_type;
 330         irq_desc[M32R_IRQ_SIO0_S].action = 0;
 331         irq_desc[M32R_IRQ_SIO0_S].depth = 1;
 332         icu_data[M32R_IRQ_SIO0_S].icucr = 0;
 333         disable_m32700ut_irq(M32R_IRQ_SIO0_S);
 334
 335         /* SIO1 : receive */
 336         irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED;
 337         irq_desc[M32R_IRQ_SIO1_R].handler = &m32700ut_irq_type;
 338         irq_desc[M32R_IRQ_SIO1_R].action = 0;
 339         irq_desc[M32R_IRQ_SIO1_R].depth = 1;
 340         icu_data[M32R_IRQ_SIO1_R].icucr = 0;
 341         disable_m32700ut_irq(M32R_IRQ_SIO1_R);
 342
 343         /* SIO1 : send */
 344         irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED;
 345         irq_desc[M32R_IRQ_SIO1_S].handler = &m32700ut_irq_type;
 346         irq_desc[M32R_IRQ_SIO1_S].action = 0;
 347         irq_desc[M32R_IRQ_SIO1_S].depth = 1;
 348         icu_data[M32R_IRQ_SIO1_S].icucr = 0;
 349         disable_m32700ut_irq(M32R_IRQ_SIO1_S);
 350
 351         /* DMA1 : */
 352         irq_desc[M32R_IRQ_DMA1].status = IRQ_DISABLED;
 353         irq_desc[M32R_IRQ_DMA1].handler = &m32700ut_irq_type;
 354         irq_desc[M32R_IRQ_DMA1].action = 0;
 355         irq_desc[M32R_IRQ_DMA1].depth = 1;
 356         icu_data[M32R_IRQ_DMA1].icucr = 0;
 357         disable_m32700ut_irq(M32R_IRQ_DMA1);
 358
 359 #ifdef CONFIG_SERIAL_M32R_PLDSIO
 360         /* INT#1: SIO0 Receive on PLD */
 361         irq_desc[PLD_IRQ_SIO0_RCV].status = IRQ_DISABLED;
 362         irq_desc[PLD_IRQ_SIO0_RCV].handler = &m32700ut_pld_irq_type;
 363         irq_desc[PLD_IRQ_SIO0_RCV].action = 0;
 364         irq_desc[PLD_IRQ_SIO0_RCV].depth = 1;   /* disable nested irq */
 365         pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
 366         disable_m32700ut_pld_irq(PLD_IRQ_SIO0_RCV);
 367
 368         /* INT#1: SIO0 Send on PLD */
 369         irq_desc[PLD_IRQ_SIO0_SND].status = IRQ_DISABLED;
 370         irq_desc[PLD_IRQ_SIO0_SND].handler = &m32700ut_pld_irq_type;
 371         irq_desc[PLD_IRQ_SIO0_SND].action = 0;
 372         irq_desc[PLD_IRQ_SIO0_SND].depth = 1;   /* disable nested irq */
 373         pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
 374         disable_m32700ut_pld_irq(PLD_IRQ_SIO0_SND);
 375 #endif  /* CONFIG_SERIAL_M32R_PLDSIO */
 376
 377         /* INT#1: CFC IREQ on PLD */
 378         irq_desc[PLD_IRQ_CFIREQ].status = IRQ_DISABLED;
 379         irq_desc[PLD_IRQ_CFIREQ].handler = &m32700ut_pld_irq_type;
 380         irq_desc[PLD_IRQ_CFIREQ].action = 0;
 381         irq_desc[PLD_IRQ_CFIREQ].depth = 1;     /* disable nested irq */
 382         pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01;       /* 'L' level sense */
 383         disable_m32700ut_pld_irq(PLD_IRQ_CFIREQ);
 384
 385         /* INT#1: CFC Insert on PLD */
 386         irq_desc[PLD_IRQ_CFC_INSERT].status = IRQ_DISABLED;
 387         irq_desc[PLD_IRQ_CFC_INSERT].handler = &m32700ut_pld_irq_type;
 388         irq_desc[PLD_IRQ_CFC_INSERT].action = 0;
 389         irq_desc[PLD_IRQ_CFC_INSERT].depth = 1; /* disable nested irq */
 390         pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00;   /* 'L' edge sense */
 391         disable_m32700ut_pld_irq(PLD_IRQ_CFC_INSERT);
 392
 393         /* INT#1: CFC Eject on PLD */
 394         irq_desc[PLD_IRQ_CFC_EJECT].status = IRQ_DISABLED;
 395         irq_desc[PLD_IRQ_CFC_EJECT].handler = &m32700ut_pld_irq_type;
 396         irq_desc[PLD_IRQ_CFC_EJECT].action = 0;
 397         irq_desc[PLD_IRQ_CFC_EJECT].depth = 1;  /* disable nested irq */
 398         pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02;    /* 'H' edge sense */
 399         disable_m32700ut_pld_irq(PLD_IRQ_CFC_EJECT);
 400
 401         /*
 402          * INT0# is used for LAN, DIO
 403          * We enable it here.
 404          */
 405         icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11;
 406         enable_m32700ut_irq(M32R_IRQ_INT0);
 407
 408         /*
 409          * INT1# is used for UART, MMC, CF Controller in FPGA.
 410          * We enable it here.
 411          */
 412         icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11;
 413         enable_m32700ut_irq(M32R_IRQ_INT1);
 414
 415 #if defined(CONFIG_USB)
 416         outw(USBCR_OTGS, USBCR);        /* USBCR: non-OTG */
 417
 418     irq_desc[M32700UT_LCD_IRQ_USB_INT1].status = IRQ_DISABLED;
 419     irq_desc[M32700UT_LCD_IRQ_USB_INT1].handler = &m32700ut_lcdpld_irq_type;
 420     irq_desc[M32700UT_LCD_IRQ_USB_INT1].action = 0;
 421     irq_desc[M32700UT_LCD_IRQ_USB_INT1].depth = 1;
 422     lcdpld_icu_data[irq2lcdpldirq(M32700UT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01;  /* "L" level sense */
 423     disable_m32700ut_lcdpld_irq(M32700UT_LCD_IRQ_USB_INT1);
 424 #endif
 425         /*
 426          * INT2# is used for BAT, USB, AUDIO
 427          * We enable it here.
 428          */
 429         icu_data[M32R_IRQ_INT2].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01;
 430         enable_m32700ut_irq(M32R_IRQ_INT2);
 431
 432 #if defined(CONFIG_VIDEO_M32R_AR)
 433         /*
 434          * INT3# is used for AR
 435          */
 436         irq_desc[M32R_IRQ_INT3].status = IRQ_DISABLED;
 437         irq_desc[M32R_IRQ_INT3].handler = &m32700ut_irq_type;
 438         irq_desc[M32R_IRQ_INT3].action = 0;
 439         irq_desc[M32R_IRQ_INT3].depth = 1;
 440         icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
 441         disable_m32700ut_irq(M32R_IRQ_INT3);
 442 #endif  /* CONFIG_VIDEO_M32R_AR */
 443 }
 444
 445 #if defined(CONFIG_SMC91X)
 446
 447 #define LAN_IOSTART     0x300
 448 #define LAN_IOEND       0x320
 449 static struct resource smc91x_resources[] = {
 450         [0] = {
 451                 .start  = (LAN_IOSTART),
 452                 .end    = (LAN_IOEND),
 453                 .flags  = IORESOURCE_MEM,
 454         },
 455         [1] = {
 456                 .start  = M32700UT_LAN_IRQ_LAN,
 457                 .end    = M32700UT_LAN_IRQ_LAN,
 458                 .flags  = IORESOURCE_IRQ,
 459         }
 460 };
 461
 462 static struct platform_device smc91x_device = {
 463         .name           = "smc91x",
 464         .id             = 0,
 465         .num_resources  = ARRAY_SIZE(smc91x_resources),
 466         .resource       = smc91x_resources,
 467 };
 468 #endif
 469
 470 #if defined(CONFIG_FB_S1D13XXX)
 471
 472 #include <video/s1d13xxxfb.h>
 473 #include <asm/s1d13806.h>
 474
 475 static struct s1d13xxxfb_pdata s1d13xxxfb_data = {
 476         .initregs               = s1d13xxxfb_initregs,
 477         .initregssize           = ARRAY_SIZE(s1d13xxxfb_initregs),
 478         .platform_init_video    = NULL,
 479 #ifdef CONFIG_PM
 480         .platform_suspend_video = NULL,
 481         .platform_resume_video  = NULL,
 482 #endif
 483 };
 484
 485 static struct resource s1d13xxxfb_resources[] = {
 486         [0] = {
 487                 .start  = 0x10600000UL,
 488                 .end    = 0x1073FFFFUL,
 489                 .flags  = IORESOURCE_MEM,
 490         },
 491         [1] = {
 492                 .start  = 0x10400000UL,
 493                 .end    = 0x104001FFUL,
 494                 .flags  = IORESOURCE_MEM,
 495         }
 496 };
 497
 498 static struct platform_device s1d13xxxfb_device = {
 499         .name           = S1D_DEVICENAME,
 500         .id             = 0,
 501         .dev            = {
 502                 .platform_data  = &s1d13xxxfb_data,
 503         },
 504         .num_resources  = ARRAY_SIZE(s1d13xxxfb_resources),
 505         .resource       = s1d13xxxfb_resources,
 506 };
 507 #endif
 508
 509 static int __init platform_init(void)
 510 {
 511 #if defined(CONFIG_SMC91X)
 512         platform_device_register(&smc91x_device);
 513 #endif
 514 #if defined(CONFIG_FB_S1D13XXX)
 515         platform_device_register(&s1d13xxxfb_device);
 516 #endif
 517         return 0;
 518 }
 519 arch_initcall(platform_init);