git.oblomov.eu Git - linux-2.6/blob - drivers/net/typhoon.c

   1 /* typhoon.c: A Linux Ethernet device driver for 3Com 3CR990 family of NICs */
   2 /*
   3         Written 2002-2004 by David Dillow <dave@thedillows.org>
   4         Based on code written 1998-2000 by Donald Becker <becker@scyld.com> and
   5         Linux 2.2.x driver by David P. McLean <davidpmclean@yahoo.com>.
   6
   7         This software may be used and distributed according to the terms of
   8         the GNU General Public License (GPL), incorporated herein by reference.
   9         Drivers based on or derived from this code fall under the GPL and must
  10         retain the authorship, copyright and license notice.  This file is not
  11         a complete program and may only be used when the entire operating
  12         system is licensed under the GPL.
  13
  14         This software is available on a public web site. It may enable
  15         cryptographic capabilities of the 3Com hardware, and may be
  16         exported from the United States under License Exception "TSU"
  17         pursuant to 15 C.F.R. Section 740.13(e).
  18
  19         This work was funded by the National Library of Medicine under
  20         the Department of Energy project number 0274DD06D1 and NLM project
  21         number Y1-LM-2015-01.
  22
  23         This driver is designed for the 3Com 3CR990 Family of cards with the
  24         3XP Processor. It has been tested on x86 and sparc64.
  25
  26         KNOWN ISSUES:
  27         *) The current firmware always strips the VLAN tag off, even if
  28                 we tell it not to. You should filter VLANs at the switch
  29                 as a workaround (good practice in any event) until we can
  30                 get this fixed.
  31         *) Cannot DMA Rx packets to a 2 byte aligned address. Also firmware
  32                 issue. Hopefully 3Com will fix it.
  33         *) Waiting for a command response takes 8ms due to non-preemptable
  34                 polling. Only significant for getting stats and creating
  35                 SAs, but an ugly wart never the less.
  36
  37         TODO:
  38         *) Doesn't do IPSEC offloading. Yet. Keep yer pants on, it's coming.
  39         *) Add more support for ethtool (especially for NIC stats)
  40         *) Allow disabling of RX checksum offloading
  41         *) Fix MAC changing to work while the interface is up
  42                 (Need to put commands on the TX ring, which changes
  43                 the locking)
  44         *) Add in FCS to {rx,tx}_bytes, since the hardware doesn't. See
  45                 http://oss.sgi.com/cgi-bin/mesg.cgi?a=netdev&i=20031215152211.7003fe8e.rddunlap%40osdl.org
  46 */
  47
  48 /* Set the copy breakpoint for the copy-only-tiny-frames scheme.
  49  * Setting to > 1518 effectively disables this feature.
  50  */
  51 static int rx_copybreak = 200;
  52
  53 /* Should we use MMIO or Port IO?
  54  * 0: Port IO
  55  * 1: MMIO
  56  * 2: Try MMIO, fallback to Port IO
  57  */
  58 static unsigned int use_mmio = 2;
  59
  60 /* end user-configurable values */
  61
  62 /* Maximum number of multicast addresses to filter (vs. rx-all-multicast).
  63  */
  64 static const int multicast_filter_limit = 32;
  65
  66 /* Operational parameters that are set at compile time. */
  67
  68 /* Keep the ring sizes a power of two for compile efficiency.
  69  * The compiler will convert <unsigned>'%'<2^N> into a bit mask.
  70  * Making the Tx ring too large decreases the effectiveness of channel
  71  * bonding and packet priority.
  72  * There are no ill effects from too-large receive rings.
  73  *
  74  * We don't currently use the Hi Tx ring so, don't make it very big.
  75  *
  76  * Beware that if we start using the Hi Tx ring, we will need to change
  77  * typhoon_num_free_tx() and typhoon_tx_complete() to account for that.
  78  */
  79 #define TXHI_ENTRIES            2
  80 #define TXLO_ENTRIES            128
  81 #define RX_ENTRIES              32
  82 #define COMMAND_ENTRIES         16
  83 #define RESPONSE_ENTRIES        32
  84
  85 #define COMMAND_RING_SIZE       (COMMAND_ENTRIES * sizeof(struct cmd_desc))
  86 #define RESPONSE_RING_SIZE      (RESPONSE_ENTRIES * sizeof(struct resp_desc))
  87
  88 /* The 3XP will preload and remove 64 entries from the free buffer
  89  * list, and we need one entry to keep the ring from wrapping, so
  90  * to keep this a power of two, we use 128 entries.
  91  */
  92 #define RXFREE_ENTRIES          128
  93 #define RXENT_ENTRIES           (RXFREE_ENTRIES - 1)
  94
  95 /* Operational parameters that usually are not changed. */
  96
  97 /* Time in jiffies before concluding the transmitter is hung. */
  98 #define TX_TIMEOUT  (2*HZ)
  99
 100 #define PKT_BUF_SZ              1536
 101
 102 #define DRV_MODULE_NAME         "typhoon"
 103 #define DRV_MODULE_VERSION      "1.5.8"
 104 #define DRV_MODULE_RELDATE      "06/11/09"
 105 #define PFX                     DRV_MODULE_NAME ": "
 106 #define ERR_PFX                 KERN_ERR PFX
 107
 108 #include <linux/module.h>
 109 #include <linux/kernel.h>
 110 #include <linux/string.h>
 111 #include <linux/timer.h>
 112 #include <linux/errno.h>
 113 #include <linux/ioport.h>
 114 #include <linux/slab.h>
 115 #include <linux/interrupt.h>
 116 #include <linux/pci.h>
 117 #include <linux/netdevice.h>
 118 #include <linux/etherdevice.h>
 119 #include <linux/skbuff.h>
 120 #include <linux/mm.h>
 121 #include <linux/init.h>
 122 #include <linux/delay.h>
 123 #include <linux/ethtool.h>
 124 #include <linux/if_vlan.h>
 125 #include <linux/crc32.h>
 126 #include <linux/bitops.h>
 127 #include <asm/processor.h>
 128 #include <asm/io.h>
 129 #include <asm/uaccess.h>
 130 #include <linux/in6.h>
 131 #include <linux/version.h>
 132 #include <linux/dma-mapping.h>
 133
 134 #include "typhoon.h"
 135 #include "typhoon-firmware.h"
 136
 137 static char version[] __devinitdata =
 138     "typhoon.c: version " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
 139
 140 MODULE_AUTHOR("David Dillow <dave@thedillows.org>");
 141 MODULE_VERSION(DRV_MODULE_VERSION);
 142 MODULE_LICENSE("GPL");
 143 MODULE_DESCRIPTION("3Com Typhoon Family (3C990, 3CR990, and variants)");
 144 MODULE_PARM_DESC(rx_copybreak, "Packets smaller than this are copied and "
 145                                "the buffer given back to the NIC. Default "
 146                                "is 200.");
 147 MODULE_PARM_DESC(use_mmio, "Use MMIO (1) or PIO(0) to access the NIC. "
 148                            "Default is to try MMIO and fallback to PIO.");
 149 module_param(rx_copybreak, int, 0);
 150 module_param(use_mmio, int, 0);
 151
 152 #if defined(NETIF_F_TSO) && MAX_SKB_FRAGS > 32
 153 #warning Typhoon only supports 32 entries in its SG list for TSO, disabling TSO
 154 #undef NETIF_F_TSO
 155 #endif
 156
 157 #if TXLO_ENTRIES <= (2 * MAX_SKB_FRAGS)
 158 #error TX ring too small!
 159 #endif
 160
 161 struct typhoon_card_info {
 162         char *name;
 163         int capabilities;
 164 };
 165
 166 #define TYPHOON_CRYPTO_NONE             0x00
 167 #define TYPHOON_CRYPTO_DES              0x01
 168 #define TYPHOON_CRYPTO_3DES             0x02
 169 #define TYPHOON_CRYPTO_VARIABLE         0x04
 170 #define TYPHOON_FIBER                   0x08
 171 #define TYPHOON_WAKEUP_NEEDS_RESET      0x10
 172
 173 enum typhoon_cards {
 174         TYPHOON_TX = 0, TYPHOON_TX95, TYPHOON_TX97, TYPHOON_SVR,
 175         TYPHOON_SVR95, TYPHOON_SVR97, TYPHOON_TXM, TYPHOON_BSVR,
 176         TYPHOON_FX95, TYPHOON_FX97, TYPHOON_FX95SVR, TYPHOON_FX97SVR,
 177         TYPHOON_FXM,
 178 };
 179
 180 /* directly indexed by enum typhoon_cards, above */
 181 static struct typhoon_card_info typhoon_card_info[] __devinitdata = {
 182         { "3Com Typhoon (3C990-TX)",
 183                 TYPHOON_CRYPTO_NONE},
 184         { "3Com Typhoon (3CR990-TX-95)",
 185                 TYPHOON_CRYPTO_DES},
 186         { "3Com Typhoon (3CR990-TX-97)",
 187                 TYPHOON_CRYPTO_DES | TYPHOON_CRYPTO_3DES},
 188         { "3Com Typhoon (3C990SVR)",
 189                 TYPHOON_CRYPTO_NONE},
 190         { "3Com Typhoon (3CR990SVR95)",
 191                 TYPHOON_CRYPTO_DES},
 192         { "3Com Typhoon (3CR990SVR97)",
 193                 TYPHOON_CRYPTO_DES | TYPHOON_CRYPTO_3DES},
 194         { "3Com Typhoon2 (3C990B-TX-M)",
 195                 TYPHOON_CRYPTO_VARIABLE},
 196         { "3Com Typhoon2 (3C990BSVR)",
 197                 TYPHOON_CRYPTO_VARIABLE},
 198         { "3Com Typhoon (3CR990-FX-95)",
 199                 TYPHOON_CRYPTO_DES | TYPHOON_FIBER},
 200         { "3Com Typhoon (3CR990-FX-97)",
 201                 TYPHOON_CRYPTO_DES | TYPHOON_CRYPTO_3DES | TYPHOON_FIBER},
 202         { "3Com Typhoon (3CR990-FX-95 Server)",
 203                 TYPHOON_CRYPTO_DES | TYPHOON_FIBER},
 204         { "3Com Typhoon (3CR990-FX-97 Server)",
 205                 TYPHOON_CRYPTO_DES | TYPHOON_CRYPTO_3DES | TYPHOON_FIBER},
 206         { "3Com Typhoon2 (3C990B-FX-97)",
 207                 TYPHOON_CRYPTO_VARIABLE | TYPHOON_FIBER},
 208 };
 209
 210 /* Notes on the new subsystem numbering scheme:
 211  * bits 0-1 indicate crypto capabilities: (0) variable, (1) DES, or (2) 3DES
 212  * bit 4 indicates if this card has secured firmware (we don't support it)
 213  * bit 8 indicates if this is a (0) copper or (1) fiber card
 214  * bits 12-16 indicate card type: (0) client and (1) server
 215  */
 216 static struct pci_device_id typhoon_pci_tbl[] = {
 217         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990,
 218           PCI_ANY_ID, PCI_ANY_ID, 0, 0,TYPHOON_TX },
 219         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_TX_95,
 220           PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_TX95 },
 221         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_TX_97,
 222           PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_TX97 },
 223         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990B,
 224           PCI_ANY_ID, 0x1000, 0, 0, TYPHOON_TXM },
 225         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990B,
 226           PCI_ANY_ID, 0x1102, 0, 0, TYPHOON_FXM },
 227         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990B,
 228           PCI_ANY_ID, 0x2000, 0, 0, TYPHOON_BSVR },
 229         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_FX,
 230           PCI_ANY_ID, 0x1101, 0, 0, TYPHOON_FX95 },
 231         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_FX,
 232           PCI_ANY_ID, 0x1102, 0, 0, TYPHOON_FX97 },
 233         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_FX,
 234           PCI_ANY_ID, 0x2101, 0, 0, TYPHOON_FX95SVR },
 235         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_FX,
 236           PCI_ANY_ID, 0x2102, 0, 0, TYPHOON_FX97SVR },
 237         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990SVR95,
 238           PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_SVR95 },
 239         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990SVR97,
 240           PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_SVR97 },
 241         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990SVR,
 242           PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_SVR },
 243         { 0, }
 244 };
 245 MODULE_DEVICE_TABLE(pci, typhoon_pci_tbl);
 246
 247 /* Define the shared memory area
 248  * Align everything the 3XP will normally be using.
 249  * We'll need to move/align txHi if we start using that ring.
 250  */
 251 #define __3xp_aligned   ____cacheline_aligned
 252 struct typhoon_shared {
 253         struct typhoon_interface        iface;
 254         struct typhoon_indexes          indexes                 __3xp_aligned;
 255         struct tx_desc                  txLo[TXLO_ENTRIES]      __3xp_aligned;
 256         struct rx_desc                  rxLo[RX_ENTRIES]        __3xp_aligned;
 257         struct rx_desc                  rxHi[RX_ENTRIES]        __3xp_aligned;
 258         struct cmd_desc                 cmd[COMMAND_ENTRIES]    __3xp_aligned;
 259         struct resp_desc                resp[RESPONSE_ENTRIES]  __3xp_aligned;
 260         struct rx_free                  rxBuff[RXFREE_ENTRIES]  __3xp_aligned;
 261         u32                             zeroWord;
 262         struct tx_desc                  txHi[TXHI_ENTRIES];
 263 } __attribute__ ((packed));
 264
 265 struct rxbuff_ent {
 266         struct sk_buff *skb;
 267         dma_addr_t      dma_addr;
 268 };
 269
 270 struct typhoon {
 271         /* Tx cache line section */
 272         struct transmit_ring    txLoRing        ____cacheline_aligned;
 273         struct pci_dev *        tx_pdev;
 274         void __iomem            *tx_ioaddr;
 275         u32                     txlo_dma_addr;
 276
 277         /* Irq/Rx cache line section */
 278         void __iomem            *ioaddr         ____cacheline_aligned;
 279         struct typhoon_indexes *indexes;
 280         u8                      awaiting_resp;
 281         u8                      duplex;
 282         u8                      speed;
 283         u8                      card_state;
 284         struct basic_ring       rxLoRing;
 285         struct pci_dev *        pdev;
 286         struct net_device *     dev;
 287         struct napi_struct      napi;
 288         spinlock_t              state_lock;
 289         struct vlan_group *     vlgrp;
 290         struct basic_ring       rxHiRing;
 291         struct basic_ring       rxBuffRing;
 292         struct rxbuff_ent       rxbuffers[RXENT_ENTRIES];
 293
 294         /* general section */
 295         spinlock_t              command_lock    ____cacheline_aligned;
 296         struct basic_ring       cmdRing;
 297         struct basic_ring       respRing;
 298         struct net_device_stats stats;
 299         struct net_device_stats stats_saved;
 300         const char *            name;
 301         struct typhoon_shared * shared;
 302         dma_addr_t              shared_dma;
 303         __le16                  xcvr_select;
 304         __le16                  wol_events;
 305         __le32                  offload;
 306
 307         /* unused stuff (future use) */
 308         int                     capabilities;
 309         struct transmit_ring    txHiRing;
 310 };
 311
 312 enum completion_wait_values {
 313         NoWait = 0, WaitNoSleep, WaitSleep,
 314 };
 315
 316 /* These are the values for the typhoon.card_state variable.
 317  * These determine where the statistics will come from in get_stats().
 318  * The sleep image does not support the statistics we need.
 319  */
 320 enum state_values {
 321         Sleeping = 0, Running,
 322 };
 323
 324 /* PCI writes are not guaranteed to be posted in order, but outstanding writes
 325  * cannot pass a read, so this forces current writes to post.
 326  */
 327 #define typhoon_post_pci_writes(x) \
 328         do { if(likely(use_mmio)) ioread32(x+TYPHOON_REG_HEARTBEAT); } while(0)
 329
 330 /* We'll wait up to six seconds for a reset, and half a second normally.
 331  */
 332 #define TYPHOON_UDELAY                  50
 333 #define TYPHOON_RESET_TIMEOUT_SLEEP     (6 * HZ)
 334 #define TYPHOON_RESET_TIMEOUT_NOSLEEP   ((6 * 1000000) / TYPHOON_UDELAY)
 335 #define TYPHOON_WAIT_TIMEOUT            ((1000000 / 2) / TYPHOON_UDELAY)
 336
 337 #define typhoon_synchronize_irq(x) synchronize_irq(x)
 338
 339 #if defined(NETIF_F_TSO)
 340 #define skb_tso_size(x)         (skb_shinfo(x)->gso_size)
 341 #define TSO_NUM_DESCRIPTORS     2
 342 #define TSO_OFFLOAD_ON          TYPHOON_OFFLOAD_TCP_SEGMENT
 343 #else
 344 #define NETIF_F_TSO             0
 345 #define skb_tso_size(x)         0
 346 #define TSO_NUM_DESCRIPTORS     0
 347 #define TSO_OFFLOAD_ON          0
 348 #endif
 349
 350 static inline void
 351 typhoon_inc_index(u32 *index, const int count, const int num_entries)
 352 {
 353         /* Increment a ring index -- we can use this for all rings execept
 354          * the Rx rings, as they use different size descriptors
 355          * otherwise, everything is the same size as a cmd_desc
 356          */
 357         *index += count * sizeof(struct cmd_desc);
 358         *index %= num_entries * sizeof(struct cmd_desc);
 359 }
 360
 361 static inline void
 362 typhoon_inc_cmd_index(u32 *index, const int count)
 363 {
 364         typhoon_inc_index(index, count, COMMAND_ENTRIES);
 365 }
 366
 367 static inline void
 368 typhoon_inc_resp_index(u32 *index, const int count)
 369 {
 370         typhoon_inc_index(index, count, RESPONSE_ENTRIES);
 371 }
 372
 373 static inline void
 374 typhoon_inc_rxfree_index(u32 *index, const int count)
 375 {
 376         typhoon_inc_index(index, count, RXFREE_ENTRIES);
 377 }
 378
 379 static inline void
 380 typhoon_inc_tx_index(u32 *index, const int count)
 381 {
 382         /* if we start using the Hi Tx ring, this needs updateing */
 383         typhoon_inc_index(index, count, TXLO_ENTRIES);
 384 }
 385
 386 static inline void
 387 typhoon_inc_rx_index(u32 *index, const int count)
 388 {
 389         /* sizeof(struct rx_desc) != sizeof(struct cmd_desc) */
 390         *index += count * sizeof(struct rx_desc);
 391         *index %= RX_ENTRIES * sizeof(struct rx_desc);
 392 }
 393
 394 static int
 395 typhoon_reset(void __iomem *ioaddr, int wait_type)
 396 {
 397         int i, err = 0;
 398         int timeout;
 399
 400         if(wait_type == WaitNoSleep)
 401                 timeout = TYPHOON_RESET_TIMEOUT_NOSLEEP;
 402         else
 403                 timeout = TYPHOON_RESET_TIMEOUT_SLEEP;
 404
 405         iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
 406         iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_STATUS);
 407
 408         iowrite32(TYPHOON_RESET_ALL, ioaddr + TYPHOON_REG_SOFT_RESET);
 409         typhoon_post_pci_writes(ioaddr);
 410         udelay(1);
 411         iowrite32(TYPHOON_RESET_NONE, ioaddr + TYPHOON_REG_SOFT_RESET);
 412
 413         if(wait_type != NoWait) {
 414                 for(i = 0; i < timeout; i++) {
 415                         if(ioread32(ioaddr + TYPHOON_REG_STATUS) ==
 416                            TYPHOON_STATUS_WAITING_FOR_HOST)
 417                                 goto out;
 418
 419                         if(wait_type == WaitSleep)
 420                                 schedule_timeout_uninterruptible(1);
 421                         else
 422                                 udelay(TYPHOON_UDELAY);
 423                 }
 424
 425                 err = -ETIMEDOUT;
 426         }
 427
 428 out:
 429         iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
 430         iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_STATUS);
 431
 432         /* The 3XP seems to need a little extra time to complete the load
 433          * of the sleep image before we can reliably boot it. Failure to
 434          * do this occasionally results in a hung adapter after boot in
 435          * typhoon_init_one() while trying to read the MAC address or
 436          * putting the card to sleep. 3Com's driver waits 5ms, but
 437          * that seems to be overkill. However, if we can sleep, we might
 438          * as well give it that much time. Otherwise, we'll give it 500us,
 439          * which should be enough (I've see it work well at 100us, but still
 440          * saw occasional problems.)
 441          */
 442         if(wait_type == WaitSleep)
 443                 msleep(5);
 444         else
 445                 udelay(500);
 446         return err;
 447 }
 448
 449 static int
 450 typhoon_wait_status(void __iomem *ioaddr, u32 wait_value)
 451 {
 452         int i, err = 0;
 453
 454         for(i = 0; i < TYPHOON_WAIT_TIMEOUT; i++) {
 455                 if(ioread32(ioaddr + TYPHOON_REG_STATUS) == wait_value)
 456                         goto out;
 457                 udelay(TYPHOON_UDELAY);
 458         }
 459
 460         err = -ETIMEDOUT;
 461
 462 out:
 463         return err;
 464 }
 465
 466 static inline void
 467 typhoon_media_status(struct net_device *dev, struct resp_desc *resp)
 468 {
 469         if(resp->parm1 & TYPHOON_MEDIA_STAT_NO_LINK)
 470                 netif_carrier_off(dev);
 471         else
 472                 netif_carrier_on(dev);
 473 }
 474
 475 static inline void
 476 typhoon_hello(struct typhoon *tp)
 477 {
 478         struct basic_ring *ring = &tp->cmdRing;
 479         struct cmd_desc *cmd;
 480
 481         /* We only get a hello request if we've not sent anything to the
 482          * card in a long while. If the lock is held, then we're in the
 483          * process of issuing a command, so we don't need to respond.
 484          */
 485         if(spin_trylock(&tp->command_lock)) {
 486                 cmd = (struct cmd_desc *)(ring->ringBase + ring->lastWrite);
 487                 typhoon_inc_cmd_index(&ring->lastWrite, 1);
 488
 489                 INIT_COMMAND_NO_RESPONSE(cmd, TYPHOON_CMD_HELLO_RESP);
 490                 smp_wmb();
 491                 iowrite32(ring->lastWrite, tp->ioaddr + TYPHOON_REG_CMD_READY);
 492                 spin_unlock(&tp->command_lock);
 493         }
 494 }
 495
 496 static int
 497 typhoon_process_response(struct typhoon *tp, int resp_size,
 498                                 struct resp_desc *resp_save)
 499 {
 500         struct typhoon_indexes *indexes = tp->indexes;
 501         struct resp_desc *resp;
 502         u8 *base = tp->respRing.ringBase;
 503         int count, len, wrap_len;
 504         u32 cleared;
 505         u32 ready;
 506
 507         cleared = le32_to_cpu(indexes->respCleared);
 508         ready = le32_to_cpu(indexes->respReady);
 509         while(cleared != ready) {
 510                 resp = (struct resp_desc *)(base + cleared);
 511                 count = resp->numDesc + 1;
 512                 if(resp_save && resp->seqNo) {
 513                         if(count > resp_size) {
 514                                 resp_save->flags = TYPHOON_RESP_ERROR;
 515                                 goto cleanup;
 516                         }
 517
 518                         wrap_len = 0;
 519                         len = count * sizeof(*resp);
 520                         if(unlikely(cleared + len > RESPONSE_RING_SIZE)) {
 521                                 wrap_len = cleared + len - RESPONSE_RING_SIZE;
 522                                 len = RESPONSE_RING_SIZE - cleared;
 523                         }
 524
 525                         memcpy(resp_save, resp, len);
 526                         if(unlikely(wrap_len)) {
 527                                 resp_save += len / sizeof(*resp);
 528                                 memcpy(resp_save, base, wrap_len);
 529                         }
 530
 531                         resp_save = NULL;
 532                 } else if(resp->cmd == TYPHOON_CMD_READ_MEDIA_STATUS) {
 533                         typhoon_media_status(tp->dev, resp);
 534                 } else if(resp->cmd == TYPHOON_CMD_HELLO_RESP) {
 535                         typhoon_hello(tp);
 536                 } else {
 537                         printk(KERN_ERR "%s: dumping unexpected response "
 538                                "0x%04x:%d:0x%02x:0x%04x:%08x:%08x\n",
 539                                tp->name, le16_to_cpu(resp->cmd),
 540                                resp->numDesc, resp->flags,
 541                                le16_to_cpu(resp->parm1),
 542                                le32_to_cpu(resp->parm2),
 543                                le32_to_cpu(resp->parm3));
 544                 }
 545
 546 cleanup:
 547                 typhoon_inc_resp_index(&cleared, count);
 548         }
 549
 550         indexes->respCleared = cpu_to_le32(cleared);
 551         wmb();
 552         return (resp_save == NULL);
 553 }
 554
 555 static inline int
 556 typhoon_num_free(int lastWrite, int lastRead, int ringSize)
 557 {
 558         /* this works for all descriptors but rx_desc, as they are a
 559          * different size than the cmd_desc -- everyone else is the same
 560          */
 561         lastWrite /= sizeof(struct cmd_desc);
 562         lastRead /= sizeof(struct cmd_desc);
 563         return (ringSize + lastRead - lastWrite - 1) % ringSize;
 564 }
 565
 566 static inline int
 567 typhoon_num_free_cmd(struct typhoon *tp)
 568 {
 569         int lastWrite = tp->cmdRing.lastWrite;
 570         int cmdCleared = le32_to_cpu(tp->indexes->cmdCleared);
 571
 572         return typhoon_num_free(lastWrite, cmdCleared, COMMAND_ENTRIES);
 573 }
 574
 575 static inline int
 576 typhoon_num_free_resp(struct typhoon *tp)
 577 {
 578         int respReady = le32_to_cpu(tp->indexes->respReady);
 579         int respCleared = le32_to_cpu(tp->indexes->respCleared);
 580
 581         return typhoon_num_free(respReady, respCleared, RESPONSE_ENTRIES);
 582 }
 583
 584 static inline int
 585 typhoon_num_free_tx(struct transmit_ring *ring)
 586 {
 587         /* if we start using the Hi Tx ring, this needs updating */
 588         return typhoon_num_free(ring->lastWrite, ring->lastRead, TXLO_ENTRIES);
 589 }
 590
 591 static int
 592 typhoon_issue_command(struct typhoon *tp, int num_cmd, struct cmd_desc *cmd,
 593                       int num_resp, struct resp_desc *resp)
 594 {
 595         struct typhoon_indexes *indexes = tp->indexes;
 596         struct basic_ring *ring = &tp->cmdRing;
 597         struct resp_desc local_resp;
 598         int i, err = 0;
 599         int got_resp;
 600         int freeCmd, freeResp;
 601         int len, wrap_len;
 602
 603         spin_lock(&tp->command_lock);
 604
 605         freeCmd = typhoon_num_free_cmd(tp);
 606         freeResp = typhoon_num_free_resp(tp);
 607
 608         if(freeCmd < num_cmd || freeResp < num_resp) {
 609                 printk("%s: no descs for cmd, had (needed) %d (%d) cmd, "
 610                         "%d (%d) resp\n", tp->name, freeCmd, num_cmd,
 611                         freeResp, num_resp);
 612                 err = -ENOMEM;
 613                 goto out;
 614         }
 615
 616         if(cmd->flags & TYPHOON_CMD_RESPOND) {
 617                 /* If we're expecting a response, but the caller hasn't given
 618                  * us a place to put it, we'll provide one.
 619                  */
 620                 tp->awaiting_resp = 1;
 621                 if(resp == NULL) {
 622                         resp = &local_resp;
 623                         num_resp = 1;
 624                 }
 625         }
 626
 627         wrap_len = 0;
 628         len = num_cmd * sizeof(*cmd);
 629         if(unlikely(ring->lastWrite + len > COMMAND_RING_SIZE)) {
 630                 wrap_len = ring->lastWrite + len - COMMAND_RING_SIZE;
 631                 len = COMMAND_RING_SIZE - ring->lastWrite;
 632         }
 633
 634         memcpy(ring->ringBase + ring->lastWrite, cmd, len);
 635         if(unlikely(wrap_len)) {
 636                 struct cmd_desc *wrap_ptr = cmd;
 637                 wrap_ptr += len / sizeof(*cmd);
 638                 memcpy(ring->ringBase, wrap_ptr, wrap_len);
 639         }
 640
 641         typhoon_inc_cmd_index(&ring->lastWrite, num_cmd);
 642
 643         /* "I feel a presence... another warrior is on the mesa."
 644          */
 645         wmb();
 646         iowrite32(ring->lastWrite, tp->ioaddr + TYPHOON_REG_CMD_READY);
 647         typhoon_post_pci_writes(tp->ioaddr);
 648
 649         if((cmd->flags & TYPHOON_CMD_RESPOND) == 0)
 650                 goto out;
 651
 652         /* Ugh. We'll be here about 8ms, spinning our thumbs, unable to
 653          * preempt or do anything other than take interrupts. So, don't
 654          * wait for a response unless you have to.
 655          *
 656          * I've thought about trying to sleep here, but we're called
 657          * from many contexts that don't allow that. Also, given the way
 658          * 3Com has implemented irq coalescing, we would likely timeout --
 659          * this has been observed in real life!
 660          *
 661          * The big killer is we have to wait to get stats from the card,
 662          * though we could go to a periodic refresh of those if we don't
 663          * mind them getting somewhat stale. The rest of the waiting
 664          * commands occur during open/close/suspend/resume, so they aren't
 665          * time critical. Creating SAs in the future will also have to
 666          * wait here.
 667          */
 668         got_resp = 0;
 669         for(i = 0; i < TYPHOON_WAIT_TIMEOUT && !got_resp; i++) {
 670                 if(indexes->respCleared != indexes->respReady)
 671                         got_resp = typhoon_process_response(tp, num_resp,
 672                                                                 resp);
 673                 udelay(TYPHOON_UDELAY);
 674         }
 675
 676         if(!got_resp) {
 677                 err = -ETIMEDOUT;
 678                 goto out;
 679         }
 680
 681         /* Collect the error response even if we don't care about the
 682          * rest of the response
 683          */
 684         if(resp->flags & TYPHOON_RESP_ERROR)
 685                 err = -EIO;
 686
 687 out:
 688         if(tp->awaiting_resp) {
 689                 tp->awaiting_resp = 0;
 690                 smp_wmb();
 691
 692                 /* Ugh. If a response was added to the ring between
 693                  * the call to typhoon_process_response() and the clearing
 694                  * of tp->awaiting_resp, we could have missed the interrupt
 695                  * and it could hang in the ring an indeterminate amount of
 696                  * time. So, check for it, and interrupt ourselves if this
 697                  * is the case.
 698                  */
 699                 if(indexes->respCleared != indexes->respReady)
 700                         iowrite32(1, tp->ioaddr + TYPHOON_REG_SELF_INTERRUPT);
 701         }
 702
 703         spin_unlock(&tp->command_lock);
 704         return err;
 705 }
 706
 707 static void
 708 typhoon_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
 709 {
 710         struct typhoon *tp = netdev_priv(dev);
 711         struct cmd_desc xp_cmd;
 712         int err;
 713
 714         spin_lock_bh(&tp->state_lock);
 715         if(!tp->vlgrp != !grp) {
 716                 /* We've either been turned on for the first time, or we've
 717                  * been turned off. Update the 3XP.
 718                  */
 719                 if(grp)
 720                         tp->offload |= TYPHOON_OFFLOAD_VLAN;
 721                 else
 722                         tp->offload &= ~TYPHOON_OFFLOAD_VLAN;
 723
 724                 /* If the interface is up, the runtime is running -- and we
 725                  * must be up for the vlan core to call us.
 726                  *
 727                  * Do the command outside of the spin lock, as it is slow.
 728                  */
 729                 INIT_COMMAND_WITH_RESPONSE(&xp_cmd,
 730                                         TYPHOON_CMD_SET_OFFLOAD_TASKS);
 731                 xp_cmd.parm2 = tp->offload;
 732                 xp_cmd.parm3 = tp->offload;
 733                 spin_unlock_bh(&tp->state_lock);
 734                 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
 735                 if(err < 0)
 736                         printk("%s: vlan offload error %d\n", tp->name, -err);
 737                 spin_lock_bh(&tp->state_lock);
 738         }
 739
 740         /* now make the change visible */
 741         tp->vlgrp = grp;
 742         spin_unlock_bh(&tp->state_lock);
 743 }
 744
 745 static inline void
 746 typhoon_tso_fill(struct sk_buff *skb, struct transmit_ring *txRing,
 747                         u32 ring_dma)
 748 {
 749         struct tcpopt_desc *tcpd;
 750         u32 tcpd_offset = ring_dma;
 751
 752         tcpd = (struct tcpopt_desc *) (txRing->ringBase + txRing->lastWrite);
 753         tcpd_offset += txRing->lastWrite;
 754         tcpd_offset += offsetof(struct tcpopt_desc, bytesTx);
 755         typhoon_inc_tx_index(&txRing->lastWrite, 1);
 756
 757         tcpd->flags = TYPHOON_OPT_DESC | TYPHOON_OPT_TCP_SEG;
 758         tcpd->numDesc = 1;
 759         tcpd->mss_flags = cpu_to_le16(skb_tso_size(skb));
 760         tcpd->mss_flags |= TYPHOON_TSO_FIRST | TYPHOON_TSO_LAST;
 761         tcpd->respAddrLo = cpu_to_le32(tcpd_offset);
 762         tcpd->bytesTx = cpu_to_le32(skb->len);
 763         tcpd->status = 0;
 764 }
 765
 766 static int
 767 typhoon_start_tx(struct sk_buff *skb, struct net_device *dev)
 768 {
 769         struct typhoon *tp = netdev_priv(dev);
 770         struct transmit_ring *txRing;
 771         struct tx_desc *txd, *first_txd;
 772         dma_addr_t skb_dma;
 773         int numDesc;
 774
 775         /* we have two rings to choose from, but we only use txLo for now
 776          * If we start using the Hi ring as well, we'll need to update
 777          * typhoon_stop_runtime(), typhoon_interrupt(), typhoon_num_free_tx(),
 778          * and TXHI_ENTRIES to match, as well as update the TSO code below
 779          * to get the right DMA address
 780          */
 781         txRing = &tp->txLoRing;
 782
 783         /* We need one descriptor for each fragment of the sk_buff, plus the
 784          * one for the ->data area of it.
 785          *
 786          * The docs say a maximum of 16 fragment descriptors per TCP option
 787          * descriptor, then make a new packet descriptor and option descriptor
 788          * for the next 16 fragments. The engineers say just an option
 789          * descriptor is needed. I've tested up to 26 fragments with a single
 790          * packet descriptor/option descriptor combo, so I use that for now.
 791          *
 792          * If problems develop with TSO, check this first.
 793          */
 794         numDesc = skb_shinfo(skb)->nr_frags + 1;
 795         if (skb_is_gso(skb))
 796                 numDesc++;
 797
 798         /* When checking for free space in the ring, we need to also
 799          * account for the initial Tx descriptor, and we always must leave
 800          * at least one descriptor unused in the ring so that it doesn't
 801          * wrap and look empty.
 802          *
 803          * The only time we should loop here is when we hit the race
 804          * between marking the queue awake and updating the cleared index.
 805          * Just loop and it will appear. This comes from the acenic driver.
 806          */
 807         while(unlikely(typhoon_num_free_tx(txRing) < (numDesc + 2)))
 808                 smp_rmb();
 809
 810         first_txd = (struct tx_desc *) (txRing->ringBase + txRing->lastWrite);
 811         typhoon_inc_tx_index(&txRing->lastWrite, 1);
 812
 813         first_txd->flags = TYPHOON_TX_DESC | TYPHOON_DESC_VALID;
 814         first_txd->numDesc = 0;
 815         first_txd->len = 0;
 816         first_txd->tx_addr = (u64)((unsigned long) skb);
 817         first_txd->processFlags = 0;
 818
 819         if(skb->ip_summed == CHECKSUM_PARTIAL) {
 820                 /* The 3XP will figure out if this is UDP/TCP */
 821                 first_txd->processFlags |= TYPHOON_TX_PF_TCP_CHKSUM;
 822                 first_txd->processFlags |= TYPHOON_TX_PF_UDP_CHKSUM;
 823                 first_txd->processFlags |= TYPHOON_TX_PF_IP_CHKSUM;
 824         }
 825
 826         if(vlan_tx_tag_present(skb)) {
 827                 first_txd->processFlags |=
 828                     TYPHOON_TX_PF_INSERT_VLAN | TYPHOON_TX_PF_VLAN_PRIORITY;
 829                 first_txd->processFlags |=
 830                     cpu_to_le32(ntohs(vlan_tx_tag_get(skb)) <<
 831                                 TYPHOON_TX_PF_VLAN_TAG_SHIFT);
 832         }
 833
 834         if (skb_is_gso(skb)) {
 835                 first_txd->processFlags |= TYPHOON_TX_PF_TCP_SEGMENT;
 836                 first_txd->numDesc++;
 837
 838                 typhoon_tso_fill(skb, txRing, tp->txlo_dma_addr);
 839         }
 840
 841         txd = (struct tx_desc *) (txRing->ringBase + txRing->lastWrite);
 842         typhoon_inc_tx_index(&txRing->lastWrite, 1);
 843
 844         /* No need to worry about padding packet -- the firmware pads
 845          * it with zeros to ETH_ZLEN for us.
 846          */
 847         if(skb_shinfo(skb)->nr_frags == 0) {
 848                 skb_dma = pci_map_single(tp->tx_pdev, skb->data, skb->len,
 849                                        PCI_DMA_TODEVICE);
 850                 txd->flags = TYPHOON_FRAG_DESC | TYPHOON_DESC_VALID;
 851                 txd->len = cpu_to_le16(skb->len);
 852                 txd->frag.addr = cpu_to_le32(skb_dma);
 853                 txd->frag.addrHi = 0;
 854                 first_txd->numDesc++;
 855         } else {
 856                 int i, len;
 857
 858                 len = skb_headlen(skb);
 859                 skb_dma = pci_map_single(tp->tx_pdev, skb->data, len,
 860                                          PCI_DMA_TODEVICE);
 861                 txd->flags = TYPHOON_FRAG_DESC | TYPHOON_DESC_VALID;
 862                 txd->len = cpu_to_le16(len);
 863                 txd->frag.addr = cpu_to_le32(skb_dma);
 864                 txd->frag.addrHi = 0;
 865                 first_txd->numDesc++;
 866
 867                 for(i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
 868                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
 869                         void *frag_addr;
 870
 871                         txd = (struct tx_desc *) (txRing->ringBase +
 872                                                 txRing->lastWrite);
 873                         typhoon_inc_tx_index(&txRing->lastWrite, 1);
 874
 875                         len = frag->size;
 876                         frag_addr = (void *) page_address(frag->page) +
 877                                                 frag->page_offset;
 878                         skb_dma = pci_map_single(tp->tx_pdev, frag_addr, len,
 879                                          PCI_DMA_TODEVICE);
 880                         txd->flags = TYPHOON_FRAG_DESC | TYPHOON_DESC_VALID;
 881                         txd->len = cpu_to_le16(len);
 882                         txd->frag.addr = cpu_to_le32(skb_dma);
 883                         txd->frag.addrHi = 0;
 884                         first_txd->numDesc++;
 885                 }
 886         }
 887
 888         /* Kick the 3XP
 889          */
 890         wmb();
 891         iowrite32(txRing->lastWrite, tp->tx_ioaddr + txRing->writeRegister);
 892
 893         dev->trans_start = jiffies;
 894
 895         /* If we don't have room to put the worst case packet on the
 896          * queue, then we must stop the queue. We need 2 extra
 897          * descriptors -- one to prevent ring wrap, and one for the
 898          * Tx header.
 899          */
 900         numDesc = MAX_SKB_FRAGS + TSO_NUM_DESCRIPTORS + 1;
 901
 902         if(typhoon_num_free_tx(txRing) < (numDesc + 2)) {
 903                 netif_stop_queue(dev);
 904
 905                 /* A Tx complete IRQ could have gotten inbetween, making
 906                  * the ring free again. Only need to recheck here, since
 907                  * Tx is serialized.
 908                  */
 909                 if(typhoon_num_free_tx(txRing) >= (numDesc + 2))
 910                         netif_wake_queue(dev);
 911         }
 912
 913         return 0;
 914 }
 915
 916 static void
 917 typhoon_set_rx_mode(struct net_device *dev)
 918 {
 919         struct typhoon *tp = netdev_priv(dev);
 920         struct cmd_desc xp_cmd;
 921         u32 mc_filter[2];
 922         __le16 filter;
 923
 924         filter = TYPHOON_RX_FILTER_DIRECTED | TYPHOON_RX_FILTER_BROADCAST;
 925         if(dev->flags & IFF_PROMISC) {
 926                 filter |= TYPHOON_RX_FILTER_PROMISCOUS;
 927         } else if((dev->mc_count > multicast_filter_limit) ||
 928                   (dev->flags & IFF_ALLMULTI)) {
 929                 /* Too many to match, or accept all multicasts. */
 930                 filter |= TYPHOON_RX_FILTER_ALL_MCAST;
 931         } else if(dev->mc_count) {
 932                 struct dev_mc_list *mclist;
 933                 int i;
 934
 935                 memset(mc_filter, 0, sizeof(mc_filter));
 936                 for(i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
 937                     i++, mclist = mclist->next) {
 938                         int bit = ether_crc(ETH_ALEN, mclist->dmi_addr) & 0x3f;
 939                         mc_filter[bit >> 5] |= 1 << (bit & 0x1f);
 940                 }
 941
 942                 INIT_COMMAND_NO_RESPONSE(&xp_cmd,
 943                                          TYPHOON_CMD_SET_MULTICAST_HASH);
 944                 xp_cmd.parm1 = TYPHOON_MCAST_HASH_SET;
 945                 xp_cmd.parm2 = cpu_to_le32(mc_filter[0]);
 946                 xp_cmd.parm3 = cpu_to_le32(mc_filter[1]);
 947                 typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
 948
 949                 filter |= TYPHOON_RX_FILTER_MCAST_HASH;
 950         }
 951
 952         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_RX_FILTER);
 953         xp_cmd.parm1 = filter;
 954         typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
 955 }
 956
 957 static int
 958 typhoon_do_get_stats(struct typhoon *tp)
 959 {
 960         struct net_device_stats *stats = &tp->stats;
 961         struct net_device_stats *saved = &tp->stats_saved;
 962         struct cmd_desc xp_cmd;
 963         struct resp_desc xp_resp[7];
 964         struct stats_resp *s = (struct stats_resp *) xp_resp;
 965         int err;
 966
 967         INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_READ_STATS);
 968         err = typhoon_issue_command(tp, 1, &xp_cmd, 7, xp_resp);
 969         if(err < 0)
 970                 return err;
 971
 972         /* 3Com's Linux driver uses txMultipleCollisions as it's
 973          * collisions value, but there is some other collision info as well...
 974          *
 975          * The extra status reported would be a good candidate for
 976          * ethtool_ops->get_{strings,stats}()
 977          */
 978         stats->tx_packets = le32_to_cpu(s->txPackets);
 979         stats->tx_bytes = le64_to_cpu(s->txBytes);
 980         stats->tx_errors = le32_to_cpu(s->txCarrierLost);
 981         stats->tx_carrier_errors = le32_to_cpu(s->txCarrierLost);
 982         stats->collisions = le32_to_cpu(s->txMultipleCollisions);
 983         stats->rx_packets = le32_to_cpu(s->rxPacketsGood);
 984         stats->rx_bytes = le64_to_cpu(s->rxBytesGood);
 985         stats->rx_fifo_errors = le32_to_cpu(s->rxFifoOverruns);
 986         stats->rx_errors = le32_to_cpu(s->rxFifoOverruns) +
 987                         le32_to_cpu(s->BadSSD) + le32_to_cpu(s->rxCrcErrors);
 988         stats->rx_crc_errors = le32_to_cpu(s->rxCrcErrors);
 989         stats->rx_length_errors = le32_to_cpu(s->rxOversized);
 990         tp->speed = (s->linkStatus & TYPHOON_LINK_100MBPS) ?
 991                         SPEED_100 : SPEED_10;
 992         tp->duplex = (s->linkStatus & TYPHOON_LINK_FULL_DUPLEX) ?
 993                         DUPLEX_FULL : DUPLEX_HALF;
 994
 995         /* add in the saved statistics
 996          */
 997         stats->tx_packets += saved->tx_packets;
 998         stats->tx_bytes += saved->tx_bytes;
 999         stats->tx_errors += saved->tx_errors;
1000         stats->collisions += saved->collisions;
1001         stats->rx_packets += saved->rx_packets;
1002         stats->rx_bytes += saved->rx_bytes;
1003         stats->rx_fifo_errors += saved->rx_fifo_errors;
1004         stats->rx_errors += saved->rx_errors;
1005         stats->rx_crc_errors += saved->rx_crc_errors;
1006         stats->rx_length_errors += saved->rx_length_errors;
1007
1008         return 0;
1009 }
1010
1011 static struct net_device_stats *
1012 typhoon_get_stats(struct net_device *dev)
1013 {
1014         struct typhoon *tp = netdev_priv(dev);
1015         struct net_device_stats *stats = &tp->stats;
1016         struct net_device_stats *saved = &tp->stats_saved;
1017
1018         smp_rmb();
1019         if(tp->card_state == Sleeping)
1020                 return saved;
1021
1022         if(typhoon_do_get_stats(tp) < 0) {
1023                 printk(KERN_ERR "%s: error getting stats\n", dev->name);
1024                 return saved;
1025         }
1026
1027         return stats;
1028 }
1029
1030 static int
1031 typhoon_set_mac_address(struct net_device *dev, void *addr)
1032 {
1033         struct sockaddr *saddr = (struct sockaddr *) addr;
1034
1035         if(netif_running(dev))
1036                 return -EBUSY;
1037
1038         memcpy(dev->dev_addr, saddr->sa_data, dev->addr_len);
1039         return 0;
1040 }
1041
1042 static void
1043 typhoon_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1044 {
1045         struct typhoon *tp = netdev_priv(dev);
1046         struct pci_dev *pci_dev = tp->pdev;
1047         struct cmd_desc xp_cmd;
1048         struct resp_desc xp_resp[3];
1049
1050         smp_rmb();
1051         if(tp->card_state == Sleeping) {
1052                 strcpy(info->fw_version, "Sleep image");
1053         } else {
1054                 INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_READ_VERSIONS);
1055                 if(typhoon_issue_command(tp, 1, &xp_cmd, 3, xp_resp) < 0) {
1056                         strcpy(info->fw_version, "Unknown runtime");
1057                 } else {
1058                         u32 sleep_ver = le32_to_cpu(xp_resp[0].parm2);
1059                         snprintf(info->fw_version, 32, "%02x.%03x.%03x",
1060                                  sleep_ver >> 24, (sleep_ver >> 12) & 0xfff,
1061                                  sleep_ver & 0xfff);
1062                 }
1063         }
1064
1065         strcpy(info->driver, DRV_MODULE_NAME);
1066         strcpy(info->version, DRV_MODULE_VERSION);
1067         strcpy(info->bus_info, pci_name(pci_dev));
1068 }
1069
1070 static int
1071 typhoon_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1072 {
1073         struct typhoon *tp = netdev_priv(dev);
1074
1075         cmd->supported = SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
1076                                 SUPPORTED_Autoneg;
1077
1078         switch (tp->xcvr_select) {
1079         case TYPHOON_XCVR_10HALF:
1080                 cmd->advertising = ADVERTISED_10baseT_Half;
1081                 break;
1082         case TYPHOON_XCVR_10FULL:
1083                 cmd->advertising = ADVERTISED_10baseT_Full;
1084                 break;
1085         case TYPHOON_XCVR_100HALF:
1086                 cmd->advertising = ADVERTISED_100baseT_Half;
1087                 break;
1088         case TYPHOON_XCVR_100FULL:
1089                 cmd->advertising = ADVERTISED_100baseT_Full;
1090                 break;
1091         case TYPHOON_XCVR_AUTONEG:
1092                 cmd->advertising = ADVERTISED_10baseT_Half |
1093                                             ADVERTISED_10baseT_Full |
1094                                             ADVERTISED_100baseT_Half |
1095                                             ADVERTISED_100baseT_Full |
1096                                             ADVERTISED_Autoneg;
1097                 break;
1098         }
1099
1100         if(tp->capabilities & TYPHOON_FIBER) {
1101                 cmd->supported |= SUPPORTED_FIBRE;
1102                 cmd->advertising |= ADVERTISED_FIBRE;
1103                 cmd->port = PORT_FIBRE;
1104         } else {
1105                 cmd->supported |= SUPPORTED_10baseT_Half |
1106                                         SUPPORTED_10baseT_Full |
1107                                         SUPPORTED_TP;
1108                 cmd->advertising |= ADVERTISED_TP;
1109                 cmd->port = PORT_TP;
1110         }
1111
1112         /* need to get stats to make these link speed/duplex valid */
1113         typhoon_do_get_stats(tp);
1114         cmd->speed = tp->speed;
1115         cmd->duplex = tp->duplex;
1116         cmd->phy_address = 0;
1117         cmd->transceiver = XCVR_INTERNAL;
1118         if(tp->xcvr_select == TYPHOON_XCVR_AUTONEG)
1119                 cmd->autoneg = AUTONEG_ENABLE;
1120         else
1121                 cmd->autoneg = AUTONEG_DISABLE;
1122         cmd->maxtxpkt = 1;
1123         cmd->maxrxpkt = 1;
1124
1125         return 0;
1126 }
1127
1128 static int
1129 typhoon_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1130 {
1131         struct typhoon *tp = netdev_priv(dev);
1132         struct cmd_desc xp_cmd;
1133         __le16 xcvr;
1134         int err;
1135
1136         err = -EINVAL;
1137         if(cmd->autoneg == AUTONEG_ENABLE) {
1138                 xcvr = TYPHOON_XCVR_AUTONEG;
1139         } else {
1140                 if(cmd->duplex == DUPLEX_HALF) {
1141                         if(cmd->speed == SPEED_10)
1142                                 xcvr = TYPHOON_XCVR_10HALF;
1143                         else if(cmd->speed == SPEED_100)
1144                                 xcvr = TYPHOON_XCVR_100HALF;
1145                         else
1146                                 goto out;
1147                 } else if(cmd->duplex == DUPLEX_FULL) {
1148                         if(cmd->speed == SPEED_10)
1149                                 xcvr = TYPHOON_XCVR_10FULL;
1150                         else if(cmd->speed == SPEED_100)
1151                                 xcvr = TYPHOON_XCVR_100FULL;
1152                         else
1153                                 goto out;
1154                 } else
1155                         goto out;
1156         }
1157
1158         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_XCVR_SELECT);
1159         xp_cmd.parm1 = xcvr;
1160         err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1161         if(err < 0)
1162                 goto out;
1163
1164         tp->xcvr_select = xcvr;
1165         if(cmd->autoneg == AUTONEG_ENABLE) {
1166                 tp->speed = 0xff;       /* invalid */
1167                 tp->duplex = 0xff;      /* invalid */
1168         } else {
1169                 tp->speed = cmd->speed;
1170                 tp->duplex = cmd->duplex;
1171         }
1172
1173 out:
1174         return err;
1175 }
1176
1177 static void
1178 typhoon_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1179 {
1180         struct typhoon *tp = netdev_priv(dev);
1181
1182         wol->supported = WAKE_PHY | WAKE_MAGIC;
1183         wol->wolopts = 0;
1184         if(tp->wol_events & TYPHOON_WAKE_LINK_EVENT)
1185                 wol->wolopts |= WAKE_PHY;
1186         if(tp->wol_events & TYPHOON_WAKE_MAGIC_PKT)
1187                 wol->wolopts |= WAKE_MAGIC;
1188         memset(&wol->sopass, 0, sizeof(wol->sopass));
1189 }
1190
1191 static int
1192 typhoon_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1193 {
1194         struct typhoon *tp = netdev_priv(dev);
1195
1196         if(wol->wolopts & ~(WAKE_PHY | WAKE_MAGIC))
1197                 return -EINVAL;
1198
1199         tp->wol_events = 0;
1200         if(wol->wolopts & WAKE_PHY)
1201                 tp->wol_events |= TYPHOON_WAKE_LINK_EVENT;
1202         if(wol->wolopts & WAKE_MAGIC)
1203                 tp->wol_events |= TYPHOON_WAKE_MAGIC_PKT;
1204
1205         return 0;
1206 }
1207
1208 static u32
1209 typhoon_get_rx_csum(struct net_device *dev)
1210 {
1211         /* For now, we don't allow turning off RX checksums.
1212          */
1213         return 1;
1214 }
1215
1216 static void
1217 typhoon_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
1218 {
1219         ering->rx_max_pending = RXENT_ENTRIES;
1220         ering->rx_mini_max_pending = 0;
1221         ering->rx_jumbo_max_pending = 0;
1222         ering->tx_max_pending = TXLO_ENTRIES - 1;
1223
1224         ering->rx_pending = RXENT_ENTRIES;
1225         ering->rx_mini_pending = 0;
1226         ering->rx_jumbo_pending = 0;
1227         ering->tx_pending = TXLO_ENTRIES - 1;
1228 }
1229
1230 static const struct ethtool_ops typhoon_ethtool_ops = {
1231         .get_settings           = typhoon_get_settings,
1232         .set_settings           = typhoon_set_settings,
1233         .get_drvinfo            = typhoon_get_drvinfo,
1234         .get_wol                = typhoon_get_wol,
1235         .set_wol                = typhoon_set_wol,
1236         .get_link               = ethtool_op_get_link,
1237         .get_rx_csum            = typhoon_get_rx_csum,
1238         .set_tx_csum            = ethtool_op_set_tx_csum,
1239         .set_sg                 = ethtool_op_set_sg,
1240         .set_tso                = ethtool_op_set_tso,
1241         .get_ringparam          = typhoon_get_ringparam,
1242 };
1243
1244 static int
1245 typhoon_wait_interrupt(void __iomem *ioaddr)
1246 {
1247         int i, err = 0;
1248
1249         for(i = 0; i < TYPHOON_WAIT_TIMEOUT; i++) {
1250                 if(ioread32(ioaddr + TYPHOON_REG_INTR_STATUS) &
1251                    TYPHOON_INTR_BOOTCMD)
1252                         goto out;
1253                 udelay(TYPHOON_UDELAY);
1254         }
1255
1256         err = -ETIMEDOUT;
1257
1258 out:
1259         iowrite32(TYPHOON_INTR_BOOTCMD, ioaddr + TYPHOON_REG_INTR_STATUS);
1260         return err;
1261 }
1262
1263 #define shared_offset(x)        offsetof(struct typhoon_shared, x)
1264
1265 static void
1266 typhoon_init_interface(struct typhoon *tp)
1267 {
1268         struct typhoon_interface *iface = &tp->shared->iface;
1269         dma_addr_t shared_dma;
1270
1271         memset(tp->shared, 0, sizeof(struct typhoon_shared));
1272
1273         /* The *Hi members of iface are all init'd to zero by the memset().
1274          */
1275         shared_dma = tp->shared_dma + shared_offset(indexes);
1276         iface->ringIndex = cpu_to_le32(shared_dma);
1277
1278         shared_dma = tp->shared_dma + shared_offset(txLo);
1279         iface->txLoAddr = cpu_to_le32(shared_dma);
1280         iface->txLoSize = cpu_to_le32(TXLO_ENTRIES * sizeof(struct tx_desc));
1281
1282         shared_dma = tp->shared_dma + shared_offset(txHi);
1283         iface->txHiAddr = cpu_to_le32(shared_dma);
1284         iface->txHiSize = cpu_to_le32(TXHI_ENTRIES * sizeof(struct tx_desc));
1285
1286         shared_dma = tp->shared_dma + shared_offset(rxBuff);
1287         iface->rxBuffAddr = cpu_to_le32(shared_dma);
1288         iface->rxBuffSize = cpu_to_le32(RXFREE_ENTRIES *
1289                                         sizeof(struct rx_free));
1290
1291         shared_dma = tp->shared_dma + shared_offset(rxLo);
1292         iface->rxLoAddr = cpu_to_le32(shared_dma);
1293         iface->rxLoSize = cpu_to_le32(RX_ENTRIES * sizeof(struct rx_desc));
1294
1295         shared_dma = tp->shared_dma + shared_offset(rxHi);
1296         iface->rxHiAddr = cpu_to_le32(shared_dma);
1297         iface->rxHiSize = cpu_to_le32(RX_ENTRIES * sizeof(struct rx_desc));
1298
1299         shared_dma = tp->shared_dma + shared_offset(cmd);
1300         iface->cmdAddr = cpu_to_le32(shared_dma);
1301         iface->cmdSize = cpu_to_le32(COMMAND_RING_SIZE);
1302
1303         shared_dma = tp->shared_dma + shared_offset(resp);
1304         iface->respAddr = cpu_to_le32(shared_dma);
1305         iface->respSize = cpu_to_le32(RESPONSE_RING_SIZE);
1306
1307         shared_dma = tp->shared_dma + shared_offset(zeroWord);
1308         iface->zeroAddr = cpu_to_le32(shared_dma);
1309
1310         tp->indexes = &tp->shared->indexes;
1311         tp->txLoRing.ringBase = (u8 *) tp->shared->txLo;
1312         tp->txHiRing.ringBase = (u8 *) tp->shared->txHi;
1313         tp->rxLoRing.ringBase = (u8 *) tp->shared->rxLo;
1314         tp->rxHiRing.ringBase = (u8 *) tp->shared->rxHi;
1315         tp->rxBuffRing.ringBase = (u8 *) tp->shared->rxBuff;
1316         tp->cmdRing.ringBase = (u8 *) tp->shared->cmd;
1317         tp->respRing.ringBase = (u8 *) tp->shared->resp;
1318
1319         tp->txLoRing.writeRegister = TYPHOON_REG_TX_LO_READY;
1320         tp->txHiRing.writeRegister = TYPHOON_REG_TX_HI_READY;
1321
1322         tp->txlo_dma_addr = le32_to_cpu(iface->txLoAddr);
1323         tp->card_state = Sleeping;
1324         smp_wmb();
1325
1326         tp->offload = TYPHOON_OFFLOAD_IP_CHKSUM | TYPHOON_OFFLOAD_TCP_CHKSUM;
1327         tp->offload |= TYPHOON_OFFLOAD_UDP_CHKSUM | TSO_OFFLOAD_ON;
1328
1329         spin_lock_init(&tp->command_lock);
1330         spin_lock_init(&tp->state_lock);
1331 }
1332
1333 static void
1334 typhoon_init_rings(struct typhoon *tp)
1335 {
1336         memset(tp->indexes, 0, sizeof(struct typhoon_indexes));
1337
1338         tp->txLoRing.lastWrite = 0;
1339         tp->txHiRing.lastWrite = 0;
1340         tp->rxLoRing.lastWrite = 0;
1341         tp->rxHiRing.lastWrite = 0;
1342         tp->rxBuffRing.lastWrite = 0;
1343         tp->cmdRing.lastWrite = 0;
1344         tp->cmdRing.lastWrite = 0;
1345
1346         tp->txLoRing.lastRead = 0;
1347         tp->txHiRing.lastRead = 0;
1348 }
1349
1350 static int
1351 typhoon_download_firmware(struct typhoon *tp)
1352 {
1353         void __iomem *ioaddr = tp->ioaddr;
1354         struct pci_dev *pdev = tp->pdev;
1355         struct typhoon_file_header *fHdr;
1356         struct typhoon_section_header *sHdr;
1357         u8 *image_data;
1358         void *dpage;
1359         dma_addr_t dpage_dma;
1360         __sum16 csum;
1361         u32 irqEnabled;
1362         u32 irqMasked;
1363         u32 numSections;
1364         u32 section_len;
1365         u32 len;
1366         u32 load_addr;
1367         u32 hmac;
1368         int i;
1369         int err;
1370
1371         err = -EINVAL;
1372         fHdr = (struct typhoon_file_header *) typhoon_firmware_image;
1373         image_data = (u8 *) fHdr;
1374
1375         if(memcmp(fHdr->tag, "TYPHOON", 8)) {
1376                 printk(KERN_ERR "%s: Invalid firmware image!\n", tp->name);
1377                 goto err_out;
1378         }
1379
1380         /* Cannot just map the firmware image using pci_map_single() as
1381          * the firmware is part of the kernel/module image, so we allocate
1382          * some consistent memory to copy the sections into, as it is simpler,
1383          * and short-lived. If we ever split out and require a userland
1384          * firmware loader, then we can revisit this.
1385          */
1386         err = -ENOMEM;
1387         dpage = pci_alloc_consistent(pdev, PAGE_SIZE, &dpage_dma);
1388         if(!dpage) {
1389                 printk(KERN_ERR "%s: no DMA mem for firmware\n", tp->name);
1390                 goto err_out;
1391         }
1392
1393         irqEnabled = ioread32(ioaddr + TYPHOON_REG_INTR_ENABLE);
1394         iowrite32(irqEnabled | TYPHOON_INTR_BOOTCMD,
1395                ioaddr + TYPHOON_REG_INTR_ENABLE);
1396         irqMasked = ioread32(ioaddr + TYPHOON_REG_INTR_MASK);
1397         iowrite32(irqMasked | TYPHOON_INTR_BOOTCMD,
1398                ioaddr + TYPHOON_REG_INTR_MASK);
1399
1400         err = -ETIMEDOUT;
1401         if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_WAITING_FOR_HOST) < 0) {
1402                 printk(KERN_ERR "%s: card ready timeout\n", tp->name);
1403                 goto err_out_irq;
1404         }
1405
1406         numSections = le32_to_cpu(fHdr->numSections);
1407         load_addr = le32_to_cpu(fHdr->startAddr);
1408
1409         iowrite32(TYPHOON_INTR_BOOTCMD, ioaddr + TYPHOON_REG_INTR_STATUS);
1410         iowrite32(load_addr, ioaddr + TYPHOON_REG_DOWNLOAD_BOOT_ADDR);
1411         hmac = le32_to_cpu(fHdr->hmacDigest[0]);
1412         iowrite32(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_0);
1413         hmac = le32_to_cpu(fHdr->hmacDigest[1]);
1414         iowrite32(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_1);
1415         hmac = le32_to_cpu(fHdr->hmacDigest[2]);
1416         iowrite32(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_2);
1417         hmac = le32_to_cpu(fHdr->hmacDigest[3]);
1418         iowrite32(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_3);
1419         hmac = le32_to_cpu(fHdr->hmacDigest[4]);
1420         iowrite32(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_4);
1421         typhoon_post_pci_writes(ioaddr);
1422         iowrite32(TYPHOON_BOOTCMD_RUNTIME_IMAGE, ioaddr + TYPHOON_REG_COMMAND);
1423
1424         image_data += sizeof(struct typhoon_file_header);
1425
1426         /* The ioread32() in typhoon_wait_interrupt() will force the
1427          * last write to the command register to post, so
1428          * we don't need a typhoon_post_pci_writes() after it.
1429          */
1430         for(i = 0; i < numSections; i++) {
1431                 sHdr = (struct typhoon_section_header *) image_data;
1432                 image_data += sizeof(struct typhoon_section_header);
1433                 load_addr = le32_to_cpu(sHdr->startAddr);
1434                 section_len = le32_to_cpu(sHdr->len);
1435
1436                 while(section_len) {
1437                         len = min_t(u32, section_len, PAGE_SIZE);
1438
1439                         if(typhoon_wait_interrupt(ioaddr) < 0 ||
1440                            ioread32(ioaddr + TYPHOON_REG_STATUS) !=
1441                            TYPHOON_STATUS_WAITING_FOR_SEGMENT) {
1442                                 printk(KERN_ERR "%s: segment ready timeout\n",
1443                                        tp->name);
1444                                 goto err_out_irq;
1445                         }
1446
1447                         /* Do an pseudo IPv4 checksum on the data -- first
1448                          * need to convert each u16 to cpu order before
1449                          * summing. Fortunately, due to the properties of
1450                          * the checksum, we can do this once, at the end.
1451                          */
1452                         csum = csum_fold(csum_partial_copy_nocheck(image_data,
1453                                                                   dpage, len,
1454                                                                   0));
1455
1456                         iowrite32(len, ioaddr + TYPHOON_REG_BOOT_LENGTH);
1457                         iowrite32(le16_to_cpu((__force __le16)csum),
1458                                         ioaddr + TYPHOON_REG_BOOT_CHECKSUM);
1459                         iowrite32(load_addr,
1460                                         ioaddr + TYPHOON_REG_BOOT_DEST_ADDR);
1461                         iowrite32(0, ioaddr + TYPHOON_REG_BOOT_DATA_HI);
1462                         iowrite32(dpage_dma, ioaddr + TYPHOON_REG_BOOT_DATA_LO);
1463                         typhoon_post_pci_writes(ioaddr);
1464                         iowrite32(TYPHOON_BOOTCMD_SEG_AVAILABLE,
1465                                ioaddr + TYPHOON_REG_COMMAND);
1466
1467                         image_data += len;
1468                         load_addr += len;
1469                         section_len -= len;
1470                 }
1471         }
1472
1473         if(typhoon_wait_interrupt(ioaddr) < 0 ||
1474            ioread32(ioaddr + TYPHOON_REG_STATUS) !=
1475            TYPHOON_STATUS_WAITING_FOR_SEGMENT) {
1476                 printk(KERN_ERR "%s: final segment ready timeout\n", tp->name);
1477                 goto err_out_irq;
1478         }
1479
1480         iowrite32(TYPHOON_BOOTCMD_DNLD_COMPLETE, ioaddr + TYPHOON_REG_COMMAND);
1481
1482         if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_WAITING_FOR_BOOT) < 0) {
1483                 printk(KERN_ERR "%s: boot ready timeout, status 0x%0x\n",
1484                        tp->name, ioread32(ioaddr + TYPHOON_REG_STATUS));
1485                 goto err_out_irq;
1486         }
1487
1488         err = 0;
1489
1490 err_out_irq:
1491         iowrite32(irqMasked, ioaddr + TYPHOON_REG_INTR_MASK);
1492         iowrite32(irqEnabled, ioaddr + TYPHOON_REG_INTR_ENABLE);
1493
1494         pci_free_consistent(pdev, PAGE_SIZE, dpage, dpage_dma);
1495
1496 err_out:
1497         return err;
1498 }
1499
1500 static int
1501 typhoon_boot_3XP(struct typhoon *tp, u32 initial_status)
1502 {
1503         void __iomem *ioaddr = tp->ioaddr;
1504
1505         if(typhoon_wait_status(ioaddr, initial_status) < 0) {
1506                 printk(KERN_ERR "%s: boot ready timeout\n", tp->name);
1507                 goto out_timeout;
1508         }
1509
1510         iowrite32(0, ioaddr + TYPHOON_REG_BOOT_RECORD_ADDR_HI);
1511         iowrite32(tp->shared_dma, ioaddr + TYPHOON_REG_BOOT_RECORD_ADDR_LO);
1512         typhoon_post_pci_writes(ioaddr);
1513         iowrite32(TYPHOON_BOOTCMD_REG_BOOT_RECORD,
1514                                 ioaddr + TYPHOON_REG_COMMAND);
1515
1516         if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_RUNNING) < 0) {
1517                 printk(KERN_ERR "%s: boot finish timeout (status 0x%x)\n",
1518                        tp->name, ioread32(ioaddr + TYPHOON_REG_STATUS));
1519                 goto out_timeout;
1520         }
1521
1522         /* Clear the Transmit and Command ready registers
1523          */
1524         iowrite32(0, ioaddr + TYPHOON_REG_TX_HI_READY);
1525         iowrite32(0, ioaddr + TYPHOON_REG_CMD_READY);
1526         iowrite32(0, ioaddr + TYPHOON_REG_TX_LO_READY);
1527         typhoon_post_pci_writes(ioaddr);
1528         iowrite32(TYPHOON_BOOTCMD_BOOT, ioaddr + TYPHOON_REG_COMMAND);
1529
1530         return 0;
1531
1532 out_timeout:
1533         return -ETIMEDOUT;
1534 }
1535
1536 static u32
1537 typhoon_clean_tx(struct typhoon *tp, struct transmit_ring *txRing,
1538                         volatile __le32 * index)
1539 {
1540         u32 lastRead = txRing->lastRead;
1541         struct tx_desc *tx;
1542         dma_addr_t skb_dma;
1543         int dma_len;
1544         int type;
1545
1546         while(lastRead != le32_to_cpu(*index)) {
1547                 tx = (struct tx_desc *) (txRing->ringBase + lastRead);
1548                 type = tx->flags & TYPHOON_TYPE_MASK;
1549
1550                 if(type == TYPHOON_TX_DESC) {
1551                         /* This tx_desc describes a packet.
1552                          */
1553                         unsigned long ptr = tx->tx_addr;
1554                         struct sk_buff *skb = (struct sk_buff *) ptr;
1555                         dev_kfree_skb_irq(skb);
1556                 } else if(type == TYPHOON_FRAG_DESC) {
1557                         /* This tx_desc describes a memory mapping. Free it.
1558                          */
1559                         skb_dma = (dma_addr_t) le32_to_cpu(tx->frag.addr);
1560                         dma_len = le16_to_cpu(tx->len);
1561                         pci_unmap_single(tp->pdev, skb_dma, dma_len,
1562                                        PCI_DMA_TODEVICE);
1563                 }
1564
1565                 tx->flags = 0;
1566                 typhoon_inc_tx_index(&lastRead, 1);
1567         }
1568
1569         return lastRead;
1570 }
1571
1572 static void
1573 typhoon_tx_complete(struct typhoon *tp, struct transmit_ring *txRing,
1574                         volatile __le32 * index)
1575 {
1576         u32 lastRead;
1577         int numDesc = MAX_SKB_FRAGS + 1;
1578
1579         /* This will need changing if we start to use the Hi Tx ring. */
1580         lastRead = typhoon_clean_tx(tp, txRing, index);
1581         if(netif_queue_stopped(tp->dev) && typhoon_num_free(txRing->lastWrite,
1582                                 lastRead, TXLO_ENTRIES) > (numDesc + 2))
1583                 netif_wake_queue(tp->dev);
1584
1585         txRing->lastRead = lastRead;
1586         smp_wmb();
1587 }
1588
1589 static void
1590 typhoon_recycle_rx_skb(struct typhoon *tp, u32 idx)
1591 {
1592         struct typhoon_indexes *indexes = tp->indexes;
1593         struct rxbuff_ent *rxb = &tp->rxbuffers[idx];
1594         struct basic_ring *ring = &tp->rxBuffRing;
1595         struct rx_free *r;
1596
1597         if((ring->lastWrite + sizeof(*r)) % (RXFREE_ENTRIES * sizeof(*r)) ==
1598                                 le32_to_cpu(indexes->rxBuffCleared)) {
1599                 /* no room in ring, just drop the skb
1600                  */
1601                 dev_kfree_skb_any(rxb->skb);
1602                 rxb->skb = NULL;
1603                 return;
1604         }
1605
1606         r = (struct rx_free *) (ring->ringBase + ring->lastWrite);
1607         typhoon_inc_rxfree_index(&ring->lastWrite, 1);
1608         r->virtAddr = idx;
1609         r->physAddr = cpu_to_le32(rxb->dma_addr);
1610
1611         /* Tell the card about it */
1612         wmb();
1613         indexes->rxBuffReady = cpu_to_le32(ring->lastWrite);
1614 }
1615
1616 static int
1617 typhoon_alloc_rx_skb(struct typhoon *tp, u32 idx)
1618 {
1619         struct typhoon_indexes *indexes = tp->indexes;
1620         struct rxbuff_ent *rxb = &tp->rxbuffers[idx];
1621         struct basic_ring *ring = &tp->rxBuffRing;
1622         struct rx_free *r;
1623         struct sk_buff *skb;
1624         dma_addr_t dma_addr;
1625
1626         rxb->skb = NULL;
1627
1628         if((ring->lastWrite + sizeof(*r)) % (RXFREE_ENTRIES * sizeof(*r)) ==
1629                                 le32_to_cpu(indexes->rxBuffCleared))
1630                 return -ENOMEM;
1631
1632         skb = dev_alloc_skb(PKT_BUF_SZ);
1633         if(!skb)
1634                 return -ENOMEM;
1635
1636 #if 0
1637         /* Please, 3com, fix the firmware to allow DMA to a unaligned
1638          * address! Pretty please?
1639          */
1640         skb_reserve(skb, 2);
1641 #endif
1642
1643         skb->dev = tp->dev;
1644         dma_addr = pci_map_single(tp->pdev, skb->data,
1645                                   PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
1646
1647         /* Since no card does 64 bit DAC, the high bits will never
1648          * change from zero.
1649          */
1650         r = (struct rx_free *) (ring->ringBase + ring->lastWrite);
1651         typhoon_inc_rxfree_index(&ring->lastWrite, 1);
1652         r->virtAddr = idx;
1653         r->physAddr = cpu_to_le32(dma_addr);
1654         rxb->skb = skb;
1655         rxb->dma_addr = dma_addr;
1656
1657         /* Tell the card about it */
1658         wmb();
1659         indexes->rxBuffReady = cpu_to_le32(ring->lastWrite);
1660         return 0;
1661 }
1662
1663 static int
1664 typhoon_rx(struct typhoon *tp, struct basic_ring *rxRing, volatile __le32 * ready,
1665            volatile __le32 * cleared, int budget)
1666 {
1667         struct rx_desc *rx;
1668         struct sk_buff *skb, *new_skb;
1669         struct rxbuff_ent *rxb;
1670         dma_addr_t dma_addr;
1671         u32 local_ready;
1672         u32 rxaddr;
1673         int pkt_len;
1674         u32 idx;
1675         __le32 csum_bits;
1676         int received;
1677
1678         received = 0;
1679         local_ready = le32_to_cpu(*ready);
1680         rxaddr = le32_to_cpu(*cleared);
1681         while(rxaddr != local_ready && budget > 0) {
1682                 rx = (struct rx_desc *) (rxRing->ringBase + rxaddr);
1683                 idx = rx->addr;
1684                 rxb = &tp->rxbuffers[idx];
1685                 skb = rxb->skb;
1686                 dma_addr = rxb->dma_addr;
1687
1688                 typhoon_inc_rx_index(&rxaddr, 1);
1689
1690                 if(rx->flags & TYPHOON_RX_ERROR) {
1691                         typhoon_recycle_rx_skb(tp, idx);
1692                         continue;
1693                 }
1694
1695                 pkt_len = le16_to_cpu(rx->frameLen);
1696
1697                 if(pkt_len < rx_copybreak &&
1698                    (new_skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
1699                         skb_reserve(new_skb, 2);
1700                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr,
1701                                                     PKT_BUF_SZ,
1702                                                     PCI_DMA_FROMDEVICE);
1703                         skb_copy_to_linear_data(new_skb, skb->data, pkt_len);
1704                         pci_dma_sync_single_for_device(tp->pdev, dma_addr,
1705                                                        PKT_BUF_SZ,
1706                                                        PCI_DMA_FROMDEVICE);
1707                         skb_put(new_skb, pkt_len);
1708                         typhoon_recycle_rx_skb(tp, idx);
1709                 } else {
1710                         new_skb = skb;
1711                         skb_put(new_skb, pkt_len);
1712                         pci_unmap_single(tp->pdev, dma_addr, PKT_BUF_SZ,
1713                                        PCI_DMA_FROMDEVICE);
1714                         typhoon_alloc_rx_skb(tp, idx);
1715                 }
1716                 new_skb->protocol = eth_type_trans(new_skb, tp->dev);
1717                 csum_bits = rx->rxStatus & (TYPHOON_RX_IP_CHK_GOOD |
1718                         TYPHOON_RX_UDP_CHK_GOOD | TYPHOON_RX_TCP_CHK_GOOD);
1719                 if(csum_bits ==
1720                    (TYPHOON_RX_IP_CHK_GOOD | TYPHOON_RX_TCP_CHK_GOOD)
1721                    || csum_bits ==
1722                    (TYPHOON_RX_IP_CHK_GOOD | TYPHOON_RX_UDP_CHK_GOOD)) {
1723                         new_skb->ip_summed = CHECKSUM_UNNECESSARY;
1724                 } else
1725                         new_skb->ip_summed = CHECKSUM_NONE;
1726
1727                 spin_lock(&tp->state_lock);
1728                 if(tp->vlgrp != NULL && rx->rxStatus & TYPHOON_RX_VLAN)
1729                         vlan_hwaccel_receive_skb(new_skb, tp->vlgrp,
1730                                                  ntohl(rx->vlanTag) & 0xffff);
1731                 else
1732                         netif_receive_skb(new_skb);
1733                 spin_unlock(&tp->state_lock);
1734
1735                 tp->dev->last_rx = jiffies;
1736                 received++;
1737                 budget--;
1738         }
1739         *cleared = cpu_to_le32(rxaddr);
1740
1741         return received;
1742 }
1743
1744 static void
1745 typhoon_fill_free_ring(struct typhoon *tp)
1746 {
1747         u32 i;
1748
1749         for(i = 0; i < RXENT_ENTRIES; i++) {
1750                 struct rxbuff_ent *rxb = &tp->rxbuffers[i];
1751                 if(rxb->skb)
1752                         continue;
1753                 if(typhoon_alloc_rx_skb(tp, i) < 0)
1754                         break;
1755         }
1756 }
1757
1758 static int
1759 typhoon_poll(struct napi_struct *napi, int budget)
1760 {
1761         struct typhoon *tp = container_of(napi, struct typhoon, napi);
1762         struct net_device *dev = tp->dev;
1763         struct typhoon_indexes *indexes = tp->indexes;
1764         int work_done;
1765
1766         rmb();
1767         if(!tp->awaiting_resp && indexes->respReady != indexes->respCleared)
1768                         typhoon_process_response(tp, 0, NULL);
1769
1770         if(le32_to_cpu(indexes->txLoCleared) != tp->txLoRing.lastRead)
1771                 typhoon_tx_complete(tp, &tp->txLoRing, &indexes->txLoCleared);
1772
1773         work_done = 0;
1774
1775         if(indexes->rxHiCleared != indexes->rxHiReady) {
1776                 work_done += typhoon_rx(tp, &tp->rxHiRing, &indexes->rxHiReady,
1777                                         &indexes->rxHiCleared, budget);
1778         }
1779
1780         if(indexes->rxLoCleared != indexes->rxLoReady) {
1781                 work_done += typhoon_rx(tp, &tp->rxLoRing, &indexes->rxLoReady,
1782                                         &indexes->rxLoCleared, budget - work_done);
1783         }
1784
1785         if(le32_to_cpu(indexes->rxBuffCleared) == tp->rxBuffRing.lastWrite) {
1786                 /* rxBuff ring is empty, try to fill it. */
1787                 typhoon_fill_free_ring(tp);
1788         }
1789
1790         if (work_done < budget) {
1791                 netif_rx_complete(dev, napi);
1792                 iowrite32(TYPHOON_INTR_NONE,
1793                                 tp->ioaddr + TYPHOON_REG_INTR_MASK);
1794                 typhoon_post_pci_writes(tp->ioaddr);
1795         }
1796
1797         return work_done;
1798 }
1799
1800 static irqreturn_t
1801 typhoon_interrupt(int irq, void *dev_instance)
1802 {
1803         struct net_device *dev = dev_instance;
1804         struct typhoon *tp = dev->priv;
1805         void __iomem *ioaddr = tp->ioaddr;
1806         u32 intr_status;
1807
1808         intr_status = ioread32(ioaddr + TYPHOON_REG_INTR_STATUS);
1809         if(!(intr_status & TYPHOON_INTR_HOST_INT))
1810                 return IRQ_NONE;
1811
1812         iowrite32(intr_status, ioaddr + TYPHOON_REG_INTR_STATUS);
1813
1814         if (netif_rx_schedule_prep(dev, &tp->napi)) {
1815                 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
1816                 typhoon_post_pci_writes(ioaddr);
1817                 __netif_rx_schedule(dev, &tp->napi);
1818         } else {
1819                 printk(KERN_ERR "%s: Error, poll already scheduled\n",
1820                        dev->name);
1821         }
1822         return IRQ_HANDLED;
1823 }
1824
1825 static void
1826 typhoon_free_rx_rings(struct typhoon *tp)
1827 {
1828         u32 i;
1829
1830         for(i = 0; i < RXENT_ENTRIES; i++) {
1831                 struct rxbuff_ent *rxb = &tp->rxbuffers[i];
1832                 if(rxb->skb) {
1833                         pci_unmap_single(tp->pdev, rxb->dma_addr, PKT_BUF_SZ,
1834                                        PCI_DMA_FROMDEVICE);
1835                         dev_kfree_skb(rxb->skb);
1836                         rxb->skb = NULL;
1837                 }
1838         }
1839 }
1840
1841 static int
1842 typhoon_sleep(struct typhoon *tp, pci_power_t state, __le16 events)
1843 {
1844         struct pci_dev *pdev = tp->pdev;
1845         void __iomem *ioaddr = tp->ioaddr;
1846         struct cmd_desc xp_cmd;
1847         int err;
1848
1849         INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_ENABLE_WAKE_EVENTS);
1850         xp_cmd.parm1 = events;
1851         err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1852         if(err < 0) {
1853                 printk(KERN_ERR "%s: typhoon_sleep(): wake events cmd err %d\n",
1854                                 tp->name, err);
1855                 return err;
1856         }
1857
1858         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_GOTO_SLEEP);
1859         err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1860         if(err < 0) {
1861                 printk(KERN_ERR "%s: typhoon_sleep(): sleep cmd err %d\n",
1862                                 tp->name, err);
1863                 return err;
1864         }
1865
1866         if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_SLEEPING) < 0)
1867                 return -ETIMEDOUT;
1868
1869         /* Since we cannot monitor the status of the link while sleeping,
1870          * tell the world it went away.
1871          */
1872         netif_carrier_off(tp->dev);
1873
1874         pci_enable_wake(tp->pdev, state, 1);
1875         pci_disable_device(pdev);
1876         return pci_set_power_state(pdev, state);
1877 }
1878
1879 static int
1880 typhoon_wakeup(struct typhoon *tp, int wait_type)
1881 {
1882         struct pci_dev *pdev = tp->pdev;
1883         void __iomem *ioaddr = tp->ioaddr;
1884
1885         pci_set_power_state(pdev, PCI_D0);
1886         pci_restore_state(pdev);
1887
1888         /* Post 2.x.x versions of the Sleep Image require a reset before
1889          * we can download the Runtime Image. But let's not make users of
1890          * the old firmware pay for the reset.
1891          */
1892         iowrite32(TYPHOON_BOOTCMD_WAKEUP, ioaddr + TYPHOON_REG_COMMAND);
1893         if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_WAITING_FOR_HOST) < 0 ||
1894                         (tp->capabilities & TYPHOON_WAKEUP_NEEDS_RESET))
1895                 return typhoon_reset(ioaddr, wait_type);
1896
1897         return 0;
1898 }
1899
1900 static int
1901 typhoon_start_runtime(struct typhoon *tp)
1902 {
1903         struct net_device *dev = tp->dev;
1904         void __iomem *ioaddr = tp->ioaddr;
1905         struct cmd_desc xp_cmd;
1906         int err;
1907
1908         typhoon_init_rings(tp);
1909         typhoon_fill_free_ring(tp);
1910
1911         err = typhoon_download_firmware(tp);
1912         if(err < 0) {
1913                 printk("%s: cannot load runtime on 3XP\n", tp->name);
1914                 goto error_out;
1915         }
1916
1917         if(typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_BOOT) < 0) {
1918                 printk("%s: cannot boot 3XP\n", tp->name);
1919                 err = -EIO;
1920                 goto error_out;
1921         }
1922
1923         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_MAX_PKT_SIZE);
1924         xp_cmd.parm1 = cpu_to_le16(PKT_BUF_SZ);
1925         err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1926         if(err < 0)
1927                 goto error_out;
1928
1929         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_MAC_ADDRESS);
1930         xp_cmd.parm1 = cpu_to_le16(ntohs(*(__be16 *)&dev->dev_addr[0]));
1931         xp_cmd.parm2 = cpu_to_le32(ntohl(*(__be32 *)&dev->dev_addr[2]));
1932         err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1933         if(err < 0)
1934                 goto error_out;
1935
1936         /* Disable IRQ coalescing -- we can reenable it when 3Com gives
1937          * us some more information on how to control it.
1938          */
1939         INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_IRQ_COALESCE_CTRL);
1940         xp_cmd.parm1 = 0;
1941         err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1942         if(err < 0)
1943                 goto error_out;
1944
1945         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_XCVR_SELECT);
1946         xp_cmd.parm1 = tp->xcvr_select;
1947         err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1948         if(err < 0)
1949                 goto error_out;
1950
1951         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_VLAN_TYPE_WRITE);
1952         xp_cmd.parm1 = __constant_cpu_to_le16(ETH_P_8021Q);
1953         err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1954         if(err < 0)
1955                 goto error_out;
1956
1957         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_OFFLOAD_TASKS);
1958         spin_lock_bh(&tp->state_lock);
1959         xp_cmd.parm2 = tp->offload;
1960         xp_cmd.parm3 = tp->offload;
1961         err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1962         spin_unlock_bh(&tp->state_lock);
1963         if(err < 0)
1964                 goto error_out;
1965
1966         typhoon_set_rx_mode(dev);
1967
1968         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_TX_ENABLE);
1969         err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1970         if(err < 0)
1971                 goto error_out;
1972
1973         INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_RX_ENABLE);
1974         err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1975         if(err < 0)
1976                 goto error_out;
1977
1978         tp->card_state = Running;
1979         smp_wmb();
1980
1981         iowrite32(TYPHOON_INTR_ENABLE_ALL, ioaddr + TYPHOON_REG_INTR_ENABLE);
1982         iowrite32(TYPHOON_INTR_NONE, ioaddr + TYPHOON_REG_INTR_MASK);
1983         typhoon_post_pci_writes(ioaddr);
1984
1985         return 0;
1986
1987 error_out:
1988         typhoon_reset(ioaddr, WaitNoSleep);
1989         typhoon_free_rx_rings(tp);
1990         typhoon_init_rings(tp);
1991         return err;
1992 }
1993
1994 static int
1995 typhoon_stop_runtime(struct typhoon *tp, int wait_type)
1996 {
1997         struct typhoon_indexes *indexes = tp->indexes;
1998         struct transmit_ring *txLo = &tp->txLoRing;
1999         void __iomem *ioaddr = tp->ioaddr;
2000         struct cmd_desc xp_cmd;
2001         int i;
2002
2003         /* Disable interrupts early, since we can't schedule a poll
2004          * when called with !netif_running(). This will be posted
2005          * when we force the posting of the command.
2006          */
2007         iowrite32(TYPHOON_INTR_NONE, ioaddr + TYPHOON_REG_INTR_ENABLE);
2008
2009         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_RX_DISABLE);
2010         typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
2011
2012         /* Wait 1/2 sec for any outstanding transmits to occur
2013          * We'll cleanup after the reset if this times out.
2014          */
2015         for(i = 0; i < TYPHOON_WAIT_TIMEOUT; i++) {
2016                 if(indexes->txLoCleared == cpu_to_le32(txLo->lastWrite))
2017                         break;
2018                 udelay(TYPHOON_UDELAY);
2019         }
2020
2021         if(i == TYPHOON_WAIT_TIMEOUT)
2022                 printk(KERN_ERR
2023                        "%s: halt timed out waiting for Tx to complete\n",
2024                        tp->name);
2025
2026         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_TX_DISABLE);
2027         typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
2028
2029         /* save the statistics so when we bring the interface up again,
2030          * the values reported to userspace are correct.
2031          */
2032         tp->card_state = Sleeping;
2033         smp_wmb();
2034         typhoon_do_get_stats(tp);
2035         memcpy(&tp->stats_saved, &tp->stats, sizeof(struct net_device_stats));
2036
2037         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_HALT);
2038         typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
2039
2040         if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_HALTED) < 0)
2041                 printk(KERN_ERR "%s: timed out waiting for 3XP to halt\n",
2042                        tp->name);
2043
2044         if(typhoon_reset(ioaddr, wait_type) < 0) {
2045                 printk(KERN_ERR "%s: unable to reset 3XP\n", tp->name);
2046                 return -ETIMEDOUT;
2047         }
2048
2049         /* cleanup any outstanding Tx packets */
2050         if(indexes->txLoCleared != cpu_to_le32(txLo->lastWrite)) {
2051                 indexes->txLoCleared = cpu_to_le32(txLo->lastWrite);
2052                 typhoon_clean_tx(tp, &tp->txLoRing, &indexes->txLoCleared);
2053         }
2054
2055         return 0;
2056 }
2057
2058 static void
2059 typhoon_tx_timeout(struct net_device *dev)
2060 {
2061         struct typhoon *tp = netdev_priv(dev);
2062
2063         if(typhoon_reset(tp->ioaddr, WaitNoSleep) < 0) {
2064                 printk(KERN_WARNING "%s: could not reset in tx timeout\n",
2065                                         dev->name);
2066                 goto truely_dead;
2067         }
2068
2069         /* If we ever start using the Hi ring, it will need cleaning too */
2070         typhoon_clean_tx(tp, &tp->txLoRing, &tp->indexes->txLoCleared);
2071         typhoon_free_rx_rings(tp);
2072
2073         if(typhoon_start_runtime(tp) < 0) {
2074                 printk(KERN_ERR "%s: could not start runtime in tx timeout\n",
2075                                         dev->name);
2076                 goto truely_dead;
2077         }
2078
2079         netif_wake_queue(dev);
2080         return;
2081
2082 truely_dead:
2083         /* Reset the hardware, and turn off carrier to avoid more timeouts */
2084         typhoon_reset(tp->ioaddr, NoWait);
2085         netif_carrier_off(dev);
2086 }
2087
2088 static int
2089 typhoon_open(struct net_device *dev)
2090 {
2091         struct typhoon *tp = netdev_priv(dev);
2092         int err;
2093
2094         err = typhoon_wakeup(tp, WaitSleep);
2095         if(err < 0) {
2096                 printk(KERN_ERR "%s: unable to wakeup device\n", dev->name);
2097                 goto out_sleep;
2098         }
2099
2100         err = request_irq(dev->irq, &typhoon_interrupt, IRQF_SHARED,
2101                                 dev->name, dev);
2102         if(err < 0)
2103                 goto out_sleep;
2104
2105         napi_enable(&tp->napi);
2106
2107         err = typhoon_start_runtime(tp);
2108         if(err < 0) {
2109                 napi_disable(&tp->napi);
2110                 goto out_irq;
2111         }
2112
2113         netif_start_queue(dev);
2114         return 0;
2115
2116 out_irq:
2117         free_irq(dev->irq, dev);
2118
2119 out_sleep:
2120         if(typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_HOST) < 0) {
2121                 printk(KERN_ERR "%s: unable to reboot into sleep img\n",
2122                                 dev->name);
2123                 typhoon_reset(tp->ioaddr, NoWait);
2124                 goto out;
2125         }
2126
2127         if(typhoon_sleep(tp, PCI_D3hot, 0) < 0)
2128                 printk(KERN_ERR "%s: unable to go back to sleep\n", dev->name);
2129
2130 out:
2131         return err;
2132 }
2133
2134 static int
2135 typhoon_close(struct net_device *dev)
2136 {
2137         struct typhoon *tp = netdev_priv(dev);
2138
2139         netif_stop_queue(dev);
2140         napi_disable(&tp->napi);
2141
2142         if(typhoon_stop_runtime(tp, WaitSleep) < 0)
2143                 printk(KERN_ERR "%s: unable to stop runtime\n", dev->name);
2144
2145         /* Make sure there is no irq handler running on a different CPU. */
2146         typhoon_synchronize_irq(dev->irq);
2147         free_irq(dev->irq, dev);
2148
2149         typhoon_free_rx_rings(tp);
2150         typhoon_init_rings(tp);
2151
2152         if(typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_HOST) < 0)
2153                 printk(KERN_ERR "%s: unable to boot sleep image\n", dev->name);
2154
2155         if(typhoon_sleep(tp, PCI_D3hot, 0) < 0)
2156                 printk(KERN_ERR "%s: unable to put card to sleep\n", dev->name);
2157
2158         return 0;
2159 }
2160
2161 #ifdef CONFIG_PM
2162 static int
2163 typhoon_resume(struct pci_dev *pdev)
2164 {
2165         struct net_device *dev = pci_get_drvdata(pdev);
2166         struct typhoon *tp = netdev_priv(dev);
2167
2168         /* If we're down, resume when we are upped.
2169          */
2170         if(!netif_running(dev))
2171                 return 0;
2172
2173         if(typhoon_wakeup(tp, WaitNoSleep) < 0) {
2174                 printk(KERN_ERR "%s: critical: could not wake up in resume\n",
2175                                 dev->name);
2176                 goto reset;
2177         }
2178
2179         if(typhoon_start_runtime(tp) < 0) {
2180                 printk(KERN_ERR "%s: critical: could not start runtime in "
2181                                 "resume\n", dev->name);
2182                 goto reset;
2183         }
2184
2185         netif_device_attach(dev);
2186         netif_start_queue(dev);
2187         return 0;
2188
2189 reset:
2190         typhoon_reset(tp->ioaddr, NoWait);
2191         return -EBUSY;
2192 }
2193
2194 static int
2195 typhoon_suspend(struct pci_dev *pdev, pm_message_t state)
2196 {
2197         struct net_device *dev = pci_get_drvdata(pdev);
2198         struct typhoon *tp = netdev_priv(dev);
2199         struct cmd_desc xp_cmd;
2200
2201         /* If we're down, we're already suspended.
2202          */
2203         if(!netif_running(dev))
2204                 return 0;
2205
2206         spin_lock_bh(&tp->state_lock);
2207         if(tp->vlgrp && tp->wol_events & TYPHOON_WAKE_MAGIC_PKT) {
2208                 spin_unlock_bh(&tp->state_lock);
2209                 printk(KERN_ERR "%s: cannot do WAKE_MAGIC with VLANS\n",
2210                                 dev->name);
2211                 return -EBUSY;
2212         }
2213         spin_unlock_bh(&tp->state_lock);
2214
2215         netif_device_detach(dev);
2216
2217         if(typhoon_stop_runtime(tp, WaitNoSleep) < 0) {
2218                 printk(KERN_ERR "%s: unable to stop runtime\n", dev->name);
2219                 goto need_resume;
2220         }
2221
2222         typhoon_free_rx_rings(tp);
2223         typhoon_init_rings(tp);
2224
2225         if(typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_HOST) < 0) {
2226                 printk(KERN_ERR "%s: unable to boot sleep image\n", dev->name);
2227                 goto need_resume;
2228         }
2229
2230         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_MAC_ADDRESS);
2231         xp_cmd.parm1 = cpu_to_le16(ntohs(*(__be16 *)&dev->dev_addr[0]));
2232         xp_cmd.parm2 = cpu_to_le32(ntohl(*(__be32 *)&dev->dev_addr[2]));
2233         if(typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL) < 0) {
2234                 printk(KERN_ERR "%s: unable to set mac address in suspend\n",
2235                                 dev->name);
2236                 goto need_resume;
2237         }
2238
2239         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_RX_FILTER);
2240         xp_cmd.parm1 = TYPHOON_RX_FILTER_DIRECTED | TYPHOON_RX_FILTER_BROADCAST;
2241         if(typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL) < 0) {
2242                 printk(KERN_ERR "%s: unable to set rx filter in suspend\n",
2243                                 dev->name);
2244                 goto need_resume;
2245         }
2246
2247         if(typhoon_sleep(tp, pci_choose_state(pdev, state), tp->wol_events) < 0) {
2248                 printk(KERN_ERR "%s: unable to put card to sleep\n", dev->name);
2249                 goto need_resume;
2250         }
2251
2252         return 0;
2253
2254 need_resume:
2255         typhoon_resume(pdev);
2256         return -EBUSY;
2257 }
2258 #endif
2259
2260 static int __devinit
2261 typhoon_test_mmio(struct pci_dev *pdev)
2262 {
2263         void __iomem *ioaddr = pci_iomap(pdev, 1, 128);
2264         int mode = 0;
2265         u32 val;
2266
2267         if(!ioaddr)
2268                 goto out;
2269
2270         if(ioread32(ioaddr + TYPHOON_REG_STATUS) !=
2271                                 TYPHOON_STATUS_WAITING_FOR_HOST)
2272                 goto out_unmap;
2273
2274         iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
2275         iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_STATUS);
2276         iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_ENABLE);
2277
2278         /* Ok, see if we can change our interrupt status register by
2279          * sending ourselves an interrupt. If so, then MMIO works.
2280          * The 50usec delay is arbitrary -- it could probably be smaller.
2281          */
2282         val = ioread32(ioaddr + TYPHOON_REG_INTR_STATUS);
2283         if((val & TYPHOON_INTR_SELF) == 0) {
2284                 iowrite32(1, ioaddr + TYPHOON_REG_SELF_INTERRUPT);
2285                 ioread32(ioaddr + TYPHOON_REG_INTR_STATUS);
2286                 udelay(50);
2287                 val = ioread32(ioaddr + TYPHOON_REG_INTR_STATUS);
2288                 if(val & TYPHOON_INTR_SELF)
2289                         mode = 1;
2290         }
2291
2292         iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
2293         iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_STATUS);
2294         iowrite32(TYPHOON_INTR_NONE, ioaddr + TYPHOON_REG_INTR_ENABLE);
2295         ioread32(ioaddr + TYPHOON_REG_INTR_STATUS);
2296
2297 out_unmap:
2298         pci_iounmap(pdev, ioaddr);
2299
2300 out:
2301         if(!mode)
2302                 printk(KERN_INFO PFX "falling back to port IO\n");
2303         return mode;
2304 }
2305
2306 static int __devinit
2307 typhoon_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2308 {
2309         static int did_version = 0;
2310         struct net_device *dev;
2311         struct typhoon *tp;
2312         int card_id = (int) ent->driver_data;
2313         void __iomem *ioaddr;
2314         void *shared;
2315         dma_addr_t shared_dma;
2316         struct cmd_desc xp_cmd;
2317         struct resp_desc xp_resp[3];
2318         int err = 0;
2319         DECLARE_MAC_BUF(mac);
2320
2321         if(!did_version++)
2322                 printk(KERN_INFO "%s", version);
2323
2324         dev = alloc_etherdev(sizeof(*tp));
2325         if(dev == NULL) {
2326                 printk(ERR_PFX "%s: unable to alloc new net device\n",
2327                        pci_name(pdev));
2328                 err = -ENOMEM;
2329                 goto error_out;
2330         }
2331         SET_NETDEV_DEV(dev, &pdev->dev);
2332
2333         err = pci_enable_device(pdev);
2334         if(err < 0) {
2335                 printk(ERR_PFX "%s: unable to enable device\n",
2336                        pci_name(pdev));
2337                 goto error_out_dev;
2338         }
2339
2340         err = pci_set_mwi(pdev);
2341         if(err < 0) {
2342                 printk(ERR_PFX "%s: unable to set MWI\n", pci_name(pdev));
2343                 goto error_out_disable;
2344         }
2345
2346         err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2347         if(err < 0) {
2348                 printk(ERR_PFX "%s: No usable DMA configuration\n",
2349                        pci_name(pdev));
2350                 goto error_out_mwi;
2351         }
2352
2353         /* sanity checks on IO and MMIO BARs
2354          */
2355         if(!(pci_resource_flags(pdev, 0) & IORESOURCE_IO)) {
2356                 printk(ERR_PFX
2357                        "%s: region #1 not a PCI IO resource, aborting\n",
2358                        pci_name(pdev));
2359                 err = -ENODEV;
2360                 goto error_out_mwi;
2361         }
2362         if(pci_resource_len(pdev, 0) < 128) {
2363                 printk(ERR_PFX "%s: Invalid PCI IO region size, aborting\n",
2364                        pci_name(pdev));
2365                 err = -ENODEV;
2366                 goto error_out_mwi;
2367         }
2368         if(!(pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) {
2369                 printk(ERR_PFX
2370                        "%s: region #1 not a PCI MMIO resource, aborting\n",
2371                        pci_name(pdev));
2372                 err = -ENODEV;
2373                 goto error_out_mwi;
2374         }
2375         if(pci_resource_len(pdev, 1) < 128) {
2376                 printk(ERR_PFX "%s: Invalid PCI MMIO region size, aborting\n",
2377                        pci_name(pdev));
2378                 err = -ENODEV;
2379                 goto error_out_mwi;
2380         }
2381
2382         err = pci_request_regions(pdev, "typhoon");
2383         if(err < 0) {
2384                 printk(ERR_PFX "%s: could not request regions\n",
2385                        pci_name(pdev));
2386                 goto error_out_mwi;
2387         }
2388
2389         /* map our registers
2390          */
2391         if(use_mmio != 0 && use_mmio != 1)
2392                 use_mmio = typhoon_test_mmio(pdev);
2393
2394         ioaddr = pci_iomap(pdev, use_mmio, 128);
2395         if (!ioaddr) {
2396                 printk(ERR_PFX "%s: cannot remap registers, aborting\n",
2397                        pci_name(pdev));
2398                 err = -EIO;
2399                 goto error_out_regions;
2400         }
2401
2402         /* allocate pci dma space for rx and tx descriptor rings
2403          */
2404         shared = pci_alloc_consistent(pdev, sizeof(struct typhoon_shared),
2405                                       &shared_dma);
2406         if(!shared) {
2407                 printk(ERR_PFX "%s: could not allocate DMA memory\n",
2408                        pci_name(pdev));
2409                 err = -ENOMEM;
2410                 goto error_out_remap;
2411         }
2412
2413         dev->irq = pdev->irq;
2414         tp = netdev_priv(dev);
2415         tp->shared = (struct typhoon_shared *) shared;
2416         tp->shared_dma = shared_dma;
2417         tp->pdev = pdev;
2418         tp->tx_pdev = pdev;
2419         tp->ioaddr = ioaddr;
2420         tp->tx_ioaddr = ioaddr;
2421         tp->dev = dev;
2422
2423         /* Init sequence:
2424          * 1) Reset the adapter to clear any bad juju
2425          * 2) Reload the sleep image
2426          * 3) Boot the sleep image
2427          * 4) Get the hardware address.
2428          * 5) Put the card to sleep.
2429          */
2430         if (typhoon_reset(ioaddr, WaitSleep) < 0) {
2431                 printk(ERR_PFX "%s: could not reset 3XP\n", pci_name(pdev));
2432                 err = -EIO;
2433                 goto error_out_dma;
2434         }
2435
2436         /* Now that we've reset the 3XP and are sure it's not going to
2437          * write all over memory, enable bus mastering, and save our
2438          * state for resuming after a suspend.
2439          */
2440         pci_set_master(pdev);
2441         pci_save_state(pdev);
2442
2443         /* dev->name is not valid until we register, but we need to
2444          * use some common routines to initialize the card. So that those
2445          * routines print the right name, we keep our oun pointer to the name
2446          */
2447         tp->name = pci_name(pdev);
2448
2449         typhoon_init_interface(tp);
2450         typhoon_init_rings(tp);
2451
2452         if(typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_HOST) < 0) {
2453                 printk(ERR_PFX "%s: cannot boot 3XP sleep image\n",
2454                        pci_name(pdev));
2455                 err = -EIO;
2456                 goto error_out_reset;
2457         }
2458
2459         INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_READ_MAC_ADDRESS);
2460         if(typhoon_issue_command(tp, 1, &xp_cmd, 1, xp_resp) < 0) {
2461                 printk(ERR_PFX "%s: cannot read MAC address\n",
2462                        pci_name(pdev));
2463                 err = -EIO;
2464                 goto error_out_reset;
2465         }
2466
2467         *(__be16 *)&dev->dev_addr[0] = htons(le16_to_cpu(xp_resp[0].parm1));
2468         *(__be32 *)&dev->dev_addr[2] = htonl(le32_to_cpu(xp_resp[0].parm2));
2469
2470         if(!is_valid_ether_addr(dev->dev_addr)) {
2471                 printk(ERR_PFX "%s: Could not obtain valid ethernet address, "
2472                        "aborting\n", pci_name(pdev));
2473                 goto error_out_reset;
2474         }
2475
2476         /* Read the Sleep Image version last, so the response is valid
2477          * later when we print out the version reported.
2478          */
2479         INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_READ_VERSIONS);
2480         if(typhoon_issue_command(tp, 1, &xp_cmd, 3, xp_resp) < 0) {
2481                 printk(ERR_PFX "%s: Could not get Sleep Image version\n",
2482                         pci_name(pdev));
2483                 goto error_out_reset;
2484         }
2485
2486         tp->capabilities = typhoon_card_info[card_id].capabilities;
2487         tp->xcvr_select = TYPHOON_XCVR_AUTONEG;
2488
2489         /* Typhoon 1.0 Sleep Images return one response descriptor to the
2490          * READ_VERSIONS command. Those versions are OK after waking up
2491          * from sleep without needing a reset. Typhoon 1.1+ Sleep Images
2492          * seem to need a little extra help to get started. Since we don't
2493          * know how to nudge it along, just kick it.
2494          */
2495         if(xp_resp[0].numDesc != 0)
2496                 tp->capabilities |= TYPHOON_WAKEUP_NEEDS_RESET;
2497
2498         if(typhoon_sleep(tp, PCI_D3hot, 0) < 0) {
2499                 printk(ERR_PFX "%s: cannot put adapter to sleep\n",
2500                        pci_name(pdev));
2501                 err = -EIO;
2502                 goto error_out_reset;
2503         }
2504
2505         /* The chip-specific entries in the device structure. */
2506         dev->open               = typhoon_open;
2507         dev->hard_start_xmit    = typhoon_start_tx;
2508         dev->stop               = typhoon_close;
2509         dev->set_multicast_list = typhoon_set_rx_mode;
2510         dev->tx_timeout         = typhoon_tx_timeout;
2511         netif_napi_add(dev, &tp->napi, typhoon_poll, 16);
2512         dev->watchdog_timeo     = TX_TIMEOUT;
2513         dev->get_stats          = typhoon_get_stats;
2514         dev->set_mac_address    = typhoon_set_mac_address;
2515         dev->vlan_rx_register   = typhoon_vlan_rx_register;
2516
2517         SET_ETHTOOL_OPS(dev, &typhoon_ethtool_ops);
2518
2519         /* We can handle scatter gather, up to 16 entries, and
2520          * we can do IP checksumming (only version 4, doh...)
2521          */
2522         dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
2523         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
2524         dev->features |= NETIF_F_TSO;
2525
2526         if(register_netdev(dev) < 0)
2527                 goto error_out_reset;
2528
2529         /* fixup our local name */
2530         tp->name = dev->name;
2531
2532         pci_set_drvdata(pdev, dev);
2533
2534         printk(KERN_INFO "%s: %s at %s 0x%llx, %s\n",
2535                dev->name, typhoon_card_info[card_id].name,
2536                use_mmio ? "MMIO" : "IO",
2537                (unsigned long long)pci_resource_start(pdev, use_mmio),
2538                print_mac(mac, dev->dev_addr));
2539
2540         /* xp_resp still contains the response to the READ_VERSIONS command.
2541          * For debugging, let the user know what version he has.
2542          */
2543         if(xp_resp[0].numDesc == 0) {
2544                 /* This is the Typhoon 1.0 type Sleep Image, last 16 bits
2545                  * of version is Month/Day of build.
2546                  */
2547                 u16 monthday = le32_to_cpu(xp_resp[0].parm2) & 0xffff;
2548                 printk(KERN_INFO "%s: Typhoon 1.0 Sleep Image built "
2549                         "%02u/%02u/2000\n", dev->name, monthday >> 8,
2550                         monthday & 0xff);
2551         } else if(xp_resp[0].numDesc == 2) {
2552                 /* This is the Typhoon 1.1+ type Sleep Image
2553                  */
2554                 u32 sleep_ver = le32_to_cpu(xp_resp[0].parm2);
2555                 u8 *ver_string = (u8 *) &xp_resp[1];
2556                 ver_string[25] = 0;
2557                 printk(KERN_INFO "%s: Typhoon 1.1+ Sleep Image version "
2558                         "%02x.%03x.%03x %s\n", dev->name, sleep_ver >> 24,
2559                         (sleep_ver >> 12) & 0xfff, sleep_ver & 0xfff,
2560                         ver_string);
2561         } else {
2562                 printk(KERN_WARNING "%s: Unknown Sleep Image version "
2563                         "(%u:%04x)\n", dev->name, xp_resp[0].numDesc,
2564                         le32_to_cpu(xp_resp[0].parm2));
2565         }
2566
2567         return 0;
2568
2569 error_out_reset:
2570         typhoon_reset(ioaddr, NoWait);
2571
2572 error_out_dma:
2573         pci_free_consistent(pdev, sizeof(struct typhoon_shared),
2574                             shared, shared_dma);
2575 error_out_remap:
2576         pci_iounmap(pdev, ioaddr);
2577 error_out_regions:
2578         pci_release_regions(pdev);
2579 error_out_mwi:
2580         pci_clear_mwi(pdev);
2581 error_out_disable:
2582         pci_disable_device(pdev);
2583 error_out_dev:
2584         free_netdev(dev);
2585 error_out:
2586         return err;
2587 }
2588
2589 static void __devexit
2590 typhoon_remove_one(struct pci_dev *pdev)
2591 {
2592         struct net_device *dev = pci_get_drvdata(pdev);
2593         struct typhoon *tp = netdev_priv(dev);
2594
2595         unregister_netdev(dev);
2596         pci_set_power_state(pdev, PCI_D0);
2597         pci_restore_state(pdev);
2598         typhoon_reset(tp->ioaddr, NoWait);
2599         pci_iounmap(pdev, tp->ioaddr);
2600         pci_free_consistent(pdev, sizeof(struct typhoon_shared),
2601                             tp->shared, tp->shared_dma);
2602         pci_release_regions(pdev);
2603         pci_clear_mwi(pdev);
2604         pci_disable_device(pdev);
2605         pci_set_drvdata(pdev, NULL);
2606         free_netdev(dev);
2607 }
2608
2609 static struct pci_driver typhoon_driver = {
2610         .name           = DRV_MODULE_NAME,
2611         .id_table       = typhoon_pci_tbl,
2612         .probe          = typhoon_init_one,
2613         .remove         = __devexit_p(typhoon_remove_one),
2614 #ifdef CONFIG_PM
2615         .suspend        = typhoon_suspend,
2616         .resume         = typhoon_resume,
2617 #endif
2618 };
2619
2620 static int __init
2621 typhoon_init(void)
2622 {
2623         return pci_register_driver(&typhoon_driver);
2624 }
2625
2626 static void __exit
2627 typhoon_cleanup(void)
2628 {
2629         pci_unregister_driver(&typhoon_driver);
2630 }
2631
2632 module_init(typhoon_init);
2633 module_exit(typhoon_cleanup);