2 * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
14 #ifndef __ASM_ARCH_MXC_BOARD_MX27ADS_H__
15 #define __ASM_ARCH_MXC_BOARD_MX27ADS_H__
17 /* external interrupt multiplexer */
18 #define MXC_EXP_IO_BASE (MXC_BOARD_IRQ_START)
20 #define MXC_VIRTUAL_INTS_BASE (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES)
21 #define MXC_SDIO1_CARD_IRQ MXC_VIRTUAL_INTS_BASE
22 #define MXC_SDIO2_CARD_IRQ (MXC_VIRTUAL_INTS_BASE + 1)
23 #define MXC_SDIO3_CARD_IRQ (MXC_VIRTUAL_INTS_BASE + 2)
25 #define MXC_MAX_BOARD_INTS (MXC_MAX_EXP_IO_LINES + \
29 * MXC UART EVB board level configurations
31 #define MXC_LL_UART_PADDR UART1_BASE_ADDR
32 #define MXC_LL_UART_VADDR AIPI_IO_ADDRESS(UART1_BASE_ADDR)
35 * @name Memory Size parameters
39 * Size of SDRAM memory
41 #define SDRAM_MEM_SIZE SZ_128M
44 * PBC Controller parameters
48 * Base address of PBC controller, CS4
50 #define PBC_BASE_ADDRESS 0xEB000000
51 #define PBC_REG_ADDR(offset) (PBC_BASE_ADDRESS + (offset))
54 * PBC Interupt name definitions
63 #define PBC_INTR_MAX_NUM 6
64 #define PBC_INTR_SHARED_MAX_NUM 8
66 /* When the PBC address connection is fixed in h/w, defined as 1 */
69 /* Offsets for the PBC Controller register */
71 * PBC Board version register offset
73 #define PBC_VERSION_REG PBC_REG_ADDR(0x00000 >> PBC_ADDR_SH)
75 * PBC Board control register 1 set address.
77 #define PBC_BCTRL1_SET_REG PBC_REG_ADDR(0x00008 >> PBC_ADDR_SH)
79 * PBC Board control register 1 clear address.
81 #define PBC_BCTRL1_CLEAR_REG PBC_REG_ADDR(0x0000C >> PBC_ADDR_SH)
83 * PBC Board control register 2 set address.
85 #define PBC_BCTRL2_SET_REG PBC_REG_ADDR(0x00010 >> PBC_ADDR_SH)
87 * PBC Board control register 2 clear address.
89 #define PBC_BCTRL2_CLEAR_REG PBC_REG_ADDR(0x00014 >> PBC_ADDR_SH)
91 * PBC Board control register 3 set address.
93 #define PBC_BCTRL3_SET_REG PBC_REG_ADDR(0x00018 >> PBC_ADDR_SH)
95 * PBC Board control register 3 clear address.
97 #define PBC_BCTRL3_CLEAR_REG PBC_REG_ADDR(0x0001C >> PBC_ADDR_SH)
99 * PBC Board control register 3 set address.
101 #define PBC_BCTRL4_SET_REG PBC_REG_ADDR(0x00020 >> PBC_ADDR_SH)
103 * PBC Board control register 4 clear address.
105 #define PBC_BCTRL4_CLEAR_REG PBC_REG_ADDR(0x00024 >> PBC_ADDR_SH)
107 * PBC Board status register 1.
109 #define PBC_BSTAT1_REG PBC_REG_ADDR(0x00028 >> PBC_ADDR_SH)
111 * PBC Board interrupt status register.
113 #define PBC_INTSTATUS_REG PBC_REG_ADDR(0x0002C >> PBC_ADDR_SH)
115 * PBC Board interrupt current status register.
117 #define PBC_INTCURR_STATUS_REG PBC_REG_ADDR(0x00034 >> PBC_ADDR_SH)
119 * PBC Interrupt mask register set address.
121 #define PBC_INTMASK_SET_REG PBC_REG_ADDR(0x00038 >> PBC_ADDR_SH)
123 * PBC Interrupt mask register clear address.
125 #define PBC_INTMASK_CLEAR_REG PBC_REG_ADDR(0x0003C >> PBC_ADDR_SH)
129 #define PBC_SC16C652_UARTA_REG PBC_REG_ADDR(0x20000 >> PBC_ADDR_SH)
131 * UART 4 Expanding Signal Status.
133 #define PBC_UART_STATUS_REG PBC_REG_ADDR(0x22000 >> PBC_ADDR_SH)
135 * UART 4 Expanding Signal Control Set.
137 #define PBC_UCTRL_SET_REG PBC_REG_ADDR(0x24000 >> PBC_ADDR_SH)
139 * UART 4 Expanding Signal Control Clear.
141 #define PBC_UCTRL_CLR_REG PBC_REG_ADDR(0x26000 >> PBC_ADDR_SH)
143 * Ethernet Controller IO base address.
145 #define PBC_CS8900A_IOBASE_REG PBC_REG_ADDR(0x40000 >> PBC_ADDR_SH)
147 * Ethernet Controller Memory base address.
149 #define PBC_CS8900A_MEMBASE_REG PBC_REG_ADDR(0x42000 >> PBC_ADDR_SH)
151 * Ethernet Controller DMA base address.
153 #define PBC_CS8900A_DMABASE_REG PBC_REG_ADDR(0x44000 >> PBC_ADDR_SH)
155 /* PBC Board Version Register bit definition */
156 #define PBC_VERSION_ADS 0x8000 /* Bit15=1 means version for ads */
157 #define PBC_VERSION_EVB_REVB 0x4000 /* BIT14=1 means version for evb revb */
159 /* PBC Board Control Register 1 bit definitions */
160 #define PBC_BCTRL1_ERST 0x0001 /* Ethernet Reset */
161 #define PBC_BCTRL1_URST 0x0002 /* Reset External UART controller */
162 #define PBC_BCTRL1_FRST 0x0004 /* FEC Reset */
163 #define PBC_BCTRL1_ESLEEP 0x0010 /* Enable ethernet Sleep */
164 #define PBC_BCTRL1_LCDON 0x0800 /* Enable the LCD */
166 /* PBC Board Control Register 2 bit definitions */
167 #define PBC_BCTRL2_VCC_EN 0x0004 /* Enable VCC */
168 #define PBC_BCTRL2_VPP_EN 0x0008 /* Enable Vpp */
169 #define PBC_BCTRL2_ATAFEC_EN 0X0010
170 #define PBC_BCTRL2_ATAFEC_SEL 0X0020
171 #define PBC_BCTRL2_ATA_EN 0X0040
172 #define PBC_BCTRL2_IRDA_SD 0X0080
173 #define PBC_BCTRL2_IRDA_EN 0X0100
174 #define PBC_BCTRL2_CCTL10 0X0200
175 #define PBC_BCTRL2_CCTL11 0X0400
177 /* PBC Board Control Register 3 bit definitions */
178 #define PBC_BCTRL3_HSH_EN 0X0020
179 #define PBC_BCTRL3_FSH_MOD 0X0040
180 #define PBC_BCTRL3_OTG_HS_EN 0X0080
181 #define PBC_BCTRL3_OTG_VBUS_EN 0X0100
182 #define PBC_BCTRL3_FSH_VBUS_EN 0X0200
183 #define PBC_BCTRL3_USB_OTG_ON 0X0800
184 #define PBC_BCTRL3_USB_FSH_ON 0X1000
186 /* PBC Board Control Register 4 bit definitions */
187 #define PBC_BCTRL4_REGEN_SEL 0X0001
188 #define PBC_BCTRL4_USER_OFF 0X0002
189 #define PBC_BCTRL4_VIB_EN 0X0004
190 #define PBC_BCTRL4_PWRGT1_EN 0X0008
191 #define PBC_BCTRL4_PWRGT2_EN 0X0010
192 #define PBC_BCTRL4_STDBY_PRI 0X0020
196 * Enumerations for SD cards and memory stick card. This corresponds to
197 * the card EN bits in the IMR: SD1_EN | MS_EN | SD3_EN | SD2_EN.
204 MXC_CARD_MIN = MXC_CARD_SD2,
205 MXC_CARD_MAX = MXC_CARD_SD1,
209 #define MXC_CPLD_VER_1_50 0x01
212 * PBC BSTAT Register bit definitions
214 #define PBC_BSTAT_PRI_INT 0X0001
215 #define PBC_BSTAT_USB_BYP 0X0002
216 #define PBC_BSTAT_ATA_IOCS16 0X0004
217 #define PBC_BSTAT_ATA_CBLID 0X0008
218 #define PBC_BSTAT_ATA_DASP 0X0010
219 #define PBC_BSTAT_PWR_RDY 0X0020
220 #define PBC_BSTAT_SD3_WP 0X0100
221 #define PBC_BSTAT_SD2_WP 0X0200
222 #define PBC_BSTAT_SD1_WP 0X0400
223 #define PBC_BSTAT_SD3_DET 0X0800
224 #define PBC_BSTAT_SD2_DET 0X1000
225 #define PBC_BSTAT_SD1_DET 0X2000
226 #define PBC_BSTAT_MS_DET 0X4000
227 #define PBC_BSTAT_SD3_DET_BIT 11
228 #define PBC_BSTAT_SD2_DET_BIT 12
229 #define PBC_BSTAT_SD1_DET_BIT 13
230 #define PBC_BSTAT_MS_DET_BIT 14
231 #define MXC_BSTAT_BIT(n) ((n == MXC_CARD_SD2) ? PBC_BSTAT_SD2_DET : \
232 ((n == MXC_CARD_SD3) ? PBC_BSTAT_SD3_DET : \
233 ((n == MXC_CARD_SD1) ? PBC_BSTAT_SD1_DET : \
234 ((n == MXC_CARD_MS) ? PBC_BSTAT_MS_DET : \
238 * PBC UART Control Register bit definitions
240 #define PBC_UCTRL_DCE_DCD 0X0001
241 #define PBC_UCTRL_DCE_DSR 0X0002
242 #define PBC_UCTRL_DCE_RI 0X0004
243 #define PBC_UCTRL_DTE_DTR 0X0100
246 * PBC UART Status Register bit definitions
248 #define PBC_USTAT_DTE_DCD 0X0001
249 #define PBC_USTAT_DTE_DSR 0X0002
250 #define PBC_USTAT_DTE_RI 0X0004
251 #define PBC_USTAT_DCE_DTR 0X0100
254 * PBC Interupt mask register bit definitions
256 #define PBC_INTR_SD3_R_EN_BIT 4
257 #define PBC_INTR_SD2_R_EN_BIT 0
258 #define PBC_INTR_SD1_R_EN_BIT 6
259 #define PBC_INTR_MS_R_EN_BIT 5
260 #define PBC_INTR_SD3_EN_BIT 13
261 #define PBC_INTR_SD2_EN_BIT 12
262 #define PBC_INTR_MS_EN_BIT 14
263 #define PBC_INTR_SD1_EN_BIT 15
265 #define PBC_INTR_SD2_R_EN 0x0001
266 #define PBC_INTR_LOW_BAT 0X0002
267 #define PBC_INTR_OTG_FSOVER 0X0004
268 #define PBC_INTR_FSH_OVER 0X0008
269 #define PBC_INTR_SD3_R_EN 0x0010
270 #define PBC_INTR_MS_R_EN 0x0020
271 #define PBC_INTR_SD1_R_EN 0x0040
272 #define PBC_INTR_FEC_INT 0X0080
273 #define PBC_INTR_ENET_INT 0X0100
274 #define PBC_INTR_OTGFS_INT 0X0200
275 #define PBC_INTR_XUART_INT 0X0400
276 #define PBC_INTR_CCTL12 0X0800
277 #define PBC_INTR_SD2_EN 0x1000
278 #define PBC_INTR_SD3_EN 0x2000
279 #define PBC_INTR_MS_EN 0x4000
280 #define PBC_INTR_SD1_EN 0x8000
284 /* For interrupts like xuart, enet etc */
285 #define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX27_PIN_TIN)
286 #define MXC_MAX_EXP_IO_LINES 16
289 * This corresponds to PBC_INTMASK_SET_REG at offset 0x38.
292 #define EXPIO_INT_LOW_BAT (MXC_EXP_IO_BASE + 1)
293 #define EXPIO_INT_OTG_FS_OVR (MXC_EXP_IO_BASE + 2)
294 #define EXPIO_INT_FSH_OVR (MXC_EXP_IO_BASE + 3)
295 #define EXPIO_INT_RES4 (MXC_EXP_IO_BASE + 4)
296 #define EXPIO_INT_RES5 (MXC_EXP_IO_BASE + 5)
297 #define EXPIO_INT_RES6 (MXC_EXP_IO_BASE + 6)
298 #define EXPIO_INT_FEC (MXC_EXP_IO_BASE + 7)
299 #define EXPIO_INT_ENET_INT (MXC_EXP_IO_BASE + 8)
300 #define EXPIO_INT_OTG_FS_INT (MXC_EXP_IO_BASE + 9)
301 #define EXPIO_INT_XUART_INTA (MXC_EXP_IO_BASE + 10)
302 #define EXPIO_INT_CCTL12_INT (MXC_EXP_IO_BASE + 11)
303 #define EXPIO_INT_SD2_EN (MXC_EXP_IO_BASE + 12)
304 #define EXPIO_INT_SD3_EN (MXC_EXP_IO_BASE + 13)
305 #define EXPIO_INT_MS_EN (MXC_EXP_IO_BASE + 14)
306 #define EXPIO_INT_SD1_EN (MXC_EXP_IO_BASE + 15)
309 * This is System IRQ used by CS8900A for interrupt generation
310 * taken from platform.h
312 #define CS8900AIRQ EXPIO_INT_ENET_INT
313 /* This is I/O Base address used to access registers of CS8900A on MXC ADS */
314 #define CS8900A_BASE_ADDRESS (PBC_CS8900A_IOBASE_REG + 0x300)
316 #define MXC_PMIC_INT_LINE IOMUX_TO_IRQ(MX27_PIN_TOUT)
319 * This is used to detect if the CPLD version is for mx27 evb board rev-a
321 #define PBC_CPLD_VERSION_IS_REVA() \
322 ((__raw_readw(PBC_VERSION_REG) & \
323 (PBC_VERSION_ADS | PBC_VERSION_EVB_REVB))\
326 /* This is used to active or inactive ata signal in CPLD .
327 * It is dependent with hardware
329 #define PBC_ATA_SIGNAL_ACTIVE() \
331 PBC_BCTRL2_ATAFEC_EN|PBC_BCTRL2_ATAFEC_SEL|PBC_BCTRL2_ATA_EN, \
332 PBC_BCTRL2_CLEAR_REG)
334 #define PBC_ATA_SIGNAL_INACTIVE() \
336 PBC_BCTRL2_ATAFEC_EN|PBC_BCTRL2_ATAFEC_SEL|PBC_BCTRL2_ATA_EN, \
339 #define MXC_BD_LED1 (1 << 5)
340 #define MXC_BD_LED2 (1 << 6)
341 #define MXC_BD_LED_ON(led) \
342 __raw_writew(led, PBC_BCTRL1_SET_REG)
343 #define MXC_BD_LED_OFF(led) \
344 __raw_writew(led, PBC_BCTRL1_CLEAR_REG)
346 /* to determine the correct external crystal reference */
347 #define CKIH_27MHZ_BIT_SET (1 << 3)
349 #endif /* __ASM_ARCH_MXC_BOARD_MX27ADS_H__ */