Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/x86/linux...
[linux-2.6] / arch / x86 / mach-visws / visws_apic.c
1 /*
2  *      Copyright (C) 1999 Bent Hagemark, Ingo Molnar
3  *
4  *  SGI Visual Workstation interrupt controller
5  *
6  *  The Cobalt system ASIC in the Visual Workstation contains a "Cobalt" APIC
7  *  which serves as the main interrupt controller in the system.  Non-legacy
8  *  hardware in the system uses this controller directly.  Legacy devices
9  *  are connected to the PIIX4 which in turn has its 8259(s) connected to
10  *  a of the Cobalt APIC entry.
11  *
12  *  09/02/2000 - Updated for 2.4 by jbarnes@sgi.com
13  *
14  *  25/11/2002 - Updated for 2.5 by Andrey Panin <pazke@orbita1.ru>
15  */
16
17 #include <linux/kernel_stat.h>
18 #include <linux/interrupt.h>
19 #include <linux/init.h>
20
21 #include <asm/io.h>
22 #include <asm/apic.h>
23 #include <asm/i8259.h>
24
25 #include "cobalt.h"
26 #include "irq_vectors.h"
27
28
29 static DEFINE_SPINLOCK(cobalt_lock);
30
31 /*
32  * Set the given Cobalt APIC Redirection Table entry to point
33  * to the given IDT vector/index.
34  */
35 static inline void co_apic_set(int entry, int irq)
36 {
37         co_apic_write(CO_APIC_LO(entry), CO_APIC_LEVEL | (irq + FIRST_EXTERNAL_VECTOR));
38         co_apic_write(CO_APIC_HI(entry), 0);
39 }
40
41 /*
42  * Cobalt (IO)-APIC functions to handle PCI devices.
43  */
44 static inline int co_apic_ide0_hack(void)
45 {
46         extern char visws_board_type;
47         extern char visws_board_rev;
48
49         if (visws_board_type == VISWS_320 && visws_board_rev == 5)
50                 return 5;
51         return CO_APIC_IDE0;
52 }
53
54 static int is_co_apic(unsigned int irq)
55 {
56         if (IS_CO_APIC(irq))
57                 return CO_APIC(irq);
58
59         switch (irq) {
60                 case 0: return CO_APIC_CPU;
61                 case CO_IRQ_IDE0: return co_apic_ide0_hack();
62                 case CO_IRQ_IDE1: return CO_APIC_IDE1;
63                 default: return -1;
64         }
65 }
66
67
68 /*
69  * This is the SGI Cobalt (IO-)APIC:
70  */
71
72 static void enable_cobalt_irq(unsigned int irq)
73 {
74         co_apic_set(is_co_apic(irq), irq);
75 }
76
77 static void disable_cobalt_irq(unsigned int irq)
78 {
79         int entry = is_co_apic(irq);
80
81         co_apic_write(CO_APIC_LO(entry), CO_APIC_MASK);
82         co_apic_read(CO_APIC_LO(entry));
83 }
84
85 /*
86  * "irq" really just serves to identify the device.  Here is where we
87  * map this to the Cobalt APIC entry where it's physically wired.
88  * This is called via request_irq -> setup_irq -> irq_desc->startup()
89  */
90 static unsigned int startup_cobalt_irq(unsigned int irq)
91 {
92         unsigned long flags;
93
94         spin_lock_irqsave(&cobalt_lock, flags);
95         if ((irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS | IRQ_WAITING)))
96                 irq_desc[irq].status &= ~(IRQ_DISABLED | IRQ_INPROGRESS | IRQ_WAITING);
97         enable_cobalt_irq(irq);
98         spin_unlock_irqrestore(&cobalt_lock, flags);
99         return 0;
100 }
101
102 static void ack_cobalt_irq(unsigned int irq)
103 {
104         unsigned long flags;
105
106         spin_lock_irqsave(&cobalt_lock, flags);
107         disable_cobalt_irq(irq);
108         apic_write(APIC_EOI, APIC_EIO_ACK);
109         spin_unlock_irqrestore(&cobalt_lock, flags);
110 }
111
112 static void end_cobalt_irq(unsigned int irq)
113 {
114         unsigned long flags;
115
116         spin_lock_irqsave(&cobalt_lock, flags);
117         if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
118                 enable_cobalt_irq(irq);
119         spin_unlock_irqrestore(&cobalt_lock, flags);
120 }
121
122 static struct irq_chip cobalt_irq_type = {
123         .typename =     "Cobalt-APIC",
124         .startup =      startup_cobalt_irq,
125         .shutdown =     disable_cobalt_irq,
126         .enable =       enable_cobalt_irq,
127         .disable =      disable_cobalt_irq,
128         .ack =          ack_cobalt_irq,
129         .end =          end_cobalt_irq,
130 };
131
132
133 /*
134  * This is the PIIX4-based 8259 that is wired up indirectly to Cobalt
135  * -- not the manner expected by the code in i8259.c.
136  *
137  * there is a 'master' physical interrupt source that gets sent to
138  * the CPU. But in the chipset there are various 'virtual' interrupts
139  * waiting to be handled. We represent this to Linux through a 'master'
140  * interrupt controller type, and through a special virtual interrupt-
141  * controller. Device drivers only see the virtual interrupt sources.
142  */
143 static unsigned int startup_piix4_master_irq(unsigned int irq)
144 {
145         init_8259A(0);
146
147         return startup_cobalt_irq(irq);
148 }
149
150 static void end_piix4_master_irq(unsigned int irq)
151 {
152         unsigned long flags;
153
154         spin_lock_irqsave(&cobalt_lock, flags);
155         enable_cobalt_irq(irq);
156         spin_unlock_irqrestore(&cobalt_lock, flags);
157 }
158
159 static struct irq_chip piix4_master_irq_type = {
160         .typename =     "PIIX4-master",
161         .startup =      startup_piix4_master_irq,
162         .ack =          ack_cobalt_irq,
163         .end =          end_piix4_master_irq,
164 };
165
166
167 static struct irq_chip piix4_virtual_irq_type = {
168         .typename =     "PIIX4-virtual",
169         .shutdown =     disable_8259A_irq,
170         .enable =       enable_8259A_irq,
171         .disable =      disable_8259A_irq,
172 };
173
174
175 /*
176  * PIIX4-8259 master/virtual functions to handle interrupt requests
177  * from legacy devices: floppy, parallel, serial, rtc.
178  *
179  * None of these get Cobalt APIC entries, neither do they have IDT
180  * entries. These interrupts are purely virtual and distributed from
181  * the 'master' interrupt source: CO_IRQ_8259.
182  *
183  * When the 8259 interrupts its handler figures out which of these
184  * devices is interrupting and dispatches to its handler.
185  *
186  * CAREFUL: devices see the 'virtual' interrupt only. Thus disable/
187  * enable_irq gets the right irq. This 'master' irq is never directly
188  * manipulated by any driver.
189  */
190 static irqreturn_t piix4_master_intr(int irq, void *dev_id)
191 {
192         int realirq;
193         irq_desc_t *desc;
194         unsigned long flags;
195
196         spin_lock_irqsave(&i8259A_lock, flags);
197
198         /* Find out what's interrupting in the PIIX4 master 8259 */
199         outb(0x0c, 0x20);               /* OCW3 Poll command */
200         realirq = inb(0x20);
201
202         /*
203          * Bit 7 == 0 means invalid/spurious
204          */
205         if (unlikely(!(realirq & 0x80)))
206                 goto out_unlock;
207
208         realirq &= 7;
209
210         if (unlikely(realirq == 2)) {
211                 outb(0x0c, 0xa0);
212                 realirq = inb(0xa0);
213
214                 if (unlikely(!(realirq & 0x80)))
215                         goto out_unlock;
216
217                 realirq = (realirq & 7) + 8;
218         }
219
220         /* mask and ack interrupt */
221         cached_irq_mask |= 1 << realirq;
222         if (unlikely(realirq > 7)) {
223                 inb(0xa1);
224                 outb(cached_slave_mask, 0xa1);
225                 outb(0x60 + (realirq & 7), 0xa0);
226                 outb(0x60 + 2, 0x20);
227         } else {
228                 inb(0x21);
229                 outb(cached_master_mask, 0x21);
230                 outb(0x60 + realirq, 0x20);
231         }
232
233         spin_unlock_irqrestore(&i8259A_lock, flags);
234
235         desc = irq_desc + realirq;
236
237         /*
238          * handle this 'virtual interrupt' as a Cobalt one now.
239          */
240         kstat_cpu(smp_processor_id()).irqs[realirq]++;
241
242         if (likely(desc->action != NULL))
243                 handle_IRQ_event(realirq, desc->action);
244
245         if (!(desc->status & IRQ_DISABLED))
246                 enable_8259A_irq(realirq);
247
248         return IRQ_HANDLED;
249
250 out_unlock:
251         spin_unlock_irqrestore(&i8259A_lock, flags);
252         return IRQ_NONE;
253 }
254
255 static struct irqaction master_action = {
256         .handler =      piix4_master_intr,
257         .name =         "PIIX4-8259",
258 };
259
260 static struct irqaction cascade_action = {
261         .handler =      no_action,
262         .name =         "cascade",
263 };
264
265
266 void init_VISWS_APIC_irqs(void)
267 {
268         int i;
269
270         for (i = 0; i < CO_IRQ_APIC0 + CO_APIC_LAST + 1; i++) {
271                 irq_desc[i].status = IRQ_DISABLED;
272                 irq_desc[i].action = 0;
273                 irq_desc[i].depth = 1;
274
275                 if (i == 0) {
276                         irq_desc[i].chip = &cobalt_irq_type;
277                 }
278                 else if (i == CO_IRQ_IDE0) {
279                         irq_desc[i].chip = &cobalt_irq_type;
280                 }
281                 else if (i == CO_IRQ_IDE1) {
282                         irq_desc[i].chip = &cobalt_irq_type;
283                 }
284                 else if (i == CO_IRQ_8259) {
285                         irq_desc[i].chip = &piix4_master_irq_type;
286                 }
287                 else if (i < CO_IRQ_APIC0) {
288                         irq_desc[i].chip = &piix4_virtual_irq_type;
289                 }
290                 else if (IS_CO_APIC(i)) {
291                         irq_desc[i].chip = &cobalt_irq_type;
292                 }
293         }
294
295         setup_irq(CO_IRQ_8259, &master_action);
296         setup_irq(2, &cascade_action);
297 }