git.oblomov.eu Git - linux-2.6/blob - drivers/video/savage/savagefb_driver.c

   1 /*
   2  * linux/drivers/video/savagefb.c -- S3 Savage Framebuffer Driver
   3  *
   4  * Copyright (c) 2001-2002  Denis Oliver Kropp <dok@directfb.org>
   5  *                          Sven Neumann <neo@directfb.org>
   6  *
   7  *
   8  * Card specific code is based on XFree86's savage driver.
   9  * Framebuffer framework code is based on code of cyber2000fb and tdfxfb.
  10  *
  11  * This file is subject to the terms and conditions of the GNU General
  12  * Public License.  See the file COPYING in the main directory of this
  13  * archive for more details.
  14  *
  15  * 0.4.0 (neo)
  16  *  - hardware accelerated clear and move
  17  *
  18  * 0.3.2 (dok)
  19  *  - wait for vertical retrace before writing to cr67
  20  *    at the beginning of savagefb_set_par
  21  *  - use synchronization registers cr23 and cr26
  22  *
  23  * 0.3.1 (dok)
  24  *  - reset 3D engine
  25  *  - don't return alpha bits for 32bit format
  26  *
  27  * 0.3.0 (dok)
  28  *  - added WaitIdle functions for all Savage types
  29  *  - do WaitIdle before mode switching
  30  *  - code cleanup
  31  *
  32  * 0.2.0 (dok)
  33  *  - first working version
  34  *
  35  *
  36  * TODO
  37  * - clock validations in decode_var
  38  *
  39  * BUGS
  40  * - white margin on bootup
  41  *
  42  */
  43
  44 #include <linux/config.h>
  45 #include <linux/module.h>
  46 #include <linux/kernel.h>
  47 #include <linux/errno.h>
  48 #include <linux/string.h>
  49 #include <linux/mm.h>
  50 #include <linux/tty.h>
  51 #include <linux/slab.h>
  52 #include <linux/delay.h>
  53 #include <linux/fb.h>
  54 #include <linux/pci.h>
  55 #include <linux/init.h>
  56 #include <linux/console.h>
  57
  58 #include <asm/io.h>
  59 #include <asm/irq.h>
  60 #include <asm/pgtable.h>
  61 #include <asm/system.h>
  62 #include <asm/uaccess.h>
  63
  64 #ifdef CONFIG_MTRR
  65 #include <asm/mtrr.h>
  66 #endif
  67
  68 #include "savagefb.h"
  69
  70
  71 #define SAVAGEFB_VERSION "0.4.0_2.6"
  72
  73 /* --------------------------------------------------------------------- */
  74
  75
  76 static char *mode_option __devinitdata = NULL;
  77
  78 #ifdef MODULE
  79
  80 MODULE_AUTHOR("(c) 2001-2002  Denis Oliver Kropp <dok@directfb.org>");
  81 MODULE_LICENSE("GPL");
  82 MODULE_DESCRIPTION("FBDev driver for S3 Savage PCI/AGP Chips");
  83
  84 #endif
  85
  86
  87 /* --------------------------------------------------------------------- */
  88
  89 static void vgaHWSeqReset(struct savagefb_par *par, int start)
  90 {
  91         if (start)
  92                 VGAwSEQ(0x00, 0x01, par);       /* Synchronous Reset */
  93         else
  94                 VGAwSEQ(0x00, 0x03, par);       /* End Reset */
  95 }
  96
  97 static void vgaHWProtect(struct savagefb_par *par, int on)
  98 {
  99         unsigned char tmp;
 100
 101         if (on) {
 102                 /*
 103                  * Turn off screen and disable sequencer.
 104                  */
 105                 tmp = VGArSEQ(0x01, par);
 106
 107                 vgaHWSeqReset(par, 1);          /* start synchronous reset */
 108                 VGAwSEQ(0x01, tmp | 0x20, par);/* disable the display */
 109
 110                 VGAenablePalette(par);
 111         } else {
 112                 /*
 113                  * Reenable sequencer, then turn on screen.
 114                  */
 115
 116                 tmp = VGArSEQ(0x01, par);
 117
 118                 VGAwSEQ(0x01, tmp & ~0x20, par);/* reenable display */
 119                 vgaHWSeqReset(par, 0);          /* clear synchronous reset */
 120
 121                 VGAdisablePalette(par);
 122         }
 123 }
 124
 125 static void vgaHWRestore(struct savagefb_par  *par, struct savage_reg *reg)
 126 {
 127         int i;
 128
 129         VGAwMISC(reg->MiscOutReg, par);
 130
 131         for (i = 1; i < 5; i++)
 132                 VGAwSEQ(i, reg->Sequencer[i], par);
 133
 134         /* Ensure CRTC registers 0-7 are unlocked by clearing bit 7 or
 135            CRTC[17] */
 136         VGAwCR(17, reg->CRTC[17] & ~0x80, par);
 137
 138         for (i = 0; i < 25; i++)
 139                 VGAwCR(i, reg->CRTC[i], par);
 140
 141         for (i = 0; i < 9; i++)
 142                 VGAwGR(i, reg->Graphics[i], par);
 143
 144         VGAenablePalette(par);
 145
 146         for (i = 0; i < 21; i++)
 147                 VGAwATTR(i, reg->Attribute[i], par);
 148
 149         VGAdisablePalette(par);
 150 }
 151
 152 static void vgaHWInit(struct fb_var_screeninfo *var,
 153                       struct savagefb_par            *par,
 154                       struct xtimings                *timings,
 155                       struct savage_reg              *reg)
 156 {
 157         reg->MiscOutReg = 0x23;
 158
 159         if (!(timings->sync & FB_SYNC_HOR_HIGH_ACT))
 160                 reg->MiscOutReg |= 0x40;
 161
 162         if (!(timings->sync & FB_SYNC_VERT_HIGH_ACT))
 163                 reg->MiscOutReg |= 0x80;
 164
 165         /*
 166          * Time Sequencer
 167          */
 168         reg->Sequencer[0x00] = 0x00;
 169         reg->Sequencer[0x01] = 0x01;
 170         reg->Sequencer[0x02] = 0x0F;
 171         reg->Sequencer[0x03] = 0x00;          /* Font select */
 172         reg->Sequencer[0x04] = 0x0E;          /* Misc */
 173
 174         /*
 175          * CRTC Controller
 176          */
 177         reg->CRTC[0x00] = (timings->HTotal >> 3) - 5;
 178         reg->CRTC[0x01] = (timings->HDisplay >> 3) - 1;
 179         reg->CRTC[0x02] = (timings->HSyncStart >> 3) - 1;
 180         reg->CRTC[0x03] = (((timings->HSyncEnd >> 3)  - 1) & 0x1f) | 0x80;
 181         reg->CRTC[0x04] = (timings->HSyncStart >> 3);
 182         reg->CRTC[0x05] = ((((timings->HSyncEnd >> 3) - 1) & 0x20) << 2) |
 183                 (((timings->HSyncEnd >> 3)) & 0x1f);
 184         reg->CRTC[0x06] = (timings->VTotal - 2) & 0xFF;
 185         reg->CRTC[0x07] = (((timings->VTotal - 2) & 0x100) >> 8) |
 186                 (((timings->VDisplay - 1) & 0x100) >> 7) |
 187                 ((timings->VSyncStart & 0x100) >> 6) |
 188                 (((timings->VSyncStart - 1) & 0x100) >> 5) |
 189                 0x10 |
 190                 (((timings->VTotal - 2) & 0x200) >> 4) |
 191                 (((timings->VDisplay - 1) & 0x200) >> 3) |
 192                 ((timings->VSyncStart & 0x200) >> 2);
 193         reg->CRTC[0x08] = 0x00;
 194         reg->CRTC[0x09] = (((timings->VSyncStart - 1) & 0x200) >> 4) | 0x40;
 195
 196         if (timings->dblscan)
 197                 reg->CRTC[0x09] |= 0x80;
 198
 199         reg->CRTC[0x0a] = 0x00;
 200         reg->CRTC[0x0b] = 0x00;
 201         reg->CRTC[0x0c] = 0x00;
 202         reg->CRTC[0x0d] = 0x00;
 203         reg->CRTC[0x0e] = 0x00;
 204         reg->CRTC[0x0f] = 0x00;
 205         reg->CRTC[0x10] = timings->VSyncStart & 0xff;
 206         reg->CRTC[0x11] = (timings->VSyncEnd & 0x0f) | 0x20;
 207         reg->CRTC[0x12] = (timings->VDisplay - 1) & 0xff;
 208         reg->CRTC[0x13] = var->xres_virtual >> 4;
 209         reg->CRTC[0x14] = 0x00;
 210         reg->CRTC[0x15] = (timings->VSyncStart - 1) & 0xff;
 211         reg->CRTC[0x16] = (timings->VSyncEnd - 1) & 0xff;
 212         reg->CRTC[0x17] = 0xc3;
 213         reg->CRTC[0x18] = 0xff;
 214
 215         /*
 216          * are these unnecessary?
 217          * vgaHWHBlankKGA(mode, regp, 0, KGA_FIX_OVERSCAN|KGA_ENABLE_ON_ZERO);
 218          * vgaHWVBlankKGA(mode, regp, 0, KGA_FIX_OVERSCAN|KGA_ENABLE_ON_ZERO);
 219          */
 220
 221         /*
 222          * Graphics Display Controller
 223          */
 224         reg->Graphics[0x00] = 0x00;
 225         reg->Graphics[0x01] = 0x00;
 226         reg->Graphics[0x02] = 0x00;
 227         reg->Graphics[0x03] = 0x00;
 228         reg->Graphics[0x04] = 0x00;
 229         reg->Graphics[0x05] = 0x40;
 230         reg->Graphics[0x06] = 0x05;   /* only map 64k VGA memory !!!! */
 231         reg->Graphics[0x07] = 0x0F;
 232         reg->Graphics[0x08] = 0xFF;
 233
 234
 235         reg->Attribute[0x00]  = 0x00; /* standard colormap translation */
 236         reg->Attribute[0x01]  = 0x01;
 237         reg->Attribute[0x02]  = 0x02;
 238         reg->Attribute[0x03]  = 0x03;
 239         reg->Attribute[0x04]  = 0x04;
 240         reg->Attribute[0x05]  = 0x05;
 241         reg->Attribute[0x06]  = 0x06;
 242         reg->Attribute[0x07]  = 0x07;
 243         reg->Attribute[0x08]  = 0x08;
 244         reg->Attribute[0x09]  = 0x09;
 245         reg->Attribute[0x0a] = 0x0A;
 246         reg->Attribute[0x0b] = 0x0B;
 247         reg->Attribute[0x0c] = 0x0C;
 248         reg->Attribute[0x0d] = 0x0D;
 249         reg->Attribute[0x0e] = 0x0E;
 250         reg->Attribute[0x0f] = 0x0F;
 251         reg->Attribute[0x10] = 0x41;
 252         reg->Attribute[0x11] = 0xFF;
 253         reg->Attribute[0x12] = 0x0F;
 254         reg->Attribute[0x13] = 0x00;
 255         reg->Attribute[0x14] = 0x00;
 256 }
 257
 258 /* -------------------- Hardware specific routines ------------------------- */
 259
 260 /*
 261  * Hardware Acceleration for SavageFB
 262  */
 263
 264 /* Wait for fifo space */
 265 static void
 266 savage3D_waitfifo(struct savagefb_par *par, int space)
 267 {
 268         int slots = MAXFIFO - space;
 269
 270         while ((savage_in32(0x48C00, par) & 0x0000ffff) > slots);
 271 }
 272
 273 static void
 274 savage4_waitfifo(struct savagefb_par *par, int space)
 275 {
 276         int slots = MAXFIFO - space;
 277
 278         while ((savage_in32(0x48C60, par) & 0x001fffff) > slots);
 279 }
 280
 281 static void
 282 savage2000_waitfifo(struct savagefb_par *par, int space)
 283 {
 284         int slots = MAXFIFO - space;
 285
 286         while ((savage_in32(0x48C60, par) & 0x0000ffff) > slots);
 287 }
 288
 289 /* Wait for idle accelerator */
 290 static void
 291 savage3D_waitidle(struct savagefb_par *par)
 292 {
 293         while ((savage_in32(0x48C00, par) & 0x0008ffff) != 0x80000);
 294 }
 295
 296 static void
 297 savage4_waitidle(struct savagefb_par *par)
 298 {
 299         while ((savage_in32(0x48C60, par) & 0x00a00000) != 0x00a00000);
 300 }
 301
 302 static void
 303 savage2000_waitidle(struct savagefb_par *par)
 304 {
 305         while ((savage_in32(0x48C60, par) & 0x009fffff));
 306 }
 307
 308 #ifdef CONFIG_FB_SAVAGE_ACCEL
 309 static void
 310 SavageSetup2DEngine(struct savagefb_par  *par)
 311 {
 312         unsigned long GlobalBitmapDescriptor;
 313
 314         GlobalBitmapDescriptor = 1 | 8 | BCI_BD_BW_DISABLE;
 315         BCI_BD_SET_BPP(GlobalBitmapDescriptor, par->depth);
 316         BCI_BD_SET_STRIDE(GlobalBitmapDescriptor, par->vwidth);
 317
 318         switch(par->chip) {
 319         case S3_SAVAGE3D:
 320         case S3_SAVAGE_MX:
 321                 /* Disable BCI */
 322                 savage_out32(0x48C18, savage_in32(0x48C18, par) & 0x3FF0, par);
 323                 /* Setup BCI command overflow buffer */
 324                 savage_out32(0x48C14,
 325                              (par->cob_offset >> 11) | (par->cob_index << 29),
 326                              par);
 327                 /* Program shadow status update. */
 328                 savage_out32(0x48C10, 0x78207220, par);
 329                 savage_out32(0x48C0C, 0, par);
 330                 /* Enable BCI and command overflow buffer */
 331                 savage_out32(0x48C18, savage_in32(0x48C18, par) | 0x0C, par);
 332                 break;
 333         case S3_SAVAGE4:
 334         case S3_PROSAVAGE:
 335         case S3_SUPERSAVAGE:
 336                 /* Disable BCI */
 337                 savage_out32(0x48C18, savage_in32(0x48C18, par) & 0x3FF0, par);
 338                 /* Program shadow status update */
 339                 savage_out32(0x48C10, 0x00700040, par);
 340                 savage_out32(0x48C0C, 0, par);
 341                 /* Enable BCI without the COB */
 342                 savage_out32(0x48C18, savage_in32(0x48C18, par) | 0x08, par);
 343                 break;
 344         case S3_SAVAGE2000:
 345                 /* Disable BCI */
 346                 savage_out32(0x48C18, 0, par);
 347                 /* Setup BCI command overflow buffer */
 348                 savage_out32(0x48C18,
 349                              (par->cob_offset >> 7) | (par->cob_index),
 350                              par);
 351                 /* Disable shadow status update */
 352                 savage_out32(0x48A30, 0, par);
 353                 /* Enable BCI and command overflow buffer */
 354                 savage_out32(0x48C18, savage_in32(0x48C18, par) | 0x00280000,
 355                              par);
 356                 break;
 357             default:
 358                 break;
 359         }
 360         /* Turn on 16-bit register access. */
 361         vga_out8(0x3d4, 0x31, par);
 362         vga_out8(0x3d5, 0x0c, par);
 363
 364         /* Set stride to use GBD. */
 365         vga_out8(0x3d4, 0x50, par);
 366         vga_out8(0x3d5, vga_in8(0x3d5, par) | 0xC1, par);
 367
 368         /* Enable 2D engine. */
 369         vga_out8(0x3d4, 0x40, par);
 370         vga_out8(0x3d5, 0x01, par);
 371
 372         savage_out32(MONO_PAT_0, ~0, par);
 373         savage_out32(MONO_PAT_1, ~0, par);
 374
 375         /* Setup plane masks */
 376         savage_out32(0x8128, ~0, par); /* enable all write planes */
 377         savage_out32(0x812C, ~0, par); /* enable all read planes */
 378         savage_out16(0x8134, 0x27, par);
 379         savage_out16(0x8136, 0x07, par);
 380
 381         /* Now set the GBD */
 382         par->bci_ptr = 0;
 383         par->SavageWaitFifo(par, 4);
 384
 385         BCI_SEND(BCI_CMD_SETREG | (1 << 16) | BCI_GBD1);
 386         BCI_SEND(0);
 387         BCI_SEND(BCI_CMD_SETREG | (1 << 16) | BCI_GBD2);
 388         BCI_SEND(GlobalBitmapDescriptor);
 389 }
 390
 391 static void savagefb_set_clip(struct fb_info *info)
 392 {
 393         struct savagefb_par *par = info->par;
 394         int cmd;
 395
 396         cmd = BCI_CMD_NOP | BCI_CMD_CLIP_NEW;
 397         par->bci_ptr = 0;
 398         par->SavageWaitFifo(par,3);
 399         BCI_SEND(cmd);
 400         BCI_SEND(BCI_CLIP_TL(0, 0));
 401         BCI_SEND(BCI_CLIP_BR(0xfff, 0xfff));
 402 }
 403 #else
 404 static void SavageSetup2DEngine(struct savagefb_par  *par) {}
 405
 406 #endif
 407
 408 static void SavageCalcClock(long freq, int min_m, int min_n1, int max_n1,
 409                             int min_n2, int max_n2, long freq_min,
 410                             long freq_max, unsigned int *mdiv,
 411                             unsigned int *ndiv, unsigned int *r)
 412 {
 413         long diff, best_diff;
 414         unsigned int m;
 415         unsigned char n1, n2, best_n1=16+2, best_n2=2, best_m=125+2;
 416
 417         if (freq < freq_min / (1 << max_n2)) {
 418                 printk(KERN_ERR "invalid frequency %ld Khz\n", freq);
 419                 freq = freq_min / (1 << max_n2);
 420         }
 421         if (freq > freq_max / (1 << min_n2)) {
 422                 printk(KERN_ERR "invalid frequency %ld Khz\n", freq);
 423                 freq = freq_max / (1 << min_n2);
 424         }
 425
 426         /* work out suitable timings */
 427         best_diff = freq;
 428
 429         for (n2=min_n2; n2<=max_n2; n2++) {
 430                 for (n1=min_n1+2; n1<=max_n1+2; n1++) {
 431                         m = (freq * n1 * (1 << n2) + HALF_BASE_FREQ) /
 432                                 BASE_FREQ;
 433                         if (m < min_m+2 || m > 127+2)
 434                                 continue;
 435                         if ((m * BASE_FREQ >= freq_min * n1) &&
 436                             (m * BASE_FREQ <= freq_max * n1)) {
 437                                 diff = freq * (1 << n2) * n1 - BASE_FREQ * m;
 438                                 if (diff < 0)
 439                                         diff = -diff;
 440                                 if (diff < best_diff) {
 441                                         best_diff = diff;
 442                                         best_m = m;
 443                                         best_n1 = n1;
 444                                         best_n2 = n2;
 445                                 }
 446                         }
 447                 }
 448         }
 449
 450         *ndiv = best_n1 - 2;
 451         *r = best_n2;
 452         *mdiv = best_m - 2;
 453 }
 454
 455 static int common_calc_clock(long freq, int min_m, int min_n1, int max_n1,
 456                              int min_n2, int max_n2, long freq_min,
 457                              long freq_max, unsigned char *mdiv,
 458                              unsigned char *ndiv)
 459 {
 460         long diff, best_diff;
 461         unsigned int m;
 462         unsigned char n1, n2;
 463         unsigned char best_n1 = 16+2, best_n2 = 2, best_m = 125+2;
 464
 465         best_diff = freq;
 466
 467         for (n2 = min_n2; n2 <= max_n2; n2++) {
 468                 for (n1 = min_n1+2; n1 <= max_n1+2; n1++) {
 469                         m = (freq * n1 * (1 << n2) + HALF_BASE_FREQ) /
 470                                 BASE_FREQ;
 471                         if (m < min_m + 2 || m > 127+2)
 472                                 continue;
 473                         if ((m * BASE_FREQ >= freq_min * n1) &&
 474                             (m * BASE_FREQ <= freq_max * n1)) {
 475                                 diff = freq * (1 << n2) * n1 - BASE_FREQ * m;
 476                                 if (diff < 0)
 477                                         diff = -diff;
 478                                 if (diff < best_diff) {
 479                                         best_diff = diff;
 480                                         best_m = m;
 481                                         best_n1 = n1;
 482                                         best_n2 = n2;
 483                                 }
 484                         }
 485                 }
 486         }
 487
 488         if (max_n1 == 63)
 489                 *ndiv = (best_n1 - 2) | (best_n2 << 6);
 490         else
 491                 *ndiv = (best_n1 - 2) | (best_n2 << 5);
 492
 493         *mdiv = best_m - 2;
 494
 495         return 0;
 496 }
 497
 498 #ifdef SAVAGEFB_DEBUG
 499 /* This function is used to debug, it prints out the contents of s3 regs */
 500
 501 static void SavagePrintRegs(void)
 502 {
 503         unsigned char i;
 504         int vgaCRIndex = 0x3d4;
 505         int vgaCRReg = 0x3d5;
 506
 507         printk(KERN_DEBUG "SR    x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 xA xB xC xD xE "
 508                "xF");
 509
 510         for (i = 0; i < 0x70; i++) {
 511                 if (!(i % 16))
 512                         printk(KERN_DEBUG "\nSR%xx ", i >> 4);
 513                 vga_out8(0x3c4, i, par);
 514                 printk(KERN_DEBUG " %02x", vga_in8(0x3c5, par));
 515         }
 516
 517         printk(KERN_DEBUG "\n\nCR    x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 xA xB xC "
 518                "xD xE xF");
 519
 520         for (i = 0; i < 0xB7; i++) {
 521                 if (!(i % 16))
 522                         printk(KERN_DEBUG "\nCR%xx ", i >> 4);
 523                 vga_out8(vgaCRIndex, i, par);
 524                 printk(KERN_DEBUG " %02x", vga_in8(vgaCRReg, par));
 525         }
 526
 527         printk(KERN_DEBUG "\n\n");
 528 }
 529 #endif
 530
 531 /* --------------------------------------------------------------------- */
 532
 533 static void savage_get_default_par(struct savagefb_par *par, struct savage_reg *reg)
 534 {
 535         unsigned char cr3a, cr53, cr66;
 536
 537         vga_out16(0x3d4, 0x4838, par);
 538         vga_out16(0x3d4, 0xa039, par);
 539         vga_out16(0x3c4, 0x0608, par);
 540
 541         vga_out8(0x3d4, 0x66, par);
 542         cr66 = vga_in8(0x3d5, par);
 543         vga_out8(0x3d5, cr66 | 0x80, par);
 544         vga_out8(0x3d4, 0x3a, par);
 545         cr3a = vga_in8(0x3d5, par);
 546         vga_out8(0x3d5, cr3a | 0x80, par);
 547         vga_out8(0x3d4, 0x53, par);
 548         cr53 = vga_in8(0x3d5, par);
 549         vga_out8(0x3d5, cr53 & 0x7f, par);
 550
 551         vga_out8(0x3d4, 0x66, par);
 552         vga_out8(0x3d5, cr66, par);
 553         vga_out8(0x3d4, 0x3a, par);
 554         vga_out8(0x3d5, cr3a, par);
 555
 556         vga_out8(0x3d4, 0x66, par);
 557         vga_out8(0x3d5, cr66, par);
 558         vga_out8(0x3d4, 0x3a, par);
 559         vga_out8(0x3d5, cr3a, par);
 560
 561         /* unlock extended seq regs */
 562         vga_out8(0x3c4, 0x08, par);
 563         reg->SR08 = vga_in8(0x3c5, par);
 564         vga_out8(0x3c5, 0x06, par);
 565
 566         /* now save all the extended regs we need */
 567         vga_out8(0x3d4, 0x31, par);
 568         reg->CR31 = vga_in8(0x3d5, par);
 569         vga_out8(0x3d4, 0x32, par);
 570         reg->CR32 = vga_in8(0x3d5, par);
 571         vga_out8(0x3d4, 0x34, par);
 572         reg->CR34 = vga_in8(0x3d5, par);
 573         vga_out8(0x3d4, 0x36, par);
 574         reg->CR36 = vga_in8(0x3d5, par);
 575         vga_out8(0x3d4, 0x3a, par);
 576         reg->CR3A = vga_in8(0x3d5, par);
 577         vga_out8(0x3d4, 0x40, par);
 578         reg->CR40 = vga_in8(0x3d5, par);
 579         vga_out8(0x3d4, 0x42, par);
 580         reg->CR42 = vga_in8(0x3d5, par);
 581         vga_out8(0x3d4, 0x45, par);
 582         reg->CR45 = vga_in8(0x3d5, par);
 583         vga_out8(0x3d4, 0x50, par);
 584         reg->CR50 = vga_in8(0x3d5, par);
 585         vga_out8(0x3d4, 0x51, par);
 586         reg->CR51 = vga_in8(0x3d5, par);
 587         vga_out8(0x3d4, 0x53, par);
 588         reg->CR53 = vga_in8(0x3d5, par);
 589         vga_out8(0x3d4, 0x58, par);
 590         reg->CR58 = vga_in8(0x3d5, par);
 591         vga_out8(0x3d4, 0x60, par);
 592         reg->CR60 = vga_in8(0x3d5, par);
 593         vga_out8(0x3d4, 0x66, par);
 594         reg->CR66 = vga_in8(0x3d5, par);
 595         vga_out8(0x3d4, 0x67, par);
 596         reg->CR67 = vga_in8(0x3d5, par);
 597         vga_out8(0x3d4, 0x68, par);
 598         reg->CR68 = vga_in8(0x3d5, par);
 599         vga_out8(0x3d4, 0x69, par);
 600         reg->CR69 = vga_in8(0x3d5, par);
 601         vga_out8(0x3d4, 0x6f, par);
 602         reg->CR6F = vga_in8(0x3d5, par);
 603
 604         vga_out8(0x3d4, 0x33, par);
 605         reg->CR33 = vga_in8(0x3d5, par);
 606         vga_out8(0x3d4, 0x86, par);
 607         reg->CR86 = vga_in8(0x3d5, par);
 608         vga_out8(0x3d4, 0x88, par);
 609         reg->CR88 = vga_in8(0x3d5, par);
 610         vga_out8(0x3d4, 0x90, par);
 611         reg->CR90 = vga_in8(0x3d5, par);
 612         vga_out8(0x3d4, 0x91, par);
 613         reg->CR91 = vga_in8(0x3d5, par);
 614         vga_out8(0x3d4, 0xb0, par);
 615         reg->CRB0 = vga_in8(0x3d5, par) | 0x80;
 616
 617         /* extended mode timing regs */
 618         vga_out8(0x3d4, 0x3b, par);
 619         reg->CR3B = vga_in8(0x3d5, par);
 620         vga_out8(0x3d4, 0x3c, par);
 621         reg->CR3C = vga_in8(0x3d5, par);
 622         vga_out8(0x3d4, 0x43, par);
 623         reg->CR43 = vga_in8(0x3d5, par);
 624         vga_out8(0x3d4, 0x5d, par);
 625         reg->CR5D = vga_in8(0x3d5, par);
 626         vga_out8(0x3d4, 0x5e, par);
 627         reg->CR5E = vga_in8(0x3d5, par);
 628         vga_out8(0x3d4, 0x65, par);
 629         reg->CR65 = vga_in8(0x3d5, par);
 630
 631         /* save seq extended regs for DCLK PLL programming */
 632         vga_out8(0x3c4, 0x0e, par);
 633         reg->SR0E = vga_in8(0x3c5, par);
 634         vga_out8(0x3c4, 0x0f, par);
 635         reg->SR0F = vga_in8(0x3c5, par);
 636         vga_out8(0x3c4, 0x10, par);
 637         reg->SR10 = vga_in8(0x3c5, par);
 638         vga_out8(0x3c4, 0x11, par);
 639         reg->SR11 = vga_in8(0x3c5, par);
 640         vga_out8(0x3c4, 0x12, par);
 641         reg->SR12 = vga_in8(0x3c5, par);
 642         vga_out8(0x3c4, 0x13, par);
 643         reg->SR13 = vga_in8(0x3c5, par);
 644         vga_out8(0x3c4, 0x29, par);
 645         reg->SR29 = vga_in8(0x3c5, par);
 646
 647         vga_out8(0x3c4, 0x15, par);
 648         reg->SR15 = vga_in8(0x3c5, par);
 649         vga_out8(0x3c4, 0x30, par);
 650         reg->SR30 = vga_in8(0x3c5, par);
 651         vga_out8(0x3c4, 0x18, par);
 652         reg->SR18 = vga_in8(0x3c5, par);
 653
 654         /* Save flat panel expansion regsters. */
 655         if (par->chip == S3_SAVAGE_MX) {
 656                 int i;
 657
 658                 for (i = 0; i < 8; i++) {
 659                         vga_out8(0x3c4, 0x54+i, par);
 660                         reg->SR54[i] = vga_in8(0x3c5, par);
 661                 }
 662         }
 663
 664         vga_out8(0x3d4, 0x66, par);
 665         cr66 = vga_in8(0x3d5, par);
 666         vga_out8(0x3d5, cr66 | 0x80, par);
 667         vga_out8(0x3d4, 0x3a, par);
 668         cr3a = vga_in8(0x3d5, par);
 669         vga_out8(0x3d5, cr3a | 0x80, par);
 670
 671         /* now save MIU regs */
 672         if (par->chip != S3_SAVAGE_MX) {
 673                 reg->MMPR0 = savage_in32(FIFO_CONTROL_REG, par);
 674                 reg->MMPR1 = savage_in32(MIU_CONTROL_REG, par);
 675                 reg->MMPR2 = savage_in32(STREAMS_TIMEOUT_REG, par);
 676                 reg->MMPR3 = savage_in32(MISC_TIMEOUT_REG, par);
 677         }
 678
 679         vga_out8(0x3d4, 0x3a, par);
 680         vga_out8(0x3d5, cr3a, par);
 681         vga_out8(0x3d4, 0x66, par);
 682         vga_out8(0x3d5, cr66, par);
 683 }
 684
 685 static void savage_set_default_par(struct savagefb_par *par,
 686                                 struct savage_reg *reg)
 687 {
 688         unsigned char cr3a, cr53, cr66;
 689
 690         vga_out16(0x3d4, 0x4838, par);
 691         vga_out16(0x3d4, 0xa039, par);
 692         vga_out16(0x3c4, 0x0608, par);
 693
 694         vga_out8(0x3d4, 0x66, par);
 695         cr66 = vga_in8(0x3d5, par);
 696         vga_out8(0x3d5, cr66 | 0x80, par);
 697         vga_out8(0x3d4, 0x3a, par);
 698         cr3a = vga_in8(0x3d5, par);
 699         vga_out8(0x3d5, cr3a | 0x80, par);
 700         vga_out8(0x3d4, 0x53, par);
 701         cr53 = vga_in8(0x3d5, par);
 702         vga_out8(0x3d5, cr53 & 0x7f, par);
 703
 704         vga_out8(0x3d4, 0x66, par);
 705         vga_out8(0x3d5, cr66, par);
 706         vga_out8(0x3d4, 0x3a, par);
 707         vga_out8(0x3d5, cr3a, par);
 708
 709         vga_out8(0x3d4, 0x66, par);
 710         vga_out8(0x3d5, cr66, par);
 711         vga_out8(0x3d4, 0x3a, par);
 712         vga_out8(0x3d5, cr3a, par);
 713
 714         /* unlock extended seq regs */
 715         vga_out8(0x3c4, 0x08, par);
 716         vga_out8(0x3c5, reg->SR08, par);
 717         vga_out8(0x3c5, 0x06, par);
 718
 719         /* now restore all the extended regs we need */
 720         vga_out8(0x3d4, 0x31, par);
 721         vga_out8(0x3d5, reg->CR31, par);
 722         vga_out8(0x3d4, 0x32, par);
 723         vga_out8(0x3d5, reg->CR32, par);
 724         vga_out8(0x3d4, 0x34, par);
 725         vga_out8(0x3d5, reg->CR34, par);
 726         vga_out8(0x3d4, 0x36, par);
 727         vga_out8(0x3d5,reg->CR36, par);
 728         vga_out8(0x3d4, 0x3a, par);
 729         vga_out8(0x3d5, reg->CR3A, par);
 730         vga_out8(0x3d4, 0x40, par);
 731         vga_out8(0x3d5, reg->CR40, par);
 732         vga_out8(0x3d4, 0x42, par);
 733         vga_out8(0x3d5, reg->CR42, par);
 734         vga_out8(0x3d4, 0x45, par);
 735         vga_out8(0x3d5, reg->CR45, par);
 736         vga_out8(0x3d4, 0x50, par);
 737         vga_out8(0x3d5, reg->CR50, par);
 738         vga_out8(0x3d4, 0x51, par);
 739         vga_out8(0x3d5, reg->CR51, par);
 740         vga_out8(0x3d4, 0x53, par);
 741         vga_out8(0x3d5, reg->CR53, par);
 742         vga_out8(0x3d4, 0x58, par);
 743         vga_out8(0x3d5, reg->CR58, par);
 744         vga_out8(0x3d4, 0x60, par);
 745         vga_out8(0x3d5, reg->CR60, par);
 746         vga_out8(0x3d4, 0x66, par);
 747         vga_out8(0x3d5, reg->CR66, par);
 748         vga_out8(0x3d4, 0x67, par);
 749         vga_out8(0x3d5, reg->CR67, par);
 750         vga_out8(0x3d4, 0x68, par);
 751         vga_out8(0x3d5, reg->CR68, par);
 752         vga_out8(0x3d4, 0x69, par);
 753         vga_out8(0x3d5, reg->CR69, par);
 754         vga_out8(0x3d4, 0x6f, par);
 755         vga_out8(0x3d5, reg->CR6F, par);
 756
 757         vga_out8(0x3d4, 0x33, par);
 758         vga_out8(0x3d5, reg->CR33, par);
 759         vga_out8(0x3d4, 0x86, par);
 760         vga_out8(0x3d5, reg->CR86, par);
 761         vga_out8(0x3d4, 0x88, par);
 762         vga_out8(0x3d5, reg->CR88, par);
 763         vga_out8(0x3d4, 0x90, par);
 764         vga_out8(0x3d5, reg->CR90, par);
 765         vga_out8(0x3d4, 0x91, par);
 766         vga_out8(0x3d5, reg->CR91, par);
 767         vga_out8(0x3d4, 0xb0, par);
 768         vga_out8(0x3d5, reg->CRB0, par);
 769
 770         /* extended mode timing regs */
 771         vga_out8(0x3d4, 0x3b, par);
 772         vga_out8(0x3d5, reg->CR3B, par);
 773         vga_out8(0x3d4, 0x3c, par);
 774         vga_out8(0x3d5, reg->CR3C, par);
 775         vga_out8(0x3d4, 0x43, par);
 776         vga_out8(0x3d5, reg->CR43, par);
 777         vga_out8(0x3d4, 0x5d, par);
 778         vga_out8(0x3d5, reg->CR5D, par);
 779         vga_out8(0x3d4, 0x5e, par);
 780         vga_out8(0x3d5, reg->CR5E, par);
 781         vga_out8(0x3d4, 0x65, par);
 782         vga_out8(0x3d5, reg->CR65, par);
 783
 784         /* save seq extended regs for DCLK PLL programming */
 785         vga_out8(0x3c4, 0x0e, par);
 786         vga_out8(0x3c5, reg->SR0E, par);
 787         vga_out8(0x3c4, 0x0f, par);
 788         vga_out8(0x3c5, reg->SR0F, par);
 789         vga_out8(0x3c4, 0x10, par);
 790         vga_out8(0x3c5, reg->SR10, par);
 791         vga_out8(0x3c4, 0x11, par);
 792         vga_out8(0x3c5, reg->SR11, par);
 793         vga_out8(0x3c4, 0x12, par);
 794         vga_out8(0x3c5, reg->SR12, par);
 795         vga_out8(0x3c4, 0x13, par);
 796         vga_out8(0x3c5, reg->SR13, par);
 797         vga_out8(0x3c4, 0x29, par);
 798         vga_out8(0x3c5, reg->SR29, par);
 799
 800         vga_out8(0x3c4, 0x15, par);
 801         vga_out8(0x3c5, reg->SR15, par);
 802         vga_out8(0x3c4, 0x30, par);
 803         vga_out8(0x3c5, reg->SR30, par);
 804         vga_out8(0x3c4, 0x18, par);
 805         vga_out8(0x3c5, reg->SR18, par);
 806
 807         /* Save flat panel expansion regsters. */
 808         if (par->chip == S3_SAVAGE_MX) {
 809                 int i;
 810
 811                 for (i = 0; i < 8; i++) {
 812                         vga_out8(0x3c4, 0x54+i, par);
 813                         vga_out8(0x3c5, reg->SR54[i], par);
 814                 }
 815         }
 816
 817         vga_out8(0x3d4, 0x66, par);
 818         cr66 = vga_in8(0x3d5, par);
 819         vga_out8(0x3d5, cr66 | 0x80, par);
 820         vga_out8(0x3d4, 0x3a, par);
 821         cr3a = vga_in8(0x3d5, par);
 822         vga_out8(0x3d5, cr3a | 0x80, par);
 823
 824         /* now save MIU regs */
 825         if (par->chip != S3_SAVAGE_MX) {
 826                 savage_out32(FIFO_CONTROL_REG, reg->MMPR0, par);
 827                 savage_out32(MIU_CONTROL_REG, reg->MMPR1, par);
 828                 savage_out32(STREAMS_TIMEOUT_REG, reg->MMPR2, par);
 829                 savage_out32(MISC_TIMEOUT_REG, reg->MMPR3, par);
 830         }
 831
 832         vga_out8(0x3d4, 0x3a, par);
 833         vga_out8(0x3d5, cr3a, par);
 834         vga_out8(0x3d4, 0x66, par);
 835         vga_out8(0x3d5, cr66, par);
 836 }
 837
 838 static void savage_update_var(struct fb_var_screeninfo *var, struct fb_videomode *modedb)
 839 {
 840         var->xres = var->xres_virtual = modedb->xres;
 841         var->yres = modedb->yres;
 842         if (var->yres_virtual < var->yres)
 843             var->yres_virtual = var->yres;
 844         var->xoffset = var->yoffset = 0;
 845         var->pixclock = modedb->pixclock;
 846         var->left_margin = modedb->left_margin;
 847         var->right_margin = modedb->right_margin;
 848         var->upper_margin = modedb->upper_margin;
 849         var->lower_margin = modedb->lower_margin;
 850         var->hsync_len = modedb->hsync_len;
 851         var->vsync_len = modedb->vsync_len;
 852         var->sync = modedb->sync;
 853         var->vmode = modedb->vmode;
 854 }
 855
 856 static int savagefb_check_var(struct fb_var_screeninfo   *var,
 857                               struct fb_info *info)
 858 {
 859         struct savagefb_par *par = info->par;
 860         int memlen, vramlen, mode_valid = 0;
 861
 862         DBG("savagefb_check_var");
 863
 864         var->transp.offset = 0;
 865         var->transp.length = 0;
 866         switch (var->bits_per_pixel) {
 867         case 8:
 868                 var->red.offset = var->green.offset =
 869                         var->blue.offset = 0;
 870                 var->red.length = var->green.length =
 871                         var->blue.length = var->bits_per_pixel;
 872                 break;
 873         case 16:
 874                 var->red.offset = 11;
 875                 var->red.length = 5;
 876                 var->green.offset = 5;
 877                 var->green.length = 6;
 878                 var->blue.offset = 0;
 879                 var->blue.length = 5;
 880                 break;
 881         case 32:
 882                 var->transp.offset = 24;
 883                 var->transp.length = 8;
 884                 var->red.offset = 16;
 885                 var->red.length = 8;
 886                 var->green.offset = 8;
 887                 var->green.length = 8;
 888                 var->blue.offset = 0;
 889                 var->blue.length = 8;
 890                 break;
 891
 892         default:
 893                 return -EINVAL;
 894         }
 895
 896         if (!info->monspecs.hfmax || !info->monspecs.vfmax ||
 897             !info->monspecs.dclkmax || !fb_validate_mode(var, info))
 898                 mode_valid = 1;
 899
 900         /* calculate modeline if supported by monitor */
 901         if (!mode_valid && info->monspecs.gtf) {
 902                 if (!fb_get_mode(FB_MAXTIMINGS, 0, var, info))
 903                         mode_valid = 1;
 904         }
 905
 906         if (!mode_valid) {
 907                 struct fb_videomode *mode;
 908
 909                 mode = fb_find_best_mode(var, &info->modelist);
 910                 if (mode) {
 911                         savage_update_var(var, mode);
 912                         mode_valid = 1;
 913                 }
 914         }
 915
 916         if (!mode_valid && info->monspecs.modedb_len)
 917                 return -EINVAL;
 918
 919         /* Is the mode larger than the LCD panel? */
 920         if (par->SavagePanelWidth &&
 921             (var->xres > par->SavagePanelWidth ||
 922              var->yres > par->SavagePanelHeight)) {
 923                 printk(KERN_INFO "Mode (%dx%d) larger than the LCD panel "
 924                        "(%dx%d)\n", var->xres,  var->yres,
 925                        par->SavagePanelWidth,
 926                        par->SavagePanelHeight);
 927                 return -1;
 928         }
 929
 930         if (var->yres_virtual < var->yres)
 931                 var->yres_virtual = var->yres;
 932         if (var->xres_virtual < var->xres)
 933                 var->xres_virtual = var->xres;
 934
 935         vramlen = info->fix.smem_len;
 936
 937         memlen = var->xres_virtual * var->bits_per_pixel *
 938                 var->yres_virtual / 8;
 939         if (memlen > vramlen) {
 940                 var->yres_virtual = vramlen * 8 /
 941                         (var->xres_virtual * var->bits_per_pixel);
 942                 memlen = var->xres_virtual * var->bits_per_pixel *
 943                         var->yres_virtual / 8;
 944         }
 945
 946         /* we must round yres/xres down, we already rounded y/xres_virtual up
 947            if it was possible. We should return -EINVAL, but I disagree */
 948         if (var->yres_virtual < var->yres)
 949                 var->yres = var->yres_virtual;
 950         if (var->xres_virtual < var->xres)
 951                 var->xres = var->xres_virtual;
 952         if (var->xoffset + var->xres > var->xres_virtual)
 953                 var->xoffset = var->xres_virtual - var->xres;
 954         if (var->yoffset + var->yres > var->yres_virtual)
 955                 var->yoffset = var->yres_virtual - var->yres;
 956
 957         return 0;
 958 }
 959
 960
 961 static int savagefb_decode_var(struct fb_var_screeninfo   *var,
 962                                struct savagefb_par        *par,
 963                                struct savage_reg          *reg)
 964 {
 965         struct xtimings timings;
 966         int width, dclk, i, j; /*, refresh; */
 967         unsigned int m, n, r;
 968         unsigned char tmp = 0;
 969         unsigned int pixclock = var->pixclock;
 970
 971         DBG("savagefb_decode_var");
 972
 973         memset(&timings, 0, sizeof(timings));
 974
 975         if (!pixclock) pixclock = 10000;        /* 10ns = 100MHz */
 976         timings.Clock = 1000000000 / pixclock;
 977         if (timings.Clock < 1) timings.Clock = 1;
 978         timings.dblscan = var->vmode & FB_VMODE_DOUBLE;
 979         timings.interlaced = var->vmode & FB_VMODE_INTERLACED;
 980         timings.HDisplay = var->xres;
 981         timings.HSyncStart = timings.HDisplay + var->right_margin;
 982         timings.HSyncEnd = timings.HSyncStart + var->hsync_len;
 983         timings.HTotal = timings.HSyncEnd + var->left_margin;
 984         timings.VDisplay = var->yres;
 985         timings.VSyncStart = timings.VDisplay + var->lower_margin;
 986         timings.VSyncEnd = timings.VSyncStart + var->vsync_len;
 987         timings.VTotal = timings.VSyncEnd + var->upper_margin;
 988         timings.sync = var->sync;
 989
 990
 991         par->depth  = var->bits_per_pixel;
 992         par->vwidth = var->xres_virtual;
 993
 994         if (var->bits_per_pixel == 16  &&  par->chip == S3_SAVAGE3D) {
 995                 timings.HDisplay *= 2;
 996                 timings.HSyncStart *= 2;
 997                 timings.HSyncEnd *= 2;
 998                 timings.HTotal *= 2;
 999         }
1000
1001         /*
1002          * This will allocate the datastructure and initialize all of the
1003          * generic VGA registers.
1004          */
1005         vgaHWInit(var, par, &timings, reg);
1006
1007         /* We need to set CR67 whether or not we use the BIOS. */
1008
1009         dclk = timings.Clock;
1010         reg->CR67 = 0x00;
1011
1012         switch(var->bits_per_pixel) {
1013         case 8:
1014                 if ((par->chip == S3_SAVAGE2000) && (dclk >= 230000))
1015                         reg->CR67 = 0x10;       /* 8bpp, 2 pixels/clock */
1016                 else
1017                         reg->CR67 = 0x00;       /* 8bpp, 1 pixel/clock */
1018                 break;
1019         case 15:
1020                 if (S3_SAVAGE_MOBILE_SERIES(par->chip) ||
1021                     ((par->chip == S3_SAVAGE2000) && (dclk >= 230000)))
1022                         reg->CR67 = 0x30;       /* 15bpp, 2 pixel/clock */
1023                 else
1024                         reg->CR67 = 0x20;       /* 15bpp, 1 pixels/clock */
1025                 break;
1026         case 16:
1027                 if (S3_SAVAGE_MOBILE_SERIES(par->chip) ||
1028                    ((par->chip == S3_SAVAGE2000) && (dclk >= 230000)))
1029                         reg->CR67 = 0x50;       /* 16bpp, 2 pixel/clock */
1030                 else
1031                         reg->CR67 = 0x40;       /* 16bpp, 1 pixels/clock */
1032                 break;
1033         case 24:
1034                 reg->CR67 = 0x70;
1035                 break;
1036         case 32:
1037                 reg->CR67 = 0xd0;
1038                 break;
1039         }
1040
1041         /*
1042          * Either BIOS use is disabled, or we failed to find a suitable
1043          * match.  Fall back to traditional register-crunching.
1044          */
1045
1046         vga_out8(0x3d4, 0x3a, par);
1047         tmp = vga_in8(0x3d5, par);
1048         if (1 /*FIXME:psav->pci_burst*/)
1049                 reg->CR3A = (tmp & 0x7f) | 0x15;
1050         else
1051                 reg->CR3A = tmp | 0x95;
1052
1053         reg->CR53 = 0x00;
1054         reg->CR31 = 0x8c;
1055         reg->CR66 = 0x89;
1056
1057         vga_out8(0x3d4, 0x58, par);
1058         reg->CR58 = vga_in8(0x3d5, par) & 0x80;
1059         reg->CR58 |= 0x13;
1060
1061         reg->SR15 = 0x03 | 0x80;
1062         reg->SR18 = 0x00;
1063         reg->CR43 = reg->CR45 = reg->CR65 = 0x00;
1064
1065         vga_out8(0x3d4, 0x40, par);
1066         reg->CR40 = vga_in8(0x3d5, par) & ~0x01;
1067
1068         reg->MMPR0 = 0x010400;
1069         reg->MMPR1 = 0x00;
1070         reg->MMPR2 = 0x0808;
1071         reg->MMPR3 = 0x08080810;
1072
1073         SavageCalcClock(dclk, 1, 1, 127, 0, 4, 180000, 360000, &m, &n, &r);
1074         /* m = 107; n = 4; r = 2; */
1075
1076         if (par->MCLK <= 0) {
1077                 reg->SR10 = 255;
1078                 reg->SR11 = 255;
1079         } else {
1080                 common_calc_clock(par->MCLK, 1, 1, 31, 0, 3, 135000, 270000,
1081                                    &reg->SR11, &reg->SR10);
1082                 /*      reg->SR10 = 80; // MCLK == 286000 */
1083                 /*      reg->SR11 = 125; */
1084         }
1085
1086         reg->SR12 = (r << 6) | (n & 0x3f);
1087         reg->SR13 = m & 0xff;
1088         reg->SR29 = (r & 4) | (m & 0x100) >> 5 | (n & 0x40) >> 2;
1089
1090         if (var->bits_per_pixel < 24)
1091                 reg->MMPR0 -= 0x8000;
1092         else
1093                 reg->MMPR0 -= 0x4000;
1094
1095         if (timings.interlaced)
1096                 reg->CR42 = 0x20;
1097         else
1098                 reg->CR42 = 0x00;
1099
1100         reg->CR34 = 0x10; /* display fifo */
1101
1102         i = ((((timings.HTotal >> 3) - 5) & 0x100) >> 8) |
1103                 ((((timings.HDisplay >> 3) - 1) & 0x100) >> 7) |
1104                 ((((timings.HSyncStart >> 3) - 1) & 0x100) >> 6) |
1105                 ((timings.HSyncStart & 0x800) >> 7);
1106
1107         if ((timings.HSyncEnd >> 3) - (timings.HSyncStart >> 3) > 64)
1108                 i |= 0x08;
1109         if ((timings.HSyncEnd >> 3) - (timings.HSyncStart >> 3) > 32)
1110                 i |= 0x20;
1111
1112         j = (reg->CRTC[0] + ((i & 0x01) << 8) +
1113              reg->CRTC[4] + ((i & 0x10) << 4) + 1) / 2;
1114
1115         if (j - (reg->CRTC[4] + ((i & 0x10) << 4)) < 4) {
1116                 if (reg->CRTC[4] + ((i & 0x10) << 4) + 4 <=
1117                     reg->CRTC[0] + ((i & 0x01) << 8))
1118                         j = reg->CRTC[4] + ((i & 0x10) << 4) + 4;
1119                 else
1120                         j = reg->CRTC[0] + ((i & 0x01) << 8) + 1;
1121         }
1122
1123         reg->CR3B = j & 0xff;
1124         i |= (j & 0x100) >> 2;
1125         reg->CR3C = (reg->CRTC[0] + ((i & 0x01) << 8)) / 2;
1126         reg->CR5D = i;
1127         reg->CR5E = (((timings.VTotal - 2) & 0x400) >> 10) |
1128                 (((timings.VDisplay - 1) & 0x400) >> 9) |
1129                 (((timings.VSyncStart) & 0x400) >> 8) |
1130                 (((timings.VSyncStart) & 0x400) >> 6) | 0x40;
1131         width = (var->xres_virtual * ((var->bits_per_pixel+7) / 8)) >> 3;
1132         reg->CR91 = reg->CRTC[19] = 0xff & width;
1133         reg->CR51 = (0x300 & width) >> 4;
1134         reg->CR90 = 0x80 | (width >> 8);
1135         reg->MiscOutReg |= 0x0c;
1136
1137         /* Set frame buffer description. */
1138
1139         if (var->bits_per_pixel <= 8)
1140                 reg->CR50 = 0;
1141         else if (var->bits_per_pixel <= 16)
1142                 reg->CR50 = 0x10;
1143         else
1144                 reg->CR50 = 0x30;
1145
1146         if (var->xres_virtual <= 640)
1147                 reg->CR50 |= 0x40;
1148         else if (var->xres_virtual == 800)
1149                 reg->CR50 |= 0x80;
1150         else if (var->xres_virtual == 1024)
1151                 reg->CR50 |= 0x00;
1152         else if (var->xres_virtual == 1152)
1153                 reg->CR50 |= 0x01;
1154         else if (var->xres_virtual == 1280)
1155                 reg->CR50 |= 0xc0;
1156         else if (var->xres_virtual == 1600)
1157                 reg->CR50 |= 0x81;
1158         else
1159                 reg->CR50 |= 0xc1;      /* Use GBD */
1160
1161         if (par->chip == S3_SAVAGE2000)
1162                 reg->CR33 = 0x08;
1163         else
1164                 reg->CR33 = 0x20;
1165
1166         reg->CRTC[0x17] = 0xeb;
1167
1168         reg->CR67 |= 1;
1169
1170         vga_out8(0x3d4, 0x36, par);
1171         reg->CR36 = vga_in8(0x3d5, par);
1172         vga_out8(0x3d4, 0x68, par);
1173         reg->CR68 = vga_in8(0x3d5, par);
1174         reg->CR69 = 0;
1175         vga_out8(0x3d4, 0x6f, par);
1176         reg->CR6F = vga_in8(0x3d5, par);
1177         vga_out8(0x3d4, 0x86, par);
1178         reg->CR86 = vga_in8(0x3d5, par);
1179         vga_out8(0x3d4, 0x88, par);
1180         reg->CR88 = vga_in8(0x3d5, par) | 0x08;
1181         vga_out8(0x3d4, 0xb0, par);
1182         reg->CRB0 = vga_in8(0x3d5, par) | 0x80;
1183
1184         return 0;
1185 }
1186
1187 /* --------------------------------------------------------------------- */
1188
1189 /*
1190  *    Set a single color register. Return != 0 for invalid regno.
1191  */
1192 static int savagefb_setcolreg(unsigned        regno,
1193                               unsigned        red,
1194                               unsigned        green,
1195                               unsigned        blue,
1196                               unsigned        transp,
1197                               struct fb_info *info)
1198 {
1199         struct savagefb_par *par = info->par;
1200
1201         if (regno >= NR_PALETTE)
1202                 return -EINVAL;
1203
1204         par->palette[regno].red    = red;
1205         par->palette[regno].green  = green;
1206         par->palette[regno].blue   = blue;
1207         par->palette[regno].transp = transp;
1208
1209         switch (info->var.bits_per_pixel) {
1210         case 8:
1211                 vga_out8(0x3c8, regno, par);
1212
1213                 vga_out8(0x3c9, red   >> 10, par);
1214                 vga_out8(0x3c9, green >> 10, par);
1215                 vga_out8(0x3c9, blue  >> 10, par);
1216                 break;
1217
1218         case 16:
1219                 if (regno < 16)
1220                         ((u32 *)info->pseudo_palette)[regno] =
1221                                 ((red   & 0xf800)      ) |
1222                                 ((green & 0xfc00) >>  5) |
1223                                 ((blue  & 0xf800) >> 11);
1224                 break;
1225
1226         case 24:
1227                 if (regno < 16)
1228                         ((u32 *)info->pseudo_palette)[regno] =
1229                                 ((red    & 0xff00) <<  8) |
1230                                 ((green  & 0xff00)      ) |
1231                                 ((blue   & 0xff00) >>  8);
1232                 break;
1233         case 32:
1234                 if (regno < 16)
1235                         ((u32 *)info->pseudo_palette)[regno] =
1236                                 ((transp & 0xff00) << 16) |
1237                                 ((red    & 0xff00) <<  8) |
1238                                 ((green  & 0xff00)      ) |
1239                                 ((blue   & 0xff00) >>  8);
1240                 break;
1241
1242         default:
1243                 return 1;
1244         }
1245
1246         return 0;
1247 }
1248
1249 static void savagefb_set_par_int(struct savagefb_par  *par, struct savage_reg *reg)
1250 {
1251         unsigned char tmp, cr3a, cr66, cr67;
1252
1253         DBG("savagefb_set_par_int");
1254
1255         par->SavageWaitIdle(par);
1256
1257         vga_out8(0x3c2, 0x23, par);
1258
1259         vga_out16(0x3d4, 0x4838, par);
1260         vga_out16(0x3d4, 0xa539, par);
1261         vga_out16(0x3c4, 0x0608, par);
1262
1263         vgaHWProtect(par, 1);
1264
1265         /*
1266          * Some Savage/MX and /IX systems go nuts when trying to exit the
1267          * server after WindowMaker has displayed a gradient background.  I
1268          * haven't been able to find what causes it, but a non-destructive
1269          * switch to mode 3 here seems to eliminate the issue.
1270          */
1271
1272         VerticalRetraceWait(par);
1273         vga_out8(0x3d4, 0x67, par);
1274         cr67 = vga_in8(0x3d5, par);
1275         vga_out8(0x3d5, cr67/*par->CR67*/ & ~0x0c, par); /* no STREAMS yet */
1276
1277         vga_out8(0x3d4, 0x23, par);
1278         vga_out8(0x3d5, 0x00, par);
1279         vga_out8(0x3d4, 0x26, par);
1280         vga_out8(0x3d5, 0x00, par);
1281
1282         /* restore extended regs */
1283         vga_out8(0x3d4, 0x66, par);
1284         vga_out8(0x3d5, reg->CR66, par);
1285         vga_out8(0x3d4, 0x3a, par);
1286         vga_out8(0x3d5, reg->CR3A, par);
1287         vga_out8(0x3d4, 0x31, par);
1288         vga_out8(0x3d5, reg->CR31, par);
1289         vga_out8(0x3d4, 0x32, par);
1290         vga_out8(0x3d5, reg->CR32, par);
1291         vga_out8(0x3d4, 0x58, par);
1292         vga_out8(0x3d5, reg->CR58, par);
1293         vga_out8(0x3d4, 0x53, par);
1294         vga_out8(0x3d5, reg->CR53 & 0x7f, par);
1295
1296         vga_out16(0x3c4, 0x0608, par);
1297
1298         /* Restore DCLK registers. */
1299
1300         vga_out8(0x3c4, 0x0e, par);
1301         vga_out8(0x3c5, reg->SR0E, par);
1302         vga_out8(0x3c4, 0x0f, par);
1303         vga_out8(0x3c5, reg->SR0F, par);
1304         vga_out8(0x3c4, 0x29, par);
1305         vga_out8(0x3c5, reg->SR29, par);
1306         vga_out8(0x3c4, 0x15, par);
1307         vga_out8(0x3c5, reg->SR15, par);
1308
1309         /* Restore flat panel expansion regsters. */
1310         if (par->chip == S3_SAVAGE_MX) {
1311                 int i;
1312
1313                 for (i = 0; i < 8; i++) {
1314                         vga_out8(0x3c4, 0x54+i, par);
1315                         vga_out8(0x3c5, reg->SR54[i], par);
1316                 }
1317         }
1318
1319         vgaHWRestore (par, reg);
1320
1321         /* extended mode timing registers */
1322         vga_out8(0x3d4, 0x53, par);
1323         vga_out8(0x3d5, reg->CR53, par);
1324         vga_out8(0x3d4, 0x5d, par);
1325         vga_out8(0x3d5, reg->CR5D, par);
1326         vga_out8(0x3d4, 0x5e, par);
1327         vga_out8(0x3d5, reg->CR5E, par);
1328         vga_out8(0x3d4, 0x3b, par);
1329         vga_out8(0x3d5, reg->CR3B, par);
1330         vga_out8(0x3d4, 0x3c, par);
1331         vga_out8(0x3d5, reg->CR3C, par);
1332         vga_out8(0x3d4, 0x43, par);
1333         vga_out8(0x3d5, reg->CR43, par);
1334         vga_out8(0x3d4, 0x65, par);
1335         vga_out8(0x3d5, reg->CR65, par);
1336
1337         /* restore the desired video mode with cr67 */
1338         vga_out8(0x3d4, 0x67, par);
1339         /* following part not present in X11 driver */
1340         cr67 = vga_in8(0x3d5, par) & 0xf;
1341         vga_out8(0x3d5, 0x50 | cr67, par);
1342         udelay(10000);
1343         vga_out8(0x3d4, 0x67, par);
1344         /* end of part */
1345         vga_out8(0x3d5, reg->CR67 & ~0x0c, par);
1346
1347         /* other mode timing and extended regs */
1348         vga_out8(0x3d4, 0x34, par);
1349         vga_out8(0x3d5, reg->CR34, par);
1350         vga_out8(0x3d4, 0x40, par);
1351         vga_out8(0x3d5, reg->CR40, par);
1352         vga_out8(0x3d4, 0x42, par);
1353         vga_out8(0x3d5, reg->CR42, par);
1354         vga_out8(0x3d4, 0x45, par);
1355         vga_out8(0x3d5, reg->CR45, par);
1356         vga_out8(0x3d4, 0x50, par);
1357         vga_out8(0x3d5, reg->CR50, par);
1358         vga_out8(0x3d4, 0x51, par);
1359         vga_out8(0x3d5, reg->CR51, par);
1360
1361         /* memory timings */
1362         vga_out8(0x3d4, 0x36, par);
1363         vga_out8(0x3d5, reg->CR36, par);
1364         vga_out8(0x3d4, 0x60, par);
1365         vga_out8(0x3d5, reg->CR60, par);
1366         vga_out8(0x3d4, 0x68, par);
1367         vga_out8(0x3d5, reg->CR68, par);
1368         vga_out8(0x3d4, 0x69, par);
1369         vga_out8(0x3d5, reg->CR69, par);
1370         vga_out8(0x3d4, 0x6f, par);
1371         vga_out8(0x3d5, reg->CR6F, par);
1372
1373         vga_out8(0x3d4, 0x33, par);
1374         vga_out8(0x3d5, reg->CR33, par);
1375         vga_out8(0x3d4, 0x86, par);
1376         vga_out8(0x3d5, reg->CR86, par);
1377         vga_out8(0x3d4, 0x88, par);
1378         vga_out8(0x3d5, reg->CR88, par);
1379         vga_out8(0x3d4, 0x90, par);
1380         vga_out8(0x3d5, reg->CR90, par);
1381         vga_out8(0x3d4, 0x91, par);
1382         vga_out8(0x3d5, reg->CR91, par);
1383
1384         if (par->chip == S3_SAVAGE4) {
1385                 vga_out8(0x3d4, 0xb0, par);
1386                 vga_out8(0x3d5, reg->CRB0, par);
1387         }
1388
1389         vga_out8(0x3d4, 0x32, par);
1390         vga_out8(0x3d5, reg->CR32, par);
1391
1392         /* unlock extended seq regs */
1393         vga_out8(0x3c4, 0x08, par);
1394         vga_out8(0x3c5, 0x06, par);
1395
1396         /* Restore extended sequencer regs for MCLK. SR10 == 255 indicates
1397          * that we should leave the default SR10 and SR11 values there.
1398          */
1399         if (reg->SR10 != 255) {
1400                 vga_out8(0x3c4, 0x10, par);
1401                 vga_out8(0x3c5, reg->SR10, par);
1402                 vga_out8(0x3c4, 0x11, par);
1403                 vga_out8(0x3c5, reg->SR11, par);
1404         }
1405
1406         /* restore extended seq regs for dclk */
1407         vga_out8(0x3c4, 0x0e, par);
1408         vga_out8(0x3c5, reg->SR0E, par);
1409         vga_out8(0x3c4, 0x0f, par);
1410         vga_out8(0x3c5, reg->SR0F, par);
1411         vga_out8(0x3c4, 0x12, par);
1412         vga_out8(0x3c5, reg->SR12, par);
1413         vga_out8(0x3c4, 0x13, par);
1414         vga_out8(0x3c5, reg->SR13, par);
1415         vga_out8(0x3c4, 0x29, par);
1416         vga_out8(0x3c5, reg->SR29, par);
1417         vga_out8(0x3c4, 0x18, par);
1418         vga_out8(0x3c5, reg->SR18, par);
1419
1420         /* load new m, n pll values for dclk & mclk */
1421         vga_out8(0x3c4, 0x15, par);
1422         tmp = vga_in8(0x3c5, par) & ~0x21;
1423
1424         vga_out8(0x3c5, tmp | 0x03, par);
1425         vga_out8(0x3c5, tmp | 0x23, par);
1426         vga_out8(0x3c5, tmp | 0x03, par);
1427         vga_out8(0x3c5, reg->SR15, par);
1428         udelay(100);
1429
1430         vga_out8(0x3c4, 0x30, par);
1431         vga_out8(0x3c5, reg->SR30, par);
1432         vga_out8(0x3c4, 0x08, par);
1433         vga_out8(0x3c5, reg->SR08, par);
1434
1435         /* now write out cr67 in full, possibly starting STREAMS */
1436         VerticalRetraceWait(par);
1437         vga_out8(0x3d4, 0x67, par);
1438         vga_out8(0x3d5, reg->CR67, par);
1439
1440         vga_out8(0x3d4, 0x66, par);
1441         cr66 = vga_in8(0x3d5, par);
1442         vga_out8(0x3d5, cr66 | 0x80, par);
1443         vga_out8(0x3d4, 0x3a, par);
1444         cr3a = vga_in8(0x3d5, par);
1445         vga_out8(0x3d5, cr3a | 0x80, par);
1446
1447         if (par->chip != S3_SAVAGE_MX) {
1448                 VerticalRetraceWait(par);
1449                 savage_out32(FIFO_CONTROL_REG, reg->MMPR0, par);
1450                 par->SavageWaitIdle(par);
1451                 savage_out32(MIU_CONTROL_REG, reg->MMPR1, par);
1452                 par->SavageWaitIdle(par);
1453                 savage_out32(STREAMS_TIMEOUT_REG, reg->MMPR2, par);
1454                 par->SavageWaitIdle(par);
1455                 savage_out32(MISC_TIMEOUT_REG, reg->MMPR3, par);
1456         }
1457
1458         vga_out8(0x3d4, 0x66, par);
1459         vga_out8(0x3d5, cr66, par);
1460         vga_out8(0x3d4, 0x3a, par);
1461         vga_out8(0x3d5, cr3a, par);
1462
1463         SavageSetup2DEngine(par);
1464         vgaHWProtect(par, 0);
1465 }
1466
1467 static void savagefb_update_start(struct savagefb_par      *par,
1468                                   struct fb_var_screeninfo *var)
1469 {
1470         int base;
1471
1472         base = ((var->yoffset * var->xres_virtual + (var->xoffset & ~1))
1473                 * ((var->bits_per_pixel+7) / 8)) >> 2;
1474
1475         /* now program the start address registers */
1476         vga_out16(0x3d4, (base & 0x00ff00) | 0x0c, par);
1477         vga_out16(0x3d4, ((base & 0x00ff) << 8) | 0x0d, par);
1478         vga_out8(0x3d4, 0x69, par);
1479         vga_out8(0x3d5, (base & 0x7f0000) >> 16, par);
1480 }
1481
1482
1483 static void savagefb_set_fix(struct fb_info *info)
1484 {
1485         info->fix.line_length = info->var.xres_virtual *
1486                 info->var.bits_per_pixel / 8;
1487
1488         if (info->var.bits_per_pixel == 8) {
1489                 info->fix.visual      = FB_VISUAL_PSEUDOCOLOR;
1490                 info->fix.xpanstep    = 4;
1491         } else {
1492                 info->fix.visual      = FB_VISUAL_TRUECOLOR;
1493                 info->fix.xpanstep    = 2;
1494         }
1495
1496 }
1497
1498 static int savagefb_set_par(struct fb_info *info)
1499 {
1500         struct savagefb_par *par = info->par;
1501         struct fb_var_screeninfo *var = &info->var;
1502         int err;
1503
1504         DBG("savagefb_set_par");
1505         err = savagefb_decode_var(var, par, &par->state);
1506         if (err)
1507                 return err;
1508
1509         if (par->dacSpeedBpp <= 0) {
1510                 if (var->bits_per_pixel > 24)
1511                         par->dacSpeedBpp = par->clock[3];
1512                 else if (var->bits_per_pixel >= 24)
1513                         par->dacSpeedBpp = par->clock[2];
1514                 else if ((var->bits_per_pixel > 8) && (var->bits_per_pixel < 24))
1515                         par->dacSpeedBpp = par->clock[1];
1516                 else if (var->bits_per_pixel <= 8)
1517                         par->dacSpeedBpp = par->clock[0];
1518         }
1519
1520         /* Set ramdac limits */
1521         par->maxClock = par->dacSpeedBpp;
1522         par->minClock = 10000;
1523
1524         savagefb_set_par_int(par, &par->state);
1525         fb_set_cmap(&info->cmap, info);
1526         savagefb_set_fix(info);
1527         savagefb_set_clip(info);
1528
1529         SavagePrintRegs();
1530         return 0;
1531 }
1532
1533 /*
1534  *    Pan or Wrap the Display
1535  */
1536 static int savagefb_pan_display(struct fb_var_screeninfo *var,
1537                                 struct fb_info           *info)
1538 {
1539         struct savagefb_par *par = info->par;
1540
1541         savagefb_update_start(par, var);
1542         return 0;
1543 }
1544
1545 static int savagefb_blank(int blank, struct fb_info *info)
1546 {
1547         struct savagefb_par *par = info->par;
1548         u8 sr8 = 0, srd = 0;
1549
1550         if (par->display_type == DISP_CRT) {
1551                 vga_out8(0x3c4, 0x08, par);
1552                 sr8 = vga_in8(0x3c5, par);
1553                 sr8 |= 0x06;
1554                 vga_out8(0x3c5, sr8, par);
1555                 vga_out8(0x3c4, 0x0d, par);
1556                 srd = vga_in8(0x3c5, par);
1557                 srd &= 0x03;
1558
1559                 switch (blank) {
1560                 case FB_BLANK_UNBLANK:
1561                 case FB_BLANK_NORMAL:
1562                         break;
1563                 case FB_BLANK_VSYNC_SUSPEND:
1564                         srd |= 0x10;
1565                         break;
1566                 case FB_BLANK_HSYNC_SUSPEND:
1567                         srd |= 0x40;
1568                         break;
1569                 case FB_BLANK_POWERDOWN:
1570                         srd |= 0x50;
1571                         break;
1572                 }
1573
1574                 vga_out8(0x3c4, 0x0d, par);
1575                 vga_out8(0x3c5, srd, par);
1576         }
1577
1578         if (par->display_type == DISP_LCD ||
1579             par->display_type == DISP_DFP) {
1580                 switch(blank) {
1581                 case FB_BLANK_UNBLANK:
1582                 case FB_BLANK_NORMAL:
1583                         vga_out8(0x3c4, 0x31, par); /* SR31 bit 4 - FP enable */
1584                         vga_out8(0x3c5, vga_in8(0x3c5, par) | 0x10, par);
1585                         break;
1586                 case FB_BLANK_VSYNC_SUSPEND:
1587                 case FB_BLANK_HSYNC_SUSPEND:
1588                 case FB_BLANK_POWERDOWN:
1589                         vga_out8(0x3c4, 0x31, par); /* SR31 bit 4 - FP enable */
1590                         vga_out8(0x3c5, vga_in8(0x3c5, par) & ~0x10, par);
1591                         break;
1592                 }
1593         }
1594
1595         return (blank == FB_BLANK_NORMAL) ? 1 : 0;
1596 }
1597
1598 static void savagefb_save_state(struct fb_info *info)
1599 {
1600         struct savagefb_par *par = info->par;
1601
1602         savage_get_default_par(par, &par->save);
1603 }
1604
1605 static void savagefb_restore_state(struct fb_info *info)
1606 {
1607         struct savagefb_par *par = info->par;
1608
1609         savagefb_blank(FB_BLANK_POWERDOWN, info);
1610         savage_set_default_par(par, &par->save);
1611         savagefb_blank(FB_BLANK_UNBLANK, info);
1612 }
1613
1614 static struct fb_ops savagefb_ops = {
1615         .owner          = THIS_MODULE,
1616         .fb_check_var   = savagefb_check_var,
1617         .fb_set_par     = savagefb_set_par,
1618         .fb_setcolreg   = savagefb_setcolreg,
1619         .fb_pan_display = savagefb_pan_display,
1620         .fb_blank       = savagefb_blank,
1621         .fb_save_state  = savagefb_save_state,
1622         .fb_restore_state = savagefb_restore_state,
1623 #if defined(CONFIG_FB_SAVAGE_ACCEL)
1624         .fb_fillrect    = savagefb_fillrect,
1625         .fb_copyarea    = savagefb_copyarea,
1626         .fb_imageblit   = savagefb_imageblit,
1627         .fb_sync        = savagefb_sync,
1628 #else
1629         .fb_fillrect    = cfb_fillrect,
1630         .fb_copyarea    = cfb_copyarea,
1631         .fb_imageblit   = cfb_imageblit,
1632 #endif
1633 };
1634
1635 /* --------------------------------------------------------------------- */
1636
1637 static struct fb_var_screeninfo __devinitdata savagefb_var800x600x8 = {
1638         .accel_flags =  FB_ACCELF_TEXT,
1639         .xres =         800,
1640         .yres =         600,
1641         .xres_virtual =  800,
1642         .yres_virtual =  600,
1643         .bits_per_pixel = 8,
1644         .pixclock =     25000,
1645         .left_margin =  88,
1646         .right_margin = 40,
1647         .upper_margin = 23,
1648         .lower_margin = 1,
1649         .hsync_len =    128,
1650         .vsync_len =    4,
1651         .sync =         FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
1652         .vmode =        FB_VMODE_NONINTERLACED
1653 };
1654
1655 static void savage_enable_mmio(struct savagefb_par *par)
1656 {
1657         unsigned char val;
1658
1659         DBG("savage_enable_mmio\n");
1660
1661         val = vga_in8(0x3c3, par);
1662         vga_out8(0x3c3, val | 0x01, par);
1663         val = vga_in8(0x3cc, par);
1664         vga_out8(0x3c2, val | 0x01, par);
1665
1666         if (par->chip >= S3_SAVAGE4) {
1667                 vga_out8(0x3d4, 0x40, par);
1668                 val = vga_in8(0x3d5, par);
1669                 vga_out8(0x3d5, val | 1, par);
1670         }
1671 }
1672
1673
1674 static void savage_disable_mmio(struct savagefb_par *par)
1675 {
1676         unsigned char val;
1677
1678         DBG("savage_disable_mmio\n");
1679
1680         if (par->chip >= S3_SAVAGE4) {
1681                 vga_out8(0x3d4, 0x40, par);
1682                 val = vga_in8(0x3d5, par);
1683                 vga_out8(0x3d5, val | 1, par);
1684         }
1685 }
1686
1687
1688 static int __devinit savage_map_mmio(struct fb_info *info)
1689 {
1690         struct savagefb_par *par = info->par;
1691         DBG("savage_map_mmio");
1692
1693         if (S3_SAVAGE3D_SERIES(par->chip))
1694                 par->mmio.pbase = pci_resource_start(par->pcidev, 0) +
1695                         SAVAGE_NEWMMIO_REGBASE_S3;
1696         else
1697                 par->mmio.pbase = pci_resource_start(par->pcidev, 0) +
1698                         SAVAGE_NEWMMIO_REGBASE_S4;
1699
1700         par->mmio.len = SAVAGE_NEWMMIO_REGSIZE;
1701
1702         par->mmio.vbase = ioremap(par->mmio.pbase, par->mmio.len);
1703         if (!par->mmio.vbase) {
1704                 printk("savagefb: unable to map memory mapped IO\n");
1705                 return -ENOMEM;
1706         } else
1707                 printk(KERN_INFO "savagefb: mapped io at %p\n",
1708                         par->mmio.vbase);
1709
1710         info->fix.mmio_start = par->mmio.pbase;
1711         info->fix.mmio_len   = par->mmio.len;
1712
1713         par->bci_base = (u32 __iomem *)(par->mmio.vbase + BCI_BUFFER_OFFSET);
1714         par->bci_ptr  = 0;
1715
1716         savage_enable_mmio(par);
1717
1718         return 0;
1719 }
1720
1721 static void savage_unmap_mmio(struct fb_info *info)
1722 {
1723         struct savagefb_par *par = info->par;
1724         DBG("savage_unmap_mmio");
1725
1726         savage_disable_mmio(par);
1727
1728         if (par->mmio.vbase) {
1729                 iounmap(par->mmio.vbase);
1730                 par->mmio.vbase = NULL;
1731         }
1732 }
1733
1734 static int __devinit savage_map_video(struct fb_info *info,
1735                                       int video_len)
1736 {
1737         struct savagefb_par *par = info->par;
1738         int resource;
1739
1740         DBG("savage_map_video");
1741
1742         if (S3_SAVAGE3D_SERIES(par->chip))
1743                 resource = 0;
1744         else
1745                 resource = 1;
1746
1747         par->video.pbase = pci_resource_start(par->pcidev, resource);
1748         par->video.len   = video_len;
1749         par->video.vbase = ioremap(par->video.pbase, par->video.len);
1750
1751         if (!par->video.vbase) {
1752                 printk("savagefb: unable to map screen memory\n");
1753                 return -ENOMEM;
1754         } else
1755                 printk(KERN_INFO "savagefb: mapped framebuffer at %p, "
1756                        "pbase == %x\n", par->video.vbase, par->video.pbase);
1757
1758         info->fix.smem_start = par->video.pbase;
1759         info->fix.smem_len   = par->video.len - par->cob_size;
1760         info->screen_base    = par->video.vbase;
1761
1762 #ifdef CONFIG_MTRR
1763         par->video.mtrr = mtrr_add(par->video.pbase, video_len,
1764                                    MTRR_TYPE_WRCOMB, 1);
1765 #endif
1766
1767         /* Clear framebuffer, it's all white in memory after boot */
1768         memset_io(par->video.vbase, 0, par->video.len);
1769
1770         return 0;
1771 }
1772
1773 static void savage_unmap_video(struct fb_info *info)
1774 {
1775         struct savagefb_par *par = info->par;
1776
1777         DBG("savage_unmap_video");
1778
1779         if (par->video.vbase) {
1780 #ifdef CONFIG_MTRR
1781                 mtrr_del(par->video.mtrr, par->video.pbase, par->video.len);
1782 #endif
1783
1784                 iounmap(par->video.vbase);
1785                 par->video.vbase = NULL;
1786                 info->screen_base = NULL;
1787         }
1788 }
1789
1790 static int savage_init_hw(struct savagefb_par *par)
1791 {
1792         unsigned char config1, m, n, n1, n2, sr8, cr3f, cr66 = 0, tmp;
1793
1794         static unsigned char RamSavage3D[] = { 8, 4, 4, 2 };
1795         static unsigned char RamSavage4[] =  { 2, 4, 8, 12, 16, 32, 64, 32 };
1796         static unsigned char RamSavageMX[] = { 2, 8, 4, 16, 8, 16, 4, 16 };
1797         static unsigned char RamSavageNB[] = { 0, 2, 4, 8, 16, 32, 2, 2 };
1798         int videoRam, videoRambytes, dvi;
1799
1800         DBG("savage_init_hw");
1801
1802         /* unprotect CRTC[0-7] */
1803         vga_out8(0x3d4, 0x11, par);
1804         tmp = vga_in8(0x3d5, par);
1805         vga_out8(0x3d5, tmp & 0x7f, par);
1806
1807         /* unlock extended regs */
1808         vga_out16(0x3d4, 0x4838, par);
1809         vga_out16(0x3d4, 0xa039, par);
1810         vga_out16(0x3c4, 0x0608, par);
1811
1812         vga_out8(0x3d4, 0x40, par);
1813         tmp = vga_in8(0x3d5, par);
1814         vga_out8(0x3d5, tmp & ~0x01, par);
1815
1816         /* unlock sys regs */
1817         vga_out8(0x3d4, 0x38, par);
1818         vga_out8(0x3d5, 0x48, par);
1819
1820         /* Unlock system registers. */
1821         vga_out16(0x3d4, 0x4838, par);
1822
1823         /* Next go on to detect amount of installed ram */
1824
1825         vga_out8(0x3d4, 0x36, par);            /* for register CR36 (CONFG_REG1), */
1826         config1 = vga_in8(0x3d5, par);    /* get amount of vram installed */
1827
1828         /* Compute the amount of video memory and offscreen memory. */
1829
1830         switch  (par->chip) {
1831         case S3_SAVAGE3D:
1832                 videoRam = RamSavage3D[(config1 & 0xC0) >> 6 ] * 1024;
1833                 break;
1834
1835         case S3_SAVAGE4:
1836                 /*
1837                  * The Savage4 has one ugly special case to consider.  On
1838                  * systems with 4 banks of 2Mx32 SDRAM, the BIOS says 4MB
1839                  * when it really means 8MB.  Why do it the same when you
1840                  * can do it different...
1841                  */
1842                 vga_out8(0x3d4, 0x68, par);     /* memory control 1 */
1843                 if ((vga_in8(0x3d5, par) & 0xC0) == (0x01 << 6))
1844                         RamSavage4[1] = 8;
1845
1846                 /*FALLTHROUGH*/
1847
1848         case S3_SAVAGE2000:
1849                 videoRam = RamSavage4[(config1 & 0xE0) >> 5] * 1024;
1850                 break;
1851
1852         case S3_SAVAGE_MX:
1853         case S3_SUPERSAVAGE:
1854                 videoRam = RamSavageMX[(config1 & 0x0E) >> 1] * 1024;
1855                 break;
1856
1857         case S3_PROSAVAGE:
1858                 videoRam = RamSavageNB[(config1 & 0xE0) >> 5] * 1024;
1859                 break;
1860
1861         default:
1862                 /* How did we get here? */
1863                 videoRam = 0;
1864                 break;
1865         }
1866
1867         videoRambytes = videoRam * 1024;
1868
1869         printk(KERN_INFO "savagefb: probed videoram:  %dk\n", videoRam);
1870
1871         /* reset graphics engine to avoid memory corruption */
1872         vga_out8(0x3d4, 0x66, par);
1873         cr66 = vga_in8(0x3d5, par);
1874         vga_out8(0x3d5, cr66 | 0x02, par);
1875         udelay(10000);
1876
1877         vga_out8(0x3d4, 0x66, par);
1878         vga_out8(0x3d5, cr66 & ~0x02, par);     /* clear reset flag */
1879         udelay(10000);
1880
1881
1882         /*
1883          * reset memory interface, 3D engine, AGP master, PCI master,
1884          * master engine unit, motion compensation/LPB
1885          */
1886         vga_out8(0x3d4, 0x3f, par);
1887         cr3f = vga_in8(0x3d5, par);
1888         vga_out8(0x3d5, cr3f | 0x08, par);
1889         udelay(10000);
1890
1891         vga_out8(0x3d4, 0x3f, par);
1892         vga_out8(0x3d5, cr3f & ~0x08, par);     /* clear reset flags */
1893         udelay(10000);
1894
1895         /* Savage ramdac speeds */
1896         par->numClocks = 4;
1897         par->clock[0] = 250000;
1898         par->clock[1] = 250000;
1899         par->clock[2] = 220000;
1900         par->clock[3] = 220000;
1901
1902         /* detect current mclk */
1903         vga_out8(0x3c4, 0x08, par);
1904         sr8 = vga_in8(0x3c5, par);
1905         vga_out8(0x3c5, 0x06, par);
1906         vga_out8(0x3c4, 0x10, par);
1907         n = vga_in8(0x3c5, par);
1908         vga_out8(0x3c4, 0x11, par);
1909         m = vga_in8(0x3c5, par);
1910         vga_out8(0x3c4, 0x08, par);
1911         vga_out8(0x3c5, sr8, par);
1912         m &= 0x7f;
1913         n1 = n & 0x1f;
1914         n2 = (n >> 5) & 0x03;
1915         par->MCLK = ((1431818 * (m+2)) / (n1+2) / (1 << n2) + 50) / 100;
1916         printk(KERN_INFO "savagefb: Detected current MCLK value of %d kHz\n",
1917                 par->MCLK);
1918
1919         /* check for DVI/flat panel */
1920         dvi = 0;
1921
1922         if (par->chip == S3_SAVAGE4) {
1923                 unsigned char sr30 = 0x00;
1924
1925                 vga_out8(0x3c4, 0x30, par);
1926                 /* clear bit 1 */
1927                 vga_out8(0x3c5, vga_in8(0x3c5, par) & ~0x02, par);
1928                 sr30 = vga_in8(0x3c5, par);
1929                 if (sr30 & 0x02 /*0x04 */) {
1930                         dvi = 1;
1931                         printk("savagefb: Digital Flat Panel Detected\n");
1932                 }
1933         }
1934
1935         if (S3_SAVAGE_MOBILE_SERIES(par->chip) && !par->crtonly)
1936                 par->display_type = DISP_LCD;
1937         else if (dvi || (par->chip == S3_SAVAGE4 && par->dvi))
1938                 par->display_type = DISP_DFP;
1939         else
1940                 par->display_type = DISP_CRT;
1941
1942         /* Check LCD panel parrmation */
1943
1944         if (par->display_type == DISP_LCD) {
1945                 unsigned char cr6b = VGArCR(0x6b, par);
1946
1947                 int panelX = (VGArSEQ(0x61, par) +
1948                               ((VGArSEQ(0x66, par) & 0x02) << 7) + 1) * 8;
1949                 int panelY = (VGArSEQ(0x69, par) +
1950                               ((VGArSEQ(0x6e, par) & 0x70) << 4) + 1);
1951
1952                 char * sTechnology = "Unknown";
1953
1954                 /* OK, I admit it.  I don't know how to limit the max dot clock
1955                  * for LCD panels of various sizes.  I thought I copied the
1956                  * formula from the BIOS, but many users have parrmed me of
1957                  * my folly.
1958                  *
1959                  * Instead, I'll abandon any attempt to automatically limit the
1960                  * clock, and add an LCDClock option to XF86Config.  Some day,
1961                  * I should come back to this.
1962                  */
1963
1964                 enum ACTIVE_DISPLAYS { /* These are the bits in CR6B */
1965                         ActiveCRT = 0x01,
1966                         ActiveLCD = 0x02,
1967                         ActiveTV = 0x04,
1968                         ActiveCRT2 = 0x20,
1969                         ActiveDUO = 0x80
1970                 };
1971
1972                 if ((VGArSEQ(0x39, par) & 0x03) == 0) {
1973                         sTechnology = "TFT";
1974                 } else if ((VGArSEQ(0x30, par) & 0x01) == 0) {
1975                         sTechnology = "DSTN";
1976                 } else  {
1977                         sTechnology = "STN";
1978                 }
1979
1980                 printk(KERN_INFO "savagefb: %dx%d %s LCD panel detected %s\n",
1981                        panelX, panelY, sTechnology,
1982                        cr6b & ActiveLCD ? "and active" : "but not active");
1983
1984                 if (cr6b & ActiveLCD)   {
1985                         /*
1986                          * If the LCD is active and panel expansion is enabled,
1987                          * we probably want to kill the HW cursor.
1988                          */
1989
1990                         printk(KERN_INFO "savagefb: Limiting video mode to "
1991                                 "%dx%d\n", panelX, panelY);
1992
1993                         par->SavagePanelWidth = panelX;
1994                         par->SavagePanelHeight = panelY;
1995
1996                 } else
1997                         par->display_type = DISP_CRT;
1998         }
1999
2000         savage_get_default_par(par, &par->state);
2001         par->save = par->state;
2002
2003         if (S3_SAVAGE4_SERIES(par->chip)) {
2004                 /*
2005                  * The Savage4 and ProSavage have COB coherency bugs which
2006                  * render the buffer useless.  We disable it.
2007                  */
2008                 par->cob_index = 2;
2009                 par->cob_size = 0x8000 << par->cob_index;
2010                 par->cob_offset = videoRambytes;
2011         } else {
2012                 /* We use 128kB for the COB on all chips. */
2013
2014                 par->cob_index  = 7;
2015                 par->cob_size   = 0x400 << par->cob_index;
2016                 par->cob_offset = videoRambytes - par->cob_size;
2017         }
2018
2019         return videoRambytes;
2020 }
2021
2022 static int __devinit savage_init_fb_info(struct fb_info *info,
2023                                          struct pci_dev *dev,
2024                                          const struct pci_device_id *id)
2025 {
2026         struct savagefb_par *par = info->par;
2027         int err = 0;
2028
2029         par->pcidev  = dev;
2030
2031         info->fix.type     = FB_TYPE_PACKED_PIXELS;
2032         info->fix.type_aux         = 0;
2033         info->fix.ypanstep         = 1;
2034         info->fix.ywrapstep   = 0;
2035         info->fix.accel       = id->driver_data;
2036
2037         switch (info->fix.accel) {
2038         case FB_ACCEL_SUPERSAVAGE:
2039                 par->chip = S3_SUPERSAVAGE;
2040                 snprintf(info->fix.id, 16, "SuperSavage");
2041                 break;
2042         case FB_ACCEL_SAVAGE4:
2043                 par->chip = S3_SAVAGE4;
2044                 snprintf(info->fix.id, 16, "Savage4");
2045                 break;
2046         case FB_ACCEL_SAVAGE3D:
2047                 par->chip = S3_SAVAGE3D;
2048                 snprintf(info->fix.id, 16, "Savage3D");
2049                 break;
2050         case FB_ACCEL_SAVAGE3D_MV:
2051                 par->chip = S3_SAVAGE3D;
2052                 snprintf(info->fix.id, 16, "Savage3D-MV");
2053                 break;
2054         case FB_ACCEL_SAVAGE2000:
2055                 par->chip = S3_SAVAGE2000;
2056                 snprintf(info->fix.id, 16, "Savage2000");
2057                 break;
2058         case FB_ACCEL_SAVAGE_MX_MV:
2059                 par->chip = S3_SAVAGE_MX;
2060                 snprintf(info->fix.id, 16, "Savage/MX-MV");
2061                 break;
2062         case FB_ACCEL_SAVAGE_MX:
2063                 par->chip = S3_SAVAGE_MX;
2064                 snprintf(info->fix.id, 16, "Savage/MX");
2065                 break;
2066         case FB_ACCEL_SAVAGE_IX_MV:
2067                 par->chip = S3_SAVAGE_MX;
2068                 snprintf(info->fix.id, 16, "Savage/IX-MV");
2069                 break;
2070         case FB_ACCEL_SAVAGE_IX:
2071                 par->chip = S3_SAVAGE_MX;
2072                 snprintf(info->fix.id, 16, "Savage/IX");
2073                 break;
2074         case FB_ACCEL_PROSAVAGE_PM:
2075                 par->chip = S3_PROSAVAGE;
2076                 snprintf(info->fix.id, 16, "ProSavagePM");
2077                 break;
2078         case FB_ACCEL_PROSAVAGE_KM:
2079                 par->chip = S3_PROSAVAGE;
2080                 snprintf(info->fix.id, 16, "ProSavageKM");
2081                 break;
2082         case FB_ACCEL_S3TWISTER_P:
2083                 par->chip = S3_PROSAVAGE;
2084                 snprintf(info->fix.id, 16, "TwisterP");
2085                 break;
2086         case FB_ACCEL_S3TWISTER_K:
2087                 par->chip = S3_PROSAVAGE;
2088                 snprintf(info->fix.id, 16, "TwisterK");
2089                 break;
2090         case FB_ACCEL_PROSAVAGE_DDR:
2091                 par->chip = S3_PROSAVAGE;
2092                 snprintf(info->fix.id, 16, "ProSavageDDR");
2093                 break;
2094         case FB_ACCEL_PROSAVAGE_DDRK:
2095                 par->chip = S3_PROSAVAGE;
2096                 snprintf(info->fix.id, 16, "ProSavage8");
2097                 break;
2098         }
2099
2100         if (S3_SAVAGE3D_SERIES(par->chip)) {
2101                 par->SavageWaitIdle = savage3D_waitidle;
2102                 par->SavageWaitFifo = savage3D_waitfifo;
2103         } else if (S3_SAVAGE4_SERIES(par->chip) ||
2104                    S3_SUPERSAVAGE == par->chip) {
2105                 par->SavageWaitIdle = savage4_waitidle;
2106                 par->SavageWaitFifo = savage4_waitfifo;
2107         } else {
2108                 par->SavageWaitIdle = savage2000_waitidle;
2109                 par->SavageWaitFifo = savage2000_waitfifo;
2110         }
2111
2112         info->var.nonstd      = 0;
2113         info->var.activate    = FB_ACTIVATE_NOW;
2114         info->var.width       = -1;
2115         info->var.height      = -1;
2116         info->var.accel_flags = 0;
2117
2118         info->fbops          = &savagefb_ops;
2119         info->flags          = FBINFO_DEFAULT |
2120                                FBINFO_HWACCEL_YPAN |
2121                                FBINFO_HWACCEL_XPAN;
2122
2123         info->pseudo_palette = par->pseudo_palette;
2124
2125 #if defined(CONFIG_FB_SAVAGE_ACCEL)
2126         /* FIFO size + padding for commands */
2127         info->pixmap.addr = kmalloc(8*1024, GFP_KERNEL);
2128
2129         err = -ENOMEM;
2130         if (info->pixmap.addr) {
2131                 memset(info->pixmap.addr, 0, 8*1024);
2132                 info->pixmap.size = 8*1024;
2133                 info->pixmap.scan_align = 4;
2134                 info->pixmap.buf_align = 4;
2135                 info->pixmap.access_align = 32;
2136
2137                 err = fb_alloc_cmap(&info->cmap, NR_PALETTE, 0);
2138                 if (!err)
2139                 info->flags |= FBINFO_HWACCEL_COPYAREA |
2140                                FBINFO_HWACCEL_FILLRECT |
2141                                FBINFO_HWACCEL_IMAGEBLIT;
2142         }
2143 #endif
2144         return err;
2145 }
2146
2147 /* --------------------------------------------------------------------- */
2148
2149 static int __devinit savagefb_probe(struct pci_dev* dev,
2150                                     const struct pci_device_id* id)
2151 {
2152         struct fb_info *info;
2153         struct savagefb_par *par;
2154         u_int h_sync, v_sync;
2155         int err, lpitch;
2156         int video_len;
2157
2158         DBG("savagefb_probe");
2159         SavagePrintRegs();
2160
2161         info = framebuffer_alloc(sizeof(struct savagefb_par), &dev->dev);
2162         if (!info)
2163                 return -ENOMEM;
2164         par = info->par;
2165         err = pci_enable_device(dev);
2166         if (err)
2167                 goto failed_enable;
2168
2169         if ((err = pci_request_regions(dev, "savagefb"))) {
2170                 printk(KERN_ERR "cannot request PCI regions\n");
2171                 goto failed_enable;
2172         }
2173
2174         err = -ENOMEM;
2175
2176         if ((err = savage_init_fb_info(info, dev, id)))
2177                 goto failed_init;
2178
2179         err = savage_map_mmio(info);
2180         if (err)
2181                 goto failed_mmio;
2182
2183         video_len = savage_init_hw(par);
2184         /* FIXME: cant be negative */
2185         if (video_len < 0) {
2186                 err = video_len;
2187                 goto failed_mmio;
2188         }
2189
2190         err = savage_map_video(info, video_len);
2191         if (err)
2192                 goto failed_video;
2193
2194         INIT_LIST_HEAD(&info->modelist);
2195 #if defined(CONFIG_FB_SAVAGE_I2C)
2196         savagefb_create_i2c_busses(info);
2197         savagefb_probe_i2c_connector(info, &par->edid);
2198         fb_edid_to_monspecs(par->edid, &info->monspecs);
2199         kfree(par->edid);
2200         fb_videomode_to_modelist(info->monspecs.modedb,
2201                                  info->monspecs.modedb_len,
2202                                  &info->modelist);
2203 #endif
2204         info->var = savagefb_var800x600x8;
2205
2206         if (mode_option) {
2207                 fb_find_mode(&info->var, info, mode_option,
2208                              info->monspecs.modedb, info->monspecs.modedb_len,
2209                              NULL, 8);
2210         } else if (info->monspecs.modedb != NULL) {
2211                 struct fb_videomode *modedb;
2212
2213                 modedb = fb_find_best_display(&info->monspecs,
2214                                               &info->modelist);
2215                 savage_update_var(&info->var, modedb);
2216         }
2217
2218         /* maximize virtual vertical length */
2219         lpitch = info->var.xres_virtual*((info->var.bits_per_pixel + 7) >> 3);
2220         info->var.yres_virtual = info->fix.smem_len/lpitch;
2221
2222         if (info->var.yres_virtual < info->var.yres)
2223                 goto failed;
2224
2225 #if defined(CONFIG_FB_SAVAGE_ACCEL)
2226         /*
2227          * The clipping coordinates are masked with 0xFFF, so limit our
2228          * virtual resolutions to these sizes.
2229          */
2230         if (info->var.yres_virtual > 0x1000)
2231                 info->var.yres_virtual = 0x1000;
2232
2233         if (info->var.xres_virtual > 0x1000)
2234                 info->var.xres_virtual = 0x1000;
2235 #endif
2236         savagefb_check_var(&info->var, info);
2237         savagefb_set_fix(info);
2238
2239         /*
2240          * Calculate the hsync and vsync frequencies.  Note that
2241          * we split the 1e12 constant up so that we can preserve
2242          * the precision and fit the results into 32-bit registers.
2243          *  (1953125000 * 512 = 1e12)
2244          */
2245         h_sync = 1953125000 / info->var.pixclock;
2246         h_sync = h_sync * 512 / (info->var.xres + info->var.left_margin +
2247                                  info->var.right_margin +
2248                                  info->var.hsync_len);
2249         v_sync = h_sync / (info->var.yres + info->var.upper_margin +
2250                            info->var.lower_margin + info->var.vsync_len);
2251
2252         printk(KERN_INFO "savagefb v" SAVAGEFB_VERSION ": "
2253                "%dkB VRAM, using %dx%d, %d.%03dkHz, %dHz\n",
2254                info->fix.smem_len >> 10,
2255                info->var.xres, info->var.yres,
2256                h_sync / 1000, h_sync % 1000, v_sync);
2257
2258
2259         fb_destroy_modedb(info->monspecs.modedb);
2260         info->monspecs.modedb = NULL;
2261
2262         err = register_framebuffer(info);
2263         if (err < 0)
2264                 goto failed;
2265
2266         printk(KERN_INFO "fb: S3 %s frame buffer device\n",
2267                info->fix.id);
2268
2269         /*
2270          * Our driver data
2271          */
2272         pci_set_drvdata(dev, info);
2273
2274         return 0;
2275
2276  failed:
2277 #ifdef CONFIG_FB_SAVAGE_I2C
2278         savagefb_delete_i2c_busses(info);
2279 #endif
2280         fb_alloc_cmap(&info->cmap, 0, 0);
2281         savage_unmap_video(info);
2282  failed_video:
2283         savage_unmap_mmio(info);
2284  failed_mmio:
2285         kfree(info->pixmap.addr);
2286  failed_init:
2287         pci_release_regions(dev);
2288  failed_enable:
2289         framebuffer_release(info);
2290
2291         return err;
2292 }
2293
2294 static void __devexit savagefb_remove(struct pci_dev *dev)
2295 {
2296         struct fb_info *info = pci_get_drvdata(dev);
2297
2298         DBG("savagefb_remove");
2299
2300         if (info) {
2301                 /*
2302                  * If unregister_framebuffer fails, then
2303                  * we will be leaving hooks that could cause
2304                  * oopsen laying around.
2305                  */
2306                 if (unregister_framebuffer(info))
2307                         printk(KERN_WARNING "savagefb: danger danger! "
2308                                "Oopsen imminent!\n");
2309
2310 #ifdef CONFIG_FB_SAVAGE_I2C
2311                 savagefb_delete_i2c_busses(info);
2312 #endif
2313                 fb_alloc_cmap(&info->cmap, 0, 0);
2314                 savage_unmap_video(info);
2315                 savage_unmap_mmio(info);
2316                 kfree(info->pixmap.addr);
2317                 pci_release_regions(dev);
2318                 framebuffer_release(info);
2319
2320                 /*
2321                  * Ensure that the driver data is no longer
2322                  * valid.
2323                  */
2324                 pci_set_drvdata(dev, NULL);
2325         }
2326 }
2327
2328 static int savagefb_suspend(struct pci_dev* dev, pm_message_t state)
2329 {
2330         struct fb_info *info = pci_get_drvdata(dev);
2331         struct savagefb_par *par = info->par;
2332
2333         DBG("savagefb_suspend");
2334
2335
2336         par->pm_state = state.event;
2337
2338         /*
2339          * For PM_EVENT_FREEZE, do not power down so the console
2340          * can remain active.
2341          */
2342         if (state.event == PM_EVENT_FREEZE) {
2343                 dev->dev.power.power_state = state;
2344                 return 0;
2345         }
2346
2347         acquire_console_sem();
2348         fb_set_suspend(info, 1);
2349
2350         if (info->fbops->fb_sync)
2351                 info->fbops->fb_sync(info);
2352
2353         savagefb_blank(FB_BLANK_POWERDOWN, info);
2354         savage_set_default_par(par, &par->save);
2355         savage_disable_mmio(par);
2356         pci_save_state(dev);
2357         pci_disable_device(dev);
2358         pci_set_power_state(dev, pci_choose_state(dev, state));
2359         release_console_sem();
2360
2361         return 0;
2362 }
2363
2364 static int savagefb_resume(struct pci_dev* dev)
2365 {
2366         struct fb_info *info = pci_get_drvdata(dev);
2367         struct savagefb_par *par = info->par;
2368         int cur_state = par->pm_state;
2369
2370         DBG("savage_resume");
2371
2372         par->pm_state = PM_EVENT_ON;
2373
2374         /*
2375          * The adapter was not powered down coming back from a
2376          * PM_EVENT_FREEZE.
2377          */
2378         if (cur_state == PM_EVENT_FREEZE) {
2379                 pci_set_power_state(dev, PCI_D0);
2380                 return 0;
2381         }
2382
2383         acquire_console_sem();
2384
2385         pci_set_power_state(dev, PCI_D0);
2386         pci_restore_state(dev);
2387
2388         if (pci_enable_device(dev))
2389                 DBG("err");
2390
2391         pci_set_master(dev);
2392         savage_enable_mmio(par);
2393         savage_init_hw(par);
2394         savagefb_set_par(info);
2395         fb_set_suspend(info, 0);
2396         savagefb_blank(FB_BLANK_UNBLANK, info);
2397         release_console_sem();
2398
2399         return 0;
2400 }
2401
2402
2403 static struct pci_device_id savagefb_devices[] __devinitdata = {
2404         {PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_MX128,
2405          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},
2406
2407         {PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_MX64,
2408          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},
2409
2410         {PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_MX64C,
2411          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},
2412
2413         {PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_IX128SDR,
2414          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},
2415
2416         {PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_IX128DDR,
2417          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},
2418
2419         {PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_IX64SDR,
2420          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},
2421
2422         {PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_IX64DDR,
2423          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},
2424
2425         {PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_IXCSDR,
2426          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},
2427
2428         {PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_IXCDDR,
2429          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},
2430
2431         {PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE4,
2432          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE4},
2433
2434         {PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE3D,
2435          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE3D},
2436
2437         {PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE3D_MV,
2438          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE3D_MV},
2439
2440         {PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE2000,
2441          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE2000},
2442
2443         {PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE_MX_MV,
2444          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE_MX_MV},
2445
2446         {PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE_MX,
2447          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE_MX},
2448
2449         {PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE_IX_MV,
2450          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE_IX_MV},
2451
2452         {PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE_IX,
2453          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE_IX},
2454
2455         {PCI_VENDOR_ID_S3, PCI_CHIP_PROSAVAGE_PM,
2456          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_PROSAVAGE_PM},
2457
2458         {PCI_VENDOR_ID_S3, PCI_CHIP_PROSAVAGE_KM,
2459          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_PROSAVAGE_KM},
2460
2461         {PCI_VENDOR_ID_S3, PCI_CHIP_S3TWISTER_P,
2462          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_S3TWISTER_P},
2463
2464         {PCI_VENDOR_ID_S3, PCI_CHIP_S3TWISTER_K,
2465          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_S3TWISTER_K},
2466
2467         {PCI_VENDOR_ID_S3, PCI_CHIP_PROSAVAGE_DDR,
2468          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_PROSAVAGE_DDR},
2469
2470         {PCI_VENDOR_ID_S3, PCI_CHIP_PROSAVAGE_DDRK,
2471          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_PROSAVAGE_DDRK},
2472
2473         {0, 0, 0, 0, 0, 0, 0}
2474 };
2475
2476 MODULE_DEVICE_TABLE(pci, savagefb_devices);
2477
2478 static struct pci_driver savagefb_driver = {
2479         .name =     "savagefb",
2480         .id_table = savagefb_devices,
2481         .probe =    savagefb_probe,
2482         .suspend =  savagefb_suspend,
2483         .resume =   savagefb_resume,
2484         .remove =   __devexit_p(savagefb_remove)
2485 };
2486
2487 /* **************************** exit-time only **************************** */
2488
2489 static void __exit savage_done(void)
2490 {
2491         DBG("savage_done");
2492         pci_unregister_driver(&savagefb_driver);
2493 }
2494
2495
2496 /* ************************* init in-kernel code ************************** */
2497
2498 static int __init savagefb_setup(char *options)
2499 {
2500 #ifndef MODULE
2501         char *this_opt;
2502
2503         if (!options || !*options)
2504                 return 0;
2505
2506         while ((this_opt = strsep(&options, ",")) != NULL) {
2507                 mode_option = this_opt;
2508         }
2509 #endif /* !MODULE */
2510         return 0;
2511 }
2512
2513 static int __init savagefb_init(void)
2514 {
2515         char *option;
2516
2517         DBG("savagefb_init");
2518
2519         if (fb_get_options("savagefb", &option))
2520                 return -ENODEV;
2521
2522         savagefb_setup(option);
2523         return pci_register_driver(&savagefb_driver);
2524
2525 }
2526
2527 module_init(savagefb_init);
2528 module_exit(savage_done);
2529
2530 module_param(mode_option, charp, 0);
2531 MODULE_PARM_DESC(mode_option, "Specify initial video mode");