Merge master.kernel.org:/pub/scm/linux/kernel/git/bart/ide-2.6
[linux-2.6] / drivers / ide / pci / hpt34x.c
1 /*
2  * linux/drivers/ide/pci/hpt34x.c               Version 0.40    Sept 10, 2002
3  *
4  * Copyright (C) 1998-2000      Andre Hedrick <andre@linux-ide.org>
5  * May be copied or modified under the terms of the GNU General Public License
6  *
7  *
8  * 00:12.0 Unknown mass storage controller:
9  * Triones Technologies, Inc.
10  * Unknown device 0003 (rev 01)
11  *
12  * hde: UDMA 2 (0x0000 0x0002) (0x0000 0x0010)
13  * hdf: UDMA 2 (0x0002 0x0012) (0x0010 0x0030)
14  * hde: DMA 2  (0x0000 0x0002) (0x0000 0x0010)
15  * hdf: DMA 2  (0x0002 0x0012) (0x0010 0x0030)
16  * hdg: DMA 1  (0x0012 0x0052) (0x0030 0x0070)
17  * hdh: DMA 1  (0x0052 0x0252) (0x0070 0x00f0)
18  *
19  * ide-pci.c reference
20  *
21  * Since there are two cards that report almost identically,
22  * the only discernable difference is the values reported in pcicmd.
23  * Booting-BIOS card or HPT363 :: pcicmd == 0x07
24  * Non-bootable card or HPT343 :: pcicmd == 0x05
25  */
26
27 #include <linux/module.h>
28 #include <linux/types.h>
29 #include <linux/kernel.h>
30 #include <linux/delay.h>
31 #include <linux/timer.h>
32 #include <linux/mm.h>
33 #include <linux/ioport.h>
34 #include <linux/blkdev.h>
35 #include <linux/hdreg.h>
36 #include <linux/interrupt.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/ide.h>
40
41 #include <asm/io.h>
42 #include <asm/irq.h>
43
44 #define HPT343_DEBUG_DRIVE_INFO         0
45
46 static void hpt34x_set_mode(ide_drive_t *drive, const u8 speed)
47 {
48         struct pci_dev *dev     = HWIF(drive)->pci_dev;
49         u32 reg1= 0, tmp1 = 0, reg2 = 0, tmp2 = 0;
50         u8                      hi_speed, lo_speed;
51
52         hi_speed = speed >> 4;
53         lo_speed = speed & 0x0f;
54
55         if (hi_speed & 7) {
56                 hi_speed = (hi_speed & 4) ? 0x01 : 0x10;
57         } else {
58                 lo_speed <<= 5;
59                 lo_speed >>= 5;
60         }
61
62         pci_read_config_dword(dev, 0x44, &reg1);
63         pci_read_config_dword(dev, 0x48, &reg2);
64         tmp1 = ((lo_speed << (3*drive->dn)) | (reg1 & ~(7 << (3*drive->dn))));
65         tmp2 = ((hi_speed << drive->dn) | (reg2 & ~(0x11 << drive->dn)));
66         pci_write_config_dword(dev, 0x44, tmp1);
67         pci_write_config_dword(dev, 0x48, tmp2);
68
69 #if HPT343_DEBUG_DRIVE_INFO
70         printk("%s: %s drive%d (0x%04x 0x%04x) (0x%04x 0x%04x)" \
71                 " (0x%02x 0x%02x)\n",
72                 drive->name, ide_xfer_verbose(speed),
73                 drive->dn, reg1, tmp1, reg2, tmp2,
74                 hi_speed, lo_speed);
75 #endif /* HPT343_DEBUG_DRIVE_INFO */
76 }
77
78 static void hpt34x_set_pio_mode(ide_drive_t *drive, const u8 pio)
79 {
80         hpt34x_set_mode(drive, XFER_PIO_0 + pio);
81 }
82
83 /*
84  * If the BIOS does not set the IO base addaress to XX00, 343 will fail.
85  */
86 #define HPT34X_PCI_INIT_REG             0x80
87
88 static unsigned int __devinit init_chipset_hpt34x(struct pci_dev *dev, const char *name)
89 {
90         int i = 0;
91         unsigned long hpt34xIoBase = pci_resource_start(dev, 4);
92         unsigned long hpt_addr[4] = { 0x20, 0x34, 0x28, 0x3c };
93         unsigned long hpt_addr_len[4] = { 7, 3, 7, 3 };
94         u16 cmd;
95         unsigned long flags;
96
97         local_irq_save(flags);
98
99         pci_write_config_byte(dev, HPT34X_PCI_INIT_REG, 0x00);
100         pci_read_config_word(dev, PCI_COMMAND, &cmd);
101
102         if (cmd & PCI_COMMAND_MEMORY)
103                 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xF0);
104         else
105                 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x20);
106
107         /*
108          * Since 20-23 can be assigned and are R/W, we correct them.
109          */
110         pci_write_config_word(dev, PCI_COMMAND, cmd & ~PCI_COMMAND_IO);
111         for(i=0; i<4; i++) {
112                 dev->resource[i].start = (hpt34xIoBase + hpt_addr[i]);
113                 dev->resource[i].end = dev->resource[i].start + hpt_addr_len[i];
114                 dev->resource[i].flags = IORESOURCE_IO;
115                 pci_write_config_dword(dev,
116                                 (PCI_BASE_ADDRESS_0 + (i * 4)),
117                                 dev->resource[i].start);
118         }
119         pci_write_config_word(dev, PCI_COMMAND, cmd);
120
121         local_irq_restore(flags);
122
123         return dev->irq;
124 }
125
126 static void __devinit init_hwif_hpt34x(ide_hwif_t *hwif)
127 {
128         hwif->set_pio_mode = &hpt34x_set_pio_mode;
129         hwif->set_dma_mode = &hpt34x_set_mode;
130 }
131
132 static const struct ide_port_info hpt34x_chipsets[] __devinitdata = {
133         { /* 0 */
134                 .name           = "HPT343",
135                 .init_chipset   = init_chipset_hpt34x,
136                 .init_hwif      = init_hwif_hpt34x,
137                 .extra          = 16,
138                 .host_flags     = IDE_HFLAG_NO_ATAPI_DMA |
139                                   IDE_HFLAG_NO_AUTODMA,
140                 .pio_mask       = ATA_PIO5,
141         },
142         { /* 1 */
143                 .name           = "HPT345",
144                 .init_chipset   = init_chipset_hpt34x,
145                 .init_hwif      = init_hwif_hpt34x,
146                 .extra          = 16,
147                 .host_flags     = IDE_HFLAG_NO_ATAPI_DMA |
148                                   IDE_HFLAG_NO_AUTODMA |
149                                   IDE_HFLAG_OFF_BOARD,
150                 .pio_mask       = ATA_PIO5,
151 #ifdef CONFIG_HPT34X_AUTODMA
152                 .swdma_mask     = ATA_SWDMA2,
153                 .mwdma_mask     = ATA_MWDMA2,
154                 .udma_mask      = ATA_UDMA2,
155 #endif
156         }
157 };
158
159 static int __devinit hpt34x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
160 {
161         const struct ide_port_info *d;
162         u16 pcicmd = 0;
163
164         pci_read_config_word(dev, PCI_COMMAND, &pcicmd);
165
166         d = &hpt34x_chipsets[(pcicmd & PCI_COMMAND_MEMORY) ? 1 : 0];
167
168         return ide_setup_pci_device(dev, d);
169 }
170
171 static const struct pci_device_id hpt34x_pci_tbl[] = {
172         { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT343), 0 },
173         { 0, },
174 };
175 MODULE_DEVICE_TABLE(pci, hpt34x_pci_tbl);
176
177 static struct pci_driver driver = {
178         .name           = "HPT34x_IDE",
179         .id_table       = hpt34x_pci_tbl,
180         .probe          = hpt34x_init_one,
181 };
182
183 static int __init hpt34x_ide_init(void)
184 {
185         return ide_pci_register_driver(&driver);
186 }
187
188 module_init(hpt34x_ide_init);
189
190 MODULE_AUTHOR("Andre Hedrick");
191 MODULE_DESCRIPTION("PCI driver module for Highpoint 34x IDE");
192 MODULE_LICENSE("GPL");